Digital background correction method irrelevant to input signal

Abstract

The invention discloses a digital background correction method irrelevant to an input signal, and belongs to the technical field of analog integrated circuits. The invention mainly aims at the nonlinear error problem caused by capacitor mismatch in a pipelined successive approximation analog-to-digital converter (Piped-SAR ADC), a single ADC is split into two independent sampling channels, and technologies such as butterfly shuffling, bit switching and perturbation injection are adopted, so that the system can generate sufficient correction information under any input condition. Error signals between code words output by the two channels are used as feedback, digital weights are updated in real time through a least mean square (LMS) iterative algorithm, background correction of capacitor mismatch and DAC establishment errors is rapidly achieved, and the overall linearity and precision of the ADC are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits and high-precision analog-to-digital conversion, and relates to a digital background calibration method independent of input signals. This method is mainly used to solve the non-linearity problem caused by capacitor mismatch in pipelined successive approximation analog-to-digital converters, and can achieve fast and high-precision background calibration under any input signals (including dynamic signals and DC signals). Background Art

[0002] With the continuous improvement of the performance requirements of analog-to-digital converters in high-speed signal processing and data acquisition systems, SAR ADCs are widely used due to their low power consumption, relatively high resolution, and good linearity. However, in the actual manufacturing process of ADCs, capacitor mismatch problems inevitably exist, which directly affect the linearity and signal-to-noise ratio of ADCs, and thus limit the system performance. Most traditional digital background calibration methods rely on fixed input signals or large-range signals to generate sufficient calibration information, resulting in slow calibration speed and limited accuracy when the input signal is complex or DC. To solve the above problems, there is an urgent need for a digital background calibration method that can be independent of the characteristics of input signals and can quickly and accurately compensate for capacitor mismatch errors. Summary of the Invention

[0003] To overcome the deficiencies in the prior art, the present invention proposes a brand-new digital background calibration method independent of input signals, and its main technical ideas and innovations include the following aspects.

[0004] Multi-channel sampling architecture: The present invention splits the traditional single-channel ADC into two independent sampling channels, and these two channels simultaneously sample and quantize the same input signal. Through the two digital output codewords obtained by independent sampling, although the internally inherent random mismatch information is correlated, it is independent of each other, thus providing a rich source of error information for the calibration algorithm. This design can not only resist the changes in the amplitude and form of input signals, but also generate sufficient calibration data under DC or low-frequency inputs.

[0005] Butterfly shuffling and random dither injection technology: In the first sub-module, the thermometer code output by the flash ADC and the dither signal generated by the pseudo-random generator are processed by the butterfly shuffler to perform zero-order scrambling on the codewords of 32 8Cu unit capacitors in the MSB DAC. This technology ensures that even under DC input conditions, each capacitor has the opportunity to receive random dither, and the LSB and MSB also receive mutually injected dither, thus effectively breaking the fixed bias, enabling the capacitor mismatch errors to be randomly distributed, and generating more abundant calibration information.

[0006] MSB and LSB Bit-Swap Mechanism: In the first stage of the pipelined SAR ADC, after the initial quantization of the MSB and LSB respectively, the mismatch information of the two originally separated parts is coupled by swapping the last three bits of the MSB with the first two bits of the LSB (both corresponding to 24 Cu). The swapping operation also uses a butterfly shuffler. This not only enables the errors of the two parts to compensate each other, but also increases the amount of random information on which the system calibration is based, thereby enhancing the sensitivity and compensation accuracy of the calibration algorithm for non-linear errors.

[0007] Residual Amplification and Multi-Stage Quantization Design: After the first-stage quantization is completed, the residual amplifier amplifies the remaining error signal by 17 times, further amplifying the tiny capacitance mismatch information for subsequent detection. The amplified signal enters the second-stage traditional SAR ADC, which adopts a two-stage bridged-capacitor DAC design and can achieve high-precision quantization of about 13 bits. The combination of the two-stage ADC enables the entire system to achieve 17-bit high-precision analog-to-digital conversion, while precisely capturing the amplified error information to provide accurate data support for subsequent digital back-end calibration.

[0008] Digital Back-End Calibration Based on the LMS Iterative Algorithm: After each channel completes a full ADC conversion, respective digital codewords are obtained. Due to the random error information formed during shuffling, dither injection, and bit swapping, there are slight differences between the two channels. Using this difference, the least mean square (LMS) iterative algorithm is used as the calibration core. By continuously comparing the differences between the output codewords of the two channels, the error signal is calculated, and the weighting coefficients of the digital codewords of each channel are updated in real time. This algorithm can automatically adapt to temperature, process, and aging changes, achieve continuous on-line calibration, and quickly converge under various input conditions to ensure that the overall ADC output meets the high linearity requirements.

[0009] Comprehensive Advantages and Applicability: Input Signal Independence: Regardless of whether the input signal is a dynamic waveform or a DC level, sufficient calibration information can be guaranteed, with extremely strong adaptability. Fast Calibration Speed: The butterfly shuffling and dither in the MSB and LSB exchangeable and bit-swap designs greatly increase the random calibration information, enabling the LMS iterative algorithm to converge quickly in a short time. High Precision and Robustness: The multi-stage quantization design combined with the residual amplification technology enables the entire system to precisely capture and compensate for tiny mismatch errors during the calibration process, improving the overall performance of the ADC.

[0010] In summary, the present invention provides a novel digital back-end calibration technology that breaks through the limitations of traditional methods, solves the problem of capacitance mismatch limiting the accuracy of the ADC, and significantly improves the calibration speed and applicability through system-level optimization design, providing solid technical support for high-precision signal acquisition systems. Brief Description of the Drawings

[0011] Figure 1 This is a schematic diagram of the overall structure of the ADC of the present invention, as well as a schematic diagram of the first-stage MSB capacitor array butterfly shuffle, dither injection, and bit swapping processing.

[0012] Figure 2 This is the overall framework of the digital background correction system.

[0013] Figure 3 This is the uncorrected spectrum.

[0014] Figure 4 This is the spectrum diagram of the present invention that has been scrambled but not corrected.

[0015] Figure 5 This is the spectrum diagram of the present invention after correction. Specific Embodiments

[0016] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. The embodiments are all beneficial implementations of the technical solutions of the present invention. The specific details can be adjusted according to actual applications, and none of them should be regarded as a limitation to the protection scope of the present invention.

[0017] Overall Structure of the ADC System: As Figure 1 shown, the entire ADC system consists of three sub-modules: The first sub-module (flash ADC): A 5-bit flash ADC is used to perform high-speed sampling on the input signal Vin. The thermometer code (D1~D31) output by this module and the pseudo-randomly generated dither signal (D32) enter the butterfly shuffler together to achieve the random distribution of the codes of 32 8Cu capacitor units in the MSB DAC. The second and third sub-modules (pipelined SAR ADC): Each module adopts a two-stage pipelined structure. The first stage is jointly composed of the MSB and LSB DACs. After coupling the mismatch information of the two parts through bit swapping, a digital codeword is output; the second stage uses a residue amplifier and a high-precision SAR ADC to amplify the remaining error signal by 17 times and perform 13-bit quantization.

[0018] Implementation of the Butterfly Shuffle and Bit Swapping Mechanism: In the first sub-module, the thermometer code output by the flash ADC and the 1-bit dither signal are zero-order scrambled by the butterfly shuffler to ensure that each MSB capacitor has the opportunity to inject the dither signal. Subsequently, in the first stage of the pipelined SAR ADC, after the MSB and LSB are each preliminarily quantized, a dedicated exchange module is used to swap the last 3 bits of the MSB and the first 2 bits of the LSB to obtain a new codeword sequence containing complementary mismatch information. This step effectively enhances the randomness between the two parts of the data and provides rich reference information for the subsequent digital background correction based on the LMS algorithm.

[0019] Residual Amplification and Multistage Quantization: After the first stage is completed, the residual amplifier implemented using switched-capacitor technology amplifies the remaining error signal, and the amplification factor is designed to be 17 times. The amplified signal enters the second-stage SAR ADC. This ADC adopts a two-stage bridged-capacitor DAC design, and further reduces the requirements for the residual amplifier through internal attenuation capacitors, achieving high-precision quantization of approximately 13 bits. This multistage quantization design not only improves the overall resolution (reaching 17 bits), but also ensures that subtle mismatch errors can be accurately captured.

[0020] Digital Background Calibration Algorithm and Real-time Calibration Process: After the ADC conversions are completed separately for two independent channels, the overall ADC output is formed through weighted averaging. At the same time, the small difference between the output codewords of the two channels constitutes the feedback error signal. The specific calibration process includes: Error Detection: Collect the output codewords of the two channels and obtain the error magnitude through comparison. This error mainly comes from capacitor mismatch and random fluctuations caused by dither injection; LMS Algorithm Iteration: Use the least mean square (LMS) algorithm. Take the detected error as the feedback input and adjust the weighting coefficients of each digital codeword in real time by setting an appropriate step factor. This iterative process is carried out in hardware at a fixed clock cycle without affecting the normal sampling of the ADC; Convergence Judgment: The system continuously monitors the difference between the output codewords of the two channels. When the difference stably drops below a predetermined threshold, it is considered that the calibration meets the requirements, and the system enters the normal quantization output state.

[0021] This calibration process is adaptive and continuously online, and can compensate for system errors caused by temperature changes, process drifts, or aging in real time.

[0022] Parameter Optimization and System Debugging: In practical applications, in order to achieve the best calibration effect, parameters such as the dither injection amplitude, butterfly shuffler design, exchange ratio, and LMS algorithm step size of the system need to be optimized. Through simulation and actual testing, the optimal parameter combination can be determined, enabling the calibration process to converge rapidly in an extremely short time while ensuring high precision and stability under various working conditions.

[0023] Effect Explanation of the Embodiment: Taking a specific embodiment as an example, in the 17-bit high-precision conversion of the ADC system adopting the technical solution of the present invention, after background calibration, both its SFDR and SNDR are significantly improved. The test results show that whether the input is a DC signal or a high-speed dynamic signal, the system can achieve error convergence within a short calibration time, verifying the superiority of the present invention in improving linearity and dynamic range.

[0024] In summary, the present invention provides an innovative digital background calibration method. Through multi-channel sampling, butterfly shuffling, bit swapping, residual amplification, and background calibration based on the LMS iterative algorithm, it effectively solves the non-linearity problem caused by capacitor mismatch in traditional ADCs. This method does not depend on the type of input signal, can generate sufficient calibration information under DC and low-frequency conditions, and can maintain fast convergence under high-speed dynamic signals, meeting the requirements of high-precision analog-to-digital converters in various complex application environments.

Claims

1. A digital background correction method independent of the input signal, characterized in that: The analog-to-digital conversion system includes three ADC sub-modules. The first sub-module uses a flash analog-to-digital converter (Flash ADC), and the second and third sub-modules both adopt a two-stage pipelined successive approximation analog-to-digital converter structure. The flash ADC generates a thermometer code during sampling, which, together with the dither signal generated by the pseudo-random generator, is processed by the butterfly shuffler and then sent to the MSB parts of the two pipelined SAR ADCs respectively. The first stage of the pipelined SAR ADC consists of an MSB DAC and an LSB DAC. The MSB DAC is composed of 32 8Cu unit capacitors. After butterfly shuffling, 31 capacitors can be randomly combined to form weighted values of 16, 8, 4, 2, and 1, and the remaining 1 capacitor is used for dither injection. The LSB DAC is composed of 32 1Cu unit capacitors, and its capacitors are fixedly allocated as 16Cu, 8Cu, 4Cu, 2Cu, and 1Cu, and redundancy is introduced in the first two bits to tolerate dither injection, mismatch between the flash ADC and the DAC, and DAC settling error. After completing their respective preliminary quantization, the last three bits of the MSB and the first two bits of the LSB are exchanged by using the butterfly shuffling method, and a digital codeword containing the exchange information is regenerated through the multiplexer. After the first-stage quantization is completed, the residual signal is amplified by the residual amplifier (amplification factor is 17 times), and this amplified signal is then highly accurately quantized by the second-stage traditional SAR ADC (about 13-bit resolution) to form the overall ADC output. The digital output codewords of the two channels are weighted and averaged to form the final output. At the same time, the differential error signal between the two-channel outputs is fed back to the LMS iterative correction module, and the digital weights are iteratively updated until the difference between the channels drops to a predetermined threshold, thereby realizing the background correction of capacitor mismatch and related errors.

2. The method according to claim 1, characterized in that: The butterfly shuffler performs zero-order scrambling on the codewords of the 32 capacitor units in the MSB DAC and randomly distributes the injected dither signal, so that even under a DC or fixed-level input, it can ensure that each capacitor unit may receive dither, thereby realizing the uniform extraction of correction information.

3. The method according to claim 1, characterized in that: The LSB part and the MSB part adopt a similar shuffling and exchange processing scheme. By exchanging the codewords between the two parts, complementary mismatch information is formed, improving the randomness and reliability of the overall correction data.

4. The method according to claim 1, wherein: The LMS iterative correction algorithm uses the difference between the digital output codewords of the two channels as the feedback error signal. By setting appropriate step-size factors and weight update formulas, the weighted parameters of each codeword are iteratively adjusted in real time to ensure that the correction process quickly and stably converges to a predetermined accuracy.

5. The method according to claim 1, characterized in that: The overall ADC system realizes 17-bit high-precision analog-to-digital conversion through the butterfly shuffling, bit exchange, and residual amplification technologies in the first stage, as well as the bridged DAC design in the second stage, while effectively overcoming the limitations of traditional digital background correction in input signal dependence and convergence speed.

Images