Digital-to-analog converter circuit and digital-to-analog converter calibration method

Abstract

The present disclosure provides a digital-to-analog converter circuit and a digital-to-analog converter calibration method, and relates to the technical field of circuits. The circuit comprises a reference voltage source, a resistance network, a resistance calibration circuit and a convergence node. The reference voltage source is configured to provide a reference voltage. The resistance network comprises a plurality of resistance branches, each of which is connected to the reference voltage source. The resistance calibration circuit is configured to calibrate the equivalent resistance of at least part of the resistance branches, so that the equivalent resistances of the resistance branches maintain a matching relationship. The convergence node is configured to converge the output signals of the resistance branches in the resistance network to generate an analog signal. The present disclosure inserts an additional resistance calibration circuit in the digital-to-analog converter circuit, so that the equivalent resistance of the resistance branches in the resistance network can be adjusted, thereby alleviating the problem of resistance mismatch in the digital-to-analog converter to some extent and improving the accuracy of the digital-to-analog converter.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of circuit, and in particular, to a digital-to-analog converter circuit and a digital-to-analog converter calibration method. BACKGROUND

[0002] In a resistor-type digital-to-analog converter, due to manufacturing tolerances and other factors, there will be a deviation between the actual value and the ideal value of the resistor in the digital-to-analog converter. This will cause resistance mismatch, resulting in a significant decrease in the accuracy of the digital-to-analog converter. SUMMARY

[0003] To overcome the problems in the related art, the present disclosure provides a digital-to-analog converter circuit and a digital-to-analog converter calibration method.

[0004] According to a first aspect of an embodiment of the present disclosure, a digital-to-analog converter circuit is provided, comprising:

[0005] a reference voltage source configured to provide a reference voltage;

[0006] a resistor network comprising a plurality of resistor branches, each resistor branch being connected to the reference voltage source;

[0007] a resistor calibration circuit configured to calibrate the equivalent resistance of at least part of the resistor branches so as to maintain a matching relationship between the equivalent resistances of the resistor branches; the resistor calibration circuit comprises a switch array, by adjusting the on-off state of the switch components in the switch array, the equivalent resistance of the resistor calibration circuit is changed;

[0008] a convergence node configured to converge the output signals of the resistor branches in the resistor network to generate an analog signal.

[0009] In some embodiments, the number of resistor calibration circuits is the same as the number of resistor branches to be calibrated in the plurality of resistor branches, and each resistor calibration circuit is connected in series with a corresponding resistor branch to be calibrated.

[0010] In some embodiments, the switch array comprises:

[0011] a plurality of resistor compensation units, each resistor compensation unit comprising at least two switch components connected in parallel to each other, and at least one switch component in each resistor compensation unit is in a closed state.

[0012] In some embodiments, the plurality of resistor compensation units in each resistor calibration circuit are connected in series with each other.

[0013] In some embodiments, the on-resistance of each switch component in the same resistor compensation unit is the same.

[0014] In some embodiments, the on-resistance of each switch component in different resistor compensation units is different.

[0015] In some embodiments, the ratio between the on-resistance of each switch component in different resistance compensation units is 2 0 :2 1 :2 2 :…:2 n-1 wherein n is the number of resistance compensation units.

[0016] In some embodiments, the equivalent resistance of the resistance calibration circuit is negatively related to the number of switch components in the closed state in the switch array.

[0017] In some embodiments, the reference voltage source comprises: a first reference voltage source for providing a high-level reference voltage, and a second reference voltage source for providing a low-level reference voltage.

[0018] Each resistance branch is configured to be selectively connected to the first reference voltage source or the second reference voltage source.

[0019] According to a second aspect of the embodiments of the present disclosure, a digital-to-analog converter calibration method is provided, applied to the digital-to-analog converter circuit as described in the first aspect, comprising:

[0020] Collecting the real output voltage of each to-be-calibrated branch in the resistance network;

[0021] For any to-be-calibrated branch, if the error between the real output voltage and the ideal output voltage of the to-be-calibrated branch is greater than a preset error, adjusting the on-off relationship of at least part of the switch components in the resistance calibration circuit connected in series with the to-be-calibrated branch to reduce the error.

[0022] The technical solutions provided by the embodiments of the present disclosure can have the following beneficial effects:

[0023] The digital-to-analog converter circuit provided by the embodiments of the present disclosure comprises: a reference voltage source, a resistance network, a resistance calibration circuit, and a convergence node. The reference voltage source is configured to provide a reference voltage. The resistance network comprises a plurality of resistance branches, each of which is connected to the reference voltage source. The resistance calibration circuit is configured to calibrate the equivalent resistance of at least part of the resistance branches, so that the equivalent resistances of the resistance branches maintain a matching relationship. The convergence node is configured to converge the output signals of the resistance branches in the resistance network to generate an analog signal. By inserting an additional resistance calibration circuit in the digital-to-analog converter circuit, the equivalent resistance of the resistance branches in the resistance network can be adjusted, thereby alleviating the problem of resistance mismatch in the digital-to-analog converter to some extent, and improving the accuracy of the digital-to-analog converter. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1An architecture schematic diagram of a digital-to-analog converter circuit in an embodiment of the present disclosure is shown.

[0025] Figure 2 A structure schematic diagram of a resistance calibration circuit in an embodiment of the present disclosure is shown.

[0026] Figure 3 A digital-to-analog converter schematic diagram based on a binary weighted network structure in an embodiment of the present disclosure is shown.

[0027] Figure 4 A digital-to-analog converter schematic diagram based on an R-2R ladder network structure in an embodiment of the present disclosure is shown.

[0028] Figure 5 A resistance calibration process schematic diagram of an MSB branch in an embodiment of the present disclosure is shown.

[0029] Figure 6 A flow schematic diagram of a digital-to-analog converter calibration method in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0030] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to various alternative embodiments as well. It is to be understood that other equipment and processes can be utilized, and that conceptual aspects of the exemplary embodiments are used herein for purposes of explanation only and are not intended to be limiting. Other embodiments are within the scope of the following claims.

[0031] The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the present disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0032] In addition, the terms "first", "second", and the like, are used herein only to describe different instances, and do not imply relative importance.

[0033] In a resistance type digital-to-analog converter (DAC), resistance mismatch is a common problem. A resistance type DAC converts a digital signal to an analog signal through a precisely set resistance network, in which the value of each resistance in the resistance network needs to be strictly matched (i.e., maintain a certain proportional relationship) with other resistances to ensure that the output analog signal can accurately reflect the input digital signal.

[0034] Resistance mismatch refers to a large deviation between the actual value and the ideal value of each resistance in a resistance array. In a resistance type DAC, ideally, each resistance in the resistance array should have the same resistance value or be arranged in a certain ratio, but due to manufacturing tolerances or other factors, the resistance value of the actual resistance may be different, which leads to resistance mismatch.

[0035] Therefore, the present disclosure provides a digital-to-analog converter circuit, which can compensate for mismatched resistances by setting an additional resistance calibration circuit.

[0036] The present example embodiment will be described in detail below with reference to the accompanying drawings and examples.

[0037] First, refer to Figure 1 , Figure 1 FIG. 1 shows an architecture schematic diagram of a digital-to-analog converter circuit in the present disclosure.

[0038] As Figure 1 shown, the digital-to-analog converter circuit provided by the present disclosure includes a reference voltage source 100, a resistance network 200, a resistance calibration circuit 300, and a convergence node 400.

[0039] The resistance network 200 includes a plurality of resistance branches 210, and each resistance branch 210 is connected to the reference voltage source 100.

[0040] The resistance calibration circuit 300 is configured to calibrate the equivalent resistance of at least part of the resistance branches 210, so as to maintain a matching relationship between the equivalent resistances of the resistance branches 210.

[0041] The convergence node 400 is configured to converge the output signals of the resistance branches 210 in the resistance network 200 to generate an analog signal.

[0042] In some embodiments, the reference voltage source 100 includes a first reference voltage source and a second reference voltage source. The first reference voltage source is configured to provide a high-level reference voltage, and the second reference voltage source is configured to provide a low-level reference voltage.

[0043] Each resistance branch 210 is configured to selectively connect to the first reference voltage source or the second reference voltage source.

[0044] Specifically, each resistance branch 210 can selectively connect to the first reference voltage source or the second reference voltage source according to the bit of the binary digital signal corresponding thereto.

[0045] For example, in the case that the received digital signal is "0100", the resistor branch 210 corresponding to the first bit (from left to right) "0" in the digital signal can be connected to the second reference voltage source, the resistor branch 210 corresponding to the second bit "1" in the digital signal can be connected to the first reference voltage source, the resistor branch 210 corresponding to the third bit "0" in the digital signal can be connected to the second reference voltage source, and the resistor branch 210 corresponding to the fourth bit "0" in the digital signal can be connected to the second reference voltage source.

[0046] That is, in the case that the bit corresponding to the resistor branch 210 is "1", the resistor branch 210 can be connected to the first reference voltage source. In the case that the bit corresponding to the resistor branch 210 is "0", the resistor branch 210 can be connected to the second reference voltage source.

[0047] Based on this, each resistor branch 210 can convert each bit in the input multi-bit digital signal into a voltage or current with a corresponding binary weight ratio by selectively connecting to the first reference voltage source or the second reference voltage source, and aggregate the voltage or current at the aggregation node 400 into an analog signal corresponding to the input digital signal.

[0048] In some embodiments, the first reference voltage source and the second reference voltage source can be constant voltage sources, and the voltage output by the first reference voltage source can be greater than the voltage output by the second reference voltage source, so that the first reference voltage source can provide a high-level reference voltage and the second reference voltage source can provide a low-level reference voltage.

[0049] In some embodiments, the voltage output by the second reference voltage source can be 0V, in which case the second reference voltage source can be a ground. That is, in the case that the bit corresponding to the resistor branch 210 is "0", the resistor branch 210 can be grounded.

[0050] In some embodiments, the number of resistor branches 210 in the resistor network 200 is the same as the maximum number of bits of the digital signal that the digital-to-analog converter circuit can support. For example, in the case that the digital-to-analog converter can be used to convert a 12-bit digital signal, the number of resistor branches 210 in the resistor network 200 is 12.

[0051] In some embodiments, the number of resistor calibration circuits 300 is the same as the number of resistor branches 210 to be calibrated, and each resistor calibration circuit 300 is connected in series with a corresponding resistor branch to be calibrated, and is used to calibrate the equivalent resistance of the resistor branch to be calibrated connected in series therewith.

[0052] The to-be-calibrated branch can be all resistance branches 210 in the resistance network 200, or can be part of the resistance branches 210 in the resistance network 200. The resistance calibration circuit 300 can be connected in series to one end of the to-be-calibrated branch close to the reference voltage source 100, or can be connected in series to one end of the to-be-calibrated branch away from the reference voltage source 100, and the embodiments of the present disclosure do not make any limitation in this regard.

[0053] Exemplarily, the resistance calibration circuit 300 can generate equivalent resistances of different sizes, so as to compensate for the equivalent resistance of the to-be-calibrated branch to a certain extent in the case of resistance mismatch of the to-be-calibrated branch, and enable the equivalent resistance of the to-be-calibrated branch to maintain a matching relationship with the equivalent resistances of the other resistance branches 210.

[0054] The matching relationship between the equivalent resistances of the resistance branches 210 can be understood as that the equivalent resistances of the resistance branches 210 maintain a certain proportional relationship within an allowable error range.

[0055] Specifically, in the digital-to-analog converter circuit, according to different architecture designs, the equivalent resistances of the resistance branches 210 can be equal in an ideal state, or can be in a 1:2:4:8:…:2 n-1 relationship (wherein n is the maximum number of bits supported by the digital-to-analog converter). Influenced by factors such as resistance production process, temperature, aging degree, etc., the equivalent resistances of the resistance branches 210 are difficult to reach the ideal state. Therefore, under the premise of meeting the output accuracy of the digital-to-analog converter, the equivalent resistances of the resistance branches 210 can have a certain allowable error.

[0056] In some embodiments, the convergence node 400 is connected to one end of each resistance branch 210 away from the reference voltage source 100, and is configured to converge the voltages or currents output by each resistance branch 210 to generate an analog signal.

[0057] Therefore, the embodiments of the present disclosure set the resistance calibration circuit 300 in the digital-to-analog converter circuit.

[0058] Next, refer to Figure 2 , Figure 2 which shows a structure schematic diagram of a resistance calibration circuit 300 in the embodiments of the present disclosure.

[0059] As Figure 2 shown, the resistance calibration circuit 300 can include a switch array 310. By adjusting the on-off state of the switch components 312 in the switch array 310, the equivalent resistance of the resistance calibration circuit 300 can be changed.

[0060] Exemplarily, a plurality of resistances based on series and / or parallel relationship can be provided in the switch array 310 (not shown in the figure). By adjusting the on-off relationship of the switch components 312, the connection relationship between the resistances can be adjusted, so that the resistance calibration circuit 300 generates different sizes of equivalent resistances.

[0061] It can be understood that, since the switch component 312 itself can generate a certain size of resistance when turned on, and the on-resistance of the switch component 312 itself is controllable. Therefore, the switch components 312 can be directly arranged in series and / or parallel with each other to obtain the resistance calibration circuit 300 with adjustable equivalent resistance size.

[0062] Please continue to refer to Figure 2 In some embodiments, the switch array 310 can include a plurality of resistance compensation units 311. Each resistance compensation unit 311 includes at least two switch components 312 in parallel with each other, and at least one switch component 312 in each resistance compensation unit 311 is in a closed state.

[0063] As mentioned before, since the switch component 312 itself has an on-resistance, the resistance calibration circuit 300 can be formed by purely switch components 312 in the manner of the present embodiment. In this way, the use of resistance elements in the resistance calibration circuit 300 can be avoided, so as to reduce the cost and area of the circuit.

[0064] In some embodiments, the equivalent resistance of the resistance calibration circuit 300 is inversely related to the number of switch components 312 in the closed state in the switch array. Specifically, the switch components 312 inside each resistance compensation unit 311 are in parallel with each other, so that the equivalent resistance of each resistance compensation unit 311 can be adjusted by adjusting the on-off relationship of the switch components 312. That is, the equivalent resistance of each resistance compensation unit 311 is inversely related to the number of switch components 312 in the on state. The sum of the equivalent resistances provided by each resistance compensation unit 311 is the total resistance of the resistance calibration circuit 300.

[0065] In some embodiments, the on-resistances of the switch components 312 in the same resistance compensation unit 311 are the same. In this way, the equivalent resistance of the resistance compensation unit 311 can be inversely proportional to the on-resistance of a single switch component 312 in the resistance compensation unit 311. That is, the equivalent resistance of the resistance compensation unit 311 = the on-resistance of the single switch component 312 ÷ the number of switch components 312 in the on state. In this way, the equivalent resistance of the resistance compensation unit 311 can be determined conveniently.

[0066] For example, for a certain resistance compensation unit 311, the on-resistance of each switch component 312 can be set to 10Ω, and the switch components 312 are in parallel. When one switch component 312 is on, the equivalent resistance of the resistance compensation unit 311 is 10Ω; when two switch components 312 are on, the equivalent resistance of the resistance compensation unit 311 is 5Ω; when three switch components 312 are on, the equivalent resistance of the resistance compensation unit 311 is 3.3333Ω; and when four switch components 312 are on, the equivalent resistance of the resistance compensation unit 311 is 2.5Ω.

[0067] By connecting the resistance compensation units 311 in series and connecting the switch components 312 in parallel in the same resistance compensation unit 311, the resistance calibration circuit 300 can have more equivalent resistances with fewer switch components 312. Thus, the consumption of the switch components 312 is reduced, and the manufacturing cost and the area of the circuit are reduced. For example, assuming that there are four resistance compensation units 311, and each resistance compensation unit has two switch components 312 with the same on-resistance. At this time, by adjusting the on-off relationship of the switch components 312, sixteen equivalent resistances can be generated by eight switch components. If the eight switch components are connected in series in groups of four, only two equivalent resistances can be provided.

[0068] In some embodiments, the on-resistances of the switch components 312 in different resistance compensation units 311 are different. It can be understood that the resistance compensation units 311 are connected in series, and thus the equivalent resistance of the resistance calibration circuit 300 is the sum of the equivalent resistances of the resistance compensation units 311. By differentiating the on-resistances of the switch components 312 in different resistance compensation units 311, a larger adjustable range of equivalent resistances can be generated by the resistance calibration circuit 300 with fewer resistance compensation units 311.

[0069] In some embodiments, the ratio between the on-resistances of the switch components 312 in different resistance compensation units 311 is 2 0 :2 1 :2 2 :……:2 n-1 , where n is the number of resistance compensation units 311. For example, the on-resistance of the switch components 312 in the first resistance compensation unit 311 is R, the on-resistance of the switch components 312 in the second resistance compensation unit 311 is 2R, the on-resistance of the switch components 312 in the third resistance compensation unit 311 is 4R, and the on-resistance of the switch components 312 in the fourth resistance compensation unit 311 is 8R, i.e., the ratio between them is 2 0 :2 1 :22 :2 3 .

[0070] By setting the on-resistance ratio in a binary relationship, the range of equivalent resistances that the resistance calibration circuit 300 can generate can be maximized.

[0071] It should be noted that the on-resistance of the switch component 312 in the resistance compensation unit 311 mentioned here refers to the on-resistance of one switch component 312 in the resistance compensation unit 311, rather than the on-resistance of all switch components 312 in parallel in the resistance compensation unit 311. By designing the on-resistance of the switch component 312 in each resistance compensation unit 311 in this way, the number of switch components 312 in the same resistance compensation unit 311 can be simplified, and the error range that the resistance calibration circuit 300 can calibrate can be larger.

[0072] In some embodiments, the number of resistance compensation units 311 can be four. Among them, the first resistance compensation unit includes two switch components with an on-resistance of 2.4Ω; the second resistance compensation unit includes two switch components with an on-resistance of 4.8Ω; the third resistance compensation unit includes two switch components with an on-resistance of 9.6Ω; and the fourth resistance compensation unit includes two switch components with an on-resistance of 19.2Ω.

[0073] In this way, the resistance calibration circuit 300 can be used to calibrate the common resistance mismatch in the digital-to-analog converter, and the area and cost of the resistance calibration circuit 300 can be minimized.

[0074] It can be understood that the switch component 312 in the present disclosure can be realized by using the on-off characteristics of MOS tubes, transistors, etc. Further, taking MOS as an example, by changing the channel length, oxide layer thickness and other parameters of the MOS tube, the on-resistance of the MOS tube can be controlled, thereby obtaining the resistance calibration circuit 300 described in the above embodiments.

[0075] In addition, it should be understood that the embodiments of the present disclosure aim to adjust the equivalent resistance of the resistance calibration circuit in the mismatch state to some extent to alleviate the resistance adaptation problem, so that the output accuracy of the digital-to-analog converter reaches the usable range, rather than making the mismatched resistance branches completely matched.

[0076] Figure 3 A schematic diagram of a digital-to-analog converter based on a binary weighted network structure in an embodiment of the present disclosure is shown, which is based on Figure 1 The digital-to-analog converter architecture shown and Figure 2 The resistance calibration circuit 300 implementation shown, the repeated parts will not be repeated.

[0077] like Figure 3 As shown, in a digital-to-analog converter based on a binary weighted network structure, the equivalent resistance of each resistor branch 210 is negatively correlated with the binary weight of the digital signal bit corresponding to each resistor branch 210.

[0078] For example, in Figure 3 In the four resistor branches 210 shown, the ideal ratio of the resistors in each resistor branch 210 from left to right is 1:2:4:8, that is, 2 0 :2 1 :2 2 :2 3 The scaling factor 1 corresponds to the most significant bit (MSB) of the digital signal, and the equivalent resistance in each resistor branch 210 needs to satisfy this scaling relationship as much as possible.

[0079] Please continue to refer to Figure 3 The resistor branch 210 corresponding to the MSB includes a fixed resistor 501, and a resistor calibration circuit 300 is connected in series below the fixed resistor 501. Therefore, when the fixed resistor 501 in the resistor branch 210 is mismatched, the resistance value of the fixed resistor 501 in the resistor branch 210 can be compensated by the equivalent resistance generated by the resistor calibration circuit 300.

[0080] It is understandable that, since the resistance calibration circuit 300 connected in series with the fixed resistor 501 has a certain resistance in any state, when designing the resistance value of the fixed resistor 501 connected in series with the resistance calibration circuit 300, the resistance of the resistance calibration circuit 300 in its default state should be subtracted. For example, if the ideal resistance in a certain resistance branch 210 is R, and the resistance of the resistance calibration circuit 300 in its default state is R', then the fixed resistor 501 in that resistance branch 210 should be R-R'. With this setting, compensation can be made in the event of resistance mismatch in that resistance branch 210 by adjusting the resistance provided by the resistance calibration circuit 300 within a certain range.

[0081] although Figure 3 Not shown in the image, but can be added according to actual needs. Figure 3 A series resistor calibration circuit 300 is connected above or below the fixed resistor 501 in any resistor branch 210.

[0082] Figure 4 A schematic diagram of a digital-to-analog converter based on an R-2R ladder network structure is shown in an embodiment of this disclosure. This digital-to-analog converter is based on... Figure 1 The digital-to-analog converter architecture shown and Figure 2 The resistor calibration circuit 300 shown is implemented; repeated details will not be repeated.

[0083] As Figure 4 shown in the digital-to-analog converter based on the R-2R ladder network structure, each resistance branch 210 includes a first resistance 601 and a second resistance 602. The first resistance 601 is used to connect the reference voltage source 100 with the output node, and the second resistance 602 is used to connect the output nodes of two adjacent resistance branches 210. At this time, the matching relationship between the resistance branches 210 is that the resistance value of the first resistance 601 in the same resistance branch 210 is twice that of the second resistance 602, the resistance value of the first resistance 601 in different resistance branches 210 is the same, and the resistance value of the second resistance 602 is the same.

[0084] Please continue to refer to Figure 4 , the first resistance 601 in the first resistance branch 210 from right to left is connected in series with a resistance calibration circuit 300 below it. Thus, when the first resistance 601 in the resistance branch 210 is mismatched, the resistance value of the first resistance 601 in the resistance branch 210 can be compensated by the equivalent resistance generated by the resistance calibration circuit 300.

[0085] It can be understood that since the resistance calibration circuit 300 connected in series with the first resistance 601 has a certain resistance in any state, when designing the resistance value of the first resistance 601 connected in series with the resistance calibration circuit 300, the resistance of the resistance calibration circuit 300 in the default state should be subtracted, and the embodiments of the present disclosure do not repeat it.

[0086] Although Figure 4 is not shown, according to actual needs, the resistance calibration circuit 300 can be connected in series above or below the first resistance 601 in any resistance branch 210 in Figure 4 .

[0087] Next, please refer to Figure 5 , Figure 5 The resistance branch corresponding to the MSB in the digital-to-analog converter shown in Figure 4 will be taken as an example to illustrate the calibration effect of the resistance calibration circuit 300 on the equivalent resistance of the resistance branch in the present disclosure.

[0088] As Figure 5 shown, the resistance branch corresponding to the MSB is connected in series with a resistance calibration circuit 300 below it, and the resistance calibration circuit 300 includes four resistance compensation units connected in series, and each resistance compensation unit is composed of two switch components with the same on-resistance. The on-resistance of the switch components in the four resistance compensation units is 2.4Ω, 4.8Ω, 9.6Ω and 19.2Ω, respectively.

[0089] In other words, the first resistance compensation unit is obtained by connecting two switching components with a conduction resistance of 2.4Ω in parallel, the second resistance compensation unit is obtained by connecting two switching components with a conduction resistance of 4.8Ω in parallel, and so on. This disclosure will not elaborate on this.

[0090] In each of the above resistance compensation units, one switching component is in a default on state to enable the resistance branch to conduct with the reference voltage source. For example, both switching components with an on-resistance of 19.2Ω can be in a default on state, allowing the resistance calibration circuit 300 to flexibly compensate the resistance branch by adjusting to produce either a larger or smaller equivalent resistance.

[0091] Ideally, in Figure 5 The circuit branch shown contains two first resistors (R) 1a1 R 1a2 The sum of the resistance values ​​of the two resistors should be equal to the sum of the resistance values ​​of the second resistor (R). 2a Twice that of R. After introducing the resistor calibration circuit 300, since the resistor calibration circuit 300 can generate an equivalent resistance of 26.4Ω by default to compensate R. 1a1 and R 1a2 Therefore, R in the resistor branch 2a With a current of 10kΩ, R can be made 1a1 The design value is 10 kΩ, and R 1a2 The design value is 9.9736kΩ.

[0092] Assuming that due to process deviations, the actual R... 1a2 This is a 0.1% reduction from the design value, which is 9.9636kΩ. In this state, any switching component in the resistor calibration circuit 300 with a conduction resistance of 19.2Ω can be turned off, causing the equivalent resistance generated by the resistor calibration circuit 300 to reach 36Ω. This allows the resistor calibration circuit 300 to interact with R... 1a1 and R 1a2 The sum of the resistance values ​​is 19.9996kΩ, with an error of only 0.004% compared to the ideal value of 10kΩ, thus meeting the accuracy requirements of the digital-to-analog converter.

[0093] Similarly, if the produced resistor unit has a resistance value 0.1% higher than the preset value, all switching components in the resistance calibration circuit 300 can be turned on, thereby reducing the equivalent resistance of the resistance calibration circuit 300 and making the resistance calibration circuit 300 and R... 1a1 and R 1a2 The sum of their resistance values ​​is 10.0012kΩ, which also meets the accuracy requirements of the digital-to-analog converter.

[0094] Based on the same inventive concept, the disclosure also provides a digital-to-analog converter calibration method, which is applied to a digital-to-analog conversion circuit with the architecture as shown in Figure 1

[0095] Specifically, Figure 6 A flowchart of a digital-to-analog converter calibration method in the embodiments of the disclosure is shown in FIG. 6, and the method provided in the embodiments of the disclosure includes the following steps. Figure 6

[0096] S601, collecting real output voltages of each to-be-calibrated branch in the resistance network.

[0097] S602, for any to-be-calibrated branch, if the error between the real output voltage and the ideal output voltage of the to-be-calibrated branch is greater than a preset error, adjusting the on-off relationship of at least part of the switch components in the resistance calibration circuit connected in series with the to-be-calibrated branch to reduce the error.

[0098] In some embodiments, the switch components in the resistance calibration circuit can have a preset on-off relationship. For example, the resistance calibration circuit can be made to correspond to the median of the equivalent resistances that can be generated by adjusting the on-off relationship of the switch components under the preset on-off relationship of the switches, so that the resistance calibration circuit can compensate for both the resistance mismatch caused by a large resistance and the resistance mismatch caused by a small resistance.

[0099] The embodiments of the disclosure are described in detail above in combination with the drawings, but the disclosure is not limited to the specific details in the above embodiments. Within the technical concept range of the disclosure, various simple modifications can be made to the technical solutions of the disclosure, and these simple modifications all belong to the protection range of the disclosure.

[0100] In addition, any combination of various different embodiments of the disclosure can also be made as long as it does not deviate from the idea of the disclosure, and it should also be considered as the disclosed content of the disclosure.​​

Claims

1. A digital-to-analog converter circuit, characterized by The application relates to a digital-to-analog converter circuit, comprising: a reference voltage source for providing a reference voltage; a resistance network comprising a plurality of resistance branches, each of which is connected to the reference voltage source; a resistance calibration circuit for calibrating the equivalent resistance of at least part of the resistance branches so as to maintain a matching relationship between the equivalent resistances of the respective resistance branches; the resistance calibration circuit comprises a switch array, and the equivalent resistance of the resistance calibration circuit is changed by adjusting the on-off state of the switch components in the switch array; a convergence node for converging the output signals of the respective resistance branches in the resistance network to generate an analog signal; The switch array comprises: a plurality of resistance compensation units connected in series, each resistance compensation unit comprising at least two switch assemblies connected in parallel, and at least one switch assembly in each resistance compensation unit being in a closed state; the on-resistance of each switch assembly in different resistance compensation units is different; the ratio between the on-resistances of each switch assembly in different resistance compensation units is 2 0 :2 1 :2 2 :……:2 n-1 , and n is the number of resistance compensation units.

2. The digital-to-analog converter circuit of claim 1, wherein, the number of the resistance calibration circuits is the same as the number of the resistance branches to be calibrated, and each resistance calibration circuit is connected in series with a corresponding resistance branch to be calibrated.

3. The digital-to-analog converter circuit of claim 1, wherein, The on-resistance of each switch component in the same resistance compensation unit is the same.

4. The digital-to-analog converter circuit of any one of claims 1 to 3, wherein, The equivalent resistance of the resistance calibration circuit is negatively related to the number of the switch components in the closed state in the switch array.

5. The digital-to-analog converter circuit of claim 1, wherein, The reference voltage source comprises a first reference voltage source for providing a high-level reference voltage and a second reference voltage source for providing a low-level reference voltage; each resistance branch is configured to be selectively connected to the first reference voltage source or the second reference voltage source.

6. A method of calibrating a digital-to-analog converter, the method comprising: The application is applied to the digital-to-analog converter circuit as claimed in any one of claims 1 to 5, comprising: collecting the real output voltage of each resistance branch to be calibrated in the resistance network; for any resistance branch to be calibrated, if the error between the real output voltage of the resistance branch to be calibrated and the ideal output voltage is greater than a preset error, the on-off relationship of at least part of the switch components in the resistance calibration circuit connected in series with the resistance branch to be calibrated is adjusted to reduce the error.

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