Analog-to-digital conversion circuit and analog-to-digital conversion method

Abstract

An analog-to-digital conversion circuit and an analog-to-digital conversion method are used for converting an input voltage into a digital code, and the circuit comprises a trigger controller, a comparison circuit, a successive approximation controller and an initial voltage search controller. The trigger controller sequentially enables the first enable signal and the second enable signal. The comparison circuit selects a successive approximation code or a search code to generate a conversion voltage, and compares the conversion voltage with an input voltage to generate a comparison result. The successive approximation controller updates the successive approximation code based on the enabled first enable signal and the comparison result. The initial voltage search controller sets the initial value based on the digital code, and updates the search code based on the enabled second enable signal and the comparison result.

Description

Technical Field

[0001] The present invention relates to an analog-to-digital conversion circuit and an analog-to-digital conversion method, and particularly to an analog-to-digital conversion circuit and an analog-to-digital conversion method that combine a successive approximation process and an initial voltage scanning process. Background Art

[0002] Non-rechargeable button batteries (CR2025) are widely used in computers, and most computers have a detection circuit for detecting the voltage of the button battery to know whether the button battery still has power. Since the button battery is a non-rechargeable battery and the button battery can be regarded as a large capacitor with the characteristic of maintaining voltage, the battery voltage may remain unchanged or even rise slightly, or may gradually decrease as the usage time lengthens. Therefore, an efficient analog-to-digital conversion circuit and an analog-to-digital conversion method are needed to more efficiently detect the voltage of the button battery. Summary of the Invention

[0003] In view of this, the present invention provides an analog-to-digital conversion circuit for converting an input voltage into a digital code, including a trigger controller, a comparison circuit, a successive approximation controller, an initial voltage search controller, and an end controller. The trigger controller enables a first enable signal and a second enable signal in sequence. The comparison circuit selects a successive approximation code or a search code to generate a conversion voltage, and compares the conversion voltage with the input voltage to generate a comparison result. The successive approximation controller updates the successive approximation code based on the enabled first enable signal and the comparison result, wherein when the comparison result changes, the successive approximation controller enables a first termination signal. The initial voltage search controller sets an initial value based on the digital code, and updates a search code based on the enabled second enable signal and the comparison result, wherein when the comparison result changes, the initial voltage search controller enables the second termination signal. The end controller sets the successive approximation code as the digital code based on the enabled first termination signal, and sets the search code as the digital code based on the enabled second termination signal.

[0004] The present invention further provides an analog-to-digital conversion method for converting an input voltage into a digital code. The analog-to-digital conversion method includes: performing a successive approximation process to obtain a successive approximation code corresponding to the input voltage; setting the successive approximation code corresponding to the input voltage as the digital code; setting an initial value based on the digital code; using the initial value to perform an initial voltage search process to obtain a search code corresponding to the input voltage; and setting the search code corresponding to the input voltage as the digital code. Brief Description of the Drawings

[0005] Figure 1 Block diagram showing an analog-to-digital conversion circuit according to an embodiment of the present invention;

[0006] Figure 2 Block diagram showing a starting voltage search controller according to an embodiment of the present invention;

[0007] Figure 3 Flowchart showing an analog-to-digital conversion method according to an embodiment of the present invention;

[0008] Figure 4 Flowchart showing an initial voltage search program according to an embodiment of the present invention.

[0009] Symbol Explanation

[0010] 100: Analog-to-digital conversion circuit

[0011] 110: Trigger controller

[0012] 120: Successive approximation controller

[0013] 130: Comparison circuit

[0014] 140: End controller

[0015] 150: Starting voltage search controller

[0016] 151: Counter

[0017] 152: Setting circuit

[0018] 153: Scan register

[0019] 154: First judgment circuit

[0020] 155: Boundary judgment circuit

[0021] 160: Limiting circuit

[0022] 171: First register

[0023] 172: Second register

[0024] 173: Third register

[0025] 174: Fourth register

[0026] VIN: Input voltage

[0027] DC[n-1:0]: Digital code

[0028] CEN: External enable signal

[0029] SEN#: Setting signal

[0030] SAR: Successive approximation value

[0031] EN1: First enable signal

[0032] EN2: Second enable signal

[0033] LG: Logic signal

[0034] SD[n-1:0]: Successive approximation code

[0035] ID[n-1:0]: Search code

[0036] VTC: Conversion voltage

[0037] CM: Comparison result

[0038] E1[n-1:0]: First termination code

[0039] E2[n-1:0]: Second termination code

[0040] EOC1: First termination signal

[0041] EOC2: Second termination signal

[0042] MUX: Multiplexer

[0043] ADC: Digital-to-analog converter

[0044] CMP1: First comparator

[0045] CMP2: Second comparator

[0046] CTC[n-1:0]: Conversion code

[0047] CNT: Count value

[0048] VREF: Reference voltage

[0049] RST1: First reset signal

[0050] RST2: Second reset signal

[0051] GOR: OR gate

[0052] L: Limit value

[0053] n: Number of bits

[0054] F: Setting value

[0055] SL: Limit signal

[0056] SW: Write signal

[0057] BOD: Boundary determination signal

[0058] SCAN_UP: Scanning signal

[0059] S301~S312, S401~S412: Step flow Detailed implementation manners

[0060] The following description is of an embodiment of the present invention. Its purpose is to illustrate the general principles of the present invention by way of example and should not be regarded as a limitation of the present invention. The scope of the present invention shall be defined by the scope of the claims.

[0061] It should be noted that the following disclosed content may provide multiple embodiments or examples for practicing different features of the present invention. The specific device examples and arrangements described below are only used to briefly elaborate the spirit of the present invention and are not used to limit the scope of the present invention.

[0062] It can be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various devices, components, regions, layers, and / or parts, these devices, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different devices, components, regions, layers, and / or parts. Therefore, the first device, component, region, layer, and / or part discussed below may be referred to as the second device, component, region, layer, and / or part without departing from the guidance of some embodiments of the present invention.

[0063] In the drawings, similar devices and / or features may have the same device symbols. Various devices of the same type may be distinguished by adding letters or numbers after the device symbols to distinguish similar devices and / or similar features.

[0064] Figure 1 A block diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention is shown, where the analog-to-digital conversion circuit 100 is used to convert the input voltage VIN into a digital code DC[n - 1:0]. As Figure 1 shown, the analog-to-digital conversion circuit 100 includes a trigger controller 110, a successive approximation controller 120, a comparison circuit 130, an end controller 140, and a starting voltage search controller 150.

[0065] When the external enable signal CEN is enabled, the trigger controller 110 enables the first enable signal EN1 based on the set signal SEN# being in the disabled state or the successive approximation value SAR being in the enabled state. According to an embodiment of the present invention, the external enable signal CEN is provided by an external host. According Figure 1In an embodiment, when the setting signal SEN# is in the disabled state, the setting signal SEN# is at a high logic level; when the setting signal SEN# is in the enabled state, the setting signal SEN# is at a low logic level. According to Figure 1 In an embodiment, when the successive approximation value SAR is in the enabled state, the successive approximation value SAR is at a high logic level; when the successive approximation value SAR is in the disabled state, the successive approximation value SAR is at a low logic level. The logic levels of the setting signal SEN# and the successive approximation value SAR are Figure 1 illustrated and explained in the embodiment of, and are not limited thereto in any way. According to an embodiment of the present invention, the setting signal SEN# is set by the user.

[0066] As Figure 1 shown, the analog-to-digital conversion circuit 100 further includes an OR gate GOR for performing a logical OR operation on the setting signal SEN# and the successive approximation value SAR to generate a logic signal LG. When the logic signal LG is at a high logic level, it represents that the setting signal SEN# is in the disabled state (i.e., high logic level) or the successive approximation value SAR is in the enabled state (i.e., high logic level). In other words, the trigger controller 110 enables the first enable signal EN1 based on the logic signal LG being at a high logic level.

[0067] The successive approximation controller 120 executes a successive-approximation program based on the enabled first enable signal EN1 to generate a successive approximation code SD[n-1:0], where n is a positive integer. The comparison circuit 130 converts the successive approximation code SD[n-1:0] into a conversion voltage VTC and compares the conversion voltage VTC with the input voltage VIN to generate a comparison result CM. In the successive approximation program, the successive approximation controller 120 continuously updates the successive approximation code SD[n-1:0] based on the comparison result CM to generate a first termination code E1[n-1:0] corresponding to the input voltage VIN and enables the first termination signal EOC1.

[0068] In other words, when the successive approximation controller 120 executes the successive approximation program, each time only the number of bits of the successive approximation code SD[n-1:0] is adjusted by no more than 2 bits, and the next bit of the successive approximation code SD[n-1:0] is adjusted based on the comparison result CM. Therefore, when the successive approximation code SD[n-1:0] is n bits, the comparison circuit 130 must compare the voltage corresponding to the successive approximation code SD[n-1:0] with the input voltage VIN n times to obtain the successive approximation code SD[n-1:0] corresponding to the input voltage VIN. In addition, the successive approximation program can search for the digital code DC[n-1:0] corresponding to the input voltage VIN within the maximum range.

[0069] AsFigure 1 As shown, the analog-to-digital conversion circuit 100 further includes a first register 171 and a second register 172. The first register 171 is used to store the successive approximation value SAR, and the second register 172 is used to store the digital code DC[n-1:0].

[0070] As Figure 1 shown, the comparison circuit 130 includes a multiplexer MUX, a digital-to-analog converter ADC, and a first comparator CMP1. The multiplexer MUX selects one of the successive approximation code SD[n-1:0] and the search code ID[n-1:0] as the conversion code CTC[n-1:0] based on the logic signal LG. In other words, when the logic signal LG is at a high logic level, the successive approximation code SD[n-1:0] is selected as the conversion code CTC[n-1:0]; when the logic signal LG is at a low logic level, the search code ID[n-1:0] is selected as the conversion code CTC[n-1:0]. The digital-to-analog converter ADC converts the conversion code CTC[n-1:0] into a conversion voltage VTC based on the reference voltage VREF. The first comparator CMP1 compares the conversion voltage VTC and the input voltage VIN, and generates a comparison result CM.

[0071] According to an embodiment of the present invention, when the input voltage VIN is greater than the conversion voltage VTC, the comparison result CM is in a first state. According to another embodiment of the present invention, when the input voltage VIN is less than the conversion voltage VTC, the comparison result CM is in a second state. In Figure 1 the shown embodiment, the first state is a high logic level, and the second state is a low logic level. In other words, the successive approximation controller 120 knows the relationship between the voltage corresponding to the successive approximation code SD[n-1:0] and the input voltage VIN based on the state of the comparison result CM, and then adjusts the successive approximation code SD[n-1:0] to generate a first termination code E1[n-1:0].

[0072] According to an embodiment of the present invention, when the first enable signal EN1 is enabled and the comparison result CM is in the first state, the successive approximation controller 120 increases the successive approximation code SD[n-1:0], so that the conversion voltage VTC increases accordingly. According to another embodiment of the present invention, when the comparison result CM changes from the first state to the second state, the successive approximation controller 120 decreases the successive approximation code SD[n-1:0], so that the conversion voltage VTC decreases accordingly. When the successive approximation program executed by the successive approximation controller 120 ends, the successive approximation controller 120 stores the successive approximation code SD[n-1:0] as the first termination code E1[n-1:0], and the successive approximation controller 120 enables the first termination signal EOC1.

[0073] According to an embodiment of the present invention, when the first termination signal EOC1 is enabled, the end controller 140, based on the enabled set signal SEN# (i.e., low logic potential), uses the second reset signal RST2 to set the successive approximation register SAR to a disabled state (i.e., low logic potential). When the analog-to-digital conversion circuit 100 is enabled again by the external enable signal CEN, the trigger controller 110, based on the logic signal LG at low logic potential, disables the first enable signal EN1 and enables the second enable signal EN2.

[0074] The starting voltage search controller 150, based on the enabled second enable signal EN2, executes a starting voltage search program to set an initial value of the search code ID[n-1:0]. The multiplexer MUX of the comparison circuit 130, based on the logic signal LG at low logic potential, selects the search code ID[n-1:0] as the conversion code CTC[n-1:0], and the digital-to-analog converter ADC converts the conversion code CTC[n-1:0] into a conversion voltage VTC for comparison with the input voltage VIN, thereby generating a comparison result CM. The starting voltage search controller 150, based on the change of the comparison result CM, obtains the search code ID[n-1:0] corresponding to the input voltage VIN and sets it as the second termination code E2[n-1:0], and enables the second termination signal EOC2. The end controller 140, based on the enabled second termination signal EOC2, stores the second termination code E2[n-1:0] in the second register 172 as the digital code DC[n-1:0].

[0075] In addition, the starting voltage search controller 150 further counts a count value CNT for counting the number of times the starting voltage search controller 150 updates the search code ID[n-1:0]. As Figure 1 shown, the analog-to-digital conversion circuit 100 further includes a third register 173, where the third register 173 is used to store the count value CNT. According to an embodiment of the present invention, whenever the trigger controller 110 is enabled by the external enable signal CEN, the trigger controller 110 uses the first reset signal RST1 to zero the count value CNT stored in the third register 173.

[0076] As Figure 1As shown, the analog-to-digital conversion circuit 100 further includes a limiting circuit 160. The limiting circuit 160 includes a fourth register 174 and a second comparator CMP2. The fourth register 174 is used to store a limiting value L, where the limiting value L is the number of bits n of the digital code DC[n-1:0] minus a set value F. According to an embodiment of the present invention, the set value F can be set by the user. According to some embodiments of the present invention, the number of bits n of the digital code DC[n-1:0] is equal to the number of execution times required for the successive approximation controller 120 to generate a successive approximation code SD[n-1:0] corresponding to the input voltage VIN.

[0077] The second comparator CMP2 compares the count value CNT and the limiting value L, and generates a limiting signal SL. According to an embodiment of the present invention, when the count value CNT is less than the limiting value L, the second comparator CMP2 disables the limiting signal SL. According to another embodiment of the present invention, when the count value CNT is not less than the limiting value L, the second comparator CMP2 enables the limiting signal SL. When the limiting signal SL is enabled, the trigger controller 110 sets the successive approximation value SAR stored in the first register 171 to an enabled state (i.e., high logic potential) using the write signal SW, and based on the enabled successive approximation value SAR, disables the starting voltage search controller 150 and enables the successive approximation controller 120.

[0078] The successive approximation program executed by the successive approximation controller 120 can perform a wide range of comparisons on the input voltage VIN to obtain a digital code DC[n-1:0] corresponding to the input voltage VIN. The starting voltage search program executed by the starting voltage search controller 150 scans the input voltage VIN near the voltage corresponding to the digital code DC[n-1:0] based on the digital code DC[n-1:0] obtained by the previous successive approximation controller 120 as an initial value. When the input voltage VIN changes little, the starting voltage search program requires fewer times than the successive approximation program to obtain the digital code DC[n-1:0].

[0079] Therefore, the analog-to-digital conversion circuit 100 first executes the successive approximation program to find the digital code DC[n-1:0] corresponding to the input voltage VIN, and then uses the starting voltage search program and uses the previous digital code DC[n-1:0] as an initial value for a small range of scans, which helps to increase the efficiency of finding the digital code DC[n-1:0] corresponding to the input voltage VIN. In addition, when the number of execution times (i.e., the count value CNT) of the starting voltage search program is not less than the limiting value L, it means that the input voltage VIN has changed significantly, and the analog-to-digital conversion circuit 100 is forced to return to the successive approximation program to more efficiently scan the input voltage VIN over a wide range.

[0080] When the change in the input voltage VIN is large, causing the number of times the starting voltage search controller 150 updates the search code ID[n-1:0] to be not less than the limit value L, the trigger controller 110 re-uses the successive approximation controller 120 in order to perform a large-range scan of the input voltage VIN with fewer execution times. The detailed operation of the starting voltage search controller 150 will be described in detail below.

[0081] Figure 2 Shows a block diagram of a starting voltage search controller according to an embodiment of the present invention. As Figure 2 shown, the starting voltage search controller 150 includes a counter 151, a setting circuit 152, a scan register 153, a first judgment circuit 154, and a boundary judgment circuit 155.

[0082] The counter 151 counts a count value CNT based on the enabled second enable signal EN2 and the boundary judgment signal BOD, where the count value CNT is used to count the number of times the starting voltage search controller 150 is executed. The setting circuit 152 generates the search code ID[n-1:0] based on the second enable signal EN2 and the digital code DC[n-1:0]. According to some embodiments of the present invention, when the second enable signal EN2 is enabled, the setting circuit 152 determines whether the digital code DC[n-1:0] is zero.

[0083] According to an embodiment of the present invention, when the digital code DC[n-1:0] is zero, the setting circuit 152 sets the initial value of the search code ID[n-1:0] to 1, and the first judgment circuit 154 disables the second termination signal EOC2 when receiving the search code ID[n-1:0]. According to another embodiment of the present invention, when the digital code DC[n-1:0] is not zero, the setting circuit 152 sets the initial value of the search code ID[n-1:0] to the digital code DC[n-1:0], and when the first judgment circuit 154 receives the search code ID[n-1:0], the second termination signal EOC2 is disabled.

[0084] The scan register 153 latches the comparison result CM as the scan signal SCAN_UP based on the count value CNT. According to an embodiment of the present invention, when the count value CNT is 1, the scan register 153 latches the comparison result CM as the scan signal SCAN_UP. According to an embodiment of the present invention, when the latched comparison result CM is in the first state (i.e., the input voltage VIN is greater than the conversion voltage VTC), the scan signal SCAN_UP is in the increasing state. According to another embodiment of the present invention, when the latched comparison result CM is in the second state (i.e., the input voltage VIN is less than the conversion voltage VTC), the scan signal SCAN_UP is in the decreasing state.

[0085] The first determination circuit 154 updates the search code ID[n-1:0], enables the second termination signal EOC2, and outputs the search code ID[n-1:0] as the second termination code E2[n-1:0] based on the boundary determination signal BOD, the scan signal SCAN_UP, the comparison result CM, and the count value CNT. The boundary determination circuit 155 determines whether the search code ID[n-1:0] exceeds the boundary based on the count value CNT, and enables or disables the boundary determination signal BOD. According to an embodiment of the present invention, the count value CNT can be regarded as the clock signal of the starting voltage search controller 150, used to trigger the scan register 153, the first determination circuit 154, and the boundary determination circuit 155 to start operating. According to some embodiments of the present invention, the upper limit of the search code ID[n-1:0] is 2 n -1, and the lower limit of the search code ID[n-1:0] is 1.

[0086] According to an embodiment of the present invention, when the scan signal SCAN_UP is in the increasing state and the search code ID[n-1:0] reaches the upper limit (i.e., 2 n -1), the boundary determination circuit 155 determines that the search code ID[n-1:0] reaches the boundary and enables the boundary determination signal BOD. According to another embodiment of the present invention, when the scan signal SCAN_UP is in the decreasing state and the search code ID[n-1:0] reaches the lower limit (i.e., 1), the boundary determination circuit 155 determines that the search code ID[n-1:0] reaches the boundary and enables the boundary determination signal BOD.

[0087] According to an embodiment of the present invention, when the boundary determination signal BOD is enabled, the counter 151 stops counting the count value CNT. According to an embodiment of the present invention, when the boundary determination signal BOD is enabled and the scan signal SCAN_UP is in the increasing state, the first determination circuit 154 maintains the search code ID[n-1:0] (i.e., 2 n -1), enables the second termination signal EOC2, and outputs the search code ID[n-1:0] as the second termination code E2[n-1:0].

[0088] According to another embodiment of the present invention, when the boundary determination signal BOD is enabled and the scan signal SCAN_UP is in the decreasing state, the first determination circuit subtracts 1 from the search code ID[n-1:0] (i.e., 0), enables the second termination signal EOC2, and outputs the updated search code ID[n-1:0] as the second termination code E2[n-1:0]. Subsequently, Figure 1 the end controller 140 sets the second termination code E2[n-1:0] as the digital code DC[n-1:0] based on the enabled second termination signal EOC2.

[0089] When the boundary determination signal BOD is disabled, the counter 151 increments the count value CNT by 1 and the first determination circuit 154 updates the search code ID[n-1:0]. According to an embodiment of the present invention, when the boundary determination signal BOD is disabled and the scan signal SCAN_UP is in the increasing state, the first determination circuit 154 increments the search code ID[n-1:0] by 1. According to another embodiment of the present invention, when the boundary determination signal BOD is disabled and the scan signal SCAN_UP is in the decreasing state, the first determination circuit 154 decrements the search code ID[n-1:0] by 1.

[0090] When the boundary determination signal BOD is disabled and after the first determination circuit 154 updates the search code ID[n-1:0] (i.e., increments the search code ID[n-1:0] by 1 when the scan signal SCAN_UP is in the increasing state and decrements the search code ID[n-1:0] by 1 when the scan signal SCAN_UP is in the decreasing state), the first determination circuit 154 further determines the states of the scan signal SCAN_UP and the comparison result CM.

[0091] According to an embodiment of the present invention, when the scan signal SCAN_UP is in the increasing state and the comparison result CM is in the second state (i.e., the input voltage VIN is less than the conversion voltage VTC), the first determination circuit 154 decrements the search code ID[n-1:0] by 1, and the first determination circuit 154 further sets the updated search code ID[n-1:0] as the second termination code E2[n-1:0] and enables the second termination signal EOC2.

[0092] According to another embodiment of the present invention, when the scan signal SCAN_UP is in the decreasing state and the comparison result CM is in the first state (i.e., the input voltage VIN is greater than the conversion voltage VTC), the first determination circuit 154 maintains the search code ID[n-1:0], and the first determination circuit 154 sets the updated search code ID[n-1:0] as the second termination code E2[n-1:0] and enables the second termination signal EOC2.

[0093] Figure 3 Displays a flowchart of the analog-to-digital conversion method according to an embodiment of the present invention. The following description of the analog-to-digital conversion method 300 will be accompanied by Figure 1 the analog-to-digital conversion circuit 100 and Figure 2 the starting voltage search controller 150 for detailed explanation.

[0094] First, when the analog-to-digital conversion circuit 100 is enabled by an external enable signal CEN, the trigger controller 110 resets the count value CNT stored in the second register 172 (step S301), and determines whether the set signal SEN# is in a disabled state or whether the successive approximation value SAR is in an enabled state (step S302). In other words, Figure 1 the trigger controller 110 of Figure 1 determines whether the conditions of step S302 are met based on the state of the logic signal LG.

[0095] When it is determined to be yes in step S302 (i.e., the logic signal LG is at a high logic level), the trigger controller 110 enables the first enable signal EN1 (step S303), and the successive approximation controller 120 executes a successive approximation program (step S304) to update the successive approximation code SD[n - 1:0]. When the successive approximation controller 120 completes the successive approximation program, the successive approximation controller 120 sets the last successive approximation code SD[n - 1:0] as the first termination code E1[n - 1:0] (step S305).

[0096] According to an embodiment of the present invention, when the first enable signal EN1 is enabled and the comparison result CM is in the first state, the successive approximation controller 120 increases the successive approximation code SD[n - 1:0], so that the conversion voltage VTC increases accordingly. According to another embodiment of the present invention, when the comparison result CM changes from the first state to the second state, the successive approximation controller 120 decreases the successive approximation code SD[n - 1:0], so that the conversion voltage VTC decreases accordingly. When the successive approximation program executed by the successive approximation controller 120 ends, the successive approximation controller 120 stores the successive approximation code SD[n - 1:0] as the first termination code E1[n - 1:0], and the successive approximation controller 120 enables the first termination signal EOC1.

[0097] Next, the end controller 140 determines whether the set signal SEN# is in an enabled state (step S306). When it is determined that the set signal SEN# is in an enabled state, the end controller 140 uses the write signal SW to disable the successive approximation value SAR (step S307), and updates the digital code DC[n - 1:0] with the first termination code E1[n - 1:0] based on the enabled first termination signal EOC1 (step S308). Subsequently, the analog-to-digital conversion method 300 ends.

[0098] When the analog-to-digital conversion circuit 100 is enabled again by the external enable signal CEN, step S301 and step S302 are executed again. Since the successive approximation value SAR has been set to the disabled state (i.e., low logic potential), and the setting signal SEN# is in the enabled state (i.e., low logic potential), the judgment in step S302 is no, and then step S309 is executed. In step S309, the trigger controller 110 disables the first enable signal EN1 and disables the second enable signal EN2.

[0099] Figure 2 The setting circuit 152 based on the enabled second enable signal EN2 determines whether the digital code DC[n-1:0] is zero (step S310). When it is determined in step S310 that the digital code DC[n-1:0] is zero, the setting circuit 152 sets the initial value of the search code ID[n-1:0] to 1 (step S311), and executes the initial voltage search program (step S312). When it is determined in step S310 that the digital code DC[n-1:0] is not zero, the setting circuit 152 sets the initial value of the search code ID[n-1:0] to the digital code DC[n-1:0] (step S313), and then executes the initial voltage search program (step S312).

[0100] In step S312, the first judgment circuit 154 searches for the search code ID[n-1:0] corresponding to the input voltage VIN based on the initial value of the search code ID[n-1:0], and stores it as the second termination code E2[n-1:0]. After step S312, return to step S308, and the end controller 140 updates the second register 172 with the second termination code E2[n-1:0], and it becomes the digital code DC[n-1:0]. The operation flow of the detailed initial voltage search program will be described in detail below.

[0101] Figure 4 Displays a flowchart of the initial voltage search program according to an embodiment of the present invention. The following description of the initial voltage search program 400 will be accompanied by Figure 1 the analog-to-digital conversion circuit 100 and Figure 2 the starting voltage search controller 150 to illustrate in detail.

[0102] First, the counter 151 based on the enabled second enable signal EN2 sets the count value to 1 (step S401). The comparison circuit 130 compares the conversion voltage VTC generated by the search code ID[n-1:0] and the input voltage VIN, and generates a comparison result CM (step S402). Then, when the count value CNT is 1, the scan register 153 latches the comparison result CM as the scan signal SCAN_UP (step S403).

[0103] According to an embodiment of the present invention, when the input voltage VIN is greater than the conversion voltage VTC corresponding to the search code ID[n-1:0], the comparison result CM is in the first state. According to another embodiment of the present invention, when the input voltage VIN is less than the conversion voltage VTC corresponding to the search code ID[n-1:0], the comparison result CM is in the second state. According to an embodiment of the present invention, when the latched comparison result CM is in the first state, the scan signal SCAN_UP is in the increasing state. According to another embodiment of the present invention, when the latched comparison result CM is in the second state, the scan signal SCAN_UP is in the decreasing state.

[0104] Next, the boundary determination circuit 155 determines the states of the scan signal SCAN_UP and the search code ID[n-1:0], and generates a boundary determination signal BOD (step S404). In step S404, the boundary determination circuit 155 determines whether the scan signal SCAN_UP is in the increasing state and the search code ID[n-1:0] reaches the upper limit, or the scan signal SCAN_UP is in the decreasing state and the search code ID[n-1:0] reaches the lower limit. According to an embodiment of the present invention, the upper limit of the search code ID[n-1:0] is 2 n -1, and the lower limit of the search code ID[n-1:0] is 1.

[0105] When it is determined to be yes in step S404, the counter 151 stops counting the count value CNT, and the first determination circuit 154 updates the search code ID[n-1:0] to the search code ID[n-1:0] plus the scan signal SCAN_UP minus 1 (step S405). That is, ID[n-1:0] = ID[n-1:0] + SCAN_UP - 1. When the scan signal SCAN_UP is in the increasing state (i.e., high logic potential), the search code ID[n-1:0] remains unchanged. When the scan signal SCAN_UP is in the decreasing state (i.e., low logic potential), the first determination circuit 154 subtracts 1 from the search code ID[n-1:0] in step S404.

[0106] When the scan signal SCAN_UP is in the increasing state and the search code ID[n-1:0] reaches 2 n -1, it means that the actual input voltage VIN exceeds the upper limit of the search code ID[n-1:0], and the initial voltage scan program should be stopped and the upper limit of the search code ID[n-1:0] should be set to the second termination code E2[n-1:0]. When the scan signal SCAN_UP is in the decreasing state and the search code ID[n-1:0] reaches 1, it means that the search code ID[n-1:0] corresponding to the input voltage VIN should be zero, and there is no need to perform a comparison via the comparison circuit 130. Therefore, the second termination code E2[n-1:0] can be directly set to zero.

[0107] When the determination in step S404 is negative, the counter 151 increments the count value CNT by 1, and the first determination circuit 154 updates the search code ID[n-1:0] to the search code ID[n-1:0] plus twice the scan signal SCAN_UP minus 1 (step S407). That is, ID[n-1:0] = ID[n-1:0] + (2*SCAN_UP - 1). In other words, when the scan signal SCAN_UP is in the increasing state, the first determination circuit 154 increments the search code ID[n-1:0] by 1 in step S407. When the scan signal SCAN_UP is in the decreasing state, the first determination circuit 154 decrements the search code ID[n-1:0] by 1 in step S407.

[0108] Returning to step S405, the first determination circuit 154 then sets the updated search code ID[n-1:0] as the second termination code E2[n-1:0] (step S406), enables the second termination signal EOC2, and returns to step S308 to set the second termination code E2[n-1:0] as the digital code DC[n-1:0]. Returning to step S407, the comparison circuit 130 then converts the search code ID[n-1:0] updated in step S407 into a conversion voltage VTC, and compares the conversion voltage VTC and the input voltage VIN to generate a comparison result CM (step S408).

[0109] Subsequently, the first determination circuit 154 determines whether the scan signal SCAN_UP is in the increasing state and the comparison result CM is in the second state, or the scan signal SCAN_UP is in the decreasing state and the comparison result CM is in the first state (step S409). When the scan signal SCAN_UP is in the increasing state and the comparison result CM is in the second state (i.e., the input voltage VIN is less than the conversion voltage VTC), it means that the conversion voltage VTC corresponding to the search code ID[n-1:0] continues to increase and has exceeded the input voltage VIN. When the scan signal SCAN_UP is in the decreasing state and the comparison result CM is in the first state (i.e., the input voltage VIN is greater than the conversion voltage VTC), it means that the conversion voltage VTC corresponding to the search code ID[n-1:0] continues to decrease and is lower than the input voltage VIN.

[0110] When the determination in step S409 is YES, the first determination circuit 154 updates the search code ID[n-1:0] to the search code ID[n-1:0] minus the scan signal SCAN_UP (step S410). That is, ID[n-1:0] = ID[n-1:0] - SCAN_UP. When the scan signal SCAN_UP is in the increasing state (i.e., high logic potential), the first determination circuit 154 updates the search code ID[n-1:0] to the search code ID[n-1:0] minus 1. When the scan signal SCAN_UP is in the decreasing state (i.e., low logic potential), the first determination circuit 154 keeps the search code ID[n-1:0] unchanged. After step S410, steps S406 and step S308 are then executed, which will not be repeated here.

[0111] When the determination in step S409 is NO, Figure 1 the limiting circuit 160 of determines whether the count value CNT is less than the limit value L (step S411). When the determination in step S411 is YES, the process returns to step S404. When the determination in step S411 is NO, the trigger controller 110 uses the write signal SW to set the successive approximation value SAR stored in the first register 171 to the enabled state (i.e., high logic potential) (step S412), forcibly ends the initial voltage search program 400 and returns to step S302, enabling the successive approximation controller 120 to scan the digital code DC[n-1:0] corresponding to the input voltage VIN over a large range using the successive approximation program.

[0112] According to an embodiment of the present invention, when the determination in step S411 is NO, it means that the initial voltage search program 400 cannot obtain the digital code DC[n-1:0] corresponding to the input voltage VIN using fewer times than the successive approximation control program, and the number of times required for the initial voltage search program 400 to scan the input voltage VIN over a large range is much higher than that of the successive approximation program. Therefore, in step S412, the successive approximation value SAR is set to the enabled state, and the process returns to the successive approximation program to more efficiently obtain the digital code DC[n-1:0] corresponding to the input voltage VIN.

[0113] The present invention first performs a successive approximation procedure on the input voltage to perform an efficient full scan to obtain a digital code corresponding to the input voltage. During the next scan and when the input voltage does not change significantly, the initial voltage scan procedure combined with the previous digital code as the initial value can obtain the digital code corresponding to the input voltage more quickly. Even when the input voltage changes significantly and the number of executions required for the initial voltage scan procedure exceeds expectations, the analog-to-digital conversion circuit and the analog-to-digital conversion method proposed by the present invention can automatically switch to the successive approximation procedure to perform a more efficient large-range scan of the input voltage. Furthermore, the user can also set signals to set to use the successive approximation procedure combined with the initial voltage scan procedure, or only use the successive approximation procedure.

[0114] Although the embodiments of the present invention and their advantages have been disclosed above, it should be understood that any person skilled in the art can make changes, substitutions, and modifications without departing from the spirit and scope of the present invention. In addition, the protection scope of the present invention is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the processes, machines, manufactures, compositions of matter, devices, methods, and steps developed currently or in the future from the disclosure of some embodiments of the present invention. As long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of the present invention.

Claims

1. An analog-to-digital conversion circuit, characterized in that, For converting an input voltage into a digital code, comprising: A trigger controller that sequentially enables a first enable signal and a second enable signal; A comparison circuit that selects a successive approximation code or a search code to generate a conversion voltage, and compares the conversion voltage with the input voltage to generate a comparison result; A successive approximation controller that updates the successive approximation code based on the enabled first enable signal and the comparison result, wherein when the comparison result changes, the successive approximation controller enables a first termination signal; A starting voltage search controller that sets an initial value based on the digital code, and updates a search code based on the enabled second enable signal and the comparison result, wherein when the comparison result changes, the starting voltage search controller enables a second termination signal; and An end controller that sets the successive approximation code as the digital code based on the enabled first termination signal, and sets the search code as the digital code based on the enabled second termination signal.

2. The analog-to-digital conversion circuit according to claim 1, wherein When the successive approximation value is in an enabled state or the setting signal is in a disabled state, the trigger controller enables the first enable signal and disables the second enable signal; Wherein when the setting signal is in the enabled state and the successive approximation value is in the disabled state, the trigger controller enables the second enable signal and disables the first enable signal; Wherein the setting signal is set by the user.

3. The analog-to-digital conversion circuit according to claim 2, wherein The comparison circuit further comprises: A multiplexer that selects the successive approximation code or the search code as a conversion code; A digital-to-analog converter that converts the conversion code into the conversion voltage; and A comparator that compares the conversion voltage with the input voltage to generate the comparison result; Wherein when the setting signal is in the enabled state and the successive approximation value is in the disabled state, the multiplexer selects the search code as the conversion code; Wherein when the successive approximation value is in the enabled state or the setting signal is in the disabled state, the multiplexer selects the successive approximation code as the conversion code; Wherein when the input voltage is greater than the conversion voltage, the comparison result is in a first state; Wherein when the input voltage is less than the conversion voltage, the comparison result is in a second state.

4. The analog-to-digital conversion circuit according to claim 3, wherein When the first enable signal is enabled and the comparison result is in the first state, the successive approximation controller increases the successive approximation code, such that the conversion voltage increases accordingly; Wherein when the comparison result is in the second state, the successive approximation controller decreases the successive approximation code, such that the conversion voltage decreases accordingly; Wherein when a successive approximation program executed by the successive approximation controller is completed, the successive approximation controller stores the successive approximation code as a first termination code, and the successive approximation controller enables the first termination signal; The end controller stores the first termination code as the digital code based on the enabled first termination signal, and the end controller sets the successive approximation value to the disabled state in accordance with the set signal being in the enabled state.

5. The analog - to - digital conversion circuit according to claim 3, wherein, When the second enable signal is enabled, the starting voltage search controller determines whether the digital code is zero; When it is determined that the digital code is not zero, the starting voltage search controller uses the digital code as the initial value of the search code and disables the second termination signal; When it is determined that the digital code is zero, the starting voltage search controller sets the search code to 1 and disables the second termination signal.

6. The analog-to-digital conversion circuit according to claim 5, characterized in that, The starting voltage search controller further includes: A counter that counts a count value based on the enabled second enable signal and a boundary determination signal, where the count value is used to count the number of times the starting voltage search controller executes; A setting circuit that generates the initial value of the search code based on the digital code; A scan register that latches the comparison result as a scan signal when the count value is 1; A boundary determination circuit that determines whether the search code exceeds the boundary to enable or disable the boundary determination signal; and A first determination circuit that updates the search code, enables the second termination signal, and outputs the search code as a second termination code based on the boundary determination signal, the scan signal, and the comparison result; When the latched comparison result is the first state, the scan signal is in an increasing state; When the latched comparison result is the second state, the scan signal is in a decreasing state; When the scan signal is in the increasing state and the search code reaches the upper limit or the scan signal is in the decreasing state and the search code reaches the lower limit, the boundary determination circuit enables the boundary determination signal.

7. A method for analog-to-digital conversion, characterized in that, For converting an input voltage into a digital code, where the analog-to-digital conversion method includes: Performing a successive approximation procedure to obtain a successive approximation code corresponding to the input voltage; Setting the successive approximation code corresponding to the input voltage as the digital code; Setting an initial value based on the digital code; Using the initial value to execute a starting voltage search procedure to obtain a search code corresponding to the input voltage; and Setting the search code corresponding to the input voltage as the digital code.

8. The analog-to-digital conversion method according to claim 7, wherein, The step of setting the initial value based on the digital code includes: Determining whether the digital code is zero; When the digital code is zero, setting the initial value to 1; and When the digital code is not zero, setting the initial value to the digital code; Where the starting voltage search procedure includes: Setting a count value to 1; Comparing the voltage corresponding to the search code with the input voltage to generate a comparison result; and When the count value is 1, latching the comparison result as a scan signal.

9. The analog-to-digital conversion method according to claim 8, characterized in that When the above input voltage is greater than the voltage corresponding to the above search code, the above comparison result is a first state; Wherein when the above input voltage is less than the voltage corresponding to the above search code, the above comparison result is a second state; Wherein when the above comparison result of the latch is the above first state, the above scan signal is an increasing state; Wherein when the above comparison result of the latch is the above second state, the above scan signal is a decreasing state; Wherein the above starting voltage search program further includes: Judging the states of the above scan signal and the above search code; When the above scan signal is the above increasing state and the above search code reaches the upper limit or the above scan signal is the above decreasing state and the above search code reaches the lower limit, stop counting the above count value, and update the above search code based on the above scan signal; After the step of updating the above search code based on the above scan signal, set the updated above search code as a second termination code; and Set the above second termination code as the above digital code; Wherein when the above scan signal is the above increasing state, maintain the above search code; Wherein when the above scan signal is the above decreasing state, update the above search code to the above search code minus 1.

10. The analog-to-digital conversion method according to claim 9, wherein The above starting voltage search program further includes: When the above scan signal is the above increasing state and the above search code does not reach the upper limit or the above scan signal is the above decreasing state and the above search code does not reach the lower limit, add 1 to the above count value, and update the above search code based on the above scan signal; and Compare the voltage corresponding to the updated above search code and the above input voltage to generate the above comparison result; Wherein when the above scan signal is the above increasing state, update the above search code to the above search code plus 1; Wherein when the above scan signal is the above decreasing state, update the above search code to the above search code minus 1.

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