Embedded PCB and method of manufacturing the same

Abstract

The application relates to the technical field of printed embedded PCBs, and discloses an embedded PCB and a manufacturing method thereof. The embedded PCB comprises a sub-board, a first dielectric layer and a first circuit layer which are sequentially and laminatedly arranged along a first direction. A device is embedded in the inside of the sub-board, the device is located on the side of the sub-board close to the first dielectric layer, a first part is arranged on the side of the device close to the first dielectric layer, and a first protection part is arranged on the first part. A first connecting hole is arranged in the inside of the first dielectric layer, the inside of the first connecting hole is filled with a first conductive part, the first protection part is connected with the first conductive part and electrically conducts, and the first conductive part is connected with the first circuit layer and electrically conducts. The embedded PCB and the manufacturing method thereof provided by the application are used for improving the problem of poor hole filling in the process of electroplating hole filling in the related art.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit boards, and in particular to an embedded PCB and a manufacturing method thereof. Background Art

[0002] With the continuous development of the electronic communications and automotive electronics industries, they are becoming increasingly miniaturized and multifunctional, and the requirements for related PCB (Printed Circuit Board) products are also becoming increasingly higher. PCBs must not only meet the requirements of high-current working environments, have ultra-high voltage resistance and excellent CAF (Conductive Anodic Filament) resistance, but also need to achieve high-density interconnection and have excellent heat dissipation performance. Therefore, for PCBs that meet the above requirements, devices (such as chips or heat sinks) are embedded in the multi-layer PCB to achieve the relevant requirements. In order to ensure good heat dissipation performance, the dielectric layer close to the device must also reach a certain thickness.

[0003] In related technologies, in order to meet the requirements of high voltage resistance and excellent CAF resistance, the thickness of the dielectric layer close to the device must be increased, and then holes are drilled on this dielectric layer to the device, and then electroplating is performed to fill the holes to connect the device. However, the problem of poor hole filling may occur during the electroplating filling process. Summary of the Invention

[0004] The present application provides an embedded PCB and a manufacturing method thereof, which are used to improve the problem of poor hole filling during the electroplating hole filling process in the related art.

[0005] In a first aspect, an embodiment of the present application provides an embedded PCB, comprising a daughter board, a first dielectric layer, and a first circuit layer arranged sequentially and stacked along a first direction, wherein a device is embedded inside the daughter board, the device is located on a side of the daughter board close to the first dielectric layer, a first portion is provided on a side of the device close to the first dielectric layer, and a first protective portion is provided on the first portion; a first connection hole is provided inside the first dielectric layer, the first connection hole is filled with a first conductive portion, the first protective portion is connected to the first conductive portion and is electrically conductive, and the first conductive portion is connected to the first circuit layer and is electrically conductive.

[0006] In some embodiments, the embedded PCB further includes a second dielectric layer and a second circuit layer stacked together, the second dielectric layer being located between the first circuit layer and the second circuit layer, a second connection hole being provided inside the second dielectric layer, the second connection hole being filled with a second conductive portion, the first circuit layer being connected to and electrically conductive with the second conductive portion, and the second circuit layer being connected to and electrically conductive with the second conductive portion.

[0007] In some embodiments, a second portion is provided on a side of the device away from the first dielectric layer, and a second protective portion is provided on the second portion; the embedded PCB further includes a third dielectric layer and a third circuit layer stacked together, the third dielectric layer being located between the third circuit layer and the daughter board, a third connection hole being provided inside the third dielectric layer, the third connection hole being filled with a third conductive portion, the second protective portion being connected to and electrically conductive with the third conductive portion, and the third circuit layer being connected to and electrically conductive with the third conductive portion.

[0008] In some embodiments, the device includes a heat sink and a chip connected thereto, and the first portion is disposed on the chip; or the device includes a heat sink, and the first portion is disposed on the heat sink.

[0009] In some embodiments, the thickness of the first protection portion is 50 μm-300 μm.

[0010] In a second aspect, an embodiment of the present application provides a method for manufacturing an embedded PCB, comprising:

[0011] Place the device into the receiving groove of the daughter board, wherein a first portion is provided on one side of the device, a first protective portion is provided on the first portion, and the size of the receiving groove is larger than the size of the device;

[0012] A first dielectric layer and a first metal layer are stacked in sequence on the daughter board, the daughter board, the first dielectric layer and the first metal layer are arranged in sequence along a first direction, and the first portion is located on a side of the device close to the first dielectric layer;

[0013] Laminating the daughter board, the device, the first dielectric layer, and the first metal layer together, with a portion of the first dielectric layer filling a gap between an inner wall of the receiving groove and the device;

[0014] A first filling hole penetrating the first metal layer and a first connection hole penetrating the first dielectric layer are processed on a side of the first metal layer facing away from the first dielectric layer, the first connection hole and the first filling hole being coaxially arranged, and the first protective portion defining a bottom surface of the first connection hole;

[0015] The first conductive part is filled in the first connecting hole by copper electroplating, and the first filling part is filled in the first filling hole by copper electroplating. The first conductive part is connected to the first filling part and is electrically conductive. The first metal layer and the first filling part constitute a first circuit layer.

[0016] In some embodiments, after filling the first conductive portion in the first connection hole, the method for manufacturing the embedded PCB further includes:

[0017] stacking a second dielectric layer and a second metal layer in sequence on the first circuit layer, wherein the second dielectric layer is located between the first circuit layer and the second metal layer;

[0018] A second filling hole penetrating the second metal layer and a second connection hole penetrating the second dielectric layer are processed on a side of the second metal layer facing away from the second dielectric layer, the second connection hole and the second filling hole are coaxially arranged, and the first circuit layer defines a bottom surface of the second connection hole;

[0019] The second conductive part is filled in the second connecting hole by copper plating, and the second filling part is filled in the second filling hole by copper plating. The second conductive part is connected to the second filling part and is electrically conductive. The second metal layer and the second filling part constitute a second circuit layer.

[0020] In some embodiments, before processing the first filling hole penetrating the first metal layer and the first connection hole penetrating the first dielectric layer from the side of the first metal layer facing away from the first dielectric layer, the thickness H0 of the first protective portion and the thickness H1 of the first dielectric layer are obtained, and the difference between H1 and H0 is H; the aperture of the first connection hole is D, and D is greater than 1.25*H.

[0021] In some embodiments, the first portion is a solder pad; before placing the device into the receiving groove of the daughter board, the first protection portion is formed on the first portion by electroplating or welding;

[0022] Alternatively, the device includes a heat sink, one side of which includes a first molded portion and a second molded portion; before placing the device into the receiving groove of the sub-board, part of the second molded portion is removed so that the first molded portion protrudes from the remaining second molded portion, and the second molded portion includes the first portion and the first protective portion.

[0023] In some embodiments, the sub-board includes a first core board, a connecting dielectric layer and a second core board that are stacked together, the first core board is provided with a first window, the connecting dielectric layer is provided with a connecting window, and the second core board is provided with a second window, the first window, the connecting window and the second window are connected and define the accommodating groove; when the sub-board, the device, the first dielectric layer and the first metal layer are pressed together, part of the connecting dielectric layer fills the gap between the inner wall of the accommodating groove and the device.

[0024] The embedded PCB provided in the embodiment of the present application has the following beneficial effects: since a device is embedded inside the daughterboard, the device is located on the side of the daughterboard close to the first dielectric layer, a first part is provided on the side of the device close to the first dielectric layer, a first protective part is provided on the first part, and a first connecting hole is provided inside the first dielectric layer, the first connecting hole is filled with a first conductive part, the first protective part is connected to the first conductive part and is electrically conductive, and the first conductive part is connected to the first circuit layer and is electrically conductive, so the first part can be electrically conductive to the first circuit layer through the first protective part and the first conductive part, thereby avoiding the occurrence of depressions at the corresponding position of the first circuit layer when the first conductive part is filled in the first connecting hole by copper plating during the manufacturing process of the circuit board, thereby avoiding the problem of poor hole filling during the electroplating hole filling process.

[0025] The beneficial effects of the method for manufacturing the embedded PCB provided in the present application compared to the prior art can be referred to the description of the beneficial effects of the embedded PCB provided in the present application compared to the prior art, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 It is a schematic diagram of the structure of an embedded PCB in the prior art;

[0028] Figure 2 This is a flow chart of a method for manufacturing an embedded PCB in one embodiment of the present application;

[0029] Figure 3 This is a schematic structural diagram of a daughter board, a device, a first dielectric layer, and a first circuit layer in one embodiment of the present application;

[0030] Figure 4 is Figure 3 A schematic diagram showing a first conductive portion being filled in a first connection hole and a first filling portion being filled in a first filling hole;

[0031] Figure 5 This is a schematic diagram of the structure of an embedded PCB in one embodiment of the present application;

[0032] Figure 6 This is a schematic structural diagram of an embedded PCB in another embodiment of the present application;

[0033] Figure 7This is a schematic structural diagram of an embedded PCB in another embodiment of the present application;

[0034] Figure 8 This is a schematic structural diagram of an embedded PCB in yet another embodiment of the present application.

[0035] The meanings of the marks in the figure are:

[0036] 1. Embedded PCB; 2. Device; 3. Blind via; 4. Recess; 5. Dielectric layer;

[0037] 10. Daughter board; 11. First core board; 12. Connecting dielectric layer; 13. Second core board;

[0038] 20. First dielectric layer; 21. First connection hole; 201. First conductive portion;

[0039] 30, first circuit layer; 300, first metal layer; 31, first filling hole; 301, first filling portion;

[0040] 40. Device; 41. Heat sink; 42. Chip; 401. First portion; 402. First protection portion; 403. Second portion; 404. Second protection portion;

[0041] 50, second dielectric layer; 501, second conductive portion;

[0042] 60. Second circuit layer; 601. Second filling portion;

[0043] 70. The third dielectric layer;

[0044] 80. The third circuit layer;

[0045] 90. Fourth dielectric layer;

[0046] 100. The fourth circuit layer. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0048] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0050] References to "one embodiment," "some embodiments," or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present invention. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0051] In order to illustrate the technical solution of the present application, the following description is given with reference to specific drawings and embodiments.

[0052] With the continuous development of the electronic communications and automotive electronics industries, they are becoming increasingly miniaturized and multifunctional, placing increasing demands on related PCB products. PCBs must not only meet the requirements of high-current working environments, possess ultra-high voltage resistance and excellent CAF resistance, but also achieve high-density interconnection and excellent heat dissipation performance. Therefore, for PCBs that meet these requirements, devices (such as chips or heat sinks) are embedded within the multi-layer PCB to achieve the relevant requirements. To ensure good heat dissipation performance, the dielectric layer close to the device must also reach a certain thickness.

[0053] Please refer to Figure 1 In the related art, in order to meet the requirements of high voltage resistance and excellent CAF resistance, the thickness of the dielectric layer 5 close to the device 2 must be increased, and then a hole is drilled on this dielectric layer 5 to the device 2, and then electroplating is performed to fill the hole to connect the device 2.

[0054] On the one hand, when the thickness of the dielectric layer 5 reaches a certain value, the electroplating and filling process becomes more difficult, and the normal electroplating and filling process cannot meet the required quality. Because the aspect ratio (depth to diameter ratio) of the blind via 3 exceeds the process capacity of the via-filling electroplating line, the electroplating and filling process may cause core wrapping, resulting in the embedded PCB 1 failing to meet the product's current-carrying requirements. Furthermore, the hole mouth depression 4 after electroplating and filling is too deep, and the corresponding pad flatness does not meet the requirements, affecting subsequent soldering. This deep depression 4 also reduces the embedded PCB 1's heat dissipation performance. Furthermore, for embedded PCBs 1 with multi-level HDI (High Density Interconnector) stacked via designs, the hole mouth depression 4 after electroplating and filling is too deep to meet the requirements of the inter-layer stacked via design, thus presenting design limitations.

[0055] At the same time, when the thickness of the dielectric layer 5 reaches a certain value, in order to avoid the blind hole 3 being electroplated and the recess 4 corresponding to the blind hole 3 being too deep, multiple hole filling electroplating processes are generally required to barely meet the requirements. This results in low production efficiency, long production cycle, and high production cost, which affects the factory's production capacity and is not suitable for mass production.

[0056] In summary, in the existing method for manufacturing the embedded PCB 1, the problem of poor hole filling may occur during the electroplating hole filling process.

[0057] On the other hand, since the device 2 needs a certain space to be placed before being embedded, the overall shape of the device 2 is usually smaller than the shape of the receiving groove of the core board of the embedded PCB 1. During pressing, the gap between the inner wall of the receiving groove and the device 2 requires a certain dielectric layer 5 to be filled with glue, which will cause the dielectric layer 5 in the area where the device 2 is embedded to partially flow into the gap between the inner wall of the receiving groove and the device 2 after pressing, resulting in a certain concave in this area.

[0058] If the device 2 includes a chip, the chip pad thickness is usually less than 15μm (nickel-gold layer or nickel-copper layer, the copper layer is generally 8μm-10μm, the total thickness of the nickel-gold layer generally does not exceed 5μm, and the total thickness of the nickel-copper layer generally does not exceed 15μm). The pad is thin, and the laser drilling energy corresponding to the ultra-thick dielectric layer 5 is relatively large. Since there is a certain concave in the embedded area after pressing, the drilling depth of the blind hole 3 is difficult to control. It is easy for the chip pad to be penetrated due to excessive laser energy during drilling, and the chip is damaged after breakdown, resulting in scrap.

[0059] At the same time, to meet the requirements of high-voltage resistance and excellent CAF resistance, the thickness of the dielectric layer 5 between the chip and the circuit layer must be increased. When the thickness of the dielectric layer 5 reaches a certain value, the processing difficulty of the blind vias 3 for interlayer conduction increases. Moreover, when the embedded area between the circuit layer and the chip is insufficiently filled with glue, resulting in a concave area, the embedded area corresponding to the circuit layer becomes uneven, and the area corresponding to the blind vias 3 is also uneven. When drilling the hole above the blind via 3, the concave embedded area causes an uneven board surface, making it difficult to control the laser drilling energy, resulting in residual glue at the bottom of the hole. After electroplating, this residual glue will delaminate between the plated layer and the low-copper layer, affecting product reliability.

[0060] In summary, in the existing method for manufacturing the embedded PCB 1 , the depth of the hole is not easy to control during the drilling process, and the pad of the device 2 may be easily penetrated due to excessive laser energy during drilling, causing the device 2 to be scrapped.

[0061] In view of this, an embodiment of the present application provides an embedded PCB and a manufacturing method thereof. Since a device is embedded inside the sub-board, the device is located on the side of the sub-board close to the first dielectric layer, a first part is provided on the side of the device close to the first dielectric layer, a first protective part is provided on the first part, and a first connecting hole is provided inside the first dielectric layer. The first connecting hole is filled with a first conductive part, the first protective part is connected to the first conductive part and is electrically conductive, and the first conductive part is connected to the first circuit layer and is electrically conductive, so the first part can be electrically conductive to the first circuit layer through the first protective part and the first conductive part, so that in the process of manufacturing the circuit board, when the first conductive part is filled in the first connecting hole by using copper plating, the corresponding position of the first circuit layer is avoided from being recessed, thereby avoiding the problem of poor hole filling during the electroplating hole filling process.

[0062] Please refer to Figures 2 to 5 An embodiment of the present application provides an embedded PCB, comprising a daughterboard 10, a first dielectric layer 20, and a first circuit layer 30 arranged sequentially and stacked along a first direction. A device 40 is embedded in the daughterboard 10. The device 40 is located on a side of the daughterboard 10 close to the first dielectric layer 20. A first portion 401 is provided on the side of the device 40 close to the first dielectric layer 20, and a first protective portion 402 is provided on the first portion 401.

[0063] The first dielectric layer 20 can be made of materials such as PP (prepreg), and the first circuit layer 30 can be made of materials such as copper, silver, or aluminum. Device 40 can include a chip 42 and / or a heat sink 41, and one or more components can be provided. First portion 401 can be a part of device 40. First protective portion 402 can be made of materials such as copper, silver, or aluminum. First protective portion 402 and first portion 401 can be integrally formed or separate components, and one or more components can be provided.

[0064] A first connection hole 21 is provided inside the first dielectric layer 20 , and the first connection hole 21 is filled with the first conductive portion 201 . The first protection portion 402 is connected to the first conductive portion 201 and is electrically conductive. The first conductive portion 201 is also connected to the first circuit layer 30 and is electrically conductive.

[0065] The material of the first conductive portion 201 can be copper, silver, aluminum, etc. For example, the material of the first conductive portion 201, the first protection portion 402 and the first circuit layer 30 are all copper.

[0066] The method for manufacturing the embedded PCB provided in the above embodiment includes:

[0067] S100 : placing the device 40 into the receiving groove of the daughter board 10 . A first portion 401 is provided on one side of the device 40 . A first protection portion 402 is provided on the first portion 401 . The size of the receiving groove is larger than that of the device 40 .

[0068] S200 : stacking the first dielectric layer 20 and the first metal layer 300 on the daughter board 10 in sequence. The daughter board 10 , the first dielectric layer 20 and the first metal layer 300 are arranged in sequence along a first direction. The first portion 401 is located on a side of the device 40 close to the first dielectric layer 20 .

[0069] Specifically, the daughter board 10 , the first dielectric layer 20 and the first metal layer 300 may be riveted together.

[0070] S300 : Pressing the daughter board 10 , the device 40 , the first dielectric layer 20 and the first metal layer 300 together, with a portion of the first dielectric layer 20 filling the gap between the inner wall of the receiving groove and the device 40 .

[0071] Specifically, due to the presence of the first protection portion 402, the embedded areas of the first dielectric layer 20 and the first metal layer 300 corresponding to the device 40 will not be concave due to the gap between the inner wall of the accommodating groove and the device 40 filled by part of the first dielectric layer 20, and the overall board surface is flat.

[0072] S400: A first filling hole 31 penetrating the first metal layer 300 and a first connection hole 21 penetrating the first dielectric layer 20 are processed on a side of the first metal layer 300 facing away from the first dielectric layer 20. The first connection hole 21 and the first filling hole 31 are coaxially arranged, and the first protective portion 402 defines the bottom surface of the first connection hole 21.

[0073] Specifically, the first filling hole 31 penetrating the first metal layer 300 and the first connecting hole 21 penetrating the first dielectric layer 20 can be machined from the side of the first metal layer 300 facing away from the first dielectric layer 20 by mechanical drilling and / or laser burning.

[0074] It is understood that due to the presence of the first protective portion 402, the embedded areas of the first dielectric layer 20 and the first metal layer 300 corresponding to the device 40 will not be recessed due to the gap between the inner wall of the accommodating groove filled by a portion of the first dielectric layer 20 and the device 40. Therefore, when the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 are machined from the side of the first metal layer 300 facing away from the first dielectric layer 20, the depth of the first filling hole 31 and the first connection hole 21 can be precisely controlled without damaging the first portion 401. When drilling, it is only necessary to sample and measure the thickness of the first dielectric layer 20 in the drilling area of ​​the same batch of products. There is no need to measure each product individually before drilling. There is also no need to set different drilling depths to prevent drilling quality issues due to uneven board surface caused by recessing.

[0075] For example, when the thickness of the first dielectric layer 20 is relatively large, a high-energy laser is required to process the first filling hole 31 and the first connecting hole 21. Since the first portion 401 of the device 40 (the solder pad of the chip 42) corresponds to a position where the first protective portion 402 is added instead of the original first portion 401 (with a thickness of 15 μm), the corresponding thickness becomes 115 μm-315 μm. Even if the laser energy is too high and drills into part of the first protective portion 402, the solder pad of the chip 42 will not be punctured, thereby causing the chip 42 to be scrapped. The laser energy can be increased to ensure that the first dielectric layer 20 at the bottom of the first connecting hole 21 is completely removed.

[0076] S500: Use copper plating to fill the first conductive part 201 in the first connection hole 21, and use copper plating to fill the first filling part 301 in the first filling hole 31. The first conductive part 201 is connected to the first filling part 301 and is electrically conductive. The first metal layer 300 and the first filling part 301 constitute the first circuit layer 30.

[0077] It can be understood that even if the thickness of the first dielectric layer 20 is relatively thick, the presence of the first protective portion 402 is equivalent to reducing the distance between the first portion 401 and the first circuit layer 30, thereby reducing the thickness of the first dielectric layer 20 at the corresponding position, and reducing the aspect ratio of the blind hole composed of the first connection hole 21 and the first filling hole 31. Therefore, when the first conductive portion 201 is filled in the first connection hole 21 by using copper plating, and the first filling portion 301 is filled in the first filling hole 31 by using copper plating, the first filling portion 301 will not be recessed. In other words, when the first conductive portion 201 is filled in the first connection hole 21 by using copper plating, the corresponding position of the first circuit layer 30 will not be recessed, thereby avoiding the problem of insufficient plating capacity during electroplating due to excessive aspect ratio during the electroplating filling process, thereby causing poor hole filling.

[0078] As can be seen from the above, the embedded PCB and its manufacturing method provided in the embodiment of the present application are as follows: since the device 40 is embedded in the interior of the daughterboard 10, the device 40 is located on the side of the daughterboard 10 close to the first dielectric layer 20, a first portion 401 is provided on the side of the device 40 close to the first dielectric layer 20, and a first protective portion 402 is provided on the first portion 401. The interior of the first dielectric layer 20 is provided with a first connection hole 21, and the interior of the first connection hole 21 is filled with the first conductive portion 201. The first protective portion 402 is connected to the first conductive portion 201 and is electrically conductive, and the first conductive portion 201 is connected to the first circuit layer 30 and is electrically conductive. Therefore, the first portion 401 can be electrically conductive to the first circuit layer 30 through the first protective portion 402 and the first conductive portion 201. Therefore, during the process of manufacturing the circuit board, it is possible to avoid the occurrence of a depression at the corresponding position of the first circuit layer 30 when the first conductive portion 201 is filled in the first connection hole 21 by using copper plating, thereby avoiding the problem of poor hole filling during the electroplating hole filling process.

[0079] The embedded PCB and its manufacturing method provided in the embodiments of the present application can solve the problem of a recessed embedded area due to insufficient glue filling when pressing the daughterboard 10, the device 40, the first dielectric layer 20, and the first metal layer 300 together. It can also solve the problem of poor hole filling during the electroplating filling process of ultra-thick dielectric layers. It can also avoid the problem of the embedded PCB being scrapped due to the breakdown of the first portion 401 when the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 are processed on the side of the first metal layer 300 facing away from the first dielectric layer 20. It can also solve the problem of ineffective hole stacking due to a recessed bottom of the first connection hole 21 or residual glue during HDI build-up.

[0080] The embedded PCB provided in the embodiment of the present application may be an embedded PCB product having an ultra-thick dielectric layer embedded with a device 40 .

[0081] Optionally, after the first conductive part 201 is filled in the first connection hole 21 by copper plating, and the first filling part 301 is filled in the first filling hole 31 by copper plating, the first circuit is made on the first circuit layer 30 by laminating, exposing, developing and etching.

[0082] In this embodiment, the device 40 includes a heat sink 41 and a chip 42 connected to each other, and the first portion 401 is disposed on the chip 42 .

[0083] By adopting the above solution, damage to the first portion 401 can be avoided when the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 are machined from the side of the first metal layer 300 facing away from the first dielectric layer 20 .

[0084] It can be understood that the first portion 401 can be a pad.

[0085] Before the device 40 is placed in the receiving groove of the daughter board 10 , the first protection portion 402 is manufactured on the first portion 401 by electroplating or welding.

[0086] With such an arrangement, the first protection portion 402 can be manufactured more conveniently.

[0087] It should be noted that the device 40 includes a heat sink 41 . When the heat sink 41 is made of ceramic, the first protection portion 402 is manufactured on the first portion 401 by electroplating or welding.

[0088] Optionally, the thickness of the first protection portion 402 is 50 μm-300 μm, such as 50 μm, 70 μm, 100 μm, 150 μm, 200 μm, 250 μm or 300 μm.

[0089] Such a configuration can avoid the problem of poor hole filling during the electroplating hole filling process, and can avoid damage to the first part 401 when the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 are processed from the side of the first metal layer 300 away from the first dielectric layer 20.

[0090] In this embodiment, the embedded PCB further includes a second dielectric layer 50 and a second circuit layer 60 that are stacked. The second dielectric layer 50 is located between the first circuit layer 30 and the second circuit layer 60. A second connection hole is provided inside the second dielectric layer 50. The interior of the second connection hole is filled with a second conductive portion 501. The first circuit layer 30 is connected to the second conductive portion 501 and is electrically conductive. The second circuit layer 60 is connected to the second conductive portion 501 and is electrically conductive.

[0091] The second dielectric layer 50 may be made of PP, the second circuit layer 60 may be made of copper, silver, or aluminum, etc. The second conductive portion 501 may be made of copper, silver, or aluminum, etc. For example, the second conductive portion 501 and the second circuit layer 60 may both be made of copper.

[0092] In the manufacturing method provided in the above embodiment, after the first conductive portion 201 is filled in the first connection hole 21, the manufacturing method of the embedded PCB further includes:

[0093] First, the second dielectric layer 50 and the second metal layer are sequentially stacked on the first circuit layer 30 , with the second dielectric layer 50 being located between the first circuit layer 30 and the second metal layer.

[0094] Secondly, a second filling hole penetrating the second metal layer and a second connection hole penetrating the second dielectric layer 50 are processed from the side of the second metal layer away from the second dielectric layer 50. The second connection hole and the second filling hole are coaxially arranged, and the first circuit layer 30 defines the bottom surface of the second connection hole.

[0095] It can be understood that the addition of the first protective portion 402 avoids the problem of concavity caused by poor filling of the first dielectric layer 20. The entire surface of the embedded PCB is flat, and the thickness of the second dielectric layer 50 is consistent, eliminating the difficulty in controlling the drilling depth due to concavity in the embedded area. Furthermore, the addition of the first protective portion 402 solves the problem of concavity in the first filling portion 301 after copper plating. As a result, the first filling portion 301 remains flat, and the problem of conductivity failure between the first circuit layer 30 and the second circuit layer 60 caused by the concavity of the first filling portion 301 is eliminated.

[0096] Then, the second conductive part 501 is filled in the second connection hole by copper electroplating, and the second filling part 601 is filled in the second filling hole by copper electroplating. The second conductive part 501 is connected to the second filling part 601 and is electrically conductive. The second metal layer and the second filling part 601 constitute the second circuit layer 60.

[0097] By adopting the above solution, the problem of poor hole filling during the electroplating hole filling process can be avoided, and a multi-layer embedded PCB can be manufactured.

[0098] It should be noted that if the first protective portion 402 is not provided, when the first filling portion 301 is sunken, when the second dielectric layer 50 and the second metal layer (build-up layer) are sequentially stacked on the first circuit layer 30, the connection of the second circuit layer 60 will not be effectively connected to the first circuit layer 30 due to the sunken and suspended hole of the first filling portion 301. In addition, the embedded area itself is sunken. When the second circuit layer 60 is overall uneven during build-up, when the second filling hole penetrating the second metal layer and the second connection hole penetrating the second dielectric layer 50 are machined on the side of the second metal layer away from the second dielectric layer 50, it will be difficult to control the drilling depth.

[0099] The reason is that conventional drilling will use a sample measurement of the dielectric layer thickness after the same batch of boards are pressed to determine the blind hole drilling depth. The embedded product has a concave area due to the glue filling problem in the embedded area, which in turn causes the dielectric layer thickness in this area to be inconsistent with other non-embedded areas. The dielectric layer thickness in the concave area cannot be determined to be consistent because the concave area cannot completely contact the pressed cover plate. During pressing, the area is under virtual pressure, and the glue in the concave area will flow randomly, resulting in uneven glue flow in this area, thereby increasing the possibility of inconsistent dielectric layer thickness in this area. Before drilling, the dielectric layer thickness of each board cannot be obtained by sampling and measuring the entire batch of boards. The thickness of the embedded area of ​​each board needs to be measured separately to set the drilling depth. If different thicknesses appear in the blind hole processing position of the embedded area of ​​a single batch of boards, the drilling parameters need to be adjusted multiple times, thereby reducing the efficiency of blind hole processing.

[0100] The recessed embedded area makes it difficult to control the drilling depth. A too large depth will cause the laser energy to excessively drill through the first filling portion 301 , while a too small depth will cause excessive adhesive residue at the bottom of the second connection hole, resulting in connection failure after electroplating.

[0101] The present application adds a first protection portion 402 to the embedded device 40 so that after pressing, the embedded area will not be sunken due to insufficient glue filling, which is beneficial for blind hole processing and electroplating filling, and a semi-buried embedded PCB can be obtained.

[0102] Optionally, after the second conductive part 501 is filled in the second connection hole by copper plating and the second filling part 601 is filled in the second filling hole by copper plating, the second circuit is made on the second circuit layer 60 by laminating, exposing, developing and etching.

[0103] Before processing the first filling hole 31 penetrating the first metal layer 300 and the first connection hole 21 penetrating the first dielectric layer 20 from the side of the first metal layer 300 facing away from the first dielectric layer 20, the thickness H0 of the first protective portion 402 and the thickness H1 of the first dielectric layer 20 are obtained, and the difference between H1 and H0 is H; the aperture of the first connection hole 21 is D, and D is greater than 1.25*H.

[0104] By adopting the above solution, it is possible to avoid the problem that the aspect ratio of the blind hole composed of the first connecting hole 21 and the first filling hole 31 is too large, which leads to insufficient electroplating depth during filling and further causes the first filling part 301 at the hole mouth to be concave after filling.

[0105] For example, the thickness H1 of the first dielectric layer 20 is 300 μm, the thickness H0 of the first protective portion 402 is 180 μm, and the difference H between H1 and H0 is 300 μm-180 μm=120 μm. When the aperture D of the first connection hole 21 is 150 μm, the aspect ratio of the blind hole is 120:150=0.8:1. If the first protective portion 402 is not provided, the aspect ratio of the blind hole is 300:150=2:1. Due to the excessive aspect ratio, the electroplating depth capability during hole filling is insufficient, resulting in a hole mouth depression after hole filling.

[0106] It should be noted that the aperture D of the first connection hole 21 can be substantially equal to the aperture of the first filling hole 31, and the aperture of the blind hole formed by the first connection hole 21 and the first filling hole 31 can be equal to the aperture D of the first connection hole 21. The thickness H1 of the first dielectric layer 20 and the aperture of the blind hole are not limited to the ranges listed in this solution and can be adjusted according to product design, while also adjusting the thickness H0 of the first protective portion 402.

[0107] In this embodiment, the sub-board 10 includes a first core board 11, a connecting dielectric layer 12 and a second core board 13 which are stacked together. The first core board 11 is provided with a first window, the connecting dielectric layer 12 is provided with a connecting window, and the second core board 13 is provided with a second window. The first window, the connecting window and the second window are connected and define a receiving groove. When the sub-board 10, the device 40, the first dielectric layer 20 and the first metal layer 300 are pressed together, part of the connecting dielectric layer 12 fills the gap between the inner wall of the receiving groove and the device 40.

[0108] By adopting the above solution, the device 40 can be tightly fixed in the receiving groove, and the first dielectric layer 20 and the first circuit layer 30 corresponding to the device 40 can be prevented from being recessed by the first protection portion 402 .

[0109] Among them, the first core board 11, the connecting medium layer 12 and the second core board 13 can be opened according to the size of the panel, and the first window, the connecting window and the second window can be processed on the first core board 11, the connecting medium layer 12 and the second core board 13 respectively. The size of the first window, the size of the connecting window and the size of the second window are all 0.1 mm larger than the size of the device 40.

[0110] Please refer to Figure 6In another embodiment, a second portion 403 is provided on a side of the device 40 away from the first dielectric layer 20, and a second protective portion 404 is provided on the second portion 403; the embedded PCB further includes a third dielectric layer 70 and a third circuit layer 80 stacked together, the third dielectric layer 70 being located between the third circuit layer 80 and the daughter board 10, a third connection hole being provided inside the third dielectric layer 70, and a third conductive portion being filled inside the third connection hole, the second protective portion 404 being connected to and electrically conductive with the third conductive portion, and the third circuit layer 80 being connected to and electrically conductive with the third conductive portion.

[0111] By adopting the above solution, the problem of poor hole filling during the electroplating hole filling process can be avoided, and the device 40 can be completely embedded in the embedded PCB to produce an embedded PCB with a fully embedded structure.

[0112] Optionally, after the third circuit is made on the third circuit layer 80, a fourth dielectric layer 90 and a fourth circuit layer 100 may be set on the side of the third circuit layer 80 away from the third dielectric layer 70, and a fourth circuit may be made on the fourth circuit layer 100. Then, the processes of AOI (Automated Optical Inspection), solder mask / character, molding (molding is completed by conventional means, dividing the large panel into multiple unit boards), quality inspection / packaging and shipment are completed in sequence.

[0113] Please refer to Figure 7 In another embodiment, the device 40 includes a heat sink 41 , and the first portion 401 is disposed on the heat sink 41 . The first portion 401 is one portion of the device 40 .

[0114] By adopting the above solution, the problem of poor hole filling during the electroplating hole filling process can be avoided, and the heat sink 41 can be embedded inside the embedded PCB to produce an embedded PCB with a semi-buried structure.

[0115] In which, the device 40 includes a heat sink 41, and one side of the heat sink 41 includes a first molded part and a second molded part; before placing the device 40 into the accommodating groove of the sub-board 10, part of the second molded part is removed so that the first molded part protrudes from the remaining second molded part, and the second molded part includes a first part 401 and a first protective part 402.

[0116] By adopting the above solution, the first portion 401 and the first protection portion 402 can be manufactured more conveniently.

[0117] For example, a portion of the second molded portion can be removed by etching or depth control. The heat sink 41 can be made of copper or aluminum.

[0118] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for manufacturing an embedded PCB, characterized in that: include: A device is placed into a receiving groove of a daughterboard, wherein a first portion is provided on one side of the device, the first portion being a solder pad, and a first protective portion is provided on the first portion, and the size of the receiving groove is larger than the size of the device, wherein the first protective portion is formed on the first portion by electroplating or welding before the device is placed into the receiving groove of the daughterboard; or the device includes a heat sink, and one side of the heat sink includes a first molded portion and a second molded portion; before the device is placed into the receiving groove of the daughterboard, a portion of the second molded portion is removed so that the first molded portion protrudes from the remaining second molded portion, and the second molded portion includes the first portion and the first protective portion; A first dielectric layer and a first metal layer are stacked in sequence on the daughter board, the daughter board, the first dielectric layer and the first metal layer are arranged in sequence along a first direction, and the first portion is located on a side of the device close to the first dielectric layer; Laminating the daughter board, the device, the first dielectric layer, and the first metal layer together, with a portion of the first dielectric layer filling a gap between an inner wall of the receiving groove and the device; A first filling hole penetrating the first metal layer and a first connection hole penetrating the first dielectric layer are processed on a side of the first metal layer facing away from the first dielectric layer, the first connection hole and the first filling hole being coaxially arranged, and the first protective portion defining a bottom surface of the first connection hole; The first conductive part is filled in the first connecting hole by copper electroplating, and the first filling part is filled in the first filling hole by copper electroplating. The first conductive part is connected to the first filling part and is electrically conductive. The first metal layer and the first filling part constitute a first circuit layer.

2. The method for manufacturing an embedded PCB according to claim 1, wherein: After the first conductive portion is filled in the first connection hole, the method for manufacturing the embedded PCB further includes: stacking a second dielectric layer and a second metal layer in sequence on the first circuit layer, wherein the second dielectric layer is located between the first circuit layer and the second metal layer; A second filling hole penetrating the second metal layer and a second connection hole penetrating the second dielectric layer are processed on a side of the second metal layer facing away from the second dielectric layer, the second connection hole and the second filling hole are coaxially arranged, and the first circuit layer defines a bottom surface of the second connection hole; The second conductive part is filled in the second connecting hole by copper plating, and the second filling part is filled in the second filling hole by copper plating. The second conductive part is connected to the second filling part and is electrically conductive. The second metal layer and the second filling part constitute a second circuit layer.

3. The method for manufacturing an embedded PCB according to claim 1, wherein: Before processing the first filling hole penetrating the first metal layer and the first connecting hole penetrating the first dielectric layer from the side of the first metal layer facing away from the first dielectric layer, obtain the thickness H0 of the first protective portion and the thickness H1 of the first dielectric layer, and the difference between H1 and H0 is H; the aperture of the first connecting hole is D, and D is greater than 1.25*H.

4. The method for manufacturing an embedded PCB according to any one of claims 1 to 3, wherein: The sub-board includes a first core board, a connecting dielectric layer and a second core board arranged in a stacked manner, the first core board is provided with a first window, the connecting dielectric layer is provided with a connecting window, and the second core board is provided with a second window. The first window, the connecting window and the second window are connected and define the accommodating groove; when the sub-board, the device, the first dielectric layer and the first metal layer are pressed together, part of the connecting dielectric layer fills the gap between the inner wall of the accommodating groove and the device.

5. An embedded PCB manufactured according to the method for manufacturing an embedded PCB according to any one of claims 1 to 4, characterized in that: The present invention comprises a daughter board, a first dielectric layer and a first circuit layer arranged in sequence and stacked along a first direction, wherein a device is embedded in the interior of the daughter board, the device is located on a side of the daughter board close to the first dielectric layer, a first portion is provided on the side of the device close to the first dielectric layer, and a first protective portion is provided on the first portion; a first connection hole is provided in the interior of the first dielectric layer, the interior of the first connection hole is filled with a first conductive portion, the first protective portion is connected to the first conductive portion and is electrically conductive, and the first conductive portion is connected to the first circuit layer and is electrically conductive.

6. The embedded PCB according to claim 5, characterized in that: The embedded PCB also includes a second dielectric layer and a second circuit layer stacked together, the second dielectric layer being located between the first circuit layer and the second circuit layer, a second connection hole being provided inside the second dielectric layer, the second connection hole being filled with a second conductive portion, the first circuit layer being connected and electrically conductive to the second conductive portion, and the second circuit layer being connected and electrically conductive to the second conductive portion.

7. The embedded PCB according to claim 6, characterized in that: A second portion is provided on a side of the device away from the first dielectric layer, and a second protective portion is provided on the second portion; the embedded PCB also includes a third dielectric layer and a third circuit layer stacked together, the third dielectric layer is located between the third circuit layer and the daughter board, a third connection hole is provided inside the third dielectric layer, and the interior of the third connection hole is filled with a third conductive portion, the second protective portion is connected to and electrically conductive with the third conductive portion, and the third circuit layer is connected to and electrically conductive with the third conductive portion.

8. The embedded PCB according to claim 5, wherein: The device includes a heat sink and a chip connected to each other, and the first part is provided on the chip; or the device includes a heat sink, and the first part is provided on the heat sink.

9. The embedded PCB according to any one of claims 5 to 8, characterized in that: The thickness of the first protection portion is 50 μm-300 μm.

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