Three-dimensional capacitor structure with high capacitance density and preparation method thereof

Abstract

The invention discloses a three-dimensional capacitor structure with high capacitance density and a preparation method thereof, and belongs to the technical field of power electronic components. Comprising the steps that a plurality of metal layer-insulating layer-metal layer structures are deposited on the surface of a substrate to form a capacitor, a metal layer serves as a polar plate of the capacitor, and an insulating layer serves as a dielectric layer of the capacitor; and the different metal layers are connected through annular through holes or through hole arrays among the insulating layers. According to the invention, the area of the polar plate is increased in a mode of overlapping multiple layers of metal, the realization is simple and effective, and meanwhile, a connection topological structure between the metal layers is innovatively provided, so that the problem of overlarge stress can be effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic components, and particularly relates to a three-dimensional capacitor structure with high capacitance density and a preparation method thereof. Background Art

[0002] In recent years, with the increasing requirement for improving the integration density of electronic components, the demand for capacitors with increased capacitance density has also been continuously increasing. According to the capacitance calculation formula C = εS / d, where ε is the dielectric constant, S is the plate area of the capacitor, and d is the distance between the capacitor plates. To achieve higher capacitance density, one method is to increase the dielectric constant, the second method is to increase the capacitor plate area S per unit volume, and the third method is to reduce the distance between the capacitor plates. The third method is restricted by the requirement for withstand voltage. The smaller the distance, the lower the withstand voltage between the capacitor plates. The first method requires the invention of new materials with high dielectric constant and consideration of their withstand voltage capabilities. The simplest and feasible method is the second method, that is, to increase the capacitor plate area per unit volume.

[0003] For this reason, Murata Company in Japan has proposed a manufacturing process for silicon capacitors. This process uses deep silicon etching technology to form three-dimensional structures such as holes, trenches, or columns on a silicon wafer. These structures are generally arranged in an array form. For example, a specific implementation form described in Patent CN118693062A is like this. Fudan University has also proposed a similar manufacturing process for fabricating three-dimensional silicon capacitors by etching deep grooves in silicon in Patent CN115547994A. A method for fabricating silicon capacitors using the through-silicon via technology is also proposed in Patent CN117766522A, which also requires etching deep grooves on silicon. The above several methods all increase the capacitor plate area in the vertical direction of silicon by vertically etching holes, grooves, or forming silicon pillars on silicon, thereby achieving an increase in the capacitance value per unit surface area on silicon. This method of increasing the capacitor plate area in the vertical direction of silicon is very effective, but the disadvantages are also obvious. First, the cost of deep silicon etching is relatively high. The deeper the depth or height of the groove or column, the larger the capacitance value per unit silicon surface area, but the corresponding etching cost is higher. Second, deeper grooves will lead to higher difficulty in depositing insulating layers or conductive layers on the surface of the grooves subsequently. Because when depositing in the grooves, the larger the aspect ratio of the grooves, the worse the conformality. For example, the thickness at the bottom of the grooves may be relatively thin. Third, the quality of the thin film formed in the deep grooves is worse than that formed on the plane, which is likely to cause difficulties in improving the withstand voltage. Summary of the Invention

[0004] Aiming at the defects of the prior art, the present invention provides a three-dimensional capacitor structure based on multi-layer metal stacking. This structure increases the capacitor plate area and improves the capacitance density by depositing multi-layer metal-insulator-metal layers on the surface of the substrate.

[0005] To achieve the above object, the present invention provides a three-dimensional capacitive structure with high capacitance density, comprising: depositing a multi-layer metal-insulator-metal structure on the surface of a substrate to form a capacitor, wherein the metal layer serves as the electrode plate of the capacitor and the insulator layer serves as the dielectric layer of the capacitor; and different metal layers are connected through annular through-holes or through-hole arrays between the insulator layers.

[0006] Furthermore, the number of the metal layers is greater than or equal to five, and each layer is a planar structure.

[0007] Furthermore, the substrate is obtained by forming a doped layer on a substrate through ion implantation or diffusion doping.

[0008] Furthermore, in each layer of the multi-layer metal-insulator-metal structure, required patterns are formed thereon through photolithography and etching, and contact holes connecting the metal layers are formed through photolithography and etching.

[0009] Furthermore, the top layer of the three-dimensional capacitive structure is a passivation layer, and passivation holes are etched to form a capacitor.

[0010] Furthermore, the insulator layer is one or a combination of several of silicon oxide, silicon nitride, and hafnium oxide; the metal layer is Al or Cu.

[0011] The present invention also provides a preparation method of a three-dimensional capacitor with high capacitance density. Based on the three-dimensional capacitive structure with high capacitance density as described above, the method comprises the following steps:

[0012] (1) Forming a doped layer on a substrate through ion implantation or diffusion doping, and simultaneously depositing a first insulator layer on the surface of the doped layer;

[0013] (2) Alternately depositing metal layers, insulator layers, and metal layers thereon, and simultaneously forming required patterns thereon through photolithography and etching in each layer, and forming contact holes connecting the metal layers through photolithography and etching;

[0014] (3) Repeating step (2) until the deposition of all metal-insulator-metal structures is completed;

[0015] (4) Depositing a passivation layer on the metal-insulator-metal structure and etching passivation holes to form a capacitor.

[0016] Advantages of the present invention:

[0017] The present invention increases the electrode plate area by stacking multiple metal layers, which is simple and effective. At the same time, an innovative connection topology structure between metal layers is proposed, which can effectively solve the problem of excessive stress. Description of the Drawings

[0018] Figure 1 Schematic diagram of a three-dimensional capacitor structure with high capacitance density according to an embodiment of the present invention.

[0019] Figure 2 Schematic flow chart of a method for preparing a three-dimensional capacitor with high capacitance density according to an embodiment of the present invention.

[0020] Figure 3 Schematic diagram of the shape of a through hole between conductive layers of a three-dimensional capacitor structure with high capacitance density according to an embodiment of the present invention.

[0021] Wherein: 1 - substrate material, 2 - highly doped layer, 3 - insulating layer, 4 - metal layer, 5 - passivation layer, 7 - upper electrode plate, 8 - lower electrode plate. Detailed implementation manners

[0022] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.

[0023] As Figure 1 shown, an embodiment of the present invention provides a three-dimensional capacitor structure with high capacitance density, which includes depositing a multi-layer metal layer-insulating layer-metal layer structure on the surface of a substrate to form a capacitor, wherein the metal layer serves as the electrode plate of the capacitor and the insulating layer serves as the dielectric layer of the capacitor; and different metal layers are connected through annular through holes or through hole arrays between the insulating layers. The metal layer is greater than or equal to five layers, and each layer is a planar structure. The substrate is obtained by ion implantation or diffusion doping on a silicon substrate to form a doped layer. A passivation layer is provided on the upper layer of the multi-layer metal layer-insulating layer-metal layer structure, and passivation holes are etched to form a capacitor.

[0024] The insulating layer can be a variety of dielectric materials or a combination of these materials. For example, it can be silicon oxide, silicon nitride, hafnium oxide and other materials or a combination of silicon oxide + silicon nitride + silicon oxide, and the deposition of the various materials can be achieved through the PECVD process or other process steps. The above-mentioned metal layer can be Al, or Cu, or other various conductive materials that can be used as the capacitor electrode plate.

[0025] As Figure 2 shown, an embodiment of the present invention also provides a method for preparing a three-dimensional capacitor with high capacitance density. Based on the above three-dimensional capacitor structure with high capacitance density, the method includes the following steps:

[0026] S101. Form a doped layer on the substrate by ion implantation or diffusion doping, and at the same time deposit a first insulating layer on the surface of the doped layer.

[0027] First, select a silicon wafer as the substrate. There is no requirement for the type of the silicon wafer. Preferably, it can be an N-type silicon wafer with as high a doping concentration as possible. In order to further reduce the series resistance of the capacitor, the doping concentration of the surface can be first increased by ion implantation on the silicon wafer surface, as Figure 2 (a) shows. The upper structure in the figure is the ion implantation doping layer. Of course, the diffusion doping method can also be used to increase the surface doping concentration. Then, thermal oxidation is carried out, and the formed oxide layer serves as the insulating layer, as Figure 2 (b) shows.

[0028] S102. Alternately deposit metal layers, insulating layers, and metal layers thereon. At the same time, form the required patterns on each layer through photolithography and etching, and form contact holes connecting the metal layers through photolithography and etching.

[0029] Deposit a metal layer on the above-mentioned insulating layer, and then form the required pattern through photolithography and etching, as Figure 2 (c) shows. Form contact holes connecting to the substrate through photolithography and etching on the above-mentioned surface, as Figure 2 (d) shows. At this time, the top view is as Figure 3 (a) shows. It can be seen that the formed contact holes are in a ring structure and arranged in a column. The three contact holes shown in the figure are only exemplary. Any number and arrangement shape are within the scope described in this patent. For example, Figure 3 (c) shows the L-shaped arrangement. Deposit a metal layer and form the required pattern through the photolithography and etching steps. At this time, the structure is as Figure 2 (e) shows. Deposit an insulating layer on the surface, photolithograph the pattern on this insulating layer, and etch through holes, as Figure 2 (f) shows. At this time, the top view is as Figure 3 (b) shows. It can be seen that the through holes are in a ring shape and multiple through holes are arranged in a column. Then deposit a metal layer and etch out the required pattern. At this time, the structure is as Figure 2 (g) shows.

[0030] S103. Repeat step S102 until the deposition of all metal layer-insulating layer-metal layer structures is completed.

[0031] The metal layer needs to be greater than or equal to five layers, and finally form the structure as Figure 2 (h) shows. It should be noted that Figure 2 (h) shows five metal layers. In fact, more layers can be added according to needs by the above method to increase the capacitance value per unit surface area.

[0032] S104. Deposit a passivation layer on the metal layer-insulating layer-metal layer structure and etch passivation holes to form a capacitor.

[0033] A passivation layer is deposited on this structure and passivation holes are etched. The positions of the passivation holes are the upper electrodes, and the structure is as shown in Figure 2 (i). Finally, the back surface of the substrate is thinned and metallized, so that the lower electrode of the capacitor is formed on the back surface.

[0034] The specific description above further details the purpose, technical solution, and beneficial effects of the invention. It should be understood that the above is only a specific embodiment of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-dimensional capacitive structure with high capacitance density, characterized in that, A capacitor is formed by depositing a multi-layer metal-insulator-metal structure on the surface of a substrate, where the metal layer serves as the electrode of the capacitor and the insulator layer serves as the dielectric layer of the capacitor; and different metal layers are connected through annular vias or via arrays between the insulator layers.

2. The three-dimensional capacitive structure with high capacitance density according to claim 1, characterized in that The metal layer is greater than or equal to five layers, and each layer is a planar structure.

3. The three-dimensional capacitive structure with high capacitance density according to claim 1, characterized in that, The substrate is obtained by forming a doped layer on a substrate through ion implantation or diffusion doping.

4. The three-dimensional capacitive structure with high capacitance density according to claim 1, characterized in that: In each layer of the multi-layer metal-insulator-metal structure, required patterns are formed thereon through photolithography and etching, and contact holes connecting the metal layers are formed through photolithography and etching.

5. The three-dimensional capacitive structure with high capacitance density according to claim 1, wherein: The uppermost layer of the three-dimensional capacitor structure is a passivation layer, and passivation holes are etched to form the capacitor.

6. The three-dimensional capacitive structure with high capacitance density according to claim 1, characterized in that: The insulator layer is a combination of one or more of silicon oxide, silicon nitride, and hafnium oxide; The metal layer is Al or Cu.

7. A method for preparing a three-dimensional capacitor with a high capacitance density, based on the three-dimensional capacitor structure with a high capacitance density according to any one of claims 1-6, characterized in that, It includes the following steps: (1) A doped layer is formed on a substrate through ion implantation or diffusion doping, and at the same time, a first insulator layer is deposited on the surface of the doped layer; (2) Metal layers, insulator layers, and metal layers are alternately deposited thereon, and required patterns are formed thereon through photolithography and etching in each layer, and contact holes connecting the metal layers are formed through photolithography and etching; (3) Step (2) is repeated until the deposition of all metal-insulator-metal structures is completed; (4) A passivation layer is deposited on the metal-insulator-metal structure and passivation holes are etched to form the capacitor.

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