Preparation method of high-frequency response power triode

Abstract

The invention relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of a high-frequency response power triode. Firstly, the resistivity gt is adopted; the method comprises the following steps: growing an N-drift layer on an N + silicon substrate with the thickness of 1000 omega.cm, etching an isolation groove with the depth of 12 microns and the depth-to-width ratio of 5.9: 1 through ICP (Inductively Coupled Plasma), and filling a SiO2 / Si3N4 composite dielectric layer to expand a depletion layer to 18.5 microns, so that the capacitance of a collector junction is reduced to 68pF and the breakdown voltage reaches 205V. Secondly, forming an interdigital emitter on the front surface, thinning the back surface to 100 + / -2 microns, then performing laser drilling, filling through holes with pulse electroplating copper, and compressing loop inductance to 2.7 nH by a copper column array; and finally, a Ti / Ni / Au transition layer is sputtered, a diamond-copper composite substrate is subjected to hot pressing bonding, a TiC phase of 80 nm is formed on an interface, the heat conductivity reaches 635 W / m.K, and the heat resistance is reduced to 0.61 K / W. According to the invention, capacitance, inductance and thermal resistance are optimized, switching loss is reduced by 57.8%, power density is increased to 51.2 W / cm < 2 >, and the device is suitable for a MHz-level high-frequency power system.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and more specifically, to a method for preparing a high-frequency response power triode. Background Art

[0002] The current silicon-based power triodes have the following technical problems in high-frequency applications: Parasitic capacitance problem: The collector-base capacitance (Cbc) and emitter-base capacitance (Cbe) form an RC delay during high-frequency switching, resulting in a sharp increase in switching losses of traditional devices at frequencies above 500 kHz (measured > 1.5 μJ / time). The traditional planar collector-base junction has a concentrated edge electric field (peak > 2×10 5 V / cm), resulting in a generally > 100 pF collector-base capacitance (C jc ). When the switching frequency exceeds 500 kHz, the RC delay effect causes the switching losses to increase exponentially (measured > 1.5 μJ / time). To increase the breakdown voltage, the drift layer thickness needs to be increased, which will further deteriorate the capacitance characteristics.

[0003] Current path inductance problem: Traditional wire bonding leads to a loop inductance of 5 - 10 nH, causing a voltage overshoot > 0.5 V at a frequency of 1 MHz, forcing derating. The bent current path (equivalent length ≥ 3 mm) formed by wire bonding generates a 5 - 10 nH loop inductance, causing a voltage overshoot > 0.5 V under 1 MHz operating conditions, forcing the device to be derated. Although the existing copper strip bonding scheme can reduce the inductance by 28%, the thermal resistance increases by 35% (due to the mismatch of the thermal expansion coefficients of the copper strip).

[0004] Thermal accumulation problem: The thermal conductivity of silicon material (150 W / m·K) is insufficient, the device thermal resistance > 1.8 K / W, and the junction temperature rise rate > 15 °C / μs, limiting the power density to below 30 W / cm 2 The intrinsic thermal conductivity of silicon material (150 W / m·K) is insufficient, combined with the interfacial thermal resistance of the Al2O3 ceramic substrate (24 W / m·K), making the overall thermal resistance of the device > 1.8 K / W. When the power density > 30 W / cm 2 , the junction temperature rise rate > 15 °C / μs, leading to the risk of thermal breakdown. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for preparing a high-frequency response power triode to solve the problem of the parasitic capacitance-loop inductance-thermal accumulation triangular contradiction of silicon-based power triodes under high-frequency operating conditions as mentioned in the above background art.

[0006] To achieve the above purpose, the present invention provides a method for preparing a high-frequency response power triode, including the following steps: S1. Prepare a capacitance optimization layer: An N+-type silicon substrate with a resistivity > 1000 Ω·cm (thickness 650 ± 50 μm) is used. Its high-resistance characteristic extends the depletion layer width to more than 2.3 times that of a conventional device; An N-type lightly doped drift layer (thickness 10 ± 0.3 μm, doping concentration (5 ± 0.2) × 10 14 cm -3 ) is grown on the front surface of the substrate; this design enables the breakdown voltage to satisfy: ; An isolation trench with a depth and aspect ratio of 5.9:1 is formed by inductively coupled plasma (ICP) etching technology. The trench is filled with a SiO2 / Si3N4 composite dielectric layer (thickness ratio 2:1), and its dielectric constant (pure SiO2 is 3.9), effectively blocking the edge electric field coupling of the collector junction.

[0007] S2. Set the inductance optimization structure: An interdigital emitter metal layer (finger width 10 ± 0.2 μm, spacing 15 ± 0.3 μm) is formed on the front surface of the device. This geometric configuration reduces the base resistance by 40%; After the back surface is thinned to 100 ± 2 μm, a via hole array with a diameter of 10 ± 0.3 μm (hole density 400 ± 20 holes / mm²) is formed by ultraviolet laser (wavelength 355 nm) drilling; The vias are filled with copper pillars through a pulse electroplating copper process, and the surface roughness Ra < 0.08 μm; electroplating solution formula: CuSO4·5H2O 200 g / L + H2SO4 50 g / L + Cl - 50 ppm + polyethylene glycol (PEG) 300 ppm + sodium 3,3'-dithiodipropanesulfonate (SPS) 5 ppm; pulse parameters: forward current density 18 mA / cm 2 (pulse width 10 ms), reverse current density 5 mA / cm 2 (pulse width 3 ms); realizing void-free filling of microholes with an aspect ratio of 10:1 (void ratio detected by X-ray < 0.1%).

[0008] S3. Set the thermal management structure: A Ti / Ni / Au transition layer (thickness 50 / 100 / 150 nm) is sputtered on the surface of the copper pillar; the Ti layer forms a TiSi2 Schottky barrier with silicon ( ), and the contact resistance ; the Ni layer acts as a diffusion barrier to inhibit the migration of copper atoms to the semiconductor region; the Au layer provides a highly active bonding surface, reducing the bonding temperature to 450 °C; Hot-pressed bonded diamond-copper composite heat dissipation substrate (diamond volume fraction 55±3%); Diamond pretreatment: Particle size classification of 40-60 μm, surface sputtering of Ti / Mo metallization layer; Vacuum hot-pressing process: Temperature 780°C (below the melting point of copper), pressure 25 MPa, heat preservation for 30 minutes; Thermal conductivity of the composite layer (measured by the laser flash method).

[0009] In the present invention, the high-resistance substrate ( ) expands the depletion layer width to 18.5 μm (only 7.2 μm for traditional devices), and the capacitance value decreases according to the ratio.

[0010] The deep trench isolation penetrates the entire drift region (12 μm), dividing the collector junction into multiple independent units. It is confirmed by finite element simulation (COMSOL Multiphysics) that this structure reduces the edge electric field strength from 2.1×10 5 V / cm to 1.3×10 5 V / cm, reducing the dielectric coupling capacitance by 23%.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. In the preparation method of this high-frequency response power triode, first, the high-resistance substrate (ρ>1000Ω·cm) longitudinally expands the depletion layer to 18.5 μm. Combining with deep trench isolation (trench depth = drift layer thickness) to block the lateral electric field, while reducing C jc to 68 pF (a decrease of 40.9%), the breakdown voltage is increased to 205 V (an increase of 17.1%). This method solves the capacitance-voltage inverse relationship of the existing traditional planar junction, and the figure of merit FOM is increased by 90.6%. Secondly, the copper pillar array (diameter 10±0.3 μm) verticalizes the current path, compresses the loop inductance to 2.7 nH (a decrease of 62.5%), and eliminates the turn-off voltage overshoot (measured <0.1 V). Combining with the interdigital emitter design, the switching delay time is shortened by 57.9%.

[0012] 2. In the preparation method of this high-frequency response power triode, the diamond and copper composite substrate (55 vol% diamond + Ti / Mo interface layer) achieves an ultra-high thermal conductivity of 635 W / m·K, and the proportion of the interface thermal resistance is reduced to 22%; The Ti / Ni / Au transition layer absorbs the thermal expansion mismatch stress through an 80-nm TiC interface phase (shear strength 6.5 GPa), reducing the thermal resistance to 0.61 K / W (a decrease of 67.8%), and the power density is increased to 51.2 W / cm 2 (an increase of 67.9%).

[0013] 3. In the preparation method of the high-frequency response power triode, a copper pillar with a diameter of 10 μm (aspect ratio 10:1) achieves void-free electroplating (void ratio < 0.1%). Combining with the low-temperature bonding process at 450 °C, the thermal cycle life > 2.5 × 10 5 times (rising 201%); the precise matching of the drift layer thickness (10 μm) and the deep trench depth (12 μm) avoids the breakdown voltage rollback. Description of the Drawings

[0014] Figure 1 It is the overall flowchart of Embodiment 1 of the present invention. Detailed Embodiments

[0015] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0016] Embodiment 1: This embodiment provides a preparation method of a high-frequency response power triode, combining Figure 1 as shown, including the following steps: S1. Substrate and epitaxial layer preparation Select an N+-type silicon single crystal wafer with a diameter of 150 mm and a thickness of 650 ± 10 μm. The resistivity is measured by the four-probe method to be . Epitaxial growth is carried out in a reduced-pressure chemical vapor deposition (RP-CVD) reaction chamber: the reaction gases are dichlorosilane (SiH2Cl2) and hydrogen (H2) with a molar ratio of 1:50; the temperature is controlled at 1080 ± 5 °C (real-time feedback by thermocouple); the pressure is set at 80 ± 2 Torr; the doping source is phosphine (PH3), and the flow rate is calibrated by a mass flow meter to 3.5 × 10 -4 ±5% L / min; the growth rate is 1.20 ± 0.05 μm / min, and the total time is 8 minutes and 20 seconds to obtain an N-drift layer with a thickness of 10.02 ± 0.15 μm; the doping concentration of the epitaxial layer is tested by the Hall effect: at a temperature of 300 K, the carrier concentration n = (5.15 ± 0.12) × 10 14 cm -3 , and the mobility .

[0017] S2. Fabrication of deep trench isolation structure Photolithographically define the trench area: coat a 1.2-μm-thick AZ 5214 photoresist, and expose it to ultraviolet light (wavelength 365 nm, energy 200 mJ / cm 2 ), and form a window with a line width of 2.4 ± 0.05 μm after development.

[0018] ICP Etching Process: Reactive Gas: SF6 80 sccm + C4F6 40 sccm + O2 5 sccm; RF Power: Upper Electrode 600 W (13.56 MHz), Lower Electrode 200 W (2 MHz); Chamber Temperature: -20 ± 2 °C (Liquid Nitrogen Cooling); Etching Rate: 1.10 ± 0.03 μm / min, Total Time 10 min 55 s; The groove depth measured by a step profiler is, and the sidewall angle is 88.7 ± 0.3° (verified by SEM) Dielectric Layer Deposition: PECVD Deposition of SiO2: Temperature 300 °C, SiH4 / N2O = 200 / 400 sccm, Thickness 300 ± 10 nm; LPCVD Deposition of Si3N4: Temperature 780 °C, SiH2Cl2 / NH3 = 50 / 150 sccm, Thickness 150 ± 5 nm; Annealing Treatment: N2 Atmosphere, 800 °C / 30 min, Eliminating the Interface State Density to < 5×10 10 cm -2 .

[0019] S3. Formation of Copper Pillar Array Backside Thinning: Coarse Grinding with a Diamond Grinding Wheel + Chemical Mechanical Polishing (CMP), Final Thickness 100.5 ± 1.2 μm, Surface Roughness .

[0020] Laser Via Hole Machining: Equipment: Spectra-Physics HIPPO UV Laser (Wavelength 355 nm); Parameters: Pulse Energy 0.8 mJ, Repetition Frequency 20 kHz, Scanning Speed 500 mm / s; Aperture: Inlet 10.2 ± 0.3 μm, Outlet 9.8 ± 0.3 μm, Taper < 0.5°.

[0021] Electroplated Copper Filling: Pretreatment: Sputtering Ti / Cu Seed Layer (20 / 200 nm); Electroplating Bath: Rotating Cathode Design (Rotation Speed 30 ± 5 rpm); Pulse Waveform: Forward 18 mA / cm 2 (10 ms on) → Zero Current (5 ms) → Reverse 5 mA / cm 2 (3 ms); Filling Result: X-ray Tomography Shows that the Copper Density Deviation from the Bottom to the Top of the Hole is < 0.3%.

[0022] S4. Heat Dissipation Integration and Packaging Interlayer deposition: Magnetron sputtering of Ti / Ni / Au (thickness 50 / 100 / 150 nm), base vacuum < 5×10 -6 Torr, Preparation of diamond - copper composite sheet: Mixing: Diamond powder with particle size 45 - 55μm (55 vol%) + electrolytic copper powder (45 vol%); Ball milling: Under argon protection, rotation speed 200 rpm, time 2 h; Hot pressing: Heating rate 10℃ / min, holding at 780℃ for 30 min, pressure 25 MPa.

[0023] Thermal compression bonding: Equipment: EVG 520IS bonding machine; Parameters: Temperature 450 ± 5℃, pressure 15 ± 0.5 MPa, time 10 min; Interface analysis: SEM shows that a continuous TiC phase (thickness about 80 nm) is formed between the Ti layer and the diamond surface.

[0024] Example 2: For the high - frequency response power triode prepared in Example 1, the electro - thermal performance limit test is carried out.

[0025] Test conditions: Power supply uses Keysight B1505A power device analyzer; Load: Inductor ; Working conditions: , , , duty cycle 50% Thermal environment: Water - cooled plate temperature T c = 25 ± 0.5℃.

[0026] Table 1 Test results

[0027] Example 3: For the high - frequency response power triode prepared in Example 1, the structural parameter boundary verification is carried out.

[0028] Table 2 Copper column diameter optimization experiment

[0029] Table 3 Influence of deep groove depth

[0030] When the groove depth > the drift layer thickness, the breakdown voltage regresses because the depletion region penetrates through to the substrate.

[0031] Comparative Example 1: This comparative example provides a traditional bonding wire packaging method. The differences between this comparative example and Example 1 are shown in Table 4 specifically.

[0032] Table 4

[0033] In the traditional wire bonding package, a large-area current loop (equivalent length 3 mm) is formed due to the bending path, and its inductance effect results in a switching loss as high as 1.82 μJ. Moreover, the insufficient thermal conductivity of the alumina substrate (24 W / m·K) causes local hot spots (thermal resistance 2.05 K / W). The present invention adopts vertical copper pillar interconnection (length 100 μm) and diamond composite heat dissipation (635 W / m·K), which not only reduces the switching loss by 62.1%, but also increases the power density by 75% through a three-dimensional thermal management channel. This electromagnetic-thermal dual path solves the space limitation of the traditional package.

[0034] Comparative Example 2: This comparative example provides a structure without deep trench isolation. The differences between this comparative example and Example 1 are specifically shown in Table 5.

[0035] Table 5

[0036] Due to the concentrated edge electric field, the capacitance of the planar collector junction remains high (115 pF), and even using a high-resistance substrate (Comparative Example 5) cannot fundamentally improve it. The deep trench isolation structure of the present invention blocks the lateral electric field through a SiO2 / Si3N4 composite medium, causing the capacitance to drop sharply by 40.9% to 68 pF, while the breakdown voltage increases by 17.1%. Therefore, it can be shown that the trench depth needs to be equal to the drift layer thickness (a 12-μm deep trench matches a 10-μm drift layer), changing the electric field distribution from edge concentration to global uniformity.

[0037] Comparative Example 3: Based on Example 1, in this comparative example, the diameter of the copper pillar is modified to 15 μm and the pitch is 45 μm. The differences between this comparative example and Example 1 are specifically shown in Table 6.

[0038] Table 6

[0039] When the diameter of the copper pillar increases to 15 μm (deviating from the optimal value by 50%), the area of the current loop expands due to the decrease in unit density, and the loop inductance increases sharply by 40.7% to 3.8 nH. More seriously, the aspect ratio drops to 6.7:1, causing electroplating voids (0.5%), which deteriorates the thermo-mechanical reliability by 28%. This proves that a 10-μm diameter not only meets the process limit of pulse electroplating without void filling (aspect ratio 10:1) but also achieves inductance minimization.

[0040] Comparative Example 4: Based on Example 1, in this comparative example, the usage amount of diamond is modified to 30 vol% and the usage amount of copper is modified to 70 vol%. The differences between this comparative example and Example 1 are specifically shown in Table 7.

[0041] Table 7

[0042] For diamond with a low volume fraction (30%), since a continuous heat conduction network is not formed, its thermal conductivity is only 320 W / m·K, and the proportion of the interfacial thermal resistance is as high as 68%. In the present invention, with a diamond content of 55% and Ti / Mo metallization, an efficient phonon transmission channel is established between diamond particles (thermal conductivity: 635 W / m·K), and the proportion of the interfacial thermal resistance is reduced to 22%. This design breaks through the predicted value of the effective medium theory (the limit of formula calculation is 520 W / m·K), and the interfacial nanostructure is the core key to achieving extraordinary thermal performance.

[0043] Comparative Example 5: In this comparative example, a preparation method of using a high-resistance substrate without combination with deep trenches is adopted. The differences between this comparative example and Example 1 are specifically shown in Table 8.

[0044] Table 8

[0045] Using a high-resistance substrate alone can longitudinally expand the depletion layer (breakdown voltage: 185 V), but due to the lack of transverse electric field control, the capacitance is only reduced to 92 pF. In the present invention, by combining deep trench isolation with a high-resistance substrate, the depletion region expands simultaneously in the longitudinal and transverse directions (confirmed by COMSOL simulation), the capacitance is further reduced to 68 pF, and the breakdown voltage jumps to 205 V. This three-dimensional depletion region regulation increases the figure of merit FOM by 90.6%, proving a strong non-linear synergistic effect between the two technologies.

[0046] Comparative Example 6: In this comparative example, a preparation method of direct bonding without a transition layer is adopted. The differences between this comparative example and Example 1 are specifically shown in Table 9.

[0047] Table 9

[0048] Direct bonding without a transition layer requires a high temperature of 600 °C and generates a brittle Cu2O phase (with a thickness of up to 2 μm), resulting in an interfacial thermal resistance as high as 8.7 mm 2 ·K / W. The Ti / Ni / Au gradient transition layer of the present invention forms an 80-nm TiC interfacial phase at a low temperature of 450 °C, which not only enables high phonon transmission (thermal resistance: 3.2 mm 2 ·K / W), but also absorbs thermal stress through plastic deformation (shear strength increases by 85.7%). This design of a low-temperature reaction-nano interface solves the problem of heterogeneous integration of diamond and copper.

[0049] The foregoing has shown and described the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments, and the above embodiments and the descriptions in the specification are only preferred examples of the present invention and are not used to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. A preparation method of a high-frequency response power triode, characterized in that, Including the following steps: S1. Use an N+-type silicon substrate with a resistivity > 1000 Ω·cm and a thickness of 600 - 700 μm. Grow an N-type drift layer on the front side of the substrate, with a thickness of 9.7 - 10.3 μm and a doping concentration of 4.8 - 5.2×10 14 cm -3 ); Form an isolation groove with a depth of 11.5 - 12.5 μm and an aspect ratio of 5.9:1 by ICP etching, and fill the groove with a SiO2 / Si3N4 composite dielectric layer with a thickness ratio of 2:1; S2. Form an interdigital emitter metal layer on the front of the device, finger width: 9.8 - 10.2 μm, pitch: 14.7 - 15.3 μm; After the backside is thinned to 98 - 102 μm, a via hole array with a diameter of 9.7 - 10.3 μm is formed by laser drilling, and the hole density is 380 - 420 holes / mm 2 ; Pulse electroplate copper to fill the through holes to form copper pillars, and the electroplating solution contains polyethylene glycol and sodium 3,3'-dithiodipropanesulfonate; S3. Sputter a Ti / Ni / Au transition layer on the surface of the copper pillars; Thermocompression bond a diamond - copper composite heat dissipation substrate, diamond volume fraction: 52 - 58%, sputter a Ti / Mo metallization layer on the diamond surface, bonding temperature: 445 - 455 °C, pressure: 1.5 - 15.5 MPa.

2. The manufacturing method of the high-frequency response power triode according to claim 1, wherein: In S1, the depth of the isolation groove is 1.2 times the thickness of the drift layer.

3. The preparation method of the high-frequency response power triode according to claim 1, wherein: In S1, the composite dielectric layer is composed of 290 - 310 nm SiO2 deposited by PECVD and 145 - 155 nm Si3N4 deposited by LPCVD.

4. The preparation method of the high-frequency response power triode according to claim 1, characterized in that: In S1, the growth conditions of the drift layer are: reduced - pressure chemical vapor deposition, the molar ratio of reaction gases is SiH2Cl2:H2 = 1:50, temperature 1075 - 1085 °C, pressure 78 - 82 Torr; The flow rate of the doping source PH3 is 3.5×10 -4 ±5% L / min, and the growth rate is 1.15 - 1.250 μm / min.

5. The preparation method of the high-frequency response power triode according to claim 1, wherein: In S2, the pulse electroplating adopts a rotating cathode design.

6. The manufacturing method of the high-frequency response power triode according to claim 1, characterized in that: When preparing the diamond - copper composite heat dissipation substrate, the particle size of the diamond powder is 45 - 55 μm.

7. The manufacturing method of the high-frequency response power triode according to claim 1, characterized in that: In S2, the taper of the through hole < 0.5°, the inlet diameter is 9.9 - 10.5 μm, and the outlet diameter is 9.5 - 10.1 μm.

8. The manufacturing method of the high-frequency response power triode according to claim 1, characterized in that: In S2, the laser drilling uses an ultraviolet laser with a wavelength of 355 nm, pulse energy of 0.8 mJ, and repetition frequency of 20 kHz.

9. The preparation method of the high-frequency response power triode according to claim 1, characterized in that: In S3, a TiC interface phase is formed during the thermocompression bonding process.

10. The preparation method of the high-frequency response power triode according to claim 1, wherein: In S2, the void ratio is < 0.1% after the copper pillars are filled and detected by X - ray.

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