Semiconductor device with temperature sensor and preparation method thereof

Abstract

The invention relates to a semiconductor device with a temperature sensor and a preparation method thereof, and the key points of the technical scheme are that the method comprises the steps: constructing a super-junction charge balance region on the surface of a substrate, and forming a body region at the top of the super-junction charge balance region; generating a first shallow trench and a second shallow trench on the body region; sequentially depositing an oxidation dielectric layer and first polycrystalline silicon in each of the first shallow trench and the second shallow trench; etching the first polycrystalline silicon in the second shallow trench, and depositing second polycrystalline silicon above the first polycrystalline silicon in the second shallow trench; depositing a dielectric layer on the surface of the body region, and etching in the dielectric layer to form a contact hole; the contact hole is communicated with the first polycrystalline silicon and the second polycrystalline silicon; the temperature detection diode structure is integrated in the epitaxial material of the device, and the problem that the internal thermal characteristics of the device cannot be fed back in time is solved by improving the manufacturing process under the condition that the characteristics of the device are not influenced by utilizing the linear relation between the forward conduction voltage and the temperature of the diode.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, it relates to a semiconductor device with a temperature sensor and a method for manufacturing the same. Background Art

[0002] With the wide application of power semiconductor devices such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated-Gate Bipolar Transistor), and diodes in household electronic devices, vehicle intelligent system devices, and industrial instrument devices, the performance requirements for semiconductor devices are constantly increasing. In addition to meeting the static characteristics required for actual applications, dynamic performance has gradually become particularly important.

[0003] Taking the superjunction MOSFET device as an example, the superjunction MOSFET device has characteristics such as fast switching speed, low on-resistance, and easy driving. Therefore, it is widely used in high-power and high-frequency related applications, such as chargers, charging piles, LEDs, UPS power supplies, etc. In the case of abnormal or overloaded operation of semiconductor devices, it is easy to cause the semiconductor device to heat up rapidly, which can easily lead to deterioration of the characteristics of the semiconductor device and even serious failure problems.

[0004] In the prior art, when it is necessary to detect the temperature of a semiconductor device, a detection device is usually additionally provided in the corresponding circuit. This detection method has problems such as slow feedback speed and inability to obtain the internal thermal characteristics of the device. In addition, in the prior art, the temperature detection device is formed by depositing polysilicon above the chip epitaxy, which cannot detect the temperature change of the junction inside the device chip in a timely and sensitive manner, and this detection device has disadvantages such as complex manufacturing process, high cost, and large area occupied on the entire chip. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a semiconductor device with a temperature sensor and a method for manufacturing the same to solve the above technical problems.

[0006] The above technical objective of the present invention is achieved through the following technical solutions: A method for manufacturing a semiconductor device with a temperature sensor, comprising:

[0007] Constructing a superjunction charge balance region on the surface of the substrate, and forming a body region on the top of the superjunction charge balance region;

[0008] Generating a first shallow trench and a second shallow trench on the body region;

[0009] An oxidation dielectric layer and a first polysilicon are sequentially deposited in both the first shallow trench and the second shallow trench;

[0010] The first polysilicon in the second shallow trench is etched, and a second polysilicon is deposited above the first polysilicon in the second shallow trench;

[0011] A dielectric layer is deposited on the surface of the body region, and a contact hole is etched in the dielectric layer; the contact hole communicates with the first polysilicon and the second polysilicon;

[0012] Source and drain electrodes are formed.

[0013] Specifically, by depositing the first polysilicon in the first shallow trench, etching and depositing the second polysilicon on the first polysilicon deposited in the second shallow trench, a temperature sensor structure is formed by the first polysilicon and the second polysilicon, and since the oxidation dielectric layer is deposited in the first shallow trench and the second shallow trench, the oxidation dielectric layer has an electrical isolation characteristic and can isolate the first polysilicon and the superjunction charge balance region, so as to integrate the temperature sensor structure in the superjunction charge balance region and the body region. Without occupying the actual active area of the chip, a temperature sensor structure capable of monitoring the junction temperature characteristics in the MOSFET device body in real time is added, and the working state of the MOSFET device can be more sensitively reflected.

[0014] Optionally, constructing the superjunction charge balance region on the substrate surface includes:

[0015] Epitaxially growing a first-conductivity-type buffer layer on the substrate surface;

[0016] A first-conductivity-type epitaxial layer is formed on the first-conductivity-type buffer layer, and a plurality of first deep trenches spaced apart are etched in the first-conductivity-type epitaxial layer; the plurality of first deep trenches divide the first-conductivity-type epitaxial layer into a plurality of first-conductivity-type columns;

[0017] Bottom implantation treatment is performed on the plurality of spaced-apart first deep trenches, and second-conductivity-type columns are epitaxially grown in the first deep trenches. The first-conductivity-type columns and the second-conductivity-type columns form the superjunction charge balance region.

[0018] Specifically, the substrate is a first-conductivity-type substrate, the substrate doping is first-conductivity-type heavy doping, the first deep trenches are formed on the first-conductivity-type epitaxial layer by a dry etching process, and after sacrificial oxidation treatment of the first deep trenches, bottom implantation treatment is performed, so as to epitaxially grow and form the second-conductivity-type columns, and the superjunction charge balance region is composed of the first-conductivity-type columns and the second-conductivity-type columns.

[0019] Optionally, the sequentially depositing an oxidation dielectric layer and a first polysilicon in both the first shallow trench and the second shallow trench includes:

[0020] An oxidation dielectric layer is formed on the top of the body region, the first shallow trench, and the second shallow trench through a furnace tube process;

[0021] Deposit the first polysilicon in the first shallow trench and the second shallow trench, and perform an etching process on the first polysilicon to etch the first polysilicon flush with the epitaxial layer of the first conductivity type.

[0022] Specifically, both the first shallow trench and the second shallow trench pass through the body region and are embedded in the column of the first conductivity type; and an oxidation dielectric layer is formed in the first shallow trench and the second shallow trench through a furnace tube process, thereby electrically isolating the first shallow trench and the second shallow trench from the column of the first conductivity type.

[0023] Optionally, the etching of the first polysilicon in the second shallow trench and the deposition of the second polysilicon above the first polysilicon in the second shallow trench include:

[0024] Pre-define the pattern of the polysilicon photomask and open a window in the area where the second shallow trench is located;

[0025] Etch the second shallow trench based on the polysilicon photomask, and the etching depth of the first polysilicon in the second shallow trench is half or 2 / 3 or 1 / 3 of the depth of the second shallow trench;

[0026] Deposit the second polysilicon in the second shallow trench, and perform an etching process on the second polysilicon to etch the second polysilicon flush with the epitaxial layer of the first conductivity type.

[0027] Specifically, perform an etching process on the first polysilicon in the area where the second shallow trench is located through the polysilicon photomask, remove part of the first polysilicon in the second shallow trench, and deposit and form the second polysilicon on the first polysilicon by using a non-doped ion implantation method. The non-doped ion type is the source species of the second conductivity type. The temperature monitoring in the column of the first conductivity type is realized through the current change of the first polysilicon and the second polysilicon in the second shallow trench at different temperatures.

[0028] Optionally, the forming of the body region on the top of the superjunction charge balance region includes:

[0029] Form the body region by lithography and doping and implanting the second conductivity type ions on the top of the superjunction charge balance region;

[0030] Form a thick field oxide layer on the top of the body region, and etch and remove the thick field oxide layer in the active region.

[0031] Specifically, the depth of the body region is less than 3.0 um, the thickness of the thick field oxide layer is 3000A - 5000A, and the active region is the region on the silicon wafer where active devices are made. By forming the thick field oxide layer on the top of the body region, the top of the body region can be isolated.

[0032] Optionally, a dielectric layer is deposited on the surface of the body region, and contact holes are etched in the dielectric layer; the contact holes communicate with the first polysilicon and the second polysilicon, including:

[0033] A dielectric layer is deposited on the surface of the body region, and gate contact holes, source contact holes, anode contact holes and cathode contact holes are etched in the dielectric layer; the gate contact holes are on the first shallow trench, the source contact holes are in the chip cell region, the anode contact holes are on the second shallow trench and on one side of the second shallow trench, and the anode contact holes communicate with the first polysilicon in the second shallow trench; the cathode contact holes are on the second shallow trench and on the other side of the second shallow trench, and the cathode contact holes communicate with the second polysilicon in the second shallow trench.

[0034] Specifically, the anode contact holes and the cathode contact holes are respectively connected to the first polysilicon and the second polysilicon in the second shallow trench, so as to connect the two ends of the temperature sensor.

[0035] Optionally, gate metal is deposited on the dielectric layer and at the gate contact holes, and the gate metal communicates with the gate contact holes; source metal is deposited on the dielectric layer and at the source contact holes, and the source metal communicates with the source contact holes; anode metal is deposited on the dielectric layer and at the anode contact holes, and the anode metal communicates with the anode contact holes; cathode metal is deposited on the dielectric layer and at the cathode contact holes, and the cathode metal communicates with the cathode contact holes;

[0036] The side of the substrate away from the superjunction charge balance region is thinned to form a drain.

[0037] Specifically, by connecting the anode metal to the anode contact holes, the cathode metal to the cathode contact holes, and using wire bonding in packaging to connect the anode metal, the cathode metal, the source metal, the gate metal and the drain metal, integration can be achieved in one packaging unit.

[0038] The present invention also provides a semiconductor device with a temperature sensor, which is fabricated by the preparation method described above, and includes: a substrate; a superjunction charge balance region is disposed on the substrate, and a body region is disposed on the superjunction charge balance region; a first shallow trench and a second shallow trench are disposed on the body region; a first polysilicon layer is disposed in both the first shallow trench and the second shallow trench; a second polysilicon layer is disposed in the second shallow trench and above the first polysilicon layer; a dielectric layer is disposed on the body region; a gate metal, a source metal, a cathode metal, and an anode metal are disposed on the dielectric layer; an active region is disposed on the body region; a source contact hole is disposed on the active region, and the source metal is connected to the source contact hole; a gate contact hole is disposed on the first polysilicon layer in the first shallow trench, and the gate metal is connected to the gate contact hole; an anode contact hole is disposed on the first polysilicon layer in the second shallow trench, and a cathode contact hole is disposed on the second polysilicon layer in the second shallow trench; the anode metal is connected to the anode contact hole, and the cathode metal is connected to the cathode contact hole.

[0039] Specifically, the temperature sensor structure is formed by the first polysilicon and the second polysilicon in the second shallow trench, and an oxide dielectric layer is disposed in the first shallow trench and the second shallow trench, which can isolate the superjunction charge balance region. By disposing the first shallow trench and the second shallow trench in the body region and the superjunction charge balance region, a temperature sensor structure capable of monitoring the junction temperature characteristics inside the MOSFET device in real time is integrated inside the chip epitaxial material. Without occupying the actual active area of the chip, the temperature sensor structure can more sensitively reflect the working state of the MOSFET device.

[0040] Optionally, the superjunction charge balance region includes a plurality of first-conductivity-type columns and a plurality of second-conductivity-type columns; the plurality of first-conductivity-type columns and the plurality of second-conductivity-type columns are alternately disposed on the substrate in sequence; the first shallow trench and the second shallow trench are both disposed on the first-conductivity-type columns.

[0041] Specifically, both the first shallow trench and the second shallow trench are disposed inside the first-conductivity-type columns, and the plurality of first-conductivity-type columns and the plurality of second-conductivity-type columns are alternately disposed. The number of the second shallow trenches can be adjusted as required on the plurality of first-conductivity-type columns. For example, the normal structural units and the structural units containing the temperature sensor can be distributed in a ratio of 1:1, 2:1, 3:1... n:1.

[0042] Optionally, a relief groove is formed on the first polysilicon layer of the second shallow trench; the second polysilicon layer is disposed in the relief groove; the cross section of the first polysilicon layer of the second shallow trench is L-shaped.

[0043] Specifically, the L-shaped first polysilicon layer aligns the anode contact hole corresponding to the first polysilicon layer of the second shallow trench and the cathode contact hole corresponding to the second polysilicon layer in a straight line, facilitating the connection of the anode contact hole.

[0044] In summary, the present invention has the following beneficial effects: By depositing the first polysilicon in the first shallow trench, etching and depositing the second polysilicon on the first polysilicon deposited in the second shallow trench, a temperature sensor structure is formed by the first polysilicon and the second polysilicon. And because the oxidation dielectric layer is deposited in the first shallow trench and the second shallow trench, and the oxidation dielectric layer has the property of electrical isolation, it can isolate the first polysilicon and the superjunction charge balance region, so as to facilitate the integration of the temperature sensor structure in the superjunction charge balance region and the body region. Without occupying the actual active area of the chip, a temperature sensor structure capable of real-time monitoring of the junction temperature characteristics inside the MOSFET device is added, which can more sensitively reflect the working state of the MOSFET device. Description of the Drawings

[0045] Figure 1 is a schematic layout diagram of the semiconductor device according to the second embodiment of the present invention;

[0046] Figure 2 is Figure 1 the cross-sectional structure schematic diagram of A-A' in

[0047] Figure 3 is Figure 1 the cross-sectional structure schematic diagram of B-B' in

[0048] Figure 4 is a schematic diagram of the structure of forming the second polysilicon along the B-B' cross-section of the semiconductor device according to the second embodiment of the present invention;

[0049] Figure 5 is a schematic diagram of the structure of forming the source region along the B-B' cross-section of the semiconductor device according to the second embodiment of the present invention;

[0050] Figure 6 is a schematic diagram of the structure of the semiconductor device according to the second embodiment of the present invention after depositing the dielectric layer along the B-B' cross-section.

[0051] In the figure: 1. Substrate; 21. First conductive type column; 22. Second conductive type column; 3. Body region; 4. First shallow trench; 5. Second shallow trench; 6. First polysilicon layer; 7. Second polysilicon layer; 8. Dielectric layer; 9. Gate metal; 10. Source metal; 11. Cathode metal; 12. Anode metal; 13. Source region; 14. Source contact hole; 15. Gate contact hole; 16. Anode contact hole; 17. Cathode contact hole; 18. Oxidation dielectric layer; 19. Drain. Detailed Embodiments

[0052] In order to make the objectives, features, and advantages of the present invention more obvious and understandable, the following provides a detailed description of the specific embodiments of the present invention with reference to the accompanying drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0053] In the present invention, unless otherwise clearly specified and defined, terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. The terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include one or more of such features.

[0054] The following describes the present invention in detail with reference to the accompanying drawings and embodiments.

[0055] Embodiment 1

[0056] This embodiment provides a method for manufacturing a semiconductor device with a temperature sensor, including: constructing a superjunction charge balance region on the surface of substrate 1, and forming a body region 3 on the top of the superjunction charge balance region;

[0057] Generating a first shallow trench 4 and a second shallow trench 5 on the body region 3;

[0058] Successively depositing an oxide dielectric layer 18 and a first polysilicon in the first shallow trench 4 and the second shallow trench 5;

[0059] Etching the first polysilicon in the second shallow trench 5, and depositing a second polysilicon above the first polysilicon in the second shallow trench 5;

[0060] Depositing a dielectric layer 8 on the surface of the body region 3, and etching a contact hole in the dielectric layer 8; the contact hole is in communication with the first polysilicon and the second polysilicon;

[0061] Forming a source electrode and a drain electrode 19.

[0062] Specifically, by depositing first polysilicon in the first shallow trench 4, etching and depositing second polysilicon on the first polysilicon deposited in the second shallow trench 5, a temperature sensor structure is formed by the first polysilicon and the second polysilicon. And because an oxidation dielectric layer 18 is deposited in the first shallow trench 4 and the second shallow trench 5, and the oxidation dielectric layer 18 has an electrical isolation property, it can isolate the first polysilicon and the superjunction charge balance region, so as to integrate the temperature sensor structure in the superjunction charge balance region and the body region 3. Without occupying the actual active area of the chip, a temperature sensor structure capable of real-time monitoring of the junction temperature characteristics inside the MOSFET device is added, which can more sensitively reflect the working state of the MOSFET device.

[0063] Among them, compared with the polysilicon structure in the prior art that forms multiple PN junctions above the epitaxial material, the temperature sensor structure formed by the first polysilicon and the second polysilicon in the second shallow trench 5 of the present invention has a relatively simple preparation method, does not require changing the lithography mask of conventional devices, and the preparation method of the present invention only changes the structural morphology of any shallow trench and does not change the adjacent cell size. Therefore, it can be compatible with the structures of various MOSFET devices and will not affect the reliability of the MOSFET device.

[0064] Optionally, constructing a superjunction charge balance region on the surface of the substrate 1 includes:

[0065] Epitaxially growing a first-conductivity-type buffer layer on the surface of the substrate 1;

[0066] Forming a first-conductivity-type epitaxial layer on the first-conductivity-type buffer layer, and etching a plurality of first deep trenches spaced apart on the first-conductivity-type epitaxial layer; the plurality of first deep trenches divide the first-conductivity-type epitaxial layer into a plurality of first-conductivity-type columns 21;

[0067] Performing a bottom injection process on the plurality of spaced-apart first deep trenches, and epitaxially growing second-conductivity-type columns 22 in the first deep trenches. The first-conductivity-type columns 21 and the second-conductivity-type columns 22 form a superjunction charge balance region.

[0068] Specifically, the substrate 1 is a first-conductivity-type substrate 1, and the substrate 1 is doped with a first-conductivity-type heavy doping. First deep trenches are formed on the first-conductivity-type epitaxial layer by a dry etching process, and after sacrificial oxidation treatment of the first deep trenches, a bottom injection process is performed, so as to epitaxially grow and form second-conductivity-type columns 22, and the superjunction charge balance region is composed of the first-conductivity-type columns 21 and the second-conductivity-type columns 22.

[0069] Among them, heavy doping means doping a large number of impurity atoms into a semiconductor material, which enhances conductivity, changes the space charge region, increases the barrier height, and narrows the bandgap. The depth of the first deep trench is usually set to 20 - 50 um, and the first deep trench has a trapezoidal shape with a wider top and a narrower bottom; the thickness of the sacrificial oxidation treatment is 200 - 600 Å, the temperature is 750 - 1100 °C, and medium-energy particle implantation equipment is used for bottom implantation, with an implantation energy of 100 KeV - 200 KeV.

[0070] Optionally, an oxide dielectric layer 18 and a first polysilicon are sequentially deposited in the first shallow trench 4 and the second shallow trench 5, including:

[0071] An oxide dielectric layer is formed on the top of the body region 3, the first shallow trench 4, and the second shallow trench 5 through a furnace tube process;

[0072] The first polysilicon is deposited in the first shallow trench 4 and the second shallow trench 5, and the first polysilicon is etched to be flush with the first conductive type epitaxial layer.

[0073] Specifically, both the first shallow trench 4 and the second shallow trench 5 pass through the body region 3 and are embedded in the first conductive type column 21; and an oxide dielectric layer is formed in the first shallow trench 4 and the second shallow trench 5 through a furnace tube process, thereby electrically isolating the first shallow trench 4 and the second shallow trench 5 from the first conductive type column 21. Among them, the first polysilicon is a self-doped first conductive type source species, and when etching the first polysilicon, a dry etching or chemical mechanical polishing process can be used.

[0074] Optionally, the first polysilicon in the second shallow trench 5 is etched, and a second polysilicon is deposited above the first polysilicon in the second shallow trench 5, including:

[0075] A pattern is defined on the polysilicon photomask in advance, and a window is opened in the area where the second shallow trench 5 is located;

[0076] Based on the polysilicon photomask, the second shallow trench 5 is etched, and the etching depth of the first polysilicon in the second shallow trench 5 is half or 2 / 3 or 1 / 3 of the depth of the second shallow trench 5;

[0077] The second polysilicon is deposited in the second shallow trench 5, and the second polysilicon is etched to be flush with the first conductive type epitaxial layer.

[0078] Specifically, the first polysilicon within the region where the second shallow trench 5 is located is etched through a polysilicon photomask, a part of the first polysilicon within the second shallow trench 5 is removed, and a second polysilicon is deposited on the first polysilicon by non-doped ion implantation. The non-doped ion type is a source species of the second conductivity type. Temperature monitoring within the first conductivity type column 21 is achieved through the current variations of the first polysilicon and the second polysilicon within the second shallow trench 5 at different temperatures.

[0079] Optionally, a body region 3 is formed at the top of the superjunction charge balance region, including:

[0080] The body region 3 is formed at the top of the superjunction charge balance region by lithography and doping with second conductivity type ions;

[0081] A thick field oxide layer is formed on the top of the body region 3, and the thick field oxide layer within the active region is etched away.

[0082] Specifically, the depth of the body region 3 is less than 3.0 um, the thickness of the thick field oxide layer is 3000A - 5000A, and the active region is the area on the silicon wafer where active devices are fabricated. By forming a thick field oxide layer on the top of the body region 3, the top of the body region 3 can be isolated.

[0083] Optionally, a dielectric layer 8 is deposited on the surface of the body region 3, and contact holes are etched within the dielectric layer 8; the contact holes are in communication with the first polysilicon and the second polysilicon, including:

[0084] A dielectric layer 8 is deposited on the surface of the body region 3, and gate contact holes 15, source contact holes 14, anode contact holes 16, and cathode contact holes 17 are etched within the dielectric layer 8; the gate contact holes 15 are on the first shallow trench 4, the source contact holes 14 are in the chip cell region, the anode contact holes 16 are on the second shallow trench 5 and on one side of the second shallow trench 5, and the anode contact holes 16 are in communication with the first polysilicon within the second shallow trench 5; the cathode contact holes 17 are on the second shallow trench 5 and on the other side of the second shallow trench 5, and the cathode contact holes 17 are in communication with the second polysilicon within the second shallow trench 5.

[0085] Specifically, the anode contact holes 16 and the cathode contact holes 17 are respectively connected to the first polysilicon and the second polysilicon within the second shallow trench 5 to facilitate connection to both ends of the temperature sensor.

[0086] Optionally, a gate metal 9 is deposited on the dielectric layer 8 at the gate contact hole 15, and the gate metal 9 communicates with the gate contact hole 15; a source metal 10 is deposited on the dielectric layer 8 at the source contact hole 14, and the source metal 10 communicates with the source contact hole 14; an anode metal 12 is deposited on the dielectric layer 8 at the anode contact hole 16, and the anode metal 12 communicates with the anode contact hole 16; a cathode metal 11 is deposited on the dielectric layer 8 at the cathode contact hole 17, and the cathode metal 11 communicates with the cathode contact hole 17;

[0087] The side of the substrate 1 away from the superjunction charge balance region is thinned to form a drain 19.

[0088] Specifically, by connecting the anode contact hole 16 through the anode metal 12, connecting the cathode contact hole 17 through the cathode metal 11, and using wire bonding in the package to connect the anode metal 12, cathode metal 11, source metal 10, gate metal 9 and drain metal, integration can be achieved in one package unit.

[0089] By integrating a temperature detection diode structure inside the first-conductivity-type epitaxial layer, using the linear relationship between the forward conduction voltage of the diode and temperature, without affecting the characteristics of the device itself, by improving the manufacturing process, the problem that the internal thermal characteristics of the device cannot be timely feedback is solved, the junction temperature is monitored timely and agilely, and the chip reliability is improved. Moreover, the temperature sensor structure formed by the present invention can be adjusted as needed in the active region. For example, the normal structural cell and the temperature sensor structure can be in a ratio of 1:1, 2:1, 3:1... n:1. Multiple temperature sensor units are integrated on the chip, which can be applied to chips of different sizes, are more evenly distributed, and the means of characterizing the junction temperature are more comprehensive.

[0090] Embodiment 2

[0091] This embodiment provides a semiconductor device with a temperature sensor, which is manufactured by the preparation method of Embodiment 1, as Figures 1-6As shown in the figure, it includes: a substrate 1; a superjunction charge balance region is provided on the substrate 1, and a body region 3 is provided on the superjunction charge balance region; a first shallow trench 4 and a second shallow trench 5 are provided on the body region 3; a first polysilicon layer 6 is provided in both the first shallow trench 4 and the second shallow trench 5; a second polysilicon layer 7 is provided in the second shallow trench 5 and above the first polysilicon layer 6; a dielectric layer 8 is provided on the body region 3; a gate metal 9, a source metal 10, a cathode metal 11, and an anode metal 12 are provided on the dielectric layer 8; an active region is provided on the body region 3; a source contact hole 14 is provided on the source region 13, and the source metal 10 is connected to the source contact hole 14; a gate contact hole 15 is provided on the first polysilicon layer 6 in the first shallow trench 4, and the gate metal 9 is connected to the gate contact hole 15; an anode contact hole 16 is provided on the first polysilicon layer 6 in the second shallow trench 5, and a cathode contact hole 17 is provided on the second polysilicon layer 7 in the second shallow trench 5; the anode metal 12 is connected to the anode contact hole 16, and the cathode metal 11 is connected to the cathode contact hole 17.

[0092] Specifically, the temperature sensor structure is formed by the first polysilicon and the second polysilicon in the second shallow trench 5, and an oxide dielectric layer 18 is provided in the first shallow trench 4 and the second shallow trench 5, which can isolate the superjunction charge balance region. By arranging the first shallow trench 4 and the second shallow trench 5 in the body region 3 and the superjunction charge balance region, a temperature sensor is integrated inside the chip epitaxial material. Without occupying the actual active area of the chip, a temperature sensor structure that can monitor the junction temperature characteristics inside the MOSFET device in real time is added, which can more sensitively reflect the working state of the MOSFET device. The substrate 1 is thinned on the side away from the superjunction charge balance region to form a drain 19.

[0093] Optionally, the superjunction charge balance region includes a plurality of first-conductivity-type columns 21 and a plurality of second-conductivity-type columns 22; the plurality of first-conductivity-type columns 21 and the plurality of second-conductivity-type columns 22 are alternately arranged on the substrate 1 in sequence; the first shallow trench 4 and the second shallow trench 5 are both arranged on the first-conductivity-type columns 21.

[0094] Specifically, the first shallow trench 4 and the second shallow trench 5 are both arranged inside the first-conductivity-type columns 21, and the plurality of first-conductivity-type columns 21 and the plurality of second-conductivity-type columns 22 are alternately arranged. The number of the second shallow trenches 5 can be adjusted as needed on the plurality of first-conductivity-type columns 21. For example, the normal structural units and the structural units containing the temperature sensor can be distributed in a ratio of 1:1, 2:1, 3:1... n:1.

[0095] Optionally, a relief groove is formed in the first polysilicon layer 6 of the second shallow trench 5; the second polysilicon layer 7 is arranged in the relief groove; the cross-section of the first polysilicon layer 6 in the second shallow trench 5 is L-shaped.

[0096] Specifically, the L-shaped first polysilicon layer 6 aligns the anodic contact hole 16 corresponding to the first polysilicon layer 6 of the second shallow trench 5 and the cathodic contact hole 17 corresponding to the second polysilicon layer 7 in a straight line, facilitating the connection to the anodic contact hole 16.

[0097] By fabricating temperature diode sensors formed by multiple first polysilicon and second polysilicon on the same substrate 1 and epitaxial material, connecting the two ends of the diode sensor through the anodic metal 12 and the cathodic metal 11 respectively, and using wire bonding for packaging to connect the anodic metal 12, cathodic metal 11, source metal 10, gate metal 9, and drain metal, integration can be achieved in one packaging unit, featuring convenience and strong applicability.

[0098] The above description is only a preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor device with a temperature sensor, characterized in that, Comprising: Construct a superjunction charge balance region on the substrate surface, and form a body region on top of the superjunction charge balance region; Generate a first shallow trench and a second shallow trench on the body region; Deposit an oxide dielectric layer and a first polysilicon in sequence in both the first shallow trench and the second shallow trench; Etch the first polysilicon in the second shallow trench, and deposit a second polysilicon above the first polysilicon in the second shallow trench; Deposit a dielectric layer on the surface of the body region, and etch a contact hole in the dielectric layer; the contact hole communicates with the first polysilicon and the second polysilicon; Form source and drain electrodes.

2. The manufacturing method of a semiconductor device with a temperature sensor according to claim 1, characterized in that, The constructing a superjunction charge balance region on the substrate surface includes: Epitaxially grow a buffer layer of a first conductivity type on the substrate surface; Form a first conductivity type epitaxial layer on the first conductivity type buffer layer, and etch a plurality of first deep trenches with spaced distribution on the first conductivity type epitaxial layer; the plurality of first deep trenches divide the first conductivity type epitaxial layer into a plurality of first conductivity type columns; Perform bottom implantation treatment on the spaced first deep trenches, and epitaxially grow second conductivity type columns in the first deep trenches, and the first conductivity type columns and the second conductivity type columns form a superjunction charge balance region.

3. The manufacturing method of a semiconductor device with a temperature sensor according to claim 2, characterized in that, The depositing an oxide dielectric layer and a first polysilicon in sequence in both the first shallow trench and the second shallow trench includes: Form an oxide dielectric layer on the top of the body region, in the first shallow trench, and in the second shallow trench by furnace tube process; Deposit a first polysilicon in the first shallow trench and the second shallow trench, and perform an etching treatment on the first polysilicon to etch the first polysilicon to be flush with the first conductivity type epitaxial layer.

4. The manufacturing method of a semiconductor device with a temperature sensor according to claim 3, characterized in that, The etching the first polysilicon in the second shallow trench and depositing a second polysilicon above the first polysilicon in the second shallow trench includes: Define a pattern on a polysilicon photomask in advance, and open a window in the region where the second shallow trench is located; Etch the second shallow trench based on the polysilicon photomask, and the etching depth of the first polysilicon in the second shallow trench is half or 2 / 3 or 1 / 3 of the depth of the second shallow trench; Deposit a second polysilicon in the second shallow trench, and perform an etching treatment on the second polysilicon to etch the second polysilicon to be flush with the first conductivity type epitaxial layer.

5. The manufacturing method of a semiconductor device with a temperature sensor according to claim 2, characterized in that, The forming a body region on the top of the superjunction charge balance region includes: Form a body region by lithography and doping implantation of second conductivity type ions on the top of the superjunction charge balance region; Form a thick field oxide layer on the top of the body region, and etch and remove the thick field oxide layer in the active region.

6. The manufacturing method of a semiconductor device with a temperature sensor according to claim 1, characterized in that, The depositing a dielectric layer on the surface of the body region and etching a contact hole in the dielectric layer; the contact hole communicates with the first polysilicon and the second polysilicon includes: Deposit a dielectric layer on the surface of the body region, and etch a gate contact hole, a source contact hole, an anode contact hole, and a cathode contact hole in the dielectric layer; the gate contact hole is on the first shallow trench, the source contact hole is in the chip cell region, the anode contact hole is on the second shallow trench and on one side of the second shallow trench, and the anode contact hole communicates with the first polysilicon in the second shallow trench; the cathode contact hole is on the second shallow trench and on the other side of the second shallow trench, and the cathode contact hole communicates with the second polysilicon in the second shallow trench.

7. The manufacturing method of a semiconductor device with a temperature sensor according to claim 1, characterized in that, Forming the source and drain includes: Depositing gate metal on the dielectric layer at the gate contact hole, the gate metal communicating with the gate contact hole; depositing source metal on the dielectric layer at the source contact hole, the source metal communicating with the source contact hole; depositing anode metal on the dielectric layer at the anode contact hole, the anode metal communicating with the anode contact hole; depositing cathode metal on the dielectric layer at the cathode contact hole, the cathode metal communicating with the cathode contact hole; Thinning the side of the substrate away from the superjunction charge balance region to form the drain.

8. A semiconductor device having a temperature sensor, characterized in that, Manufactured by the manufacturing method according to any one of claims 1-7, including: a substrate; a superjunction charge balance region is provided on the substrate, and a body region is provided on the superjunction charge balance region; a first shallow trench and a second shallow trench are provided on the body region; a first polysilicon layer is provided in both the first shallow trench and the second shallow trench; a second polysilicon layer is provided above the first polysilicon layer in the second shallow trench; a dielectric layer is provided on the body region; a gate metal, a source metal, a cathode metal, and an anode metal are provided on the dielectric layer; an active region is provided on the body region; a source contact hole is provided on the active region, and the source metal is connected to the source contact hole; a gate contact hole is provided on the first polysilicon layer in the first shallow trench, and the gate metal is connected to the gate contact hole; an anode contact hole is provided on the first polysilicon layer in the second shallow trench, and a cathode contact hole is provided on the second polysilicon layer in the second shallow trench; the anode metal is connected to the anode contact hole, and the cathode metal is connected to the cathode contact hole.

9. A semiconductor device with a temperature sensor according to claim 8, characterized in that, The superjunction charge balance region includes a plurality of first conductive type columns and a plurality of second conductive type columns; the plurality of first conductive type columns and the plurality of second conductive type columns are alternately arranged on the substrate in sequence; the first shallow trench and the second shallow trench are both provided on the first conductive type columns.

10. A semiconductor device with a temperature sensor according to claim 8, characterized in that, A relief groove is formed in the first polysilicon layer of the second shallow trench; the second polysilicon layer is arranged in the relief groove; the cross section of the first polysilicon layer of the second shallow trench is L-shaped.

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