P-GaN gate HEMT device with in-situ resistive passivation layer

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a p-GaN gate HEMT device with an in-situ resistive passivation layer. According to the core scheme, the p-GaN layer in the area outside the grid electrode is partially reserved, oxygen injection processing is carried out on the reserved p-GaN layer through the ICP technology, and the resistance value of the in-situ passivation layer can be accurately adjusted by adjusting and controlling the oxygen injection dosage. Different from a traditional insulation passivation method, the in-situ resistive passivation layer allows hole current to flow through the interior of the passivation layer, so that the surface potential of the device is linearly distributed, a depletion region below a grid electrode rapidly expands towards a drain electrode, local electric field accumulation is effectively avoided, and the electric field peak of a drift region is weakened. According to the in-situ resistive passivation scheme provided by the invention, by regulating and controlling the interface charge and optimizing the surface electric field, the coupling problem of the voltage withstanding performance and the on-resistance of the device is fundamentally solved. Meanwhile, according to the scheme, the dynamic characteristic of the device is remarkably improved, and the comprehensive performance of the device is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and more specifically, relates to a p-GaN gate HEMT device with an in-situ resistive passivation layer. Background Art

[0002] With the rapid development of social economy, people's requirements for power demand and management are constantly increasing. Especially in the field of power conversion, the application environment is becoming increasingly complex and challenging. The continuous progress of power semiconductor technology has significantly improved the utilization efficiency of electric energy. As one of the most promising wide-bandgap semiconductor materials, GaN has become an ideal choice for high-power switching applications due to its excellent properties such as high breakdown field strength, low dielectric constant, high electron mobility, and high thermal conductivity. In the design of power switches, to balance circuit safety and power loss, breakdown voltage and on-resistance are key parameters for evaluating device performance. However, the optimization paths of these two performances usually restrict each other, resulting in significant trade-off problems when improving performance. In addition, the channel layer of the GaN HEMT device is separated from the surface by only a barrier layer about ten nanometers thick, and the AlGaN / passivation layer interface has an important impact on the dynamic performance of the device. Therefore, optimizing the passivation layer and AlGaN interface problem is not only a key means to solve the trade-off problem between breakdown voltage and on-resistance, but also an effective way to improve the dynamic performance of the device.

[0003] Existing surface passivation technologies usually use insulating materials. Although these materials can effectively suppress interface leakage, they are limited in regulating the surface electric field distribution and have limited help in improving the breakdown voltage performance of the device. In addition, the growth process of the passivation layer may introduce interface contamination or cause surface damage. Even the low-damage ALD (Atomic Layer Deposition) passivation technology is difficult to completely avoid these problems. These defects often have a negative impact on the dynamic characteristics of the device. To overcome the above limitations, it is urgent to develop innovative surface passivation technologies, starting from optimizing the surface electric field distribution and regulating interface charges, to improve the breakdown voltage performance of the device and reduce the on-resistance. At the same time, interface contamination and surface damage should be avoided as much as possible to further improve the dynamic performance of the device. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a device solution with in-situ resistive passivation. By retaining part of the p-GaN as the passivation layer, surface contamination and process-induced damage are effectively reduced, and n-type traps in the barrier layer are compensated at the same time, thus significantly optimizing the dynamic performance of the device. The resistivity of the in-situ resistive passivation layer is adjusted by means of oxygen ion implantation. When the hole current passes through the resistive material, the surface potential of the device can be linearly distributed, thereby optimizing the electric field distribution on the surface. In addition, introducing positive charges on the surface can attract an equal amount of negative charges in the channel, increasing the concentration of two-dimensional electron gas (2DEG), thereby reducing the on-resistance. Through this technical solution, the fabricated device not only improves the breakdown voltage performance, but also reduces the on-resistance, while optimizing the dynamic characteristics, significantly improving the reliability of the device.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A p-GaN gate HEMT device with an in-situ resistive passivation layer, characterized in that it includes an in-situ resistive passivation layer 1, an Si substrate 2, a nucleation layer 3, a buffer layer 4, a channel layer 5, an interface layer 6, a barrier layer 7, a drain 8, a source 9, a p-type cap layer 10, and a gate 11;

[0007] The Si substrate 2, the nucleation layer 3, and the buffer layer 4 are stacked in sequence from bottom to top;

[0008] The channel layer 5 is located on the upper surface of the buffer layer 4, and the lateral width of the channel layer 5 is smaller than the lateral width of the buffer layer 4; the interface layer 6 is located on the upper surface of the channel layer 5, and the barrier layer 7 is located on the upper surface of the interface layer 6;

[0009] The drain 8 and the source 9 are respectively arranged on both sides of the upper surface of the barrier layer 7, and the lower ends of the drain 8 and the source 9 are embedded in the upper layer of the barrier layer 7. At the same time, there is a gap between the lower surfaces of the drain 8 and the source 9 and the upper surface of the barrier layer 7;

[0010] The in-situ resistive passivation layer 1 is located on the upper surface of the barrier layer 7 between the drain 8 and the source 9;

[0011] The p-type cap layer 10 is located on the upper surface of the middle part of the barrier layer 7, and the p-type cap layer 10 penetrates the in-situ resistive passivation layer 1 in the vertical direction of the device, dividing the in-situ resistive passivation layer 1 into two parts in the lateral direction of the device; the thickness of the p-type cap layer 10 is greater than the thickness of the in-situ resistive passivation layer 1;

[0012] The gate 11 is located on the upper surface of the p-type cap layer 10;

[0013] After the in-situ resistive passivation layer 1 is processed by oxygen implantation, it is equivalent to a variable resistor. When the hole current flows through the in-situ resistive passivation layer 1, the surface potential of the device shows a linear distribution, enabling the depletion region under the gate 11 to rapidly expand towards the drain 8 direction, thereby avoiding the surface electric field concentration phenomenon and increasing the breakdown voltage.

[0014] Further, the material used for the in-situ resistive passivation layer 1 is P-type doped GaN;

[0015] Further, the doping concentration range of the P-type doped resistive passivation layer 1 is 1×10 13 cm -3 —1×10 19 cm -3 ;

[0016] Further, the thickness range of the in-situ resistive passivation layer 1 is 2 - 70 nm;

[0017] Further, the length of the in-situ resistive passivation layer 1 is less than the length of the barrier layer;

[0018] Further, the in-situ resistive passivation layer 1 is in contact with the drain region 8 and the source region 9;

[0019] Further, by partially etching the p-type cap layer 10, the remaining p-type cap layer 10 is used as the in-situ resistive passivation layer 1;

[0020] Further, the thickness of the in-situ resistive passivation layer 1 is the same as the remaining thickness of the p-type cap layer 10;

[0021] Further, the in-situ resistive passivation layer 1 adjusts its resistance value by means of ICP oxygen ion implantation;

[0022] Further, the region of the in-situ resistive passivation layer 1 implanted with oxygen ions is the p-type cap layer 10 other than the gate 11 region;

[0023] The beneficial effects of the present invention are reflected in that by proposing a HEMT device with in-situ resistive passivation, the surface potential of the device shows a linear distribution, thereby optimizing the global electric field distribution and ensuring the interface quality to the greatest extent. This technical solution not only significantly improves the breakdown voltage performance of the device, but also effectively reduces the on-resistance, while improving the dynamic characteristics, thus comprehensively enhancing the comprehensive performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of a p-GaN gate HEMT device with an in-situ resistive passivation layer in an embodiment of the present invention;

[0025] Figure 2Schematic diagram of the structure of the in-situ resistive passivation layer proposed by the present invention;

[0026] Figure 3 Schematic diagram of the surface circuit equivalent of the in-situ resistive passivation device proposed by the present invention;

[0027] Figure 4 Schematic diagram of the surface potential distribution of the in-situ resistive passivation device proposed by the present invention;

[0028] Figure 5 Schematic diagram of the internal electric field distribution of the in-situ resistive passivation device proposed by the present invention;

[0029] Figure 6 Comparison chart (experimental data) of the breakdown voltages of the in-situ resistive passivation device and the conventional device proposed by the present invention;

[0030] Figure 7 Ratio chart (experimental data) of the dynamic / static resistances of the in-situ resistive passivation device and the conventional device proposed by the present invention;

[0031] Figure 8 Schematic diagram of the output characteristics of the conventional device proposed by the present invention (experimental data);

[0032] Figure 9 Schematic diagram of the output characteristics of the in-situ resistive passivation device proposed by the present invention (experimental data). Detailed implementation manners

[0033] The technical solutions of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] As Figure 1 shown, the structure of the in-situ resistive passivation device proposed by the present invention includes: an in-situ resistive passivation layer 1, a Si substrate 2, a nucleation layer 3, a buffer layer 4, a channel layer 5, an interface layer 6, a barrier layer 7, a drain 8, a source 9, a p-type capping layer 10, and a gate 11; the nucleation layer 3 is located on the Si substrate 2; the buffer layer 4 is located on the nucleation layer 3; the channel layer 5 is located on the buffer layer 4; the interface layer 6 is located on the channel layer 5; the barrier layer 7 is located on the interface layer 6, wherein a heterojunction structure is formed between the barrier layer 7 and the channel layer 5; the drain 8 is located on the channel layer 4 to form an ohmic contact; the source 9 is located on the channel layer 4 to form an ohmic contact; the p-type capping layer 10 is located on the barrier layer 7; the gate 11 is located on the p-type capping layer 10 to form a Schottky contact; the in-situ resistive passivation layer 1 is located on the barrier layer 7;

[0035] The working mechanism of the proposed in-situ resistive passivation device is described below with reference to the accompanying drawings:

[0036] As Figure 2As shown, when etching the p-type cap layer 10 of the device with in-situ resistive passivation proposed by the present invention, an appropriate thickness needs to be reserved (conventional devices require the p-type cap layer in the non-gate region to be completely etched away). To solve the problem of the depletion of the two-dimensional electron gas in the channel by the remaining p-type cap layer 10 and optimize the electric field distribution on the device surface, oxygen implantation treatment must be performed on the in-situ resistive passivation layer. After the oxygen implantation treatment, the in-situ resistive passivation layer is divided into an insulating region and a high-resistance region, and its resistance value can be controlled by adjusting the oxygen implantation dose, which is equivalent to adding a variable resistor on the device surface (such as Figure 3 ). When the hole current flows through the in-situ resistive passivation layer, the surface potential of the device shows a linear distribution (such as Figure 4 ), which causes the depletion region under the gate to rapidly expand towards the drain direction, thus avoiding the surface electric field concentration phenomenon (such as Figure 5 ), and improving the breakdown voltage. From the perspective of charge conservation, the additional positive charges on the surface will attract more electrons in the channel, increasing the concentration of the two-dimensional electron gas, thus significantly reducing the on-resistance of the device. In addition, since the in-situ resistive passivation layer is essentially a part of the p-type cap layer, it can avoid the interface state problem caused by secondary process pollution. Some holes in the in-situ resistive layer can fill the n-type traps in the barrier layer, effectively optimizing the dynamic characteristics of the device. In summary, the proposed in-situ resistive passivation device not only significantly improves the breakdown voltage performance of the device, but also effectively reduces the on-resistance and optimizes the dynamic characteristics, thus greatly improving the comprehensive performance of the device. (such as Figures 6 - 9 ).

[0037] The structure of the present invention can be prepared by the following method, and the process steps are as follows:

[0038] 1. Epitaxially grow an AlN nucleation layer 3, an (Al)GaN buffer layer 4, a channel layer 5, an interface layer 6, a barrier layer 7, and a p-type cap layer 10 on the substrate 2 in sequence.

[0039] 2. Realize the blocking of the conductive channel by etching. Use SiO2 as a hard mask to partially etch the p-type cap layer 10, and determine the etching stop position according to the required thickness of the in-situ passivation layer. Use an ICP etching machine to perform oxygen implantation treatment on the remaining p-type cap layer 10, and determine the ICP treatment time according to the required resistance value.

[0040] 3. Etch the multi-layer AlGaN / GaN heterojunction in the source-drain contact region of the active region, and deposit metal to form an ohmic contact.

[0041] 4. Deposit gate metal in the gate region to form a Schottky contact with the P-type material.

Claims

1. A p-GaN gate HEMT device with an in-situ resistive passivation layer, characterized in that, It includes an in-situ resistive passivation layer (1), a Si substrate (2), a nucleation layer (3), a buffer layer (4), a channel layer (5), an interface layer (6), a barrier layer (7), a drain (8), a source (9), a p-type cap layer (10), and a gate (11); The Si substrate (2), the nucleation layer (3), and the buffer layer (4) are stacked in sequence from bottom to top; The channel layer (5) is located on the upper surface of the buffer layer (4), and the lateral width of the channel layer (5) is smaller than the lateral width of the buffer layer (4); the interface layer (6) is located on the upper surface of the channel layer (5), and the barrier layer (7) is located on the upper surface of the interface layer (6); The drain (8) and the source (9) are respectively arranged on both sides of the upper surface of the barrier layer (7), and the lower ends of the drain (8) and the source (9) are embedded in the upper layer of the barrier layer (7). At the same time, there is a gap between the lower surfaces of the drain (8) and the source (9) and the upper surface of the barrier layer (7); The in-situ resistive passivation layer (1) is located on the upper surface of the barrier layer (7) between the drain (8) and the source (9); The p-type cap layer (10) is located on the upper surface of the middle part of the barrier layer (7), and the p-type cap layer (10) penetrates the in-situ resistive passivation layer (1) in the vertical direction of the device, dividing the in-situ resistive passivation layer (1) into two parts in the lateral direction of the device; the thickness of the p-type cap layer (10) is greater than the thickness of the in-situ resistive passivation layer (1); The gate (11) is located on the upper surface of the p-type cap layer (10); After the in-situ resistive passivation layer (1) undergoes oxygen implantation treatment, it is equivalent to a variable resistor. When a hole current flows through the in-situ resistive passivation layer (1), the surface potential of the device shows a linear distribution, enabling the depletion region under the gate (11) to rapidly expand towards the drain (8) direction, thereby avoiding the surface electric field concentration phenomenon and increasing the breakdown voltage.

2. The p-GaN gate HEMT device with an in-situ resistive passivation layer according to claim 1, characterized in that, The in-situ resistive passivation layer (1) is formed by partially etching the p-type cap layer (10).

3. A p-GaN gate HEMT device with an in-situ resistive passivation layer according to claim 1, wherein, The material used for the in-situ resistive passivation layer is p-doped GaN, p-doped AlGaN, AlGaN, GaN, or other non-insulating materials.

4. A p-GaN gate HEMT device with an in-situ resistive passivation layer according to claim 1, characterized in that, The doping concentration range of the in-situ resistive passivation layer (1) is 1×10 3 cm -3 —1×10 19 cm -3 .

5. The p-GaN gate HEMT device with an in-situ resistive passivation layer according to claim 1, wherein, The thickness range of the in-situ resistive passivation layer (1) is 2 - 70 nm.

6. The p-GaN gate HEMT device with an in-situ resistive passivation layer according to claim 1, wherein, The in-situ resistive passivation layer (1) adjusts its resistance value by means of ICP oxygen ion implantation.

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