PIN junction-based low-grid electric leakage p-GaN HEMT device and preparation method thereof
By introducing PIN junction structure and gradient-doped p-AlGaN layer into the p-GaN HEMT device, the problems of large gate leakage and low threshold voltage are solved, and p-GaN HEMT devices with high switching speed and high breakdown voltage are realized, extending device life and reducing power loss.
Patent Information
- Application Number
- CN202510710762.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-08-01
AI Technical Summary
Existing p-GaN HEMT devices have problems such as large gate leakage, low threshold voltage and slow switching speed, especially when using Schottky gate metal, resulting in a shortened device life and an increased power loss.
Using a PIN junction structure, by setting a lightly doped semiconductor layer and a heavily doped semiconductor layer between the gate electrode and the p-AlGaN layer, an ohmic contact is formed, and combined with the gradient-doped p-AlGaN layer, the use of the dielectric layer is avoided and high reliability and high breakdown voltage is achieved.
It effectively reduces gate leakage, improves the threshold voltage and switching speed of the device, reduces power loss, extends device life, and increases gate breakdown voltage.
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Figure CN120417433A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of microelectronic technology, and particularly relates to a low-gate-leakage p-GaN HEMT device based on a PIN junction and a preparation method thereof. Background Art
[0002] GaN-based power devices have become an important application field for a new generation of power switching devices due to their advantages such as wide bandgap, high mobility, and high breakdown field strength. Affected by the polarization effect and piezoelectric effect, a two-dimensional electron gas with a high concentration and high saturation drift velocity is generated in the AlGaN / GaN heterojunction without doping. Using it as a conductive channel can provide a large output current, and such devices are widely used in power radio frequency circuits.
[0003] GaN-based power devices usually belong to normally-off devices. Normally-off devices have the characteristic of operating under a positive threshold voltage, are safer to operate, and have a fast switching response speed, making them an ideal choice for power switch applications. Among them, p-GaN can lower the Fermi level of the two-dimensional electron gas in the channel below the conduction band to achieve the normally-off characteristic of the device; when the gate voltage exceeds the threshold voltage of the device, the Fermi level of the two-dimensional electron gas in the channel returns above the conduction band, and the two-dimensional electron gas is generated, thereby realizing the device turn-on. However, the gate leakage channel introduced by this turn-on mode causes a large number of holes to be injected into the conductive channel, resulting in gate degradation, reducing the carrier concentration in the channel, increasing the power loss in the circuit, limiting the gate service life of the p-GaN HEMT power device. At the same time, due to the low activation rate of the Mg dopant in p-GaN, the threshold voltage of the p-GaN HEMT is relatively low. In addition, due to the use of a Schottky gate metal, the gate metal not aligned with p-GaN will reduce the switching speed of the device. Therefore, it is very necessary to provide a p-GaN enhanced GaN HEMT device with a high switching speed, a high threshold voltage, and low gate leakage. Summary of the Invention
[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-gate-leakage p-GaN HEMT device based on a PIN junction and a preparation method thereof. The technical problems to be solved by the present invention are achieved through the following technical solutions:
[0005] In a first aspect, the present invention provides a low-gate-leakage p-GaN HEMT device based on a PIN junction, including:
[0006] A substrate, a buffer layer, a channel layer, and a barrier layer stacked in sequence;
[0007] A source electrode and a drain electrode, spaced apart on the upper surface of the barrier layer;
[0008] The p-AlGaN layer is located on the upper surface of the barrier layer and between the source electrode and the drain electrode;
[0009] The lightly doped semiconductor layer is located on the upper surface of the p-AlGaN layer;
[0010] The heavily doped semiconductor layer is located on the upper surface of the lightly doped semiconductor layer;
[0011] The gate electrode is located on the upper surface of the heavily doped semiconductor layer.
[0012] In a second aspect, the present invention provides a method for manufacturing a p-GaN HEMT device with low gate leakage based on a PIN junction, which is used to manufacture the p-GaN HEMT device with low gate leakage based on a PIN junction provided above, and includes:
[0013] Provide a substrate;
[0014] Grow an epitaxial wafer of a buffer layer, a channel layer, a barrier layer, a p-AlGaN layer, a lightly doped semiconductor layer, and a heavily doped semiconductor layer on the substrate in sequence to form a heterojunction;
[0015] Perform photolithography on the upper surface of the epitaxial wafer to reserve a gate electrode region; use an etching process to etch away the heavily doped semiconductor layer, the lightly doped semiconductor layer, and the p-AlGaN layer corresponding to the region outside the gate electrode region, exposing a part of the barrier layer;
[0016] Deposit an ohmic stack metal on the upper surface of the exposed barrier layer respectively to form a source electrode and a drain electrode, and perform annealing to form an ohmic contact of the source electrode and an ohmic contact of the drain electrode respectively;
[0017] Perform ion implantation or etching on the barrier layer and the channel layer to achieve device isolation;
[0018] Perform photolithography in the gate electrode region and deposit a gate stack metal in the gate electrode region to form a gate electrode.
[0019] Advantages of the present invention:
[0020] A p-GaN HEMT device with low gate leakage based on a PIN junction and a preparation method thereof provided by the present invention include a substrate, as well as a buffer layer, a channel layer, and a barrier layer stacked on the substrate, a p-AlGaN layer, a source electrode, and a drain electrode provided on the barrier layer. The source electrode and the drain electrode are respectively located on both sides of the p-AlGaN layer and are arranged at intervals. A lightly doped semiconductor layer, a heavily doped semiconductor layer, and a gate electrode are stacked on the p-AlGaN layer. In the present invention, a lightly doped semiconductor layer and a heavily doped semiconductor layer are provided on the p-AlGaN layer. The heavily doped semiconductor layer (heavily doped n-type semiconductor layer) is in direct contact with the gate electrode metal. The heavily doped semiconductor layer is beneficial to achieving an ohmic contact with the gate electrode metal, enabling the gate electrode voltage to be evenly distributed on the p-AlGaN, which is beneficial to reducing the channel resistance. The lightly doped semiconductor layer is for further improving the gate breakdown voltage design. The low doping concentration can achieve a larger depletion region thickness, which is beneficial to maintaining a higher breakdown voltage.
[0021] The following will further describe the present invention in detail with reference to the drawings and embodiments. Description of the Drawings
[0022] Figure 1 is a schematic diagram of a p-GaN HEMT device with low gate leakage based on a PIN junction provided by an embodiment of the present invention;
[0023] Figure 2a is a schematic diagram of the electric field comparison between a conventional p-GaN HEMT and a p-GaN HEMT with a PIN gate structure provided by an embodiment of the present invention;
[0024] Figure 2b is a schematic diagram of the output characteristic curve under a positive gate voltage provided by an embodiment of the present invention;
[0025] Figure 3 is a schematic diagram of the comparison with different doping concentrations of the lightly doped semiconductor layer provided by an embodiment of the present invention;
[0026] Figure 4 is a schematic diagram of the threshold voltage and output current of a p-GaN HEMT device provided by an embodiment of the present invention;
[0027] Figure 5 is a schematic diagram of the comparison with different doping concentrations of the heavily doped semiconductor layer provided by an embodiment of the present invention;
[0028] Figure 6 is another schematic diagram of the threshold voltage and output current of a p-GaN HEMT device provided by an embodiment of the present invention;
[0029] Figure 7It is a flowchart of a preparation method of a low-gate-leakage P-GaN HEMT device based on a PIN junction provided by an embodiment of the present invention;
[0030] Figures 8a - 8g It is a schematic diagram of a preparation method of a low-gate-leakage p-GaN HEMT device based on a PIN junction provided by an embodiment of the present invention. Detailed implementation manners
[0031] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.
[0032] In the existing technical solutions, a dielectric layer is inserted between the gate electrode and the p-GaN layer to form a MIS (metal-oxide-semiconductor) gate to reduce gate leakage. However, the interface states and defects introduced by the dielectric layer will cause the threshold voltage of the device to drift.
[0033] In view of this, the present invention provides a low-gate-leakage p-GaN HEMT device based on a PIN junction. By using a graded-doped p-AlGaN layer, it not only eliminates the need for the preparation process of the dielectric layer, is simple and effective, but also will not cause threshold voltage drift, and can fabricate high-reliability enhancement-mode devices. At the same time, a lightly doped semiconductor layer and a heavily doped semiconductor layer are provided between the gate electrode and the p-AlGaN layer to form a PIN gate electrode structure. The PIN gate electrode structure p-GaN HEMT has a higher gate breakdown voltage than the PN gate electrode structure p-GaN HEMT.
[0034] Please refer to Figure 1 , Figure 1 It is a schematic diagram of a low-gate-leakage p-GaN HEMT device based on a PIN junction provided by an embodiment of the present invention. A low-gate-leakage p-GaN HEMT device based on a PIN junction provided by the present invention includes:
[0035] A substrate, a buffer layer, a channel layer, and a barrier layer stacked in sequence;
[0036] A source electrode and a drain electrode, spaced apart on the upper surface of the barrier layer;
[0037] A p-AlGaN layer, located on the upper surface of the barrier layer and between the source electrode and the drain electrode;
[0038] A lightly doped semiconductor layer, located on the upper surface of the p-AlGaN layer;
[0039] A heavily doped semiconductor layer, located on the upper surface of the lightly doped semiconductor layer;
[0040] A gate electrode, located on the upper surface of the heavily doped semiconductor layer.
[0041] Specifically, please continue to refer toFigure 1 , the low gate leakage p-GaN HEMT device provided in this embodiment includes a substrate, and a buffer layer, a channel layer, and a barrier layer stacked on the substrate, a p-AlGaN layer, a source electrode, and a drain electrode provided on the barrier layer. The source electrode and the drain electrode are respectively located on both sides of the p-AlGaN layer and are arranged at intervals. A lightly doped semiconductor layer, a heavily doped semiconductor layer, and a gate electrode are stacked on the p-AlGaN layer. The orthographic projection of the gate electrode, the orthographic projection of the heavily doped semiconductor layer, and the orthographic projection of the lightly doped semiconductor layer overlap, that is, the structures of the gate electrode, the p-AlGaN layer, the heavily doped semiconductor layer, and the lightly doped semiconductor layer are the same. The orthographic projection of the gate electrode does not overlap with the orthographic projections of other heavily doped semiconductor layers and lightly doped semiconductor layers, that is, the structures of the gate electrode, the p-AlGaN layer, the heavily doped semiconductor layer, and the lightly doped semiconductor layer are different. In this embodiment, a lightly doped semiconductor layer and a heavily doped semiconductor layer are provided on the p-AlGaN layer. The heavily doped semiconductor layer (heavily doped n-type semiconductor layer) is in direct contact with the gate electrode metal. The heavily doped semiconductor layer is conducive to achieving an ohmic contact with the gate electrode metal, enabling the gate electrode voltage to be evenly distributed on the p-AlGaN, which is beneficial to reducing the channel resistance; the lightly doped semiconductor layer (lightly doped p-type semiconductor layer) is for further improving the gate breakdown voltage design. The low doping concentration can achieve a larger depletion region thickness, which is beneficial to maintaining a higher breakdown voltage; it can be understood that by providing a lightly doped semiconductor layer and a heavily doped semiconductor layer on the p-AlGaN layer, a PIN structure is formed, and its breakdown voltage characteristics are used to enhance the gate electrode breakdown characteristics. The purpose of providing the heavily doped semiconductor layer is to form a quasi-self-aligned characteristic and reduce the channel on-resistance.
[0042] As Figure 2a and Figure 2b shown, Figure 2a is a schematic diagram of the electric field comparison between the conventional p-GaN HEMT and the p-GaN HEMT with a PIN gate structure provided by an embodiment of the present invention. It can be found that the PIN gate stack reduces the peak electric field in the semiconductor body and has the function of effectively improving the gate breakdown voltage; Figure 2b A schematic diagram of the output characteristic curve under the forward gate voltage provided by an embodiment of the present invention. The channel on-resistance of the PIN structure is 13.8 Ω·mm, and that of the conventional structure is 15.4 Ω·mm. It can be seen that the PIN structure reduces the channel on-resistance and reduces the circuit conduction power consumption.
[0043] In an optional embodiment of the present invention, the doping concentration of the lightly doped semiconductor layer is 1e15~1e18 cm -3 .
[0044] Specifically, in this embodiment, as the concentration of the lightly doped semiconductor layer decreases, the energy band becomes flatter, presenting a wider depletion region width, which is beneficial to improving the gate breakdown voltage and threshold voltage of the device. It can be understood that after the doping concentration of the lightly doped semiconductor layer decreases, the depletion region formed with the heavily doped semiconductor layer becomes wider, which can improve the threshold voltage and gate breakdown voltage. For example, Figure 3 and Figure 4 , Figure 3 is a schematic diagram of the comparison of different doping concentrations of the lightly doped semiconductor layer provided by an embodiment of the present invention, Figure 4 is a schematic diagram of the threshold voltage and output current of the p-GaN HEMT device provided by an embodiment of the present invention.
[0045] In an alternative embodiment of the present invention, the doping concentration of the heavily doped semiconductor layer is 1e18 - 5e19 cm -3 .
[0046] Specifically, in this embodiment, as the concentration of the heavily doped semiconductor layer increases, the energy band becomes more inclined, presenting a narrower depletion region width, which can achieve better gate control ability, increase the switching speed and output current of the device. It can be understood that after the doping concentration of the heavily doped semiconductor layer increases, better ohmic characteristics are formed with the gate electrode metal, the gate voltage is more evenly distributed, and the channel resistance decreases. However, as the doping concentration increases, the depletion region formed with the underlying lightly doped semiconductor becomes narrower, which will reduce the threshold voltage and gate breakdown voltage. Therefore, the doping concentration of the heavily doped layer needs to be comprehensively considered according to the actual situation. For example, Figure 5 and 6 shown, Figure 5 is a schematic diagram of the comparison of different doping concentrations of the heavily doped semiconductor layer provided by an embodiment of the present invention, Figure 6 is another schematic diagram of the threshold voltage and output current of the p-GaN HEMT device provided by an embodiment of the present invention.
[0047] It should be noted that in the present invention, the energy band shape is regulated by adjusting the thickness and doping concentration of the lightly doped semiconductor layer and the heavily doped semiconductor layer, and then the threshold voltage of the device is regulated. For example, a thick lightly doped semiconductor layer and a low doping concentration can increase the threshold voltage of the device.
[0048] In an alternative embodiment of the present invention, the Al component in the middle decreases, and the p-type doping concentration of the p-AlGaN layer increases;
[0049] Along the direction perpendicular to the substrate, the proportion of the Al component in the p-AlGaN layer gradually increases from bottom to top.
[0050] Specifically, in this embodiment, a high electric field strength and gate electrode breakdown occur at the top of p-AlGaN. The top of the graded p-AlGaN layer is the side with a higher Al composition. The side with a higher Al composition is in contact with the lightly doped semiconductor layer. Compared with the scheme where the side with a lower Al composition is in contact with the lightly doped semiconductor layer, p-AlGaN has a higher bandgap width and breakdown field strength, which can improve the gate breakdown voltage of the p-GaN HEMT device. In addition, the bottom of p-AlGaN has a lower Al composition, which is beneficial to achieving a high Mg doping concentration and is beneficial to improving the threshold voltage of p-GaN HEMT.
[0051] In an alternative embodiment of the present invention, as Figure 1 shown, it further includes: an insulating layer; the insulating layer covers the exposed surfaces of the source electrode, drain electrode, and gate electrode, as well as the exposed sides of the p-AlGaN layer, lightly doped semiconductor layer, and heavily doped semiconductor layer;
[0052] The insulating layer includes a plurality of openings, which are respectively located on the upper surfaces of the source electrode, drain electrode, and gate electrode, and are used to expose at least part of the surfaces of the source electrode, drain electrode, and gate electrode.
[0053] Based on the same inventive concept, please refer to Figure 7 , Figure 7 which is a flowchart of a method for manufacturing a p-GaN HEMT device with low gate leakage based on a PIN junction provided by an embodiment of the present invention. The present invention also provides a method for manufacturing a p-GaN HEMT device with low gate leakage based on a PIN junction, which is used to manufacture the p-GaN HEMT device with low gate leakage based on a PIN junction provided by the above embodiments of the present invention. For the device embodiments, please refer to the above, and details will not be described here again; the manufacturing method includes:
[0054] S101. Provide a substrate;
[0055] S102. Grow an epitaxial wafer of a buffer layer, a channel layer, a barrier layer, a p-AlGaN layer, a lightly doped semiconductor layer, and a heavily doped semiconductor layer on the substrate in sequence to form a heterojunction;
[0056] S103. Perform photolithography on the upper surface of the epitaxial wafer to reserve a gate electrode region; use an etching process to etch away the heavily doped semiconductor layer, lightly doped semiconductor layer, and p-AlGaN layer corresponding to the region outside the gate electrode region, and expose part of the barrier layer;
[0057] S104. Deposit ohmic stack metals on the upper surface of the exposed barrier layer respectively to form a source electrode and a drain electrode, and perform annealing to form an ohmic contact of the source electrode and an ohmic contact of the drain electrode respectively;
[0058] S105. Perform ion implantation or etching on the barrier layer and the channel layer to achieve device isolation;
[0059] S106. Perform photolithography in the gate electrode region and deposit gate stack metal in the gate electrode region to form a gate electrode.
[0060] In an optional embodiment of the present invention, the preparation process of the p-AlGaN layer includes:
[0061] Using a metal organic chemical vapor deposition (MOCVD) apparatus, dynamically adjust the gas phase flow rate ratio of trimethylaluminum (TMAl) and trimethylgallium (TMGa) to achieve a gradually increasing Al component from bottom to top. During the epitaxial growth process, gradually increase the gas phase flow rate of trimethylaluminum (TMAl) to achieve a gradual change of the p-AlGaN from a low component to a high component from bottom to top.
[0062] In an optional embodiment of the present invention, it further includes:
[0063] Deposit an insulating layer on the surfaces exposed by the source electrode, the drain electrode, and the gate electrode, as well as on the side surfaces exposed by the p-AlGaN layer, the lightly doped semiconductor layer, and the heavily doped semiconductor layer;
[0064] Open holes in the insulating layer, respectively located on the upper surfaces of the source electrode, the drain electrode, and the gate electrode, for exposing at least partial surfaces of the source electrode, the drain electrode, and the gate electrode.
[0065] In an optional embodiment of the present invention, the ohmic stack metal includes Ti, Al, Ni, and Au.
[0066] In an optional embodiment of the present invention, the gate stack metal includes Ni and Au.
[0067] In an optional embodiment of the present invention, please refer to Figures 8a - 8g , Figures 8a - 8g is a schematic diagram of a method for preparing a low gate leakage p-GaN HEMT device based on a PIN junction provided by an embodiment of the present invention. The low gate leakage p-GaN HEMT device based on a PIN junction is prepared through the following process, specifically:
[0068] S1. Provide a substrate, as Figure 8a shown; optionally, the substrate can be one of Si, SiC, or sapphire.
[0069] S2. Use a Metal-Organic Chemical Vapor Deposition (MOCVD) equipment to grow an epitaxial wafer of a buffer layer, a channel layer, a barrier layer, a p-AlGaN layer, a lightly doped semiconductor layer, and a heavily doped semiconductor layer on a substrate in sequence to form a heterojunction of heavily doped semiconductor layer / lightly doped semiconductor layer / p-AlGaN / AlGaN / GaN, as Figure 8b shown; Optionally, the buffer layer is made of GaN material with a thickness of 0.5 - 5 μm, the channel layer is made of i-GaN material with a thickness of 100 - 900 nm, the barrier layer is made of AlGaN material with a thickness of 5 - 50 nm, the doping of the p-AlGaN layer is 1e19 cm-3 - 5e19 cm -3 , with a thickness of 50 - 150 nm, and the doping concentration of the heavily doped semiconductor layer is 5e17 cm-3 - 3e19 cm -3 , with a thickness of 1 - 50 nm.
[0070] S3. Etch the epitaxial wafer and retain the gate electrode region; use an Inductively Coupled Plasma (ICP) dry etching technique to etch away the P-type semiconductor layer, In2O3 layer, NiO layer, and p-GaN layer corresponding to the region outside the gate electrode region to expose part of the barrier layer, as Figure 8c shown.
[0071] S4. Use an electron beam evaporation equipment to deposit an ohmic stack metal of Ti / Al / Ni / Au = 20 / 160 / 55 / 45 nm on the upper surface of the exposed barrier layer to form source and drain electrodes, and perform rapid annealing for 60 s at a temperature of 860 °C in an N2 atmosphere to form ohmic contacts of the source and drain electrodes, as Figure 8d shown.
[0072] S5. Use an ion implantation or etching equipment for ion implantation or etching to achieve device isolation, as shown in 8e.
[0073] S6. Perform photolithography in the gate electrode region and use an electron beam evaporation equipment to deposit the gate stack metal in the gate electrode region to form a gate electrode, as shown in 8f.
[0074] S7. Use a metal organic chemical vapor deposition equipment to deposit an insulating layer on the exposed surface of the entire device, that is, deposit a 120-nm-thick SiN passivation layer, as shown in 8g.
[0075] S8. The inductively coupled plasma dry etching technique is used to open holes and etch on the insulating layer. The etching gas is CF4 / O2, with a flow rate of 25 / 5 sccm, a chamber pressure of 5 mTorr, an ICP upper electrode power of 80 W, and a lower electrode power of 10 W. Openings are formed above the source electrode, drain electrode, and gate electrode respectively, exposing the upper surfaces of the source electrode, drain electrode, and gate electrode, as shown in Figure 8g.
[0076] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant are intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the article or device including the said element. "Connection" or "connected" and other similar words are not limited to physical or mechanical connection, but may include electrical connection, whether direct or indirect. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.
[0077] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.
[0078] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.
Claims
1. A low gate leakage p-GaN HEMT device based on a PIN junction, characterized in that, Comprising: A substrate, a buffer layer, a channel layer, and a barrier layer stacked in sequence; A source electrode and a drain electrode, spaced apart on the upper surface of the barrier layer; A p-AlGaN layer, located on the upper surface of the barrier layer and between the source electrode and the drain electrode; A lightly doped semiconductor layer, located on the upper surface of the p-AlGaN layer; A heavily doped semiconductor layer, located on the upper surface of the lightly doped semiconductor layer; A gate electrode, located on the upper surface of the heavily doped semiconductor layer.
2. The low gate leakage p-GaN HEMT device based on a PIN junction according to claim 1, wherein The doping concentration of the lightly doped semiconductor layer is 1e15 to 1e18 cm -3 .
3. The p-GaN HEMT device with low gate leakage based on PIN junction according to claim 1, characterized in that The doping concentration of the heavily doped semiconductor layer is 1e18 to 5e19 cm -3 .
4. The p-GaN HEMT device with low gate leakage based on PIN junction according to claim 1, wherein The Al component in the p-AlGaN layer decreases, and the p-type doping concentration of the p-AlGaN layer increases; Along the direction perpendicular to the substrate, the proportion of the Al component in the p-AlGaN layer gradually increases from bottom to top.
5. The p-GaN HEMT device with low gate leakage based on PIN junction according to claim 1, wherein Further comprising: An insulating layer; The insulating layer covers the exposed surfaces of the source electrode, the drain electrode, and the gate electrode, as well as the exposed sides of the p-AlGaN layer, the lightly doped semiconductor layer, and the heavily doped semiconductor layer; The insulating layer includes a plurality of openings, respectively located on the upper surfaces of the source electrode, the drain electrode, and the gate electrode, for exposing at least part of the surfaces of the source electrode, the drain electrode, and the gate electrode.
6. A preparation method of a low gate leakage p-GaN HEMT device based on a PIN junction, which is used to prepare the low gate leakage p-GaN HEMT device based on a PIN junction according to any one of claims 1 to 5, and is characterized in that, Comprising: Providing a substrate; Growing epitaxial wafers of a buffer layer, a channel layer, a barrier layer, a p-AlGaN layer, a lightly doped semiconductor layer, and a heavily doped semiconductor layer on the substrate in sequence to form a heterojunction; Performing photolithography on the upper surface of the epitaxial wafer to reserve a gate electrode region; Using an etching process to etch away the heavily doped semiconductor layer, the lightly doped semiconductor layer, and the p-AlGaN layer corresponding to the region outside the gate electrode region, exposing part of the barrier layer; Depositing ohmic stack metals on the exposed upper surface of the barrier layer to form a source electrode and a drain electrode respectively, and performing annealing to form an ohmic contact of the source electrode and an ohmic contact of the drain electrode respectively; Performing ion implantation or etching on the barrier layer and the channel layer to achieve device isolation; Performing photolithography on the gate electrode region and depositing gate stack metals in the gate electrode region to form a gate electrode.
7. The manufacturing method of the low gate leakage p-GaN HEMT device based on PIN junction according to claim 6, characterized in that, The preparation process of the p-AlGaN layer includes: Using a metalorganic chemical vapor deposition device to dynamically adjust the gas phase flow ratio of trimethylaluminum and trimethylgallium to achieve a gradual increase in the Al component from bottom to top.
8. The preparation method of the low gate leakage p-GaN HEMT device based on PIN junction according to claim 6, characterized in that, Further comprising: Depositing an insulating layer on the exposed surfaces of the source electrode, the drain electrode, and the gate electrode, as well as the exposed sides of the p-AlGaN layer, the lightly doped semiconductor layer, and the heavily doped semiconductor layer; Opening holes in the insulating layer, respectively located on the upper surfaces of the source electrode, the drain electrode, and the gate electrode, for exposing at least part of the surfaces of the source electrode, the drain electrode, and the gate electrode.
9. The preparation method of the low-gate-leakage p-GaN HEMT device based on PIN junction according to claim 6, characterized in that, The ohmic stack metal includes Ti, Al, Ni, and Au.
10. The manufacturing method of the low gate leakage p-GaN HEMT device based on PIN junction according to claim 6, characterized in that, The gate stack metal includes Ni and Au.