Super-junction MOSFET (metal-oxide-semiconductor field effect transistor) structure and manufacturing method

Abstract

The invention provides a super junction MOSFET structure and a manufacturing method, and the method comprises the steps: providing a substrate, arranging an epitaxial layer on the substrate, forming a filling layer and a groove in the epitaxial layer, and enabling the groove and the filling layer to be spaced at a preset distance; a well region and a shielding region are formed in the epitaxial layer, the well region extends downwards into the epitaxial layer from the upper surface of the epitaxial layer, the epitaxial layer on the periphery of the well region forms a JFET region, and the groove is located in the JFET region; forming a source region and a well contact region in the well region, wherein the well contact region penetrates through the source region and extends into the well region; and forming a gate structure on the well region and the JFET region, wherein the gate structure extends into the groove and is connected with the shielding region. According to the invention, the gate structure extends into the groove of the JEFT region, a high-concentration carrier path can be formed in the JEFT region, and the on-resistance is reduced; and meanwhile, the width of the JFET region is reduced, and the shielding region is arranged below the groove, so that the electric field concentration of the gate oxide layer under high-voltage reverse bias can be effectively shielded, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a super junction MOSFET structure and a manufacturing method. Background Art

[0002] The reliability of SiC MOSFETs is a significant factor limiting their automotive-grade applications. The JFET region between the cell structures that make up SiC MOSFETs is one of the key structural points where reliability issues are prone to occur. To achieve lower on-resistance, a relatively wide JFET region is typically used to achieve a larger current-carrying area. This also leads to an increase in the local electric field in the widened JFET region. Under high-voltage reverse bias, the voltage on the gate oxide layer is high, causing the electric field in the local area to exceed the critical breakdown field strength of the gate oxide layer, causing the device to break down prematurely and reducing reliability. If the JFET region width is reduced, the overall on-resistance of the device will increase, and the current-carrying capacity will weaken.

[0003] Therefore, how to provide a MOSFET structure and a manufacturing method to reduce the on-resistance while increasing the breakdown voltage of the gate oxide layer has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a super junction MOSFET structure and a manufacturing method for solving the problem in the prior art that the breakdown voltage of the gate oxide layer is reduced when the device on-resistance is reduced, resulting in poor device reliability.

[0005] To achieve the above and other related objectives, the present invention provides a method for manufacturing a super junction MOSFET structure, comprising the following steps:

[0006] Providing a first conductive type substrate, on which a first conductive type epitaxial layer is provided, and forming a second conductive type filling layer in the epitaxial layer;

[0007] forming a trench in the epitaxial layer, wherein the trench is spaced apart from the filling layer by a predetermined distance, and the depth of the trench is less than the depth of the filling layer;

[0008] forming a second conductivity type well region and a second conductivity type shield region in the epitaxial layer, wherein the well region extends downward from the upper surface of the epitaxial layer into the interior of the epitaxial layer and partially overlaps with the filling layer, the epitaxial layer outside the well region constitutes a JFET region, the trench is located in the JFET region, the shield region is located below the trench, and the depth of the shield region is not less than the depth of the well region;

[0009] A source region of a first conductivity type and a well contact region of a second conductivity type are formed in the well region, wherein the well contact region penetrates through the source region and extends into the well region;

[0010] A gate structure is formed on the well region and the JFET region, and the gate structure extends into the trench and is connected to the shielding region.

[0011] Optionally, the step of forming the gate structure includes:

[0012] A gate oxide layer is formed on the upper surface of the well region, the upper surface of the JFET region, and the inner surface of the trench;

[0013] A gate metal layer is formed on the gate oxide layer.

[0014] Optionally, after forming the gate oxide layer and before forming the gate metal layer, the following steps are further included:

[0015] A source metal layer is formed on the epitaxial layer, and the source metal layer is electrically connected to the source region and the well contact region;

[0016] A drain metal layer is formed under the substrate;

[0017] An annealing process is used to anneal the source metal layer and the drain metal layer.

[0018] Optionally, the ratio range of the depth of the trench to the depth of the well region is 1 / 2 to 2 / 3.

[0019] Optionally, the ratio range of the width of the trench to the width of the JFET region does not exceed 1 / 5.

[0020] Optionally, the width of the shielding region does not exceed the bottom width of the trench.

[0021] The present invention also provides a superjunction MOSFET structure, including:

[0022] A substrate of a first conductivity type, a first conductivity type epitaxial layer is provided on the substrate, and a second conductivity type filling layer is provided in the epitaxial layer;

[0023] A well region of a second conductivity type, located in the epitaxial layer, and the well region is located above the filling layer, and the epitaxial layer outside the well region constitutes a JFET region;

[0024] A trench, located in the JFET region, and the depth of the trench is less than the depth of the well region;

[0025] A second conductivity type shielding region, located under the trench, and the depth of the shielding region is not lower than the depth of the well region;

[0026] A source region of a first conductivity type, located in the well region;

[0027] A drain contact region of a second conductivity type, extending through the source region into the well region;

[0028] A gate structure, located above the well region and the JFET region, and the gate structure extends into the trench to connect with the shielding region.

[0029] Optionally, the gate structure includes a gate oxide layer and a gate metal layer stacked from bottom to top.

[0030] Optionally, it further includes:

[0031] A source metal layer, located above the epitaxial layer, and the source metal layer is electrically connected to the source region and the drain contact region;

[0032] A drain metal layer, located below the substrate.

[0033] Optionally, the ratio range of the depth of the trench to the depth of the well region is 1 / 2 to 2 / 3.

[0034] Optionally, the ratio range of the width of the trench to the width of the JFET region does not exceed 1 / 5.

[0035] Optionally, the width of the shielding region does not exceed the bottom width of the trench.

[0036] As described above, in the superjunction MOSFET structure and manufacturing method of the present invention, the gate structure extends into the trench of the JEFT region, which can form a high-concentration carrier path in the JEFT region, reducing the on-resistance; at the same time, the width of the JFET region is reduced, and a shielding region is arranged below the trench, which can effectively shield the electric field concentration of the gate oxide layer under high-voltage reverse bias, realizing a reduction in the total specific on-resistance and an improvement in device reliability. Brief Description of the Drawings

[0037] Figure 1 It shows a process flow chart of the manufacturing method of the superjunction MOSFET structure of the present invention.

[0038] Figure 2 It shows a schematic diagram of forming a filling layer in the manufacturing method of the superjunction MOSFET structure of the present invention.

[0039] Figure 3 It shows a schematic diagram of forming a trench in the manufacturing method of the superjunction MOSFET structure of the present invention.

[0040] Figure 4 It shows a schematic diagram of forming a well region and a shielding region in the manufacturing method of the superjunction MOSFET structure of the present invention.

[0041] Figure 5 Schematic diagram showing the formation of the source region in the manufacturing method of the superjunction MOSFET structure of the present invention.

[0042] Figure 6 Schematic diagram showing the formation of the well contact region in the manufacturing method of the superjunction MOSFET structure of the present invention.

[0043] Figure 7 Schematic diagram showing the formation of the gate structure, source metal layer, and drain metal layer in the manufacturing method of the superjunction MOSFET structure of the present invention.

[0044] Description of component labels

[0045] 1 Substrate

[0046] 2 Epitaxial layer

[0047] 3 Filling layer

[0048] 4 Trench

[0049] 5 Well region

[0050] 6 JFET region

[0051] 7 Shielding region

[0052] 8 Source region

[0053] 9 Well contact region

[0054] 10 Gate structure

[0055] 10A Gate oxide layer

[0056] 10B Gate metal layer

[0057] 11 Source metal layer

[0058] 12 Drain metal layer

[0059] Steps S1 to S5 Detailed implementation manners

[0060] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] Please refer to Figures 1 to 7It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0062] This embodiment provides a method for manufacturing a superjunction MOSFET structure. Please refer to Figure 1 , which shows a process flow chart of this manufacturing method, including the following steps:

[0063] S1: Provide a substrate of a first conductivity type, with an epitaxial layer of the first conductivity type provided on the substrate, and form a filling layer of a second conductivity type in the epitaxial layer;

[0064] S2: Form a trench in the epitaxial layer. The trench is spaced a preset distance from the filling layer, and the depth of the trench is less than the depth of the filling layer;

[0065] S3: Form a well region of the second conductivity type and a shielding region of the second conductivity type in the epitaxial layer. The well region extends downward from the upper surface of the epitaxial layer into the interior of the epitaxial layer and partially overlaps with the filling layer. The epitaxial layer outside the well region constitutes a JFET region. The trench is located in the JFET region, and the shielding region is located below the trench. The depth of the shielding region is not lower than the depth of the well region;

[0066] S4: Form a source region of the first conductivity type and a well contact region of the second conductivity type in the well region. Among them, the well contact region penetrates through the source region and extends into the well region;

[0067] S5: Form a gate structure on the well region and the JFET region, and the gate structure extends into the trench and is connected to the shielding region.

[0068] First, please refer to Figure 2 , and perform step S1: Provide a substrate 1 of a first conductivity type, with an epitaxial layer 2 of the first conductivity type provided on the substrate 1, and form a filling layer 3 of a second conductivity type in the epitaxial layer 2.

[0069] As an example, the substrate 1 can be a silicon substrate, a germanium substrate, or a silicon-germanium compound substrate, or can also be a silicon nitride substrate, a gallium nitride substrate, or other semiconductor substrates known to those skilled in the art; the epitaxial layer 2 has the same material as the substrate 1 (homoepitaxy), or the epitaxial layer 2 has a different material from the substrate 1 (heteroepitaxy), which is selected according to requirements. Specifically, in this embodiment, the substrate 1 adopts a 4H-SiC substrate, and the epitaxial layer 2 adopts a 4H-SiC epitaxial layer.

[0070] As an example, the first conduction type is N-type and the second conduction type is P-type; or the first conduction type is P-type and the second conduction type is N-type. Specifically, in this embodiment, the first conduction type is N-type and the second conduction type is P-type. Among them, the doping concentration of the substrate 1 is greater than that of the epitaxial layer 2, the substrate 1 serves as the drain region, and the epitaxial layer 2 serves as the drift region.

[0071] As an example, the step of forming the filling layer 3 includes: etching the epitaxial layer 2 to form a groove, and epitaxially filling in the groove to form the filling layer 3.

[0072] As an example, the number of the filling layers 3 is multiple, and the epitaxial layer 2 between adjacent filling layers 3 serves as an N-type column, and the filling layer 3 serves as a P-type column. The P-type columns and the N-type columns are alternately arranged to form a superjunction structure.

[0073] Next, please refer to Figure 3 , and perform step S2: forming a trench 4 in the epitaxial layer 2. The trench 4 is spaced from the filling layer 3 by a preset distance, and the depth of the trench 4 is less than the depth of the filling layer 3.

[0074] As an example, the trench 4 is formed by an etching method. The trench 4 is located between adjacent filling layers 3. In the vertical direction, the lower surface of the trench 4 is higher than the lower surface of the filling layer 3.

[0075] Next, please refer to Figure 4 , and perform step S3: forming a well region 5 of the second conduction type and a shielding region 7 of the second conduction type in the epitaxial layer 2. The well region 5 extends downward from the upper surface of the epitaxial layer 2 into the interior of the epitaxial layer 2 and partially overlaps with the filling layer 3. The epitaxial layer 2 outside the well region 5 constitutes a JFET region 6. The trench 4 is located in the JFET region 6. The shielding region 7 is located below the trench 4, and the depth of the shielding region 7 is not lower than the depth of the well region 5.

[0076] As an example, the well region 5 and the shielding region 7 are formed by ion implantation. The steps of forming the well region 5 and the shielding region 7 include:

[0077] (1) Forming an implantation sacrificial layer on the upper surface of the epitaxial layer 2 by chemical vapor deposition, forming an implantation blocking layer on the implantation sacrificial layer, and etching the implantation blocking layer to form an opening to define an implantation region. In this embodiment, the implantation sacrificial layer is an SiO2 layer, and the implantation blocking layer is an Al layer, an SiO2 layer, an SiN layer, or other suitable blocking layers;

[0078] (2) The well region 5 and the shielding region 7 are formed by ion implantation. In this embodiment, a multiple implantation process is adopted to improve the implantation uniformity. For example, four times of Al ion implantation are carried out at an ambient temperature of 650 °C, and the implantation energies are 450 keV, 300 keV, 200 keV, and 120 keV respectively, and the implantation doses are 7.97×10 13 cm -2 、4.69×10 13 cm -2 、3.27×10 13 cm -2 and 2.97×10 13 cm -2 ;

[0079] (3) After the implantation is completed, the surface of the silicon carbide is cleaned according to the RCA cleaning standard, and a carbon film protection is made after drying; then ion activation annealing is carried out in an argon atmosphere at 1700 - 1750 °C for 10 min;

[0080] (4) Remove the implantation sacrificial layer and the implantation barrier layer.

[0081] As an example, different well regions 5 can be regarded as different cell regions, and the epitaxial layer between adjacent well regions 5 serves as the JFET region between cell structures.

[0082] Next, please refer to Figures 5 to 6 , and perform step S4: form a source region 8 of the first conduction type and a well contact region 9 of the second conduction type in the well region 5, wherein the well contact region 9 penetrates through the source region 8 and extends into the well region 5.

[0083] As an example, the source region 8 is N-type heavily doped, and the well contact region 9 is P-type heavily doped.

[0084] As an example, the steps of forming the source region 8 include:

[0085] (1) A chemical vapor deposition method is used to form an implantation sacrificial layer on the upper surface of the epitaxial layer 2, an implantation barrier layer is formed on the implantation sacrificial layer, and the implantation barrier layer is etched to form an opening to define the implantation region. In this embodiment, the implantation sacrificial layer is an SiO2 layer, and the implantation barrier layer is an Al layer, an SiO2 layer, a SiN layer, or other suitable barrier layers;

[0086] (2) The source region 8 is formed by ion implantation. In this embodiment, a multiple implantation process is adopted to improve the implantation uniformity. For example, two times of N ion implantation are carried out at an ambient temperature of 650 °C, and the implantation energies are 80 keV and 30 keV respectively, and the implantation doses are 3.9×10 14 cm -2 and 1.88×1014 cm -2 ;

[0087] (3) After the implantation is completed, the surface of the silicon carbide is cleaned according to the RCA cleaning standard, and a carbon film protection is made after drying; then, ion activation annealing is performed in an argon atmosphere at 1700 - 1750 °C for 10 min;

[0088] (4) Remove the implanted sacrificial layer and the implantation barrier layer.

[0089] As an example, the steps of forming the well contact region 9 include:

[0090] (1) A chemical vapor deposition method is used to form an implanted sacrificial layer on the upper surface of the epitaxial layer 2, an implantation barrier layer is formed on the implanted sacrificial layer, and the implantation barrier layer is etched to form an opening to define the implantation region. In this embodiment, the implanted sacrificial layer is an SiO2 layer, and the implantation barrier layer is an Al layer, an SiO2 layer, an SiN layer, or other suitable barrier layers;

[0091] (2) The well contact region 9 is formed by an ion implantation method. In this embodiment, a multiple implantation process is used to improve the implantation uniformity. For example, two Al ion implantations are performed at an ambient temperature of 650 °C, with implantation energies of 90 keV and 30 keV respectively, and implantation doses of 1.88×10 14 cm -2 and 3.8×10 14 cm -2 ;

[0092] (3) After the implantation is completed, the surface of the silicon carbide is cleaned according to the RCA cleaning standard, and a carbon film protection is made after drying; then, ion activation annealing is performed in an argon atmosphere at 1700 - 1750 °C for 10 min;

[0093] (4) Remove the implanted sacrificial layer and the implantation barrier layer.

[0094] Next, please refer to Figure 7 , and perform step S5: A gate structure 10 is formed on the well region 5 and the JFET region 6, and the gate structure 10 extends into the trench 4 and is connected to the shielding region 7.

[0095] As an example, the steps of forming the gate structure 10 include:

[0096] (1) A thermal oxidation method is used to form a gate oxide layer 10A on the upper surface of the well region 5, the upper surface of the JFET region 6, and the inner surface of the trench 4;

[0097] (2) A magnetron sputtering method or an electron beam evaporation method is used to form a gate metal layer 10B on the gate oxide layer 10A, and the material of the gate metal layer 10B is Al.

[0098] As an example, after forming the gate oxide layer 10A and before forming the gate metal layer 10B, the following steps are further included:

[0099] (1) A source metal layer 11 is formed on the epitaxial layer 2 by magnetron sputtering or electron beam evaporation. The source metal layer 11 is electrically connected to the source region 8 and the well contact region 9. The source metal layer 11 includes a stacked Ti / Al / Ni composite layer;

[0100] (2) A drain metal layer 12 is formed under the substrate 1 by magnetron sputtering or electron beam evaporation. The drain metal layer 12 includes a stacked Ti / Ni composite layer;

[0101] (3) A rapid thermal annealing process is used to perform rapid thermal annealing on the source metal layer 11 and the drain metal layer 12. The annealing temperature is 1000 °C and the annealing time is 3 Min.

[0102] As an example, annealing the source metal layer 11 and the drain metal layer 12 and then forming the gate metal layer 10B can avoid the thermal diffusion of the gate metal layer 10B into the gate oxide layer 10A.

[0103] As an example, the gate structure 10 extends into the trench 4 in the JEFT region, which can form a high-concentration carrier path in the JEFT region, reducing the on-resistance; at the same time, the width of the JFET region is reduced, and a shielding region 7 is provided below the trench 4, which can effectively shield the electric field concentration of the gate oxide layer 10A under high-voltage reverse bias, realizing a reduction in the total specific on-resistance and an improvement in device reliability.

[0104] As an example, the ratio range of the depth of the trench 4 to the depth of the well region 5 is 1 / 2 to 2 / 3. If the trench 4 is too shallow, the high-concentration carrier path formed by gate biasing is too short, resulting in too large a resistance in the JEFT region. If the trench 4 is too deep, breakdown occurs prematurely at the gate oxide inflection point at the bottom of the trench, and the reverse breakdown voltage decreases.

[0105] As an example, the ratio range of the width of the trench 4 to the width of the JFET region 6 does not exceed 1 / 5. If the width of the trench 4 is too large, the conduction path in the JEFT region becomes narrow and the resistance becomes large.

[0106] As an example, the width of the shielding region 7 does not exceed the bottom width of the trench 4, and the lower surface of the shielding region 7 is flush with the lower surface of the well region 5 or slightly lower than the lower surface of the well region 5, which can prevent the depletion pinch-off of the well region and the epitaxial layer from being slower during reverse biasing, resulting in electric field breakdown at the gate oxide corner and a decrease in the reverse breakdown voltage. Preferably, in this embodiment, the width of the shielding region 7 is equal to the bottom width of the trench 4. Vertically, there is a high-concentration carrier path with a certain length even beyond the depth of the trench 4. If the shielding region 7 is too wide, the width of this path will become narrower and the on-resistance will increase.

[0107] Thus, a superjunction MOSFET structure is fabricated. Please refer to Figure 7 , the superjunction MOSFET structure includes a first-conductivity-type substrate 1, a second-conductivity-type well region 5, a trench 4, a second-conductivity-type shielding region 7, a first-conductivity-type source region 8, a second-conductivity-type well contact region 9, and a gate structure 10. The substrate 1 is provided with a first-conductivity-type epitaxial layer 2, and a second-conductivity-type filling layer 3 is provided in the epitaxial layer 2; the well region 5 is located in the epitaxial layer 2, and the well region 5 is located above the filling layer 3, and the epitaxial layer outside the well region 5 constitutes a JFET region 6; the trench 4 is located in the JFET region 6, and the depth of the trench 4 is less than the depth of the well region 5; the shielding region 7 is located below the trench 4, and the depth of the shielding region 7 is not lower than the depth of the well region 5; the source region 8 is located in the well region 5; the well contact region 9 penetrates through the source region 8 and extends into the well region 5; the gate structure 10 is located above the well region 5 and the JFET region 6, and the gate structure 10 extends into the trench 4 and is connected to the shielding region 7.

[0108] As an example, the substrate 1 is a 4H-SiC substrate, and the epitaxial layer 2 is a 4H-SiC epitaxial layer.

[0109] As an example, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type. Specifically, in this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. Among them, the doping concentration of the substrate 1 is greater than the doping concentration of the epitaxial layer 2, and the substrate 1 serves as the drain region, and the epitaxial layer 2 serves as the drift region.

[0110] As an example, the number of the filling layers 3 is multiple, and the epitaxial layer 2 between adjacent filling layers 3 serves as an N-type column, and the filling layer 3 serves as a P-type column. The P-type columns and the N-type columns are arranged alternately to form a superjunction structure.

[0111] As an example, the ratio range between the depth of the trench 4 and the depth of the well region 5 is 1 / 2 to 2 / 3, the ratio range between the width of the trench 4 and the width of the JFET region 6 does not exceed 1 / 5, and the lower surface of the shielding region 6 is flush with the lower surface of the well region 5 or the lower surface of the shielding region 6 is slightly lower than the lower surface of the well region 5.

[0112] As an example, the source region 8 is heavily doped with N-type, and the well contact region 9 is heavily doped with P-type.

[0113] As an example, the gate structure 10 includes a gate oxide layer 10A and a gate metal layer 10B stacked from bottom to top.

[0114] As an example, it further includes a source metal layer 11 and a drain metal layer 12. The source metal layer 11 is located above the epitaxial layer 2, and the source metal layer 11 is electrically connected to the source region 8 and the well contact region 9. The drain metal layer 12 is located below the substrate 1.

[0115] In summary, in the superjunction MOSFET structure and manufacturing method of the present invention, the gate structure extends into the trench in the JEFT region, which can form a high-concentration carrier path in the JEFT region and reduce the on-resistance. At the same time, the width of the JFET region is reduced, and a shielding region is provided below the trench, which can effectively shield the electric field concentration of the gate oxide layer under high-voltage reverse bias, realize the reduction of the total specific on-resistance, and improve the device reliability. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0116] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A manufacturing method of a superjunction MOSFET structure, characterized in that, Comprising: Providing a substrate of a first conductivity type, on which an epitaxial layer of the first conductivity type is provided, and forming a filling layer of a second conductivity type in the epitaxial layer; Forming a trench in the epitaxial layer, the trench being spaced from the filling layer by a preset distance, and the depth of the trench being less than the depth of the filling layer; Forming a well region of a second conductivity type and a shielding region of a second conductivity type in the epitaxial layer, the well region extending downward from the upper surface of the epitaxial layer into the interior of the epitaxial layer and partially overlapping with the filling layer, the epitaxial layer outside the well region constituting a JFET region, the trench being located in the JFET region, the shielding region being located below the trench, and the depth of the shielding region not being lower than the depth of the well region; Forming a source region of a first conductivity type and a well contact region of a second conductivity type in the well region, wherein the well contact region penetrates through the source region and extends into the well region; Forming a gate structure on the well region and the JFET region, and the gate structure extending into the trench and connecting with the shielding region.

2. The manufacturing method of the superjunction MOSFET structure according to claim 1, characterized in that The step of forming the gate structure includes: Forming a gate oxide layer on the upper surface of the well region, the upper surface of the JFET region, and the inner surface of the trench; Forming a gate metal layer on the gate oxide layer.

3. The manufacturing method of the superjunction MOSFET structure according to claim 2, characterized in that, After forming the gate oxide layer and before forming the gate metal layer, the following steps are further included: Forming a source metal layer on the epitaxial layer, the source metal layer being electrically connected to the source region and the well contact region; Forming a drain metal layer below the substrate; Annealing the source metal layer and the drain metal layer by an annealing process.

4. The manufacturing method of the superjunction MOSFET structure according to claim 1, characterized in that: The ratio range of the depth of the trench to the depth of the well region is 1 / 2 to 2 / 3.

5. The manufacturing method of the superjunction MOSFET structure according to claim 1, characterized in that: The ratio range of the width of the trench to the width of the JFET region does not exceed 1 / 5.

6. The manufacturing method of the superjunction MOSFET structure according to claim 1, characterized in that: The width of the shielding region does not exceed the bottom width of the trench.

7. A superjunction MOSFET structure, characterized in that, Comprising: A substrate of a first conductivity type, on which an epitaxial layer of the first conductivity type is provided, and a filling layer of a second conductivity type is provided in the epitaxial layer; A well region of a second conductivity type, located in the epitaxial layer, and the well region is located above the filling layer, and the epitaxial layer outside the well region constitutes a JFET region; A trench, located in the JFET region, and the depth of the trench is less than the depth of the well region; A shielding region of a second conductivity type, located below the trench, and the depth of the shielding region is not lower than the depth of the well region; A source region of a first conductivity type, located in the well region; A well contact region of a second conductivity type, penetrating through the source region and extending into the well region; A gate structure, located above the well region and the JFET region, and the gate structure extends into the trench and connects with the shielding region.

8. The super-junction MOSFET structure according to claim 7, characterized in that: The gate structure includes a gate oxide layer and a gate metal layer stacked from bottom to top.

9. The superjunction MOSFET structure according to claim 7, wherein Further comprising: A source metal layer, located above the epitaxial layer, the source metal layer being electrically connected to the source region and the well contact region; A drain metal layer, located below the substrate.

10. The superjunction MOSFET structure according to claim 7, characterized in that: The ratio range of the depth of the trench to the depth of the well region is 1 / 2 to 2 / 3.

11. The superjunction MOSFET structure according to claim 7, characterized in that: The ratio range of the width of the trench to the width of the JFET region does not exceed 1 / 5.

12. The super junction MOSFET structure according to claim 7, characterized in that: The width of the shielding region does not exceed the bottom width of the trench.

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