Silicon carbide MOSFET device based on double-trench gate structure and manufacturing method thereof

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a silicon carbide MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device based on a double-trench gate structure, which consists of a plurality of parallel MOS cells, and is characterized in that each MOS cell sequentially comprises a drain electrode, a semiconductor epitaxial layer, a gate electrode and a source electrode from bottom to top, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a main P + layer, a main N well layer and a main P well layer, an L-shaped double groove is etched in the single MOS cell and located in the main N well layer, a filling medium is filled in the L-shaped double groove, and the filling medium is in ohmic contact with the source electrode. According to the invention, the L-shaped double grooves are designed in the main N-well layer and are filled with the medium, and the carrier transmission path and the electric field distribution are optimized by combining the L-shaped cross section profile of the main N-well layer. According to the structure, the control capability of the grid electrode on a channel is remarkably enhanced, and the current path tortuosity of a traditional plane grid structure is reduced, so that the on-resistance is reduced and the switching speed is improved.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to a silicon carbide MOSFET device based on a double-groove gate structure and a manufacturing method thereof. Background Art

[0002] Based on the current silicon carbide MOSFET technology field, traditional planar gates or single-groove gate structures have significant limitations: on the one hand, the uniformly doped drift region is prone to electric field concentration under high blocking voltages, restricting the improvement of breakdown voltage; on the other hand, the planar gate has weak channel control ability, resulting in tortuous carrier transport paths, high on-resistance (Ron), and the JFET effect further degrading the on-state characteristics under high-voltage and high-current conditions. Although the introduction of the trench gate design can partially improve the gate control ability, it is still difficult to synergistically optimize the electric field distribution, carrier injection efficiency, and current spreading ability, restricting breakthroughs in device switching speed, power density, and reliability.

[0003] A prior patent discloses a double-groove SS-SiC MOSFET structure (CN109768091A), including: a silicon carbide substrate; a silicon carbide N-type electron drift epitaxial layer, a silicon carbide N-type current spreading epitaxial layer, a silicon carbide P-type base region layer, a silicon carbide N-type heavily doped layer, and two symmetrically distributed silicon carbide source P-type heavily doped ion implantation regions that extend from the top of the silicon carbide N-type heavily doped layer to the silicon carbide N-type current spreading epitaxial layer, stacked on the substrate in sequence. In the technology disclosed in this prior patent, due to electric field concentration at the gate trench, the breakdown voltage reliability is insufficient, the JFET effect introduced by the P-type shielding region increases the on-resistance, and the tortuous carrier transport path restricts the switching performance. Summary of the Invention

[0004] The present invention provides a silicon carbide MOSFET device based on a double-groove gate structure and a manufacturing method thereof to solve the existing technical problems, and solve the electric field concentration problem caused by traditional uniform doping.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a silicon carbide MOSFET device based on a double-groove gate structure is composed of a plurality of juxtaposed MOS cells. Each individual MOS cell sequentially includes a drain, a semiconductor epitaxial layer, a gate, and a source from bottom to top. The semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a main P+ layer, a main N well layer, and a main P well layer. An L-shaped double groove is etched inside the main N well layer within each individual MOS cell, and the L-shaped double groove is filled with a filling medium, and the filling medium is in ohmic contact with the source. The cross-sectional profile of the main N well layer is in an "L" shape, and one end of the main N well layer is in ohmic contact with the source, and the other end of the main N well layer extends below the gate.

[0006] Further, the filling medium is a filled P-layer.

[0007] Further, the filling medium includes a filled P+-layer, a filled P-well layer, and a filled N-well layer.

[0008] Further, the filled N-well layer is located between the filled P+-layer and the gate, and both the filled P+-layer and the filled N-well layer are in ohmic contact with the source; The filled P-well layer is located below the filled N-well layer, and the other end of the filled P-well layer extends below the gate.

[0009] Further, a heavily doped N+-layer is formed by ion implantation between two main P-well layers in a single MOS cell, and the middle of the bottom end of the heavily doped N+-layer is convex downward.

[0010] Further, a middle P-layer is provided in the middle of the heavily doped N+-layer. The bottom end of the middle P-layer is in contact with the N diffusion layer, and the middle P-layer divides the heavily doped N+-layer into left and right parts.

[0011] Further, a variably doped N+-layer is formed by ion implantation inside the N diffusion layer of a single MOS cell. The variably doped N+-layer is in contact with the N substrate layer, and the cross-sectional profile of the variably doped N+-layer is convex in the middle.

[0012] Further, the doping concentration of the variably doped N+-layer in a single MOS cell is low in the middle and high on both sides.

[0013] A manufacturing method of a silicon carbide MOSFET device based on a double-groove gate structure specifically includes: S1. Epitaxially grow an N diffusion layer on the surface of an N substrate layer, and sequentially form a main P+-layer, a main N-well layer, and a main P-well layer above the N diffusion layer by ion implantation, wherein the main N-well layer realizes an L-shaped cross-sectional profile through mask design; S2. In the main N-well layer in the area of a single MOS cell, form an L-shaped double-groove structure by dry etching, ensuring that one end of the groove extends below the predetermined position of the gate and the other end is exposed in the contact area of the source; S3. Selectively form a filling medium in the L-shaped groove: if it is a filled P-layer, it is realized by P-type ion implantation; if it is a multi-layer structure, sequentially implant a filled P+-layer, a filled P-well layer, and a filled N-well layer, and control the filled P-well layer to extend below the gate; S4. Inject and form a heavily doped N+-layer between the main P-well layers, and control its bottom end to be convex downward through a mask; at the same time, inject a variably doped N+-layer into the N diffusion layer, and adjust the injection dose to make the doping concentration low in the middle and high on both sides, forming a convex cross-sectional profile; S5. Inject an intermediate P- layer into the raised part of the heavily doped N+ layer so that its bottom end is connected to the N diffusion layer, separating the heavily doped N+ layer into a left-right symmetric structure; S6. Grow a gate oxide layer on the sidewalls of the trench and the surface of the filling medium, deposit polysilicon to fill the trench and pattern it to form a gate; S7. Deposit a metal layer on the top of the cell to form a source ohmic contact with the filling medium, the main N well layer and the main P+ layer; form a drain metal layer on the back of the N substrate layer.

[0014] A silicon carbide MOSFET device based on a double trench gate structure and a manufacturing method thereof provided by the present invention. Compared with the prior art, the effects achieved by this method are as follows: 1. By designing an L-shaped double trench in the main N well layer and filling it with a medium, and combining with the L-shaped cross-sectional profile of the main N well layer, the present invention optimizes the carrier transport path and the electric field distribution. This structure significantly enhances the gate's control ability over the channel, reduces the tortuosity of the current path in the traditional planar gate structure, thereby reducing the on-resistance and improving the switching speed.

[0015] 2. The present invention provides two schemes for filling the medium, namely a single P- layer to simplify the process and maintain the electric field regulation and a multi-layer structure. In the multi-layer structure, by extending the filled P well layer under the gate, the carrier injection and the electric field shielding effect are synergistically optimized, effectively reducing the switching loss. This design flexibility takes into account both the manufacturing cost and the high-performance requirements.

[0016] 3. By injecting a heavily doped N+ layer with a raised bottom end between the main P well layers, the present invention broadens the current channel from the source contact area to the drift area. This raised structure alleviates the problem of increased on-resistance caused by the JFET effect in traditional devices, especially improving the current-carrying capacity under high-voltage and high-current conditions.

[0017] 4. By injecting an intermediate P- layer connected to the N diffusion layer into the raised part of the heavily doped N+ layer, the N+ layer is separated into a left-right symmetric structure. The intermediate P- layer forms an electric field buffer, dispersing the peak value of the high electric field region and avoiding local breakdown, significantly improving the breakdown voltage and long-term reliability of the device.

[0018] 5. The present invention forms a variably doped N+ layer with a "low in the middle and high on both sides" doping concentration in the N diffusion layer, and its raised cross-sectional profile reconstructs the electric field distribution in the drift area. The gradient doping design reduces the peak electric field intensity in the high-voltage blocking state, thereby increasing the breakdown voltage and solving the problem of electric field concentration caused by traditional uniform doping. Description of the Drawings

[0019] Figure 1 It is a schematic diagram of Embodiment 1 in the present invention; Figure 2 It is a schematic diagram of Embodiment 2 in the present invention; Figure 3 Schematic diagram of Embodiment 3 in the present invention; Figure 4 Schematic diagram of Embodiment 4 in the present invention; Figure 5 Schematic diagram of Embodiment 5 in the present invention; Figure 6 Schematic diagram of Embodiment 6 in the present invention.

[0020] In the figure: 1, drain; 2, gate; 3, source; 4, N substrate layer; 5, N diffusion layer; 6, filling medium; 7, main P+ layer; 8, main N well layer; 9, main P well layer; 10, heavily doped N+ layer; 11, intermediate P- layer; 12, variably doped N+ layer; 61, filling P- layer; 62, filling P+ layer; 63, filling P well layer; 64, filling N well layer. Detailed implementation manners

[0021] To make the technical solution of the present invention clearer, the following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0022] As Figure 1-6 shown, according to one aspect of the present invention, a manufacturing method of a silicon carbide MOSFET device based on a double trench gate structure is provided, specifically including: Step 1: Epitaxially grow an N diffusion layer 5 on the surface of the N substrate layer 4, and sequentially form a main P+ layer 7, a main N well layer 8, and a main P well layer 9 above the N diffusion layer 5 by ion implantation. Among them, the main N well layer 8 realizes an L-shaped cross-sectional profile through mask design; in this step, the L-shaped cross-sectional profile of the main N well layer is precisely controlled by the mask, providing a structural basis for subsequent L-shaped trench etching. The L-shaped design enables one end of the main N well layer 8 to be connected to the source and the other end to extend under the gate 2 (Embodiment 1), which can optimize the carrier path, enhance the gate's control ability over the channel, and solve the problem of weak control of the traditional planar gate.

[0023] Step 2: In the main N well layer 8 of a single MOS cell region, form an L-shaped double trench structure by dry etching, ensuring that one end of the trench extends under the predetermined position of the gate 2 and the other end is exposed in the contact area of the source 3; precisely open slots in the L-shaped main N well layer 8 by directional etching to ensure that one end of the trench is exposed in the source contact area and the other end extends under the predetermined position of the gate 2. This structure provides an electric field regulation space for the filling medium 6, coordinates with the L-shaped main N well layer 8 to optimize the electric field distribution, and lays a topological foundation for reducing the on-resistance.

[0024] Step 3: Selectively form a filling dielectric 6 in the L-shaped trench. If a P-layer 61 is to be filled, this is achieved through P-type ion implantation. If a multi-layer structure is to be formed, a P+ layer 62, a P-well layer 63, and an N-well layer 64 are implanted in sequence, and the P-well layer 63 is controlled to extend below the gate 2. This step provides two optimization solutions: 1) The single filling P-layer 61 can simplify the process and maintain electric field control; 2) The multi-layer filling extends to the bottom of the gate 2 by filling the P-well layer 63, and collaboratively fills the P+ layer 52 and the N-well layer 64 to optimize carrier injection and shielding effects, significantly reducing switching losses.

[0025] Step 4: A heavily doped N+ layer 10 is formed by implantation between the main P-well layers 9, and its bottom is convex downwardly controlled by mask control; at the same time, a variable doped N+ layer 12 is implanted into the N diffusion layer 5, and the implantation dose is adjusted so that the doping concentration is low in the middle and high on both sides, forming a raised cross-sectional profile; the raised heavily doped N+ layer 10 widens the current channel from the source contact region to the drift region, suppressing the resistance increase caused by the JFET effect; the variable doped N+ layer 12 adopts a "low in the middle and high on both sides" concentration gradient design to form a raised cross-section to optimize the electric field distribution in the drift region and improve the breakdown voltage.

[0026] Step 5: An intermediate P- layer 11 is implanted into the raised portion of the heavily doped N+ layer 10, with its bottom end connected to the N diffused layer 5, dividing the heavily doped N+ layer 10 into a bilaterally symmetrical structure. The intermediate P- layer 11 divides the heavily doped N+ layer 10 into a symmetrical structure, with its bottom end connected to the N diffused layer 5 to form an electric field buffer. This design disperses peaks in high electric field areas, preventing localized breakdown and significantly improving device withstand voltage reliability.

[0027] Step 6: growing a gate oxide layer on the trench sidewalls and the surface of the filling dielectric 6 , depositing polysilicon to fill the trench and patterning to form a gate 2 .

[0028] Step 7: Deposit a metal layer on the top of the cell to form an ohmic contact between the source 3 and the filling dielectric 6, the main N-well layer 8 and the main P+ layer 7; and form a drain 1 metal layer on the back of the N-substrate layer 4.

[0029] Example 1 like Figure 1As shown, the silicon carbide MOSFET device based on a double-groove gate structure is composed of a number of MOS cells arranged side by side. A single MOS cell includes a drain 1, a semiconductor epitaxial layer, a gate 2, and a source 3 in sequence from bottom to top. The semiconductor epitaxial layer includes an N substrate layer 4, an N diffusion layer 5, a main P+ layer 7, a main N well layer 8, and a main P well layer 9. An L-shaped double groove is etched inside the main N well layer 8 of a single MOS cell, and the L-shaped double groove is filled with a filling medium 6, and the filling medium 6 is in ohmic contact with the source 3; the cross-sectional profile of the main N well layer 8 is in an "L" shape, and one end of the main N well layer 8 is in ohmic contact with the source 3, and the other end of the main N well layer 8 extends below the gate 2. An L-shaped double groove is etched in the main N well layer 8 and filled with the medium 6, and the main N well layer 8 is designed with an L-shaped cross-section, one end connected to the source 3, and the other end extending below the gate 2. It solves the problems of weak gate control ability and high on-resistance of the traditional planar structure. And through the L-shaped groove and the filling medium 6, the electric field distribution is optimized, the control of the gate 2 over the channel is enhanced, the on-resistance is reduced, and the switching performance of the device is improved.

[0030] Embodiment 2 As Figure 2 shown, the filling medium 6 is a filled P- layer 61. The filling medium 6 adopts a single P- layer 61. It can solve the problems of complex process and high cost of the multi-layer filling structure, simplify the manufacturing process, reduce the process difficulty, while maintaining the effective regulation of the electric field in the groove, and improve the production efficiency.

[0031] Embodiment 3 As Figure 3 shown, the filling medium 6 includes a filled P+ layer 62, a filled P well layer 63, and a filled N well layer 64. The filled N well layer 64 is located between the filled P+ layer 62 and the gate 2, and both the filled P+ layer 62 and the filled N well layer 64 are in ohmic contact with the source 3; the filled P well layer 63 is located below the filled N well layer 64, and the other end of the filled P well layer 63 extends below the gate 2. The filling medium 6 is composed of three layers (filled P+ layer 62, filled P well layer 63, filled N well layer 64), and the filled P well layer 63 extends below the gate 2. This method solves the problem that it is difficult for a single filling layer to balance the carrier injection and the electric field shielding effect. And the multi-layer structure synergistically optimizes the carrier transport path, and the extended design of the filled P well layer 63 enhances the control of the gate over the channel, significantly reducing the switching loss.

[0032] Embodiment 4 As Figure 4As shown, a heavily doped N+ layer 10 is formed by ion implantation in a single MOS cell and between two main P-well layers 9. The middle of the bottom end of the heavily doped N+ layer 10 is convex downward. The heavily doped N+ layer 10 with a convex bottom end is implanted between the main P-well layers 9. This can solve the problem that the on-resistance increases due to the JFET effect between the contact region and the drift region of the source electrode 3. And the convex structure widens the current channel, suppresses the JFET effect, and reduces the on-resistance at a specific current density.

[0033] Embodiment 5 As Figure 5 shown, an intermediate P- layer 11 is provided in the middle of the heavily doped N+ layer 10. The bottom end of the intermediate P- layer 11 is in contact with the N diffusion layer 5, and the intermediate P- layer 11 divides the heavily doped N+ layer 10 into left and right parts. The intermediate P- layer 11 connected to the N diffusion layer 5 is implanted at the convex part of the heavily doped N+ layer 10 to separate the heavily doped N+ layer 10 into a left-right symmetric structure. This can solve the problem that the heavily doped N+ layer 10 is prone to local breakdown under high electric fields. And the intermediate P- layer 11 forms an electric field buffer, evenly disperses the electric field peak value, and improves the breakdown voltage and reliability of the device.

[0034] Embodiment 6 As Figure 6 shown, a variable-doped N+ layer 12 is formed by ion implantation inside the N diffusion layer 5 of a single MOS cell. The variable-doped N+ layer 12 is in contact with the N substrate layer 4, and the cross-sectional profile of the variable-doped N+ layer 12 is convex in the middle. The doping concentration of the variable-doped N+ layer 12 in a single MOS cell is low in the middle and high on both sides. The variable-doped N+ layer 12 with a "low in the middle and high on both sides" doping concentration and a convex cross-section is formed in the N diffusion layer 5. This solves the problem that the uneven electric field distribution in the drift region limits the breakdown voltage. And the gradient doping design optimizes the electric field distribution, reduces the peak electric field in the high-voltage blocking state, and significantly improves the breakdown voltage.

[0035] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. A silicon carbide MOSFET device based on a double-groove gate structure, which is composed of a plurality of juxtaposed MOS cells. Each of the single MOS cells sequentially includes a drain (1), a semiconductor epitaxial layer, a gate (2), and a source (3) from bottom to top. The semiconductor epitaxial layer includes an N substrate layer (4), an N diffusion layer (5), a main P+ layer (7), a main N well layer (8), and a main P well layer (9), and is characterized in that: An L-shaped double trench is etched inside a single MOS cell and is located within the main N-well layer (8), and the L-shaped double trench is filled with a filling medium (6). The cross-sectional profile of the main N-well layer (8) is in an "L" shape, and one end of the main N-well layer (8) is in ohmic contact with the source electrode (3), and the other end of the main N-well layer (8) extends below the gate electrode (2).

2. The silicon carbide MOSFET device based on the double-groove gate structure according to claim 1, wherein: The filling medium (6) is a filled P-layer (61).

3. The silicon carbide MOSFET device based on a double-groove gate structure according to claim 1, wherein: The filling medium (6) includes a filled P+ layer (62), a filled P-well layer (63), and a filled N-well layer (64).

4. The silicon carbide MOSFET device based on a double-groove gate structure according to claim 3, wherein: The filled N-well layer (64) is located between the filled P+ layer (62) and the gate electrode (2), and both the filled P+ layer (62) and the filled N-well layer (64) are in ohmic contact with the source electrode (3). The filled P-well layer (63) is located below the filled N-well layer (64), and the other end of the filled P-well layer (63) extends below the gate electrode (2).

5. The silicon carbide MOSFET device based on the double-groove gate structure according to claim 3, wherein: A heavily doped N+ layer (10) is formed by ion implantation between two main P-well layers (9) in a single MOS cell, and the middle of the bottom end of the heavily doped N+ layer (10) is convex downward.

6. The silicon carbide MOSFET device based on a double-groove gate structure according to claim 5, characterized in that: An intermediate P-layer (11) is provided in the middle of the heavily doped N+ layer (10), the bottom end of the intermediate P-layer (11) is in contact with the N diffusion layer (5), and the intermediate P-layer (11) divides the heavily doped N+ layer (10) into left and right parts.

7. The silicon carbide MOSFET device based on a double-groove gate structure according to claim 1, characterized in that: A variable-doped N+ layer (12) is formed by ion implantation inside the N diffusion layer (5) of a single MOS cell, the variable-doped N+ layer (12) is in contact with the N substrate layer (4), and the cross-sectional profile of the variable-doped N+ layer (12) is convex in the middle.

8. The silicon carbide MOSFET device based on a double-groove gate structure according to claim 7, characterized in that: In a single MOS cell, the doping concentration of the variable-doped N+ layer (12) is low in the middle and high on both sides.

9. A manufacturing method of a silicon carbide MOSFET device based on a double-groove gate structure, characterized in that, Applied to the manufacturing method of the silicon carbide MOSFET device according to any one of claims 1-8, the manufacturing method specifically includes: S1. Epitaxially grow an N diffusion layer (5) on the surface of the N substrate layer (4), and sequentially form a main P+ layer (7), a main N-well layer (8), and a main P-well layer (9) above the N diffusion layer (5) by ion implantation, wherein the main N-well layer (8) realizes an L-shaped cross-sectional profile through mask design. S2. In the main N-well layer (8) in the area of a single MOS cell, form an L-shaped double trench structure by dry etching, ensuring that one end of the trench extends below a predetermined position of the gate electrode (2), and the other end is exposed in the contact area of the source electrode (3). S3. Selectively form a filling medium (6) in the L-shaped trench: if it is a filled P-layer (61), it is realized by P-type ion implantation. If it is a multi-layer structure, sequentially implant the filled P+ layer (62), the filled P-well layer (63), and the filled N-well layer (64), and control the filled P-well layer (63) to extend below the gate electrode (2). S4. Inject and form a heavily doped N+ layer (10) between the main P-well layers (9), and control its bottom end to be convex downward through a mask. At the same time, inject a variable-doped N+ layer (12) into the N diffusion layer (5), and adjust the injection dose so that the doping concentration is low in the middle and high on both sides, forming a convex cross-sectional profile. S5. Inject an intermediate P- layer (11) at the raised portion of the heavily doped N+ layer (10) so that its bottom end is connected to the N diffusion layer (5), separating the heavily doped N+ layer (10) into a left-right symmetric structure; S6. Grow a gate oxide layer on the sidewalls of the trench and the surface of the filling medium (6), deposit polysilicon to fill the trench and pattern it to form a gate (2); S7. Deposit a metal layer on the top of the cell to form an ohmic contact with the filling medium (6), the main N well layer (8) and the main P+ layer (7) to form a source electrode (3); form a drain (1) metal layer on the back of the N substrate layer (4).

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