Novel layout structure for optimizing crosstalk and anti-crosstalk power module

Abstract

The invention relates to the field of power devices, and discloses a novel layout structure for optimizing crosstalk and an anti-crosstalk power module, the layout structure is provided with symmetrical copper layer arrangements, two Mosfet assemblies, two capacitors, a gate resistor and a crossover line, s poles of the two Mosfet assemblies are connected with two groups of inner copper layers in a one-to-one correspondence manner, and the two Mosfet assemblies are connected with the crossover line in a one-to-one correspondence manner; the bottom ends of the capacitors are connected with the two sets of inner copper layers in a one-to-one correspondence mode, the top ends of the two capacitors are connected with the g poles of the two Mosfet assemblies in a one-to-one correspondence mode, crosstalk voltage is reduced, misconduction is avoided, the gate pole resistor is connected with the other ends of the two capacitors, the two ends of the overline are connected with the two sets of inner copper layers in a one-to-one correspondence mode, parasitic inductance connected with the s poles of the symmetrical Mosfet assemblies is reduced, and the stability of the symmetrical Mosfet assemblies is improved. High-frequency resonance is suppressed, global crosstalk optimization is realized, and the performance of a product is ensured.

Description

Technical Field

[0001] The present invention relates to the field of power devices, and in particular to a novel layout structure for optimizing crosstalk and a crosstalk-resistant power module. Background Art

[0002] In multi-chip parallel MOSFET modules, although thermal coupling design alleviates the problem of uneven thermal stress, differences in parasitic parameters (such as parasitic inductance and capacitance) can still lead to high-frequency oscillations (>100MHz) during transient switching, which can easily cause gate overvoltage stress damage. However, existing traditional methods rely on increasing gate resistance to suppress oscillations, but symmetrical layout is difficult to achieve due to space constraints. The lack of optimization for the parasitic inductance differences at the S poles of parallel chips makes it difficult to effectively attenuate the oscillation energy. At the same time, while the internal gate-level gate resistance can suppress gate resonance, it weakens the Miller clamping effect at the application end, resulting in increased crosstalk voltage during switching, which may falsely trigger the lower tube to turn on and cause damage. Summary of the Invention

[0003] In order to solve the above problems, the present invention provides a new layout structure for optimizing crosstalk. The new layout structure is provided with a symmetrical copper layer arrangement, two MOSFET components, two capacitors, a gate resistor and a crossover line. The s-poles of the two MOSFET components are connected to the two groups of inner copper layers in a one-to-one correspondence, the bottom ends of the capacitors are connected to the two groups of inner copper layers in a one-to-one correspondence, and the top ends of the two capacitors are connected to the g-poles of the two MOSFET components in a one-to-one correspondence, thereby reducing the crosstalk voltage and avoiding misconduction. The gate resistor is connected to the other end of the two capacitors, and the two ends of the crossover line are connected to the two groups of inner copper layers in a one-to-one correspondence, thereby reducing the parasitic inductance of the s-pole connection of the symmetrical MOSFET components, suppressing high-frequency resonance, achieving global crosstalk optimization, and ensuring product performance.

[0004] In order to achieve the above objectives, the present invention provides a novel layout structure for optimizing crosstalk, wherein the layout design structure includes:

[0005] The copper layer is symmetrically divided from the outside to the inside into two groups of outer copper layers, two groups of inner copper layers and one group of central copper layers;

[0006] Two MOSFET components, the S-poles of the two MOSFET components are connected to the two groups of inner copper layers in a one-to-one correspondence;

[0007] Two capacitors, the bottom ends of the two capacitors are connected to the two groups of the inner copper layers in a one-to-one correspondence, and the top ends of the two capacitors are connected to the g-poles of the two Mosfet components in a one-to-one correspondence;

[0008] a gate resistor connected to the other ends of the two capacitors;

[0009] Cross - wire, both ends of the cross - wire are correspondingly connected to two groups of the inner copper layers one by one.

[0010] Preferably, two Mosfet components are horizontally and correspondingly mounted on two groups of the outer copper layers.

[0011] Preferably, the gate resistor is mounted on the central copper layer and is horizontally aligned with the g - poles of two groups of Mosfet components.

[0012] Preferably, two capacitors are correspondingly mounted on two groups of the inner copper layers, and two capacitors are correspondingly aligned between the g - poles of two groups of Mosfet components and the gate resistor;

[0013] The cross - wire spans across the central copper layer and is horizontally aligned with the s - poles of two groups of Mosfet components.

[0014] Preferably, welding electrodes are provided at the top and bottom of the capacitor, and the bottom of the capacitor is welded to the inner copper layer.

[0015] On the other hand, the present invention provides a crosstalk - resistant power module, which includes:

[0016] A housing;

[0017] An upper cover plate, arranged on the top of the housing and hermetically connected to the housing;

[0018] A heat dissipation plate, closely arranged at the bottom end of the housing;

[0019] Multiple groups of copper - clad ceramic components, arranged in the cavity of the housing, and the copper - clad ceramic components are composed of multiple groups of new layout structures, and the new layout structure includes:

[0020] A copper layer, which symmetrically divides two groups of outer copper layers, two groups of inner copper layers and one group of central copper layer from outside to inside;

[0021] Two Mosfet components, the S - poles of two Mosfet components are correspondingly connected to two groups of the inner copper layers one by one;

[0022] Two capacitors, the bottom ends of two capacitors are correspondingly connected to two groups of the inner copper layers, and the top ends of two capacitors are correspondingly connected to the g - poles of two Mosfet components one by one;

[0023] A gate resistor, the gate resistor is connected to the other ends of two capacitors through a cross - wire;

[0024] Cross - wire, both ends of the cross - wire are correspondingly connected to two groups of the inner copper layers one by one.

[0025] Preferably, the two Mosfet components are horizontally and correspondingly mounted on the two groups of outer copper layers one by one.

[0026] Preferably, the gate resistor is mounted on the central copper layer and is horizontally aligned with the g poles of the two groups of Mosfet components.

[0027] Preferably, the two capacitors are correspondingly mounted on the two groups of inner copper layers one by one, and the two capacitors are correspondingly aligned between the g poles of the two groups of Mosfet components and the gate resistor;

[0028] The jumper wire spans across the central copper layer and is horizontally aligned with the s poles of the two groups of Mosfet components.

[0029] Preferably, welding electrodes are provided at the top and bottom of the capacitor, and the bottom end of the capacitor is welded to the inner copper layer.

[0030] Through the above technical solutions, in this new layout structure, by arranging symmetric copper layer layouts, two Mosfet components, two capacitors, a gate resistor, and a jumper wire, the s poles of the two Mosfet components are correspondingly connected to the two groups of inner copper layers one by one, the bottom ends of the capacitors are correspondingly connected to the two groups of inner copper layers one by one, and the top ends of the two capacitors are correspondingly connected to the g poles of the two Mosfet components one by one. The gate resistor is connected to the other ends of the two capacitors, and the two ends of the jumper wire are correspondingly connected to the two groups of inner copper layers one by one; the two Mosfet components are correspondingly mounted on the two groups of outer copper layers one by one, the gate resistor is mounted on the central copper layer and is horizontally aligned with the g poles of the two groups of Mosfet components, and the introduced capacitors can be correspondingly mounted on the two groups of inner copper layers one by one, and the two capacitors are correspondingly aligned between the g poles of the two groups of Mosfet components and the gate resistor, so that the capacitors can reduce the crosstalk voltage and avoid mis-conduction. The jumper wire spans across the central copper layer and is horizontally aligned with the s poles of the two groups of Mosfet components, which is used to reduce the parasitic inductance of the s pole connection of the symmetric Mosfet components and suppress high-frequency resonance to ensure the performance of the product; and welding electrodes are provided at the top and bottom of the capacitor, and the bottom end of the capacitor is welded to the inner copper layer to ensure stable connection. Description of the Drawings

[0031] Figure 1 is a schematic diagram of a new layout structure according to an embodiment of the present invention;

[0032] Figure 2 is a schematic diagram of the structure of a power module according to an embodiment of the present invention;

[0033] Figure 3 is a schematic diagram of the structure of a capacitor according to an embodiment of the present invention.

[0034] Description of the Reference Numerals

[0035] 1. Copper layer 2. Mosfet component

[0036] 3. Capacitor 4. Gate resistor

[0037] 5. Jumper wire 6. Housing

[0038] 7. Upper cover plate 8. Heat sink

[0039] 9. Copper-clad ceramic component 11. Outer copper layer

[0040] 12. Inner copper layer 13. Central copper layer

[0041] 21. S pole of Mosfet component 22. G pole of Mosfet component

[0042] 31. Welding electrode Specific implementation manner

[0043] The following will describe in detail the specific implementation manner of the embodiments of the present invention in conjunction with the accompanying drawings. It should be understood that the specific implementation manner described here is only used to illustrate and explain the embodiments of the present invention, and is not used to limit the embodiments of the present invention.

[0044] In the embodiments of the present invention, unless otherwise stated, the orientation words such as "upper, lower, top, bottom" are usually in the direction shown in the drawings or in terms of the vertical, perpendicular or gravitational directions for describing the relative positional relationship of each component.

[0045] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, such descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those skilled in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0046] As Figure 1 shown is a schematic diagram of a novel layout structure according to an embodiment of the present invention; in Figure 1Among them, the novel layout structure includes a copper layer 1, two Mosfet components 2, two capacitors 3, a gate resistor 4, and a cross wire 5. The copper layer 1 can be symmetrically divided into two groups of outer copper layers 11, two groups of inner copper layers 12, and a group of central copper layers 13 from the outside to the inside. The s-poles 21 of the two Mosfet components are respectively connected to the two groups of inner copper layers 12 in a one-to-one correspondence. The bottoms of the two capacitors 3 are respectively connected to the two groups of inner copper layers 12 in a one-to-one correspondence, and the tops of the two capacitors 3 are respectively connected to the g-poles 22 of the two Mosfet components in a one-to-one correspondence. The gate resistor 4 is connected to the other ends of the two capacitors 3. The two ends of the cross wire 5 are respectively connected to the two groups of inner copper layers 12 in a one-to-one correspondence. The capacitor 3 connecting the gate resistor 4 and the Mosfet component 2 reduces the crosstalk voltage and avoids mis-conduction. The cross wire 5 connecting the two groups of inner copper layers 12 is used to reduce the parasitic inductance connected to the s-pole 21 of the symmetric Mosfet component and suppress high-frequency resonance.

[0047] Through the above technical solution, a capacitor is introduced between the gate resistor and the Mosfet component in the novel layout structure to absorb the transient current generated by the Miller effect, reduce the crosstalk voltage, avoid mis-conduction. The two ends of the cross wire are respectively connected to the two groups of inner copper layers in a one-to-one correspondence, reducing the parasitic inductance connected to the s-pole of the symmetric Mosfet component and suppressing high-frequency resonance, realizing global crosstalk optimization and ensuring the performance of the product.

[0048] In Figure 1 In order to reasonably arrange the Mosfet component 2 and ensure the symmetric arrangement of the two Mosfet components 2, in an embodiment of the present invention, based on the symmetric arrangement of the copper layer 1, the two Mosfet components 2 can be horizontally and correspondingly installed on the two groups of outer copper layers 11.

[0049] In Figure 1 In order to reasonably arrange the gate resistor 4 and reduce the parasitic inductance, in an embodiment of the present invention, the gate resistor 4 can be installed on the central copper layer 13 and be horizontally aligned with the g-poles 22 of the two groups of Mosfet components.

[0050] In Figure 1 In order to reasonably arrange the capacitor 3 and the cross wire 5, considering the space limitation and ensuring the functions of the capacitor 3 and the cross wire 5, in an embodiment of the present invention, based on the symmetric arrangement of the copper layer 1, the two capacitors 3 are respectively installed on the two groups of inner copper layers 12 in a one-to-one correspondence, and the two capacitors 3 are respectively aligned between the g-poles 22 of the two groups of Mosfet components and the gate resistor 4 in a one-to-one correspondence; the cross wire 5 can span across the central copper layer 13 and be horizontally aligned with the s-poles 21 of the two groups of Mosfet components, so as to ensure protection at a reasonable symmetric position and reduce the parasitic inductance generated by the symmetric Mosfet component 2.

[0051] As Figure 3 shown is a schematic structural diagram of a capacitor according to an embodiment of the present invention; inFigure 1 and 3 In 3 , considering the installation and connection method of the capacitor 3, in an embodiment of the present invention, welding electrodes 31 are provided at the top and bottom of the capacitor 3, and the bottom end of the capacitor 3 is welded to the inner copper layer 12, so as to complete the purpose of reducing the crosstalk voltage while ensuring the stability of the capacitor 3.

[0052] Through the above technical solution, the new layout structure is provided with symmetric copper layer arrangements, two Mosfet components, two capacitors, gate resistors and jumper wires. The s poles of the two Mosfet components are respectively connected to two groups of inner copper layers in one-to-one correspondence. The bottom ends of the capacitors are respectively connected to two groups of inner copper layers in one-to-one correspondence. The top ends of the two capacitors are respectively connected to the g poles of the two Mosfet components in one-to-one correspondence. The gate resistors are connected to the other ends of the two capacitors. The two ends of the jumper wires are respectively connected to two groups of inner copper layers in one-to-one correspondence. The two Mosfet components are respectively installed on two groups of outer copper layers. The gate resistors are installed on the central copper layer and are horizontally aligned with the g poles of the two groups of Mosfet components. The introduced capacitors can be respectively installed on two groups of inner copper layers, and the two capacitors are respectively aligned between the g poles of the two groups of Mosfet components and the gate resistors, so that the capacitors can reduce the crosstalk voltage and avoid mis-conduction. The jumper wires span across the central copper layer and are horizontally aligned with the s poles of the two groups of Mosfet components, which is used to reduce the parasitic inductance of the s pole connection of the symmetric Mosfet components and suppress high-frequency resonance to ensure the performance of the product. The top and bottom ends of the capacitor are provided with welding electrodes, and the bottom end of the capacitor is welded to the inner copper layer to ensure stable connection.

[0053] As Figure 2 shown is a schematic structural diagram of a power module according to an embodiment of the present invention. On the other hand, the present invention provides a crosstalk-resistant power module, which includes a housing 6, an upper cover plate 7, a heat sink 8, and a copper-clad ceramic component 9. The copper-clad ceramic component 9 can be composed of multiple groups of new layout structures. Specifically, the upper cover plate 7 can be arranged on the top of the housing 6 and is hermetically connected to the housing 6. The heat sink 8 can be closely arranged at the bottom end of the housing 6. Multiple groups of copper-clad ceramic components 9 can be arranged in the cavity of the housing 6. The copper layer 1, two Mosfet components 2, two capacitors 3, gate resistors 4, and jumper wires 5 in the new layout structure can be reasonably electrically connected to ensure the crosstalk-resistant performance.

[0054] Through the power module as Figure 2 can operate through the copper-clad ceramic component composed of the above multiple groups of new layout structures, ensure the crosstalk-resistant performance of the product, realize the global crosstalk optimization, perform thermal management on the upper cover plate seal and the heat sink, ensure the stable operation of the power module, improve the service life, accelerate heat conduction, and ensure the continuous working ability of the power module.

[0055] In Figure 1In order to reasonably arrange the Mosfet components 2 and ensure the symmetrical arrangement of the two Mosfet components 2, in an embodiment of the present invention, based on the symmetrical arrangement of the copper layer 1, the two Mosfet components 2 can be horizontally and correspondingly mounted on two sets of outer copper layers 11 one by one.

[0056] In Figure 1 order to reasonably arrange the gate resistors 4 and reduce the parasitic inductance, in an embodiment of the present invention, the gate resistors 4 can be mounted on the central copper layer 13 and be horizontally aligned with the g electrodes 22 of the two sets of Mosfet components.

[0057] In Figure 1 order to reasonably arrange the capacitors 3 and the jumper wires 5, considering the space limitation and ensuring the functions of the capacitors 3 and the jumper wires 5, in an embodiment of the present invention, based on the symmetrical arrangement of the copper layer 1, the two capacitors 3 are correspondingly mounted on two sets of inner copper layers 12 one by one, and the two capacitors 3 are correspondingly aligned between the g electrodes 22 of the two sets of Mosfet components and the gate resistors 4; the jumper wires 5 can span across the central copper layer 13 and be horizontally aligned with the s electrodes 21 of the two sets of Mosfet components, so as to ensure protection at reasonable symmetrical positions and reduce the parasitic inductance generated by the symmetrical Mosfet components 2.

[0058] In Figure 1 and 3 order to consider the installation and connection method of the capacitors 3, in an embodiment of the present invention, welding electrodes 31 are provided at the top and bottom of the capacitors 3, and the bottom of the capacitors 3 is welded to the inner copper layer 12 to complete the purpose of reducing the crosstalk voltage while ensuring the stability of the capacitors 3.

[0059] Through the above technical solutions, the power module can work through the copper-clad ceramic component composed of the above multi-group novel layout structures, ensure the anti-crosstalk performance of the product, reduce the parasitic inductance of the s electrode connection of the symmetrical Mosfet components, suppress high-frequency resonance, ensure the global crosstalk optimization of the product performance, perform thermal management on the upper cover plate seal and the heat dissipation plate, ensure the stable operation of the power module, improve the service life, accelerate heat conduction, and ensure the continuous working ability of the power module.

[0060] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, and these simple modifications all belong to the protection scope of the present invention. In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.

[0061] In addition, any combination can be made among various different embodiments of the present invention, as long as it does not violate the idea of the present invention, and it should equally be regarded as the content disclosed by the present invention.

Claims

1. A novel layout structure for optimizing crosstalk, characterized in that The layout structure includes: A copper layer, which symmetrically divides into two groups of outer copper layers, two groups of inner copper layers, and one group of central copper layer from outside to inside; Two Mosfet components, and the s poles of the two Mosfet components are respectively connected to the two groups of inner copper layers in one-to-one correspondence; Two capacitors, the bottom ends of the two capacitors are respectively connected to the two groups of inner copper layers in one-to-one correspondence, and the top ends of the two capacitors are respectively connected to the g poles of the two Mosfet components in one-to-one correspondence; A gate resistor, which is connected to the other ends of the two capacitors; A jumper wire, and the two ends of the jumper wire are respectively connected to the two groups of inner copper layers in one-to-one correspondence.

2. The novel layout structure according to claim 1 is characterized in that: The two Mosfet components are horizontally and correspondingly installed on the two groups of outer copper layers.

3. The novel layout structure according to claim 2, wherein The gate resistor is installed on the central copper layer and is horizontally aligned with the g poles of the two groups of Mosfet components.

4. The novel layout structure according to claim 3, wherein, The two capacitors are respectively installed on the two groups of inner copper layers, and the two capacitors are respectively aligned between the g poles of the two groups of Mosfet components and the gate resistor; The jumper wire straddles the central copper layer and is horizontally aligned with the s poles of the two groups of Mosfet components.

5. The novel layout structure according to claim 4, characterized in that, Welding electrodes are provided at the top and bottom ends of the capacitor, and the bottom end of the capacitor is welded to the inner copper layer.

6. A crosstalk-resistant power module, characterized in that, The power module includes: A housing; An upper cover plate, which is arranged on the top of the housing and is hermetically connected to the housing; A heat dissipation plate, which is closely arranged at the bottom end of the housing; Multiple groups of copper-clad ceramic components, which are arranged in the cavity of the housing, and the copper-clad ceramic components are composed of multiple groups of new layout structures. The new layout structure includes: A copper layer, which symmetrically divides into two groups of outer copper layers, two groups of inner copper layers, and one group of central copper layer from outside to inside; Two Mosfet components, and the S poles of the two Mosfet components are respectively connected to the two groups of inner copper layers in one-to-one correspondence; Two capacitors, the bottom ends of the two capacitors are respectively connected to the two groups of inner copper layers in one-to-one correspondence, and the top ends of the two capacitors are respectively connected to the g poles of the two Mosfet components in one-to-one correspondence; A gate resistor, which is connected to the other ends of the two capacitors through a jumper wire; A jumper wire, and the two ends of the jumper wire are respectively connected to the two groups of inner copper layers in one-to-one correspondence.

7. The power module according to claim 6, characterized in that, The two Mosfet components are horizontally and correspondingly installed on the two groups of outer copper layers.

8. The power module according to claim 7, characterized in that, The gate resistor is installed on the central copper layer and is horizontally aligned with the g poles of the two groups of Mosfet components.

9. The power module according to claim 8, characterized in that, The two capacitors are respectively installed on the two groups of inner copper layers, and the two capacitors are respectively aligned between the g poles of the two groups of Mosfet components and the gate resistor; The jumper wire straddles the central copper layer and is horizontally aligned with the s poles of the two groups of Mosfet components.

10. The power module according to claim 9, characterized in that, Welding electrodes are provided at the top and bottom ends of the capacitor, and the bottom end of the capacitor is welded to the inner copper layer.

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