Electrostatic discharge protection structure, semiconductor power device and manufacturing method of semiconductor power device

Abstract

The invention provides an electrostatic discharge protection structure, a semiconductor power device and a manufacturing method of the semiconductor power device. The electrostatic discharge protection structure comprises a first groove structure, a second groove structure, a first diode string, a first interval oxide layer and a second diode string. The first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. The second trench structure includes a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure. The first diode string is adjacent to the first polysilicon structure and the second polysilicon structure, and is disposed between the first trench structure and the second trench structure. The first spacer oxide layer is disposed on the first diode string. The second diode string is disposed on the first spacer oxide layer and is connected in parallel with the first diode string.

Description

Technical Field

[0001] The present invention relates to an electrostatic discharge protection structure, a semiconductor power device, and a method for manufacturing a semiconductor power device. More specifically, it relates to a trench-type semiconductor power device having an electrostatic discharge protection structure and a method for manufacturing the same. Background Art

[0002] Semiconductor power devices are widely used in the electronics field. A trench power device forms a gate by growing a gate oxide layer on the sidewalls of a gate trench and filling it with polysilicon. It is one of the currently popular power switching devices. The trench power device can improve the utilization efficiency of the device area, enabling a larger device unit channel width to be obtained per unit area, thereby achieving a greater current conduction capacity.

[0003] Semiconductor power devices are vulnerable to voltage spikes caused by electrostatic discharge (ESD) events. The instantaneous large current and voltage caused by an ESD event can cause the gate oxide layer of the trench power device to be broken down, resulting in damage, or even burnout or high leakage. Therefore, semiconductor power devices need to have the function of electrostatic discharge protection. Summary of the Invention

[0004] Embodiments of the present disclosure relate to an electrostatic discharge protection structure. The electrostatic discharge protection structure includes: a first trench structure, a second trench structure, a first diode string, a first spacer oxide layer, and a second diode string. The first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. The second trench structure includes a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure. The first diode string is adjacent to the first polysilicon structure and the second polysilicon structure, and is disposed between the first trench structure and the second trench structure. The first spacer oxide layer is disposed on the first diode string. The second diode string is disposed on the first spacer oxide layer and is disposed in parallel with the first diode string.

[0005] Embodiments of the present disclosure relate to a semiconductor power device. The semiconductor power device includes: a substrate, a lightly doped layer, a first trench structure, a source doping region, an interlayer dielectric layer, a source electrode, a gate electrode, and an electrostatic discharge protection structure. The lightly doped layer is disposed on the substrate. The first trench structure is disposed in the lightly doped layer and extends toward the substrate. The first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. The source doping region is disposed in the lightly doped layer and away from the substrate. The interlayer dielectric layer is disposed on the lightly doped layer. The source electrode is coupled to the source doping region. The gate electrode is coupled to the first polysilicon structure. The electrostatic discharge protection structure is disposed in the interlayer dielectric layer and includes a first diode string, a second diode string, and a first spacer oxide layer. The second diode string is disposed on the first diode string. The first spacer oxide layer is disposed between the first diode string and the second diode string. The first diode string and the second diode string are connected in parallel between the source electrode and the gate electrode.

[0006] Embodiments of the present disclosure relate to a method of manufacturing a semiconductor power device. The manufacturing method includes: forming a lightly doped layer on a substrate; forming a first opening, a second opening, and a third opening extending toward the substrate on the lightly doped layer; forming a first diode string on the second opening and the third opening; forming a first spacer oxide layer on the first diode string and surrounding the first diode string; forming a second diode string on the first spacer oxide layer; forming a first trench structure in the first opening, wherein the first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; forming a source doping region in the lightly doped layer, wherein the source doping region is disposed between the first trench structure and the second opening; and forming a source electrode coupled to the source doping region and forming a gate electrode coupled to the first polysilicon structure. The first diode string and the second diode string are connected in parallel between the source electrode and the gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of some embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0008] Figure 1 is a circuit diagram of a semiconductor power device according to some embodiments of the present disclosure.

[0009] Figure 2 is a schematic diagram of a semiconductor power device according to some embodiments of the present disclosure.

[0010] Figure 3A is a schematic diagram of an electrostatic discharge protection structure according to some embodiments of the present disclosure.

[0011] Figure 3BIt is a circuit diagram of an electrostatic discharge protection structure according to some embodiments of the present disclosure.

[0012] Figure 4 It is a flowchart of a manufacturing method of a semiconductor power device according to some embodiments of the present disclosure.

[0013] Figures 5 to 34 It is a schematic diagram of a manufacturing process of a semiconductor power device according to some embodiments of the present disclosure.

[0014] Figure 35 It is a schematic diagram of a semiconductor power device according to other embodiments of the present disclosure.

[0015] Figure 36 It is a schematic diagram of a semiconductor power device according to other embodiments of the present disclosure and a partial enlarged view.

[0016] The same or similar components are labeled with the same reference numerals in the drawings and the detailed description. From the following detailed description and in conjunction with the accompanying drawings, several embodiments of the present disclosure will be immediately understood. Detailed Description of Specific Embodiments

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are only examples and are not intended to be restrictive. In the present disclosure, a reference to forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Embodiments of the present disclosure are discussed in detail below. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are illustrative only and do not limit the scope of the present disclosure.

[0019] An electrostatic discharge protection structure provided by the present disclosure. The electrostatic discharge protection structure utilizes a stacked design such that a plurality of diode strings for releasing instantaneous large currents can be arranged in parallel with each other according to a stacked structure, not only without occupying additional circuit area (footprint), but also increasing the current value that can be conducted by electrostatic discharge. Compared with a general electrostatic discharge protection structure, the electrostatic discharge protection structure of the present disclosure can have more diode strings for releasing instantaneous large currents on the same circuit area, thereby having a greater electrostatic discharge protection ability.

[0020] The present disclosure further provides a semiconductor power device and a manufacturing method thereof. The semiconductor power device includes the electrostatic discharge protection structure described above. Therefore, compared with a general semiconductor power device, it can have more diode strings for releasing instantaneous large currents on the same circuit area and has a greater electrostatic discharge protection ability.

[0021] Figure 1 FIG. 5 is a circuit diagram of a semiconductor power device 1 according to some embodiments of the present disclosure. The semiconductor power device 1 has a gate electrode G, a drain electrode D, and a source electrode S (or are respectively referred to as a gate terminal G, a drain terminal D, and a source terminal S), and includes a power transistor, a gate resistor RG, and an electrostatic discharge protection structure 150. In some embodiments, the power transistor may be a vertical power transistor 10. The power transistor 10 may be a semiconductor power device of different types or manufactured by different technologies. The source and drain of the power transistor 10 are respectively connected to the source electrode S and the drain electrode D. The gate of the power transistor 10 is coupled to the gate electrode G via the gate resistor RG. The electrostatic discharge protection structure 150 is coupled between the gate electrode G and the source electrode S.

[0022] In Figure 1 the embodiment of, the power transistor 10 is an N-type transistor. However, the present disclosure is not limited thereto. In other embodiments, the power transistor 10 may be a P-type transistor.

[0023] In some embodiments, the electrostatic discharge protection structure 150 includes a plurality of diode strings, and these diode strings are coupled between the gate electrode G and the source electrode S in parallel. Each diode string is formed by connecting a plurality of back-to-back diodes in series. In some embodiments, the arrangement of each diode string is the same.

[0024] As Figure 1 shown in the embodiment of, the electrostatic discharge protection structure 150 includes a diode string 151 and a diode string 156, and the diode string 151 and the diode string 156 each include two back-to-back diodes. It should be understood that the present disclosure uses the number of diode strings and back-to-back diodes shown in Figure 1 as an illustration. However, the present disclosure is not limited thereto, and various numbers of diode strings and various numbers of back-to-back diodes are within the scope of the present disclosure.

[0025] The number of back-to-back diodes in a single diode string determines the breakdown voltage of the electrostatic discharge protection structure 150, and the number of diode strings in parallel determines the conduction current value of the electrostatic discharge protection structure 150. The electrostatic discharge protection structure 150 can be regarded as a current path. The number of back-to-back diodes in a single diode string determines the conduction voltage threshold, and the number of diode strings in parallel determines the width of the current path.

[0026] In some embodiments, the number of back-to-back diodes is determined by the breakdown voltage of the semiconductor power device 10, such as the breakdown voltage of the gate oxide layer of the power transistor 10. More specifically, when an electrostatic discharge event occurs, the gate resistor RG can prevent the large instantaneous current caused by the electrostatic discharge event from directly attacking the gate (such as the gate oxide) of the power transistor 10 from the gate electrode G. The above-mentioned large instantaneous current can flow to the source electrode S through the electrostatic discharge protection structure 150 so as to be conducted away from the power transistor 10. In some embodiments, the source electrode S is coupled to the ground terminal, so the large instantaneous current caused by the electrostatic discharge event can flow to the ground terminal through the electrostatic discharge protection structure 150. In other words, when an electrostatic discharge event occurs, the gate resistor RG and the electrostatic discharge protection structure 150 can provide electrostatic discharge protection for the power transistor 10. However, on the premise that the electrostatic discharge protection structure 150 can function, the condition is that the breakdown voltage of the electrostatic discharge protection structure 150 is less than the breakdown voltage of the gate oxide layer of the power transistor 10. When the voltage caused by the large instantaneous current first reaches the breakdown voltage of the electrostatic discharge protection structure 150, the electrostatic discharge protection structure 150 can be turned on and will not flow to the gate of the power transistor 10. Therefore, the number of back-to-back diodes in each diode string is limited by the breakdown voltage of the gate oxide layer of the power transistor 10.

[0027] Figure 2 FIG. 1 is a schematic diagram of a semiconductor power device 1 according to some embodiments of the present disclosure. The semiconductor power device 1 includes a substrate 100, a lightly doped layer 110, and an interlayer dielectric layer 130 stacked. The lightly doped layer 110 is disposed on the substrate 100, and the interlayer dielectric layer 130 is disposed on the lightly doped layer 110.

[0028] In some embodiments, the substrate 100 can be disposed adjacent to the upper surface of a silicon wafer or other semiconductor material substrate. In some embodiments, the substrate 100 is part of a silicon wafer. The material of the substrate 100 may include single crystal silicon material, epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the doping concentration of the substrate 100 is greater than the doping concentration of the lightly doped region 110.

[0029] In some embodiments, the lightly doped layer 110 may include, for example, single-crystalline silicon material, epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials, which may be N-type or P-type. In some embodiments, the lightly doped layer 110 is an N-type (first conductivity type) epitaxial material. For ease of illustration, the lightly doped layer 110 is taken as an example of N-type, and the power transistor 10 of N-type is taken as an example, but the present disclosure is not limited thereto. The lightly doped layer 110 of N-type (first conductivity type) or P-type (second conductivity type) can be adjusted according to the conductivity type of the power transistor 10.

[0030] The semiconductor power device 1 further includes a plurality of trench structures TR1, trench structure TR2, trench structure TR3, and an electrostatic discharge protection structure 150. The plurality of trench structures TR1, trench structure TR2, and trench structure TR3 are disposed in the lightly doped layer 110, extend toward the substrate 100, and do not contact the substrate 100. Each trench structure may have sidewalls and a bottom surface. In some embodiments, each trench structure has vertical sidewalls and an arc-shaped bottom surface. The electrostatic discharge protection structure 150 is disposed in the interlayer dielectric layer 130.

[0031] Each trench structure TR1 includes a polysilicon structure 142 and an oxide layer 141 surrounding the polysilicon structure 142. The trench structure TR2 includes a polysilicon structure 144 and an oxide layer 143 surrounding the polysilicon structure 144. The trench structure TR3 includes a polysilicon structure 146 and an oxide layer 145 surrounding the polysilicon structure 146. In some embodiments, the plurality of trench structures TR1 are part of the gate structure of the power transistor 10, and the oxide layer 141 in the trench structure TR1 is the gate oxide layer of the power transistor 10. In some embodiments, the trench structures TR2 and TR3 are part of the electrostatic discharge protection structure 150.

[0032] The semiconductor power device 1 further includes a plurality of body doping regions 121, a plurality of source doping regions 122, a plurality of heavily doped regions 123, a drain doping region 124, a heavily doped region 125, a plurality of conductive plugs CP1, and a conductive plug CP2. The body doping regions 121, source doping regions 122, heavily doped regions 123, drain doping region 124, and heavily doped region 125 are disposed in the lightly doped layer 110. One of the body doping regions 121 is located between two adjacent trench structures TR1 and is adjacent to the oxide layers 141 of the two trench structures TR1. Another body doping region 121 is located between the trench structure TR1 and the adjacent trench structure TR2 and is adjacent to the oxide layer 141 of the trench structure TR1 and the oxide layer 143 of the trench structure TR2. One of the source doping regions 122 is located between two adjacent trench structures TR1 and on the corresponding body doping region 121, and another source doping region 122 is located between the trench structure TR1 and the adjacent trench structure TR2 and on the corresponding body doping region 121. In some embodiments, the thickness of the source doping region 122 is less than the thickness of the body doping region 121. The source doping region 122 is adjacent to the body doping region 121, the oxide layer 141, and / or the oxide layer 143. The drain doping region 124 is spaced apart from the trench structure TR1, the trench structure TR2, and the trench structure TR3.

[0033] The plurality of heavily doped regions 123 are respectively disposed in the plurality of body doping regions 121. In some embodiments, the heavily doped region 123 is not adjacent to the source doping region 122. The heavily doped region 125 is disposed in the lightly doped layer 110, under the drain doping region 124, and is not adjacent to the drain doping region 124. The plurality of conductive plugs CP1 pass through the interlayer dielectric layer 130 and further respectively pass through the heavily doped regions 123 from the plurality of source doping regions 122 to the plurality of body doping regions 121. The conductive plug CP2 passes through the interlayer dielectric layer 130 and into the heavily doped region 125 from the drain doping region 124. The configuration of each conductive plug may vary according to process or electrical requirements. The material of the conductive plug may include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or other metals or alloys. In some embodiments, the conductive plug CP1 and the conductive plug CP2 have approximately the same length. In some embodiments, the conductive plug CP1 and the conductive plug CP2 have a configuration that is wider at the top and narrower at the bottom.

[0034] The semiconductor power device 1 further includes metal wires 161, 162, and 163 disposed on the interlayer dielectric layer 130. The metal wire 161 is electrically coupled to the source doping region 122 through the conductive plug CP1 and is connected to the source electrode S through an interconnect structure (not shown). The metal wire 162 is electrically coupled to the polysilicon structure 142 in the trench structure TR1 and is connected to the gate electrode G through an interconnect structure. The metal wire 163 is electrically coupled to the drain doping region 124 through the conductive plug CP2 and is connected to the drain electrode D through an interconnect structure. The electrostatic discharge protection structure 150 is coupled between the metal wire 161 and the metal wire 162. In other words, the electrostatic discharge protection structure 150 is coupled between the source electrode S and the gate electrode G.

[0035] In some embodiments, the width of the metal wire 161 is greater than that of the metal wires 162 and 163. The materials of the metal wires 161, 162, and 163 may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys. In some embodiments, the metal wires 161, 162, and 163 are the metal layers (such as the M1 layer) closest to the lightly doped layer 110.

[0036] For ease of illustration and to keep the drawings simple, for the symbol and details of the electrostatic discharge protection structure 150, please refer to Figure 3A and Figure 3B . Figure 3A is Figure 2 a schematic diagram of the electrostatic discharge protection structure 150 in Figure 3B is Figure 2 the circuit diagram of the electrostatic discharge protection structure 150 in

[0037] The electrostatic discharge protection structure 150 includes trench structures TR2, TR3, diode strings 151, 156, spacer oxide layers SX1, SX2, conductive plugs CP3, and conductive plugs CP4. The trench structures TR2 and TR3 are disposed in the lightly doped layer 110. The diode string 151 is coupled between the trench structures TR2 and TR3 and is disposed on the lightly doped layer 110. The diode string 156 is disposed on the diode string 151 and is electrically isolated from each other by the spacer oxide layer SX1. The spacer oxide layer SX2 is disposed on the diode string 156 and surrounds the diode string 156.

[0038] The conductive plug CP3 and the conductive plug CP4 are electrically coupled to the source electrode S and the gate electrode G through the metal lines 161 and 162, respectively. The diode strings 151 and 156 are connected in parallel between the conductive plug CP3 and the conductive plug CP4. In other words, the diode strings 151 and 156 are connected in parallel between the source electrode S and the gate electrode G.

[0039] The trench structure TR2 includes a polysilicon structure 144 and an oxide layer 143 surrounding the polysilicon structure 144. The trench structure TR3 includes a polysilicon structure 146 and an oxide layer 145 surrounding the polysilicon structure 146. As Figure 2 and Figure 3A shown, the oxide layer 143 and the oxide layer 145 extend along the lightly doped layer 110 and are adjacent to each other. In some embodiments, the oxide layer 143 and the oxide layer 145 are a single continuous structure.

[0040] The diode string 151 includes a plurality of doped regions 151a and a plurality of doped regions 151b arranged alternately. The doped regions 151a and the doped regions 151b have different conductivity types. Hereinafter, the doped region 151a is an N-type and the doped region 151b is a P-type for illustration, and the number of doped regions in Figure 2 and Figure 3A is taken as an example, which is not intended to limit the present disclosure.

[0041] In some embodiments, the diode string 151 includes three N-type doped regions 151a and two P-type doped regions 151b. The doped region 151a includes the doped region 151a1, the doped region 151a1, and the doped region 151a3, and the doped region 151b includes the doped region 151b1 and the doped region 151b2. The doped region 151a1, the doped region 151b1, the doped region 151a2, the doped region 151b2, and the doped region 151a3 are arranged in sequence, and the doped region 151a1 and the doped region 151a3 are used as the first end and the second end of the diode string 151. The first end of the diode string 151 is coupled to the source electrode S and is adjacent to the polysilicon structure 144 of the trench structure TR2. In some embodiments, the doped region 151a1 and the polysilicon structure 144 are a single continuous structure. The second end of the diode string 151 is coupled to the gate electrode G and is adjacent to the polysilicon structure 146 of the trench structure TR3. In some embodiments, the doped region 151a3 and the polysilicon structure 146 are a single continuous structure.

[0042] In the diode string 151, two adjacent doped regions have different conductivity types, so PN junctions are formed at the adjacent interfaces. As Figure 3B shown, the diode string 151 includes four adjacent interfaces, so four PN junctions are formed. Because different conductivity types are arranged alternately, these four PN junctions form two back-to-back diode strings connected in series.

[0043] In some embodiments, the diode string 151 and the diode string 156 have the same number and type of doped regions. In some embodiments, the structures of the diode string 151 and the diode string 156 are the same.

[0044] In some embodiments, the diode string 156 includes three N-type doped regions 156a and two P-type doped regions 156b. The doped region 156a includes the doped regions 156a1, 156a2, and 156a3, and the doped region 156b includes the doped regions 156b1 and 156b2. The doped regions 156a1, 156b1, 156a2, 156b2, and 156a3 are arranged in sequence, and the doped regions 156a1 and 156a3 serve as the first end and the second end of the diode string 156. The first end of the diode string 156 is coupled to the source electrode S, and the second end of the diode string 156 is coupled to the gate electrode G. Four adjacent interfaces are included in the diode string 156, thus forming four PN junctions. These four PN junctions form two back-to-back diodes connected in series.

[0045] The spacer oxide layer SX1 is disposed on the diode string 151 and surrounds the diode string 151. As Figure 2 shown, the spacer oxide layer SX1 further extends on the surface of the doped layer 110 and covers the source doped region 122, the drain doped region 124, and the trench structure TR1, wherein the conductive plugs CP1 and CP2 further penetrate through the spacer oxide layer SX1. The spacer oxide layer SX2 is disposed on the diode string 156 and surrounds the diode string 156. The spacer oxide layer SX2 is adjacent to the spacer oxide layer SX1 along the side surface of the diode string 156. The diode string 151 and the diode string 156 are separated from the interlayer dielectric layer 130 by the spacer oxide layer SX1 and the spacer oxide layer SX2.

[0046] The electrostatic discharge protection structure 150 further includes a heavily doped region 147 and a heavily doped region 148. The heavily doped region 147 is disposed in the doped region 151a1, and the heavily doped region 148 is disposed in the doped region 151a3. The conductive plug CP3 penetrates through the spacer oxide layer SX2, the doped region 156a1, and the spacer oxide layer SX1 to the heavily doped region 147 in the doped region 151a1, and couples the source electrode S to the doped regions 151a1 and 156a1. The conductive plug CP4 penetrates through the spacer oxide layer SX2, the doped region 156a3, and the spacer oxide layer SX1 to the heavily doped region 148 in the doped region 151a3, and couples the gate electrode G to the doped regions 151a3 and 156a3.

[0047] One end of the conductive plug CP3 contacts the heavily doped region 147, and the width of the heavily doped region 147 is greater than the width of one end of the conductive plug CP3. Therefore, the heavily doped region 147 surrounds one end of the conductive plug CP3. One end of the conductive plug CP4 contacts the heavily doped region 148, and the width of the heavily doped region 148 is greater than the width of one end of the conductive plug CP4. Therefore, the heavily doped region 148 surrounds one end of the conductive plug CP4.

[0048] Under a preset fixed breakdown voltage, the current that can be conducted by some prior art electrostatic discharge protection structures is limited by the available circuit area. Generally, multiple diodes in the electrostatic discharge protection structure are arranged on the same plane. Compared with the present disclosure, the multiple diodes in the electrostatic discharge protection structure 150 provided by the present disclosure make more use of the three-dimensional space, are stacked in the available circuit area, and the diode strings in different layers are separated by the spacer oxide layer SX1. Therefore, for the same circuit area, the electrostatic discharge protection structure 150 provided by the present disclosure has a higher density of diodes, and then the parallel connection is used to increase the width of the equivalent current path and reduce the resistance value, thereby increasing the current value that the electrostatic discharge protection structure 150 can conduct.

[0049] Figure 4 is a flowchart of a manufacturing method 4 of a semiconductor power device according to some embodiments of the present disclosure. The manufacturing method 4 includes steps S41, S42, S43, S44, S45, S46, and S47. Figures 5 to 34 is a schematic diagram of a manufacturing process of a semiconductor power device according to some embodiments of the present disclosure. For ease of understanding, the manufacturing method 4 is described in conjunction with Figures 5 to 34 for illustration.

[0050] Refer to Figure 5 . In step S41, a lightly doped layer 110 is formed on the substrate 100. Then, a hard mask oxide layer 201 is formed on the lightly doped layer 110 using a thermal oxidation process, and a patterned photoresist layer 202 is formed on the hard mask oxide layer 201. The hard mask oxide layer 201 is etched according to the patterned photoresist layer 202 to transfer the pattern on the photoresist layer 202 to the hard mask oxide layer 201. In some embodiments, when the pattern on the photoresist layer 202 is transferred to the hard mask oxide layer 201, the photoresist layer 202 is removed.

[0051] Refer to Figure 6 . In step S42, a plurality of openings O1, O2, and O3 extending towards the substrate 100 are formed in the lightly doped layer 110. Among them, the positions of the plurality of openings O1, O2, and O3 correspond to the pattern of the hard mask oxide layer 201. Refer to Figure 7 . After the plurality of openings O1, O2, and O3 are formed, the hard mask oxide layer 201 is removed.

[0052] In some embodiments, after the oxide hard mask 201 is removed, a sacrificial oxide layer is formed on the exposed surface of the lightly doped layer 110 through an oxidation process, and then the sacrificial oxide layer is removed. The oxidation process can be performed by adding oxygen and heating to form an oxide, such as silicon dioxide, on the surface of the lightly doped layer 110. In some embodiments, the formation and removal of the sacrificial oxide layer is intended to optimize the surface of the lightly doped layer 110.

[0053] refer to Figures 8 to 10 In step S43, a diode string 151 is formed on the opening O2 and the opening O3. Figure 8 As shown, a gate oxide layer 203 is formed on the surface of the lightly doped layer 110. The gate oxide layer 203 is also formed on the surface of the opening O1, the opening O2, and the opening O3. In some embodiments, the thickness of the gate oxide layer 203 is substantially uniform. Figure 9 As shown, polysilicon is formed on the gate oxide layer 203 and fills the openings O1, O2, and O3. In some embodiments, a planarization process is performed after the polysilicon is formed to provide a flat surface. Next, an ion implantation process is performed on the polysilicon to form polysilicon 204 of the second conductivity type (P-type). In some embodiments, a thermal annealing process is performed on the polysilicon 204 to remove damage caused by the ion implantation process.

[0054] like Figure 10 As shown, a photoresist layer 205 is formed on the polysilicon 204. The photoresist layer 205 defines the locations of the doped regions 151a1, 1511a2, and 151a3 in the diode string 151. The openings in the photoresist layer 205 expose a portion of the surface of the polysilicon 204. Next, using the photoresist layer 205 as a mask, an ion implantation process is performed on the exposed portion of the polysilicon 204, thereby forming the doped regions 151a1, 1511a2, and 151a3 in the exposed portion of the polysilicon 204. Furthermore, the polysilicon 204 in the openings O2 and O3 is also implanted to change its doping concentration, thereby converting the polysilicon 204 in the opening O2 into the polysilicon structure 144, and the polysilicon 204 in the opening O3 into the polysilicon structure 146. After the ion implantation process, the photoresist layer 205 is removed. Since part of the polysilicon 204 is formed into the doping region 151a1, the doping region 151a2 and the doping region 151a3, the polysilicon 204 between the doping region 151a1 and the doping region 151a3 is the doping region 151b1 and the doping region 151b2. Therefore, the doping region 151a and the doping region 151b of the diode string 151 are Figure 10formed by the steps in. The conductivity types of the doped regions 151a1, 151a2, 151a3, the polysilicon structure 144, and the polysilicon structure 146 formed after the ion implantation process are different from the conductivity type of the polysilicon 204. In other words, the conductivity types of the doped regions 151a1, 151a2, 151a3, the polysilicon structure 144, and the polysilicon structure 146 are different from the conductivity types of the doped regions 151b1 and 151b2.

[0055] Reference Figure 11 . A hard mask layer 206 is formed on the polysilicon 204, the doped region 151a, and the doped region 151b, and a photoresist layer 207 is formed on the hard mask layer 206. The photoresist layer 207 is used to define the position of the electrostatic discharge protection structure 150. More specifically, the photoresist layer 207 covers the position of the electrostatic discharge protection structure 150. Reference Figure 12 . An etching process is performed on the hard mask layer 206 according to the photoresist layer 207, so that the portion of the hard mask layer 206 not covered by the photoresist layer 207 is removed. Then, the photoresist layer 207 is removed.

[0056] Reference Figure 13 . An etching process is performed on the polysilicon 204 according to the hard mask layer 206 to remove the polysilicon 204 not covered by the hard mask layer 206. In some embodiments, the polysilicon 204 filled in the opening O1 is not removed. When the etching process is completed, the top surface of the remaining polysilicon 204 is substantially coplanar with the top surface of the lightly doped layer 110. Reference Figure 14 . The hard mask layer 206 covering the diode string 151 and the gate oxide layer 203 covering the lightly doped layer 110 are removed. The original gate oxide layer 203 becomes discontinuous multiple parts. The gate oxide layer 203 in the opening O1 becomes the oxide layer 141, and the gate oxide layers 203 in the openings O2 and O3 become the oxide layers 143 and 145 respectively.

[0057] Reference Figure 15 . An oxide layer 207 is formed on the lightly doped layer 110. The oxide layer 207 further covers the diode string 151, the oxide layer 141, the polysilicon 204, a part of the oxide layer 143, and a part of the oxide layer 145. In some embodiments, the oxide layer 207 is formed by a thermal oxidation process. Reference Figure 16 . A photoresist layer 208 is formed on the oxide layer 207. The photoresist layer 208 is used to define the position of the body doped region 121. Then, an ion implantation process is performed on the lightly doped layer 110 according to the photoresist layer 208 to make a part of the lightly doped layer 110 become the body doped region 121. Reference Figure 17 . When the body doped region 121 is formed, the photoresist layer 208 and the oxide layer 207 are removed.

[0058] Reference Figure 18 。In step S44, an isolation oxide layer SX1 is formed on the diode string 151 and surrounds the diode string 151. The isolation oxide layer SX1 is further formed on the lightly doped layer 110, the polysilicon 204, the oxide layer 141, the oxide layer 143, and the oxide layer 145. After the isolation oxide layer SX1 is formed, the diode string 151 is surrounded by the isolation oxide layer SX1, the oxide layer 143, and the oxide layer 145. In some embodiments, the thickness of the isolation oxide layer SX1 is greater than the thickness of the oxide layer 207. In some embodiments, the isolation oxide layer SX1 is formed by a thin film process, such as a chemical vapor deposition (CVD) process. In some embodiments, the isolation degree between the diode string 151 and adjacent components can be determined by the thickness of the isolation oxide layer SX1, and the isolation oxide layer SX1 formed by CVD can precisely control the deposition thickness.

[0059] Reference Figures 19 to 24 。In step S45, a diode string 156 is formed on the isolation oxide layer SX1. As Figure 19 shown, polysilicon 209 of the second conductivity type (P-type) is formed on the isolation oxide layer SX1. In some embodiments, the polysilicon 209 is conformally formed on the isolation oxide layer SX1. As Figure 20 shown, a hard mask layer 210 is formed on the polysilicon 209, and a photoresist layer 211 is formed on the hard mask layer 210. The photoresist layer 211 is used to define the position of the diode string 156. As Figure 21 shown, according to the photoresist layer 211, an etching process is performed on the hard mask layer 210, so that the hard mask layer 210 located under the photoresist layer 211 is retained, and the other parts of the hard mask layer 210 are removed. After the etching process is completed, the photoresist layer 211 is removed. As Figure 22 shown, according to the remaining hard mask layer 210, another etching process is performed on the polysilicon 209, so that the polysilicon 209 not covered by the hard mask layer 210 is removed, and the polysilicon 209 located under the hard mask layer 210 is retained. When the etching process on the polysilicon 209 is completed, the hard mask layer 210 is removed.

[0060] As Figure 23 shown, an isolation oxide layer SX2 is formed on the polysilicon 209 and surrounds the isolation oxide layer SX2. Among them, the isolation oxide layer SX2 extends along the sidewall of the polysilicon 209 and is adjacent to the isolation oxide layer SX1.

[0061] As Figure 24As shown, a photoresist layer 211 is formed on the spacer oxide layer SX2. The photoresist layer 211 is used to define the positions of the doped region 156a, the source doped region 122, and the drain doped region 124. Then, in step 46, an ion implantation process is performed on the polysilicon 209, the lightly doped region 110, and the body doped region 121 according to the photoresist layer 211 to form the trench structure TR1 and the source doped region 122. The regions of the polysilicon 209 without the photoresist layer 211 form the N-type (first conductivity type) doped regions 156a1, 156a2, and 156a3; the upper part of the body doped region 121 forms the source doped region 122; the polysilicon 204 becomes the polysilicon structure 142; and a part of the lightly doped region 110 forms the drain doped region 124. Since a part of the polysilicon 209 is formed into the doped regions 156a1, 156a2, and 156a3, the polysilicon 209 between the doped region 156a1 and the doped region 156a3 is the doped regions 156b1 and 156b2. Therefore, the doped regions 156a and 156b of the diode string 156 are formed in Figure 24 the steps in which the doped regions 156a and 156b have different conductivity types.

[0062] Reference Figure 25 . After the ion implantation process is completed, the photoresist layer 211 is removed. In some embodiments, after the photoresist layer 211 is removed, a thermal annealing process is performed on the polysilicon structure 142, the source doped region 122, the doped region 156a, and the drain doped region 124.

[0063] Reference Figure 26 . An interlayer dielectric layer 130 is formed on the spacer oxide layer SX1 and the spacer oxide layer SX2.

[0064] Reference Figure 27 . A photoresist layer 212 is formed on the interlayer dielectric layer 130. The photoresist layer 212 is used to define the positions of the conductive plugs CP1, CP2, CP3, and CP4. Reference Figure 28 . According to the photoresist layer 212, an etching process is performed on the interlayer dielectric layer 130, the spacer oxide layer SX1, and the spacer oxide layer SX2 to form the openings OC1, OC2, OC3, and OC4. Specifically, the openings OC1, OC2, OC3, and OC4 respectively correspond to the conductive plugs CP1, CP2, CP3, and CP4. A part of the source doped region 122 is exposed through the opening OC1; a part of the drain doped region 124 is exposed through the opening OC2; a part of the doped region 156a1 is exposed through the opening OC3; and a part of the doped region 156a3 is exposed through the opening OC4. Reference Figure 29After the etching process is completed, the photoresist layer 212 is removed.

[0065] Reference Figure 30 An etching process is performed on the source doping region 122, the drain doping region 124, the doping region 156a1, and the doping region 156a3 through the openings OC1, OC2, OC3, and OC4. After the etching process, the opening OC1 extends into the substrate 100 to the top surface of the body doping region 121, the opening OC2 extends into the substrate 100 to the bottom surface of the drain doping region 124, and the openings OC3 and OC4 extend into the substrate 100 to the top surface of the spacer oxide layer SX1. In some embodiments, a portion of the interlayer dielectric layer 130 is etched simultaneously, so the thickness of the interlayer dielectric layer 130 is reduced.

[0066] Reference Figure 31 An etching process is performed on the spacer oxide layer SX1 through the openings OC3 and OC4, causing the openings OC3 and OC4 to extend into the substrate 100 and penetrate the spacer oxide layer SX1 to the top surfaces of the doping regions 151a1 and 151a3.

[0067] Reference Figure 32 An etching process is performed on the body doping region 121, the lightly doped layer 110, the doping region 151a1, and the doping region 151a3 through the openings OC1, OC2, OC3, and OC4. After the etching process, the opening OC1 extends into the substrate 100 into the body doping region 121, the opening OC2 extends into the substrate 100 into the lightly doped layer 110, the opening OC3 extends into the substrate 100 into the doping region 151a1, and the opening OC4 extends into the substrate 100 into the doping region 151a3.

[0068] Reference Figure 33 After an ion implantation process is performed on the body doping region 121, the lightly doped layer 110, the doping region 151a1, and the doping region 151a3 through the openings OC1, OC2, OC3, and OC4, heavily doped regions 123, 125, 147, and 148 are formed. The heavily doped regions 123, 125, 147, and 148 are P-type (second conductivity type) doping regions, which are used as ohmic contacts between the conductive plugs and the doping regions.

[0069] Reference Figure 34 And Figure 2 In step 47, a source electrode S is formed to couple the source doping region 122 and a gate electrode G is formed to couple the polysilicon structure 142. As Figure 34As shown, a conductive material is formed in openings OC1, OC2, OC3, and OC4 and on the interlayer dielectric layer 130, and then a back-etching process is performed to make the top surface of the interlayer dielectric layer 130 coplanar with the top surface of the conductive material. After the openings OC1, OC2, OC3, and OC4 are filled with the conductive material, conductive plugs CP1, CP2, CP3, and CP4 are formed. In some embodiments, the filled conductive material is a metal. In some embodiments, the filled conductive material is tungsten (W).

[0100] Referring again to Figure 2 . Metal lines 161, 162, and 163 are formed on the interlayer dielectric layer 130, where the metal lines 161, 162, and 163 are separated from each other. The metal line 161 is used to connect to the source electrode S; the metal line 162 is used to connect to the gate electrode G; and the metal line 163 is used to connect to the drain electrode D. The metal line 161 is adjacent to the conductive plugs CP1 and CP3, so that the conductive plugs CP1 and CP3 can be electrically connected to the source electrode S through the metal line 161. The metal line 162 is adjacent to the conductive plug CP4, so that the conductive plug CP4 can be electrically connected to the gate electrode G through the metal line 162. The metal line 163 is adjacent to the conductive plug CP2, so that the conductive plug C2 can be electrically connected to the drain electrode D through the metal line 163.

[0101] It should be understood that the semiconductor power device 1 of the present disclosure is not limited to the above structure. For example, implementing the gate of the semiconductor power device 1 with a different structure is also within the scope of the present disclosure. Referring to Figure 35 and Figure 36 . Figure 35 is a schematic diagram of a semiconductor power device 2 according to other embodiments of the present disclosure. Figure 36 is a schematic diagram and a partial enlarged view of a semiconductor power device 3 according to other embodiments of the present disclosure. For ease of understanding, Figure 35 and Figure 36 The symbols in Figure 1 , Figure 2 are the same as the symbols in FIG. 3, however, it does not mean that the elements with the same symbols must be the same.

[0102] The semiconductor power device 2 is substantially similar to the semiconductor power device 1, except for the trench structure. Specifically, the trench structure TR1 of the semiconductor power device 2 is arranged in the form of a split-gate. The trench structure TR1 of the semiconductor power device 2 has two separate polysilicon structures, namely the polysilicon structure 142a and the polysilicon structure 142b, where the polysilicon structure 142a is arranged on the polysilicon structure 142b. In addition, the oxide layer 141 of the trench structure TR1 further extends between the polysilicon structure 142a and the polysilicon structure 142b. In some embodiments, the polysilicon structure 142a serves as part of the gate structure, while the polysilicon structure 142b serves as part of the source structure.

[0103] The semiconductor power device 3 is substantially similar to the semiconductor power device 1, except that the power transistor of the semiconductor power device 3 includes a dual trench structure. The semiconductor power device 3 further includes a trench structure TR5, a conductive plug CP5, a heavily doped region 126, and a heavily doped region 127. The trench structure TR5 is arranged between two trench structures TR1 and between the trench structure TR1 and the trench structure TR2. The trench structure TR5 is arranged in the lightly doped layer 110 and extends into the substrate 110 through the source doping region 122 and protrudes from the body doping region 121, where the depth of the trench structure TR5 is less than the depth of the trench structure TR1. The trench structure TR5 includes a polysilicon structure 172 and an oxide layer 171 surrounding the polysilicon structure 172. The conductive plug CP5 is arranged on both sides of the trench structure TR5. The conductive plug CP5 is connected to the metal wire 161 and passes through the interlayer dielectric layer 130, the spacer oxide layer SX1, and the source doping region 122 to the heavily doped region 126 in the body doping region 121. The heavily doped region 127 is arranged in the polysilicon structure 142 and is adjacent to the spacer oxide layer SX1. The conductive plug CP1 is arranged on the trench structure TR1 and extends into the heavily doped region 127. In some embodiments, the oxide layer 171 and the polysilicon structure 172 are part of the gate structure, and the oxide layer 141 and the polysilicon structure 142 are part of the source structure.

[0070] In this document, spatial relative terms such as "under", "below", "lower", "above", "upper", "left", "right", etc. may be used for the convenience of description to describe the relationship between one component or feature and another or more components or features as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be intermediate components.

[0071] As used herein, the terms "about", "substantially", "essentially", and "approximately" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs nearly. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges may be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include the endpoints unless otherwise specified. The term "substantially coplanar" may refer to a positional difference between two surfaces located along the same plane that is within a number of micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm of being located along the same plane. When a numerical value or characteristic is referred to as being "substantially" the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of the value.

[0072] The foregoing outlines the features of several embodiments and the detailed aspects of the present disclosure. The embodiments described in the present disclosure can be readily used as a basis for designing or modifying other processes and structures so as to facilitate the implementation of the same or similar purposes and / or achieve the same or similar advantages of the embodiments presented herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. An electrostatic discharge protection structure, comprising: A first trench structure, including a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; A second trench structure, including a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure; A first diode string, adjacent to the first polysilicon structure and the second polysilicon structure, and disposed between the first trench structure and the second trench structure; A first spacer oxide layer, disposed on the first diode string; and A second diode string, disposed on the first spacer oxide layer, and disposed in parallel with the first diode string.

2. The electrostatic discharge protection structure according to claim 1, wherein the first diode string includes: A plurality of first doped regions having a first conductivity type; and A plurality of second doped regions having a second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are alternately arranged, and a PN junction is formed at an interface where each first doped region is adjacent to a second doped region.

3. The electrostatic discharge protection structure according to claim 2, wherein a first one of the plurality of first doped regions is adjacent to the first polysilicon structure, and a second one of the plurality of first doped regions is adjacent to the second polysilicon structure.

4. The electrostatic discharge protection structure according to claim 3, wherein the first polysilicon structure and the second polysilicon structure have the first conductivity type.

5. The electrostatic discharge protection structure according to claim 3, wherein the first conductivity type is N-type, and the second conductivity type is P-type.

6. The electrostatic discharge protection structure according to claim 3, wherein the second diode string includes: A plurality of third doped regions having the first conductivity type; and A plurality of fourth doped regions having the second conductivity type, wherein the plurality of third doped regions and the plurality of fourth doped regions are alternately arranged, and a PN junction is formed at an interface where each third doped region is adjacent to a fourth doped region.

7. The electrostatic discharge protection structure according to claim 6, further comprising: A first conductive plug, passing through a first one of the plurality of third doped regions and the first spacer oxide layer to a first one of the plurality of first doped regions, and coupling the first electrode to the first one of the plurality of third doped regions and the first one of the plurality of first doped regions; A second conductive plug, passing through a second one of the plurality of third doped regions and the first spacer oxide layer to a second one of the plurality of first doped regions, and coupling the second electrode to the second one of the plurality of third doped regions and the second one of the plurality of first doped regions; A first heavily doped region, disposed in a first one of the plurality of first doped regions and surrounding one end of the first conductive plug; And A second heavily doped region, disposed in a second one of the plurality of first doped regions and surrounding one end of the second conductive plug.

8. The electrostatic discharge protection structure according to claim 1, further comprising: A second spacer oxide layer, disposed on the second diode string and surrounding the second diode string.

9. The electrostatic discharge protection structure according to claim 1, wherein the first oxide layer and the second oxide layer are adjacent to each other, and the first diode string is disposed between the first spacer oxide layer and the mutually adjacent first oxide layer and second oxide layer.

10. The electrostatic discharge protection structure according to claim 1, wherein each of the first diode string and the second diode string includes a plurality of back-to-back diode strings connected in series.

11. A semiconductor power device, comprising: a substrate; a lightly doped layer disposed on the substrate; a first trench structure disposed in the lightly doped layer and extending into the substrate, wherein the first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; a source doping region disposed in the lightly doped layer and away from the substrate; an interlayer dielectric layer disposed on the lightly doped layer; a source electrode coupled to the source doping region; a gate electrode coupled to the first polysilicon structure; and an electrostatic discharge protection structure disposed in the interlayer dielectric layer, comprising: a first diode string; a second diode string disposed on the first diode string; and a first spacer oxide layer disposed between the first diode string and the second diode string; wherein the first diode string and the second diode string are connected in parallel between the source electrode and the gate electrode.

12. The semiconductor power device according to claim 11, wherein the electrostatic discharge protection structure further comprises: a second spacer oxide layer disposed on the side surfaces of the second diode string and the second diode string and adjacent to the first spacer oxide layer.

13. The semiconductor power device according to claim 11, wherein each of the first diode string and the second diode string includes: a plurality of first doping regions having a first conductivity type; a plurality of second doping regions having a second conductivity type, wherein the plurality of second doping regions are alternately arranged with the plurality of first doping regions, and a PN junction is formed at an interface where each first doping region is adjacent to a second doping region.

14. The semiconductor power device according to claim 13, further comprising: A first conductive plug penetrates through the second diode string and the spacer oxide layer to the first diode string, and couples the source electrode to the first ends of the plurality of first doped regions of the first diode string and the first ends of the plurality of first doped regions of the second diode string; and a second conductive plug passing through the second diode string and the spacer oxide layer to the first diode string, and coupling the gate electrode to the second ends of the plurality of first doping regions of the first diode string and the plurality of first doping regions of the second diode string; a first heavily doped region disposed in the first ends of the plurality of first doping regions of the first diode string and surrounding one end of the first conductive plug; and a second heavily doped region disposed in the second ends of the plurality of first doping regions of the first diode string and surrounding one end of the second conductive plug.

15. The semiconductor power device according to claim 14, wherein the first conductivity type is N-type and the second conductivity type is P-type.

16. The semiconductor power device according to claim 11, further comprising: A body doping region is disposed in the lightly doped layer and adjacent to the first oxide layer; and A drain doping region is disposed in the lightly doped layer, wherein the source doping region is disposed in the body doping region.

17. The semiconductor power device according to claim 16, wherein the first spacer oxide layer extends to the sidewalls of the first diode string and the lightly doped layer, and covers the source doping region, the drain doping region, and the first trench structure.

18. The semiconductor power device according to claim 16, further comprising: A third heavily doped region is disposed in the body doping region; and A third conductive plug is coupled to the source electrode and penetrates through the interlayer dielectric layer and the source doping region into the body doping region, wherein the third heavily doped region surrounds one end of the third conductive plug.

19. The semiconductor power device according to claim 16, further comprising: A drain electrode is disposed on the interlayer dielectric layer; A fourth heavily doped region is disposed in the body doping region; and A fourth conductive plug is coupled to the drain electrode and penetrates through the interlayer dielectric layer and the drain doping region into the lightly doped layer, wherein the fourth heavily doped region surrounds one end of the fourth conductive plug.

20. The semiconductor power device according to claim 11, wherein the breakdown voltage of the first diode string is substantially equal to the breakdown voltage of the second diode string.

21. The semiconductor power device according to claim 11, wherein the breakdown voltage of the first diode string is less than the breakdown voltage of the first oxide layer.

22. A method of manufacturing a semiconductor power device, comprising: Forming a lightly doped layer on a substrate; Forming a first opening, a second opening, and a third opening extending into the substrate on the lightly doped layer; Forming a first diode string on the second opening and the third opening; Forming a first spacer oxide layer on the first diode string and surrounding the first diode string; Forming a second diode string on the first spacer oxide layer; Forming a first trench structure in the first opening, wherein the first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure; Forming a source doping region in the lightly doped layer, wherein the source doping region is disposed between the first trench structure and the second opening; And Forming a source electrode coupled to the source doping region and forming a gate electrode coupled to the first polysilicon structure, wherein the first diode string and the second diode string are disposed in parallel between the source electrode and the gate electrode.

23. The manufacturing method according to claim 22, further comprising: Forming a second spacer oxide layer disposed on the second diode string, surrounding the second diode string, and adjacent to the first spacer oxide layer; and Forming an interlayer dielectric layer on the lightly doped layer, wherein the source electrode and the gate electrode are formed on the interlayer dielectric layer.

24. The manufacturing method according to claim 23, further comprising: Form a first conductive plug, a second conductive plug, and a third conductive plug. Wherein the first conductive plug penetrates through the interlayer dielectric layer and the first spacer oxide layer to the source doping region, and the second conductive plug and the third conductive plug penetrate through the second spacer oxide layer, the second diode string, the first spacer oxide layer to the first diode string.

25. The manufacturing method according to claim 24, wherein the first conductive plug couples the source electrode to the source doping region, the second conductive plug couples the source electrode to the first diode string and the second diode string, and the third conductive plug couples the gate electrode to the first diode string and the second diode string.

26. The manufacturing method according to claim 23, further comprising: Form a drain doping region in the lightly doped layer; Form a fourth conductive plug that penetrates through the interlayer dielectric layer and the first spacer oxide layer to the drain doping region; and Form a drain electrode, Wherein the fourth conductive plug couples the drain electrode to the drain doping region.

27. The manufacturing method according to claim 22, wherein the step of forming the first diode string on the second opening and the third opening comprises: Form a first semiconductor material on the second opening and the third opening; And Patterning the first semiconductor material; Performing ion implantation on the patterned first semiconductor material to form a plurality of first doping regions having a first conductivity type and a plurality of second doping regions having a second conductivity type, wherein the plurality of first doping regions and the plurality of second doping regions are alternately arranged, and a PN junction is formed at an interface adjacent to each first doping region and second doping region.

28. The manufacturing method according to claim 22, wherein the step of forming the second diode string on the first spacer oxide layer comprises: Form a second semiconductor material in the first spacer oxide layer; and Patterning the second semiconductor material; Performing ion implantation on the patterned second semiconductor material to form a plurality of third doping regions having the first conductivity type and a plurality of fourth doping regions having the second conductivity type, wherein the plurality of third doping regions and the plurality of fourth doping regions are alternately arranged, and a PN junction is formed at an interface adjacent to each third doping region and fourth doping region.

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