Multi-thread storage method, unit, chip and electronic equipment

Abstract

The invention provides a multi-thread storage unit, and relates to the field of integrated circuit design. The multi-thread storage unit comprises a first memory used for storing instructions corresponding to different threads in a linked list; the controller is connected with the first memory, and the controller is used for receiving a to-be-stored instruction and storing the to-be-stored instruction into a linked list of the first memory; and the linked list state table module is connected with the first memory and is used for responding to the storage of the to-be-stored instruction in the linked list of the first memory and generating a storage record of the to-be-stored instruction in the first memory. According to the multi-thread storage unit, the occupation of instruction temporary storage circuits of different threads on the chip area can be reduced.

Description

Multi-thread storage method, unit, chip and electronic device Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a multi-threaded storage method, unit, chip, and electronic device. Background Art

[0002] In some multi-threaded devices, such as shaders, when executing instructions from different threads, the instructions from different threads need to be output to the execution units corresponding to different threads respectively, so the instructions from different threads will be output in different queues respectively.

[0003] As shown in Figure 1, currently, multiple FIFOs (First In First Out, a first-in, first-out data buffer) are set up to temporarily store instructions from queues corresponding to different threads, that is, multiple instructions for each thread are combined into a queue, each of which can store multiple instructions from a queue, and then a scheduler is used to control the output of instructions in each FIFO. However, since the number of instructions required to be stored for each thread is different, and the number of instructions for the same thread is also different at different times, this method requires that each FIFO can store enough instructions. For example, each FIFO in Figure 1 needs to be able to store 64 instructions. This method causes each FIFO to occupy a large chip area. In addition, in actual use, the number of instructions output to each execution unit may be uneven. For example, the number of instructions stored in some FIFOs exceeds 30, or even exceeds 64, while the number of instructions stored in other FIFOs may be less than 10. This makes it impossible to fully utilize the storage space of each FIFO. If a larger FIFO is set, there will be a problem of causing a large waste of chip area.

[0004] Application Contents

[0005] In view of this, the present application aims to provide a multi-thread storage method, unit, chip and electronic device to reduce the chip area occupied by the circuit when temporarily storing instructions of different threads and reduce the waste of chip area.

[0006] In a first aspect, an embodiment of the present application provides a multi-threaded storage unit, comprising: a first memory, for storing instructions corresponding to different threads as a data field of a linked list; a controller, connected to the first memory, for receiving instructions to be stored and storing the instructions to be stored in the first memory; a linked list status table module, connected to the first memory, for generating a storage record of the instructions to be stored in the first memory in response to the storage of the instructions to be stored in the first memory, the storage record including the address of the instruction to be stored in the first memory, and the address being used to represent a pointer field of a node in the linked list.

[0007] In an embodiment of the present application, a first memory is used to temporarily store instructions of different threads, and a linked list status table module is set to generate a record of the instructions stored in the first memory. Therefore, if an instruction is regarded as a node of a linked list, the first memory is equivalent to the data field of the linked list node, and the linked list status table module is equivalent to the pointer field of the linked list node. Therefore, through the first memory and the linked list status table module, when storing and reading instructions corresponding to each thread, a linked list method can be used to enable the instructions to be correctly stored and read in the multi-thread storage unit. Compared with the method of setting up a memory that can store enough instructions for multiple threads respectively, the first memory stores the storage of instructions of different threads in a mixed manner, which can reduce the chip area occupied by the memory corresponding to each thread, or eliminate the need to set up multiple memories, thereby reducing the chip area occupied by the circuit for storing instructions of different threads. In addition, if the first memory and multiple smaller capacity memories are used in combination, when storing the same number of instructions, the total capacity of the memory is reduced, and the capacity utilization rate is improved, thereby reducing the waste of chip area caused by insufficient memory utilization.

[0008] In one embodiment, the multi-threaded storage unit also includes: multiple second memories, each of which is connected to the first memory and the linked list status table module, and the second memories are used to temporarily store and output instructions; wherein the number of second memories matches the maximum parallel number of the threads, and different second memories are used to temporarily store instructions corresponding to different threads; the controller is specifically used to determine whether the second memory of the thread corresponding to the instruction to be stored is idle; the controller is used to store the instruction to be stored in the first memory when the second memory is not idle; the controller is also used to store the instruction to be stored in the first memory when the second memory corresponding to the thread to be stored is idle; the controller is also used to output the instruction of the thread corresponding to the second memory in the first memory to the second memory when any second memory is idle.

[0009] In an embodiment of the present application, a second memory can be set up outside the first memory for each thread. On the one hand, when the second memory corresponding to the thread is idle, the instruction is directly output to the second memory, and the second memory directly outputs the instruction. Thus, there is no need to store the instruction through the first memory, and the linked list status table module does not need to generate storage records, which simplifies the control difficulty. On the other hand, when the second memory is not idle, the instruction can be stored in the first memory, which allows the capacity of the second memory to be set smaller, reducing the chip area occupied by the second memory. In addition, when the second memory is idle, if the instruction of the corresponding thread is stored in the first memory, the instruction is output to the second memory, so that the instructions of different threads can be output normally.

[0010] In one embodiment, the linked list status table module includes a status table submodule; the status table submodule includes a status vector register, and the status vector register is used to record the idle status of each storage row of the first memory; each storage row of the first memory is used to store the data fields of different nodes of the linked list; the controller is also used to determine the idle storage rows of the first memory based on the status vector register in response to the receipt of the instruction to be stored; the controller is also used to store the instruction to be stored in the idle storage row; the status vector register is also used to update the record of the idle storage row to a non-idle state in response to the storage of the instruction to be stored in the idle storage row.

[0011] In an embodiment of the present application, a state vector register is used to record the idle status of each storage row in the first memory. Therefore, when storing instructions, the idle storage row can be determined and the instruction can be stored in the idle storage row. Moreover, after the instruction is written to the idle storage row, it is updated to a non-idle state so that no instruction is stored before the instruction is output, thereby effectively reducing the possibility of instruction storage errors or losses and improving the accuracy of the multi-threaded storage unit in storing and outputting multi-threaded instructions.

[0012] In one embodiment, the linked list status table module also includes a pointer table submodule; the pointer table submodule includes multiple write address registers, different write address registers correspond to different threads, and the write pointer recorded in the write address register is the address of the last inserted node in the first memory; the status table submodule also includes a node address register, and the node address register is used to record the address of each node inserted into the linked list in the first memory; the controller is also used to determine the write address register of the thread corresponding to the instruction to be stored from the pointer table submodule, determine the address of the last inserted node in the node address register according to the write address register of the corresponding thread, and update the address of the free storage row in the first register at the address of the last inserted node in the node address register; and the controller is also used to update the pointer field of the last inserted node recorded in the write address register of the thread corresponding to the instruction to the address of the free storage row in the first register.

[0013] In an embodiment of the present application, a node address register is used to record the address of the instruction to be stored in the first memory, that is, the pointer field for storing the instruction. Then, the node address register can be used to query the instruction in the first memory and obtain the required instruction. For each thread, the write pointer of the corresponding write address register is set to the address of the last inserted node. Then, according to the write pointer of the write address register, the corresponding address is queried in the node address register, and the address of the node to be stored in the instruction is updated at the address, so that the node address register can store each instruction in the form of a linked list, and call the address in the form of a linked list, thereby realizing a function similar to a linked list structure together with the data field stored in the first memory. Then, the pointer field of the last inserted node recorded in the write address register is updated to the address of the free storage row in the first register, so that subsequent instructions can be converted into the form of a linked list for recording after being written. Through the write address register and the node address register, the multi-thread storage unit can accurately store the instructions of different threads in the form of a linked list.

[0014] In one embodiment, the multi-threaded storage unit also includes a scheduler, which is connected to the first memory and the linked list status table module, and the scheduler is used to schedule the output of instructions in the second memory; the pointer table submodule also includes multiple read address registers, and different read address registers correspond to different threads; the read pointer recorded in the read address register is the pointer field of the node output from the first memory; the controller is also used to determine whether the first memory stores the instruction of the thread corresponding to the second memory in response to the output of the instruction in the second memory; the controller is also used to obtain the read pointer from the read address register of the thread corresponding to the instruction when the first memory stores the instruction of the thread corresponding to the second memory, output the instruction of the thread corresponding to the second memory from the first memory to the second memory according to the read pointer, and update the read pointer to the address of the next node of the output instruction in the first memory.

[0015] In an embodiment of the present application, for a structure including multiple second memories, a scheduler can be used to control each second memory to output its stored instructions. After the instructions in the first memory are output to the second memory, they are recorded using a read address register. Thus, the output status of the instructions can be accurately recorded through the read address register, so that each instruction can be accurately output based on this record.

[0016] In one embodiment, the state vector register is further configured to update the memory row where the instruction of the thread corresponding to the second memory is located to a free memory row in response to outputting the instruction of the thread corresponding to the second memory from the first memory.

[0017] In the embodiment of the present application, after an instruction is output from the first memory, the record in the state vector register is updated to a free memory row, thereby allowing the first memory to input new instructions. This update allows the first memory to cyclically store different instructions, thereby eliminating the need to set the first memory capacity to be extremely large and reducing the possibility of the first memory occupying an excessively large area.

[0018] In one embodiment, the instruction to be stored is inserted into the preset position of the linked list in the form of a node of the linked list; the linked list status table module is specifically used to: obtain the first address of the instruction to be stored in the first memory and the second address of the node after the preset position; update the pointer field of the node before the preset position to the first address; and update the pointer field of the node corresponding to the preset position to the second address.

[0019] When instructions are stored in a linked list, when an instruction to be stored is inserted into the linked list, the pointer field of the node before the preset position of the insertion can be modified to the address corresponding to the instruction to be stored, and the pointer field of the node of the instruction to be stored can be modified to the second address of the node after the preset position, thereby realizing the insertion of the instruction to be stored. The linked list structure supports the insertion or removal of nodes at any position. The embodiment of the present application stores instructions in a linked list, which can enable instructions of different threads to be mixed and stored in the same first memory, and distinguish the instructions corresponding to different threads by the addresses recorded in the linked list status table module. Therefore, for multiple threads, there is no need to set up a large memory to store the instructions of each thread, so as to reduce the chip area occupied by the memory.

[0020] In a second aspect, an embodiment of the present application provides a chip, comprising: a multi-threaded storage unit as described in any one of the first aspects.

[0021] In a third aspect, an embodiment of the present application provides an electronic device comprising the chip as described in the second aspect.

[0022] In a fourth aspect, an embodiment of the present application provides a multi-threaded storage method, which is applied to a multi-threaded storage unit, and the multi-threaded storage method includes: receiving an instruction to be stored; storing the instruction to be stored in a linked list of a first memory, wherein the first memory is used to store instructions corresponding to different threads as a data field of the linked list; in response to the storage of the instruction to be stored in the first memory, generating a storage record of the instruction to be stored in the first memory, wherein the storage record includes the address of the instruction to be stored in the first memory, and the address is used to represent a pointer field of a node in the linked list.

[0023] Compared to the method of setting up a memory that can store enough instructions for multiple threads separately, in the embodiment provided by this application, the multi-thread storage unit can store the instructions of different threads in a form similar to a linked list. The first memory stores the storage of instructions of different threads in a mixed manner, which can reduce the chip area occupied by the memory corresponding to each thread, or eliminate the need to set up multiple memories, thereby reducing the chip area occupied by the circuits storing instructions for different threads. In addition, if the first memory is used in combination with multiple smaller-capacity memories, when storing the same number of instructions, the total capacity of the memory is reduced, and the capacity utilization rate is improved, thereby reducing the waste of chip area caused by underutilization of memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0025] FIG1 is a schematic diagram of an existing multi-threaded storage unit;

[0026] FIG2 is a schematic diagram of a multi-threaded storage unit provided in one embodiment of the present application;

[0027] FIG3 is a schematic diagram of the structure of a linked list provided in an embodiment of the present application;

[0028] FIG4 is a schematic diagram of an expansion of a multi-thread storage unit provided in one embodiment of the present application;

[0029] FIG5 is a flowchart of a multi-threaded storage method provided in an embodiment of the present application.

[0030] Icon: multi-threaded storage unit 100; first memory 110; controller 120; judgment circuit 121; linked list status table module 130; status table submodule 131; state vector register 1311; node address register 1312; pointer table submodule 132; write address register 1321; read address register 1322; second memory 140; scheduler 150. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0032] Please refer to FIG2 , which is a schematic diagram of a multi-thread storage unit provided in an embodiment of the present application. The multi-thread storage unit 100 includes: a first memory 110 , a controller 120 , and a linked list status table module 130 .

[0033] The first memory 110 is configured to store instructions corresponding to different threads in a linked list.

[0034] In this embodiment, the first memory 110 can be implemented as various types of memory, such as RAM (Random Access Memory), DRAM (Dynamic Random Access Memory), PSRAM (Pseudo static random access memory), etc., without limitation herein. Each storage row of the first memory 110 storing data must be able to store at least one instruction, that is, the width of the first memory 110 is greater than or equal to the size of the instruction to be stored. For example, if an instruction is 8 bits, the width of the first memory 110 is at least 8 bits. The depth of the first memory 110 can be configured according to actual conditions, for example, according to the number of threads, instruction generation and processing efficiency, etc. For example, in some embodiments, the depth of the first memory 110 can be 64, that is, the first memory 110 has 64 storage rows, each storage row can store 1 instruction, and the first memory 110 can store 64 instructions. The above is only an example and should not be a limitation of this application. For ease of understanding, in the embodiment of the present application, when each memory stores an instruction, each storage row of the memory stores one storage instruction.

[0035] In this embodiment, the first memory 110 is used to store instructions, wherein instructions of different threads can be stored in the first memory 110 .

[0036] A linked list is a data structure commonly used in computer programming. See Figure 3, which is a schematic diagram of the linked list structure provided in one embodiment of the present application. A linked list includes multiple nodes. The first node in the linked list is the head node, the last node in the linked list is the tail node, and the nodes between the head and tail nodes are intermediate nodes. Except for the head node, each node includes a data field and a pointer field. The data field is used to store data, and the pointer field of the node is used to store the address of the next node connected to the node. The data field of the head node is empty, or is considered to have no data field, and the pointer field of the tail node is empty.

[0037] In an embodiment of the present application, the first memory 110 stores instructions corresponding to different threads, wherein the first memory 110 is specifically used to store instructions corresponding to different threads, so that each instruction constitutes a data field of a linked list.

[0038] The controller 120 is connected to the first memory 110 , and is configured to receive instructions to be stored and store the instructions to be stored in a linked list of the first memory 110 .

[0039] In this embodiment, the controller 120 includes various functional circuits, such as a judgment circuit and a circuit for controlling level changes, and is not a specific device. The various functional circuits of the controller 120 can be connected to the first memory 110, the linked list status table module 130, and the like. This will be described later in conjunction with other structures of the multi-threaded storage unit 100, and the specific structure of the controller 120 will not be expanded upon here. In some embodiments, the controller 120 can also be implemented as a device capable of being configured with a program, and the program of the device is configured to implement the functions of the various functional circuits.

[0040] The linked list status table module 130 is connected to the first memory 110 and is used to generate a storage record of the to-be-stored instruction in the first memory 110 in response to the storage of the to-be-stored instruction in the linked list of the first memory 110 .

[0041] In this embodiment, the linked list status table module 130 can be implemented as various modules capable of recording data. For example, the linked list status table module 130 can be implemented as a combination of one or more registers, or the linked list status table module 130 can be implemented as various memories, etc.

[0042] In this embodiment, the storage record may include the address of the instruction to be stored in the first memory 110, the storage order of the instructions corresponding to each thread, etc., and may also include the usage of the first memory 110, such as whether each storage row stores instructions.

[0043] There are many ways to insert nodes into a linked list, such as head insertion, middle insertion, and tail insertion. Taking the tail insertion method as an example, the process includes: obtaining the address of the newly inserted node, writing the address of the newly inserted node into the pointer field of the original tail node, making the newly inserted node the new tail node. Similarly, the head insertion method is to write the data field of the newly inserted node into the original head node and update the address of the newly inserted node to the pointer field of the new head node. The middle insertion method is to insert the newly inserted node into the preset position, update the pointer field of the node before the preset node to the address of the newly inserted node, and update the pointer field of the newly inserted node to the address of the node after the preset position.

[0044] In an embodiment of the present application, after the instruction to be stored is stored in the first memory 110 , the linked list status table module 130 generates a storage record for the instruction to be stored.

[0045] In this embodiment, the storage record can record the instructions of different threads in the form of a linked list. That is, for the previously stored instruction, the address of the instruction in the first memory 110 and the address of the next instruction of the instruction can be recorded. For the latest stored instruction, the address of the instruction in the first memory 110 can be written to the previous instruction, so that the previous instruction records its own address and the address of the latest stored instruction at the same time. The location of the latest stored instruction storing the next instruction address is empty, waiting for the new instruction to be stored. If the latest stored instruction is the first instruction to be stored, the address of the instruction in the first memory 110 can be recorded at the free location. Therefore, the address recorded in the linked list status table module 130 can be regarded as the pointer field of the node in the linked list, and combined with the data field stored in the first memory 110, the function of the linked list is realized.

[0046] That is, in an embodiment of the present application, the instruction to be stored can be inserted into a preset position of the linked list in the form of a node of the linked list. The preset position is used to record the node corresponding to the instruction to be stored. The preset position can be before the head node of the linked list, or after the tail node, or any middle position of the linked list.

[0047] Accordingly, in some embodiments of the present application, the update of the storage record may be: obtaining the first address of the instruction to be stored in the first memory 110 and the second address of the node after the preset position; updating the pointer field of the node before the preset position to the first address; and updating the pointer field of the node corresponding to the preset position to the second address.

[0048] The position at which a node is inserted into the linked list is predefined and determined by the selected insertion method, such as head insertion, tail insertion, or middle insertion. For details, please refer to the previous article and will not be elaborated on here. If head insertion is used, the pointer field of the node preceding the preset position may not be updated with each insertion instruction. Similarly, if tail insertion is used, the pointer field of the node corresponding to the preset position may not be updated with each insertion instruction.

[0049] In this embodiment, the storage of instructions can be analogized to a node in a linked list. The data field of the node is stored in the first memory 110, and the pointer field is stored in the linked list status table module 130. The pointer field is the address of the instruction in the first memory 110, i.e., the first address. When a node is inserted into a preset position, the pointer fields of the nodes adjacent to the node need to be modified.

[0050] For example, the content of each row of the storage record is the current node pointer field and the next node pointer field. When using the tail insertion method, the instruction can be stored in the first memory 110, and the first address is obtained. The next node pointer field of the original tail node in the linked list status table module 130 is updated to the first address, and a new row is added to record that the address of the instruction to be stored in the first storage node is the current node pointer field of the new tail node.

[0051] Since the tail insertion method inserts a new node after the tail node, which does not have a next node, the next node pointer field of the new tail node may not be updated. For another example, when performing an intermediate insertion, the process may be similar to the tail insertion method, except that the address of the node after the original preset position needs to be written into the next node pointer field of the new tail node.

[0052] The principle of using the head insertion method is similar. For example, when using the head insertion method, the instruction will be stored in the data field of the original head node. Correspondingly, in the storage record of the linked list status table module 130, the instruction will be written at the address corresponding to the pointer field of the original head node, and a new node will be added, and its pointer field will record the address of the free storage row of the new first memory 110, so that the newly added node becomes the new head node.

[0053] The above is only an example. The specific process can be reasonably selected and adjusted according to actual needs and will not be elaborated here.

[0054] In addition, there can be multiple types of linked lists. The multi-threaded storage unit 100 of the present application can store instructions for different threads based on a circular linked list or a bidirectional linked list. Compared to ordinary unidirectional linked lists, bidirectional linked lists and circular linked lists can improve the utilization of the first memory 110 and the linked list status table module 130, thereby reducing the requirements for the first memory 110 and the linked list status table module 130, and further reducing the chip area occupied by the multi-threaded storage unit 100.

[0055] Correspondingly, when the multi-threaded storage unit 100 outputs data, the controller 120 can be connected to the linked list status table module 130. The controller 120 obtains the pointer field of the instruction to be output from the linked list status table module 130 and retrieves the instruction from the first memory 110 according to the address recorded in the pointer field. After the instruction is output, the pointer field of the node connected to the instruction in the linked list status table is correspondingly modified. The output process is the opposite of the write process. For details, please refer to the existing process of removing nodes from a linked list and will not be elaborated here.

[0056] In the multi-thread storage unit 100 provided in the embodiment of the present application, the function of the linked list can be realized through the first memory 110 and the linked list status table module 130. When storing instructions, there is no need to classify and store the instructions of each thread, that is, they can be stored arbitrarily in the first memory 110, and the address recorded by the linked list status table module 130 is used to record the order of the linked list nodes. Therefore, there is no need to set up a FIFO for each thread to store the corresponding instructions, or a smaller FIFO can be set to store the instructions of each thread. For example, each FIFO originally needs to be able to store 64 instructions, that is, 64 storage rows are required. Then, through the first memory 110 and the linked list status table module 130, each FIFO can only store 3 instructions. The chip area occupied by the first memory 110 and the linked list status table module 130 is much smaller than the chip area occupied by multiple large-capacity FIFOs. When no FIFO is set or only multiple small-capacity FIFOs are set, the chip area occupied can be effectively reduced.

[0057] In addition, in actual use, the use of FIFOs may be uneven. For example, among multiple FIFOs that can originally store 64 instructions, one FIFO may store 20 instructions, one FIFO may store 5 instructions, and one FIFO may store 2 instructions. The utilization rate of the FIFO that stores 5 or 2 instructions is obviously low, and the waste is large. In actual use, different FIFOs may store more instructions, and the size of each FIFO cannot be set according to the thread. In the multi-threaded storage unit 100 provided in the present application, a smaller capacity FIFO is set, for example, a FIFO that can store 3 instructions is set. For each FIFO, the utilization rate can be improved. For example, the utilization rate of the FIFO that can originally store 64 instructions is 2 / 64 or 3 / 64. After replacing it with a FIFO with a capacity of 3, the utilization rate becomes 2 / 3 or 1, which effectively improves the utilization rate and reduces the waste of chip area. When the FIFO cannot store an instruction, the instruction is stored in the first memory 110 to avoid the loss of the instruction.

[0058] Accordingly, in some embodiments of the present application, the multi-threaded storage unit 100 may further include: multiple second memories 140 .

[0059] Please refer to Figure 4, which is an expanded schematic diagram of a multi-threaded storage unit 100 provided in one embodiment of the present application. In this embodiment, multiple second memories 140 may be provided, and second memories 140 may be FIFOs or other memories. The number of second memories 140 matches the maximum number of parallel threads, and different second memories 140 are used to temporarily store instructions corresponding to different threads. That is, each second memory 140 corresponds to a thread and stores the instructions of that thread.

[0060] In this embodiment, the controller 120 may further include a judgment circuit 121. The judgment circuit 121 may include a multiplexer, wherein the output end of the judgment circuit 121 is connected to the second memory 140, and different input ends are respectively connected to the output end of the instruction to be stored and the first memory 110, wherein the output end of the instruction to be stored is also connected to the first memory 110. The judgment circuit 121 is used to control the gating between the output end and the different input ends based on whether the second memory is idle. The judgment circuit 121 is specifically used to determine whether the second memory 140 corresponding to the thread of the instruction to be stored is idle. If the second memory 140 is idle, the output end of the instruction to be stored is controlled to be connected to the second memory 140, thereby controlling the instruction to be stored to be directly stored in the second memory 140. Conversely, if the second memory 140 is not idle, the judgment circuit 121 controls the connection between the first memory 110 and the second memory 140, and disconnects the output terminal of the instruction to be stored from the second memory 140. Thus, when there is no idle space in the second memory 140, the instruction to be stored is first stored in the first memory 110, and then the instruction to be stored is controlled to be output to the second memory 140 through the first memory 110. In addition, the controller 120 may further include a device capable of configuring a program, and the program of the device is configured to implement the functions of the aforementioned judgment circuit.

[0061] In this embodiment, the controller 120 may further include a monitoring circuit (not shown) connected to the output end of each second memory 140. When any second memory 140 is detected to output an instruction, that is, when any second memory 140 is idle, the controller 120 outputs the instruction of the thread corresponding to the second memory 140 in the first memory 110 to the second memory 140. In addition, the controller 120 may further include a device capable of configuring a program, and the program of the device is configured to implement the functions of the aforementioned monitoring circuit.

[0062] In the above embodiment, the first memory 110 and the second memory 140 are used in conjunction. When the second memory 140 is idle, the second memory 140 stores instructions, eliminating the need to store instructions in the first memory 110. This simplifies the instruction output process and reduces the time and power consumption required for instruction temporary storage and output. Furthermore, when the second memory 140 is not idle, the first memory 110 stores instructions, eliminating the need for a large capacity for each second memory 140, thereby preventing the second memory 140 from occupying an excessive amount of chip area.

[0063] Please continue to refer to FIG. 4 . In one embodiment of the present application, the linked list status table module 130 may include a pointer table submodule 132 and a status table submodule 131 .

[0064] The pointer table submodule 132 is primarily used to record the address of each thread's previous insertion node and the address of the previous instruction read. The addresses are the addresses in the instruction first memory 110. In the pointer table submodule 132, each address is recorded as a pointer, i.e., a pointer field corresponding to each instruction. Thus, through the pointer field recorded in the pointer table submodule 132 and the data field recorded in the first memory 110, instructions can be stored and output in a linked list format.

[0065] The status table submodule 131 is mainly used to record the usage of the first memory 110 and the address of each instruction in the first memory 110, for example, to record whether each storage row in the first memory 110 is used, and the address of each instruction in the first memory 110 is recorded in the form of a combination of the pointer field of the corresponding node and the pointer field of the next node.

[0066] In one embodiment, the state table submodule 131 may include a state vector register 1311. The state vector register 1311 is used to record the idle state of each storage row of the first memory 110.

[0067] In this embodiment, each storage row of the first memory 110 is used to store data fields of different nodes of the linked list, and the state vector register 1311 can be used for recording. For example, if the first memory 110 has 64 rows, the state vector register 1311 can have 64 data bits, each data bit corresponding to a storage row of the first memory 110. If the memory does not store an instruction, the corresponding data bit is 0. Conversely, if the storage row stores an instruction, the corresponding data bit is 1.

[0068] Accordingly, the controller 120 may determine the free storage row of the first memory 110 based on the state vector register 1311 in response to receiving the instruction to be stored, so that when the control instruction is stored in the first memory 110 , the instruction to be stored may be stored in the free storage row.

[0069] Furthermore, the state vector register 1311 may also update the record of the idle storage row to a non-idle state in response to the storage of the instruction to be stored in the idle storage row, for example, changing the data bit corresponding to the storage row from 0 to 1.

[0070] Conversely, the state vector register 1311 may also update the storage row of the instruction corresponding to the thread of the second memory 140 to a free storage row in response to the instruction corresponding to the thread of the second memory 140 being output from the first memory 110. For example, the data bit corresponding to the storage row is changed from 1 to 0.

[0071] Through the state vector register 1311, the usage of the first memory 110 can be accurately known, so that the instructions to be stored can be stored in the free storage line, reducing the occurrence of abnormal situations such as instruction loss, thereby improving the accuracy of multi-threaded instruction storage and output.

[0072] Accordingly, the state table submodule 131 may further include a node address register 1312. The node address register 1312 is used to record the address of each node inserted into the linked list in the first memory 110.

[0073] In this embodiment, the node address register 1312 can store the address of each node as a node pointer field and a next node pointer field. This facilitates searching for node addresses. For example, based on the address of a node, the pointer field of the next node can be queried. Furthermore, by having the pointer field of each node sequentially point to the next node, a structure similar to a linked list is formed, enabling instruction storage and output in the form of a linked list. Each node corresponds to one instruction, and a node includes a data field and a pointer field. The data field refers to the instruction data itself, and the pointer field refers to the instruction address in the first memory 110. This will not be further described below.

[0074] In one embodiment, the pointer table submodule 132 includes multiple write address registers 1321 and multiple read address registers 1322, different write address registers 1321 correspond to different threads, and different read address registers 1322 correspond to different threads. The write pointer recorded in the write address register 1321 is the address of the last inserted node in the first memory 110, and the read pointer recorded in the write address register 1321 is the address of the last read node in the first memory 110.

[0075] In this embodiment, one thread corresponds to one write address register and one read address register 1322. Different write address registers 1321 and read address registers 1322 are used to record the addresses of instructions of different threads.

[0076] In this embodiment, the controller 120 is also used to determine the write address register 1321 of the thread corresponding to the instruction to be stored from the pointer table sub-module 132, determine the address of the last inserted node in the node address register 1312 according to the write address register 1321 of the corresponding thread, and update the address of the free storage row in the first register at the address of the last inserted node in the node address register 1312.

[0077] After the instruction is written into the first memory 110, the corresponding record needs to be updated so that the instructions corresponding to each thread can be distinguished and accurately stored and output. In addition, the instructions need to be stored in a manner similar to a linked list, and the pointer field of the node corresponding to the previous instruction needs to be updated.

[0078] Therefore, after the write instruction, the controller 120 can determine the thread corresponding to the instruction, and then determine the corresponding write address register 1321 based on the thread. What the write address register 1321 records is the address of the last inserted node, that is, the pointer field of the last inserted node. Taking the tail insertion method as an example, what the write address register 1321 records is the address of the tail node. If a new node is inserted, the pointer field of the original tail node is updated to the address of the newly inserted node. The pointer field (i.e., write pointer) of the original tail node can be determined by the write address register 1321, and then the original tail node can be found from the node address register 1312 based on the write pointer. The pointer field of the original tail node is updated to the address of the newly inserted node, and a row is re-established to record the address of the newly inserted node. Thus, the newly inserted node can be made into a new tail node.

[0079] At the same time, the write pointer of the original tail node recorded in write address register 1321 is updated to record the address of the newly inserted node. That is, the pointer field of the previously inserted node recorded in write address register 1321 of the thread corresponding to the instruction is updated to the address of the free storage row of the newly inserted node recorded in the first register. Thus, the next time a node is inserted, the node can be found based on the write pointer in write address register 1321.

[0080] The above description is about the instruction writing process. Accordingly, the multi-threaded memory also supports the reading of data. In some embodiments of the present application, a scheduler 150 may be provided. The scheduler 150 is connected to each second memory 140 to schedule the output of instructions in each second memory 140.

[0081] In an embodiment of the present application, the scheduler 150 may be connected to the controller 120, the first memory 110, and the linked list status table module 130. After any instruction in the second memory 140 is output, the scheduler 150 sends a signal to the controller 120 to notify the controller 120, the first memory 110, and the linked list status table module 130 so that the controller 120, the first memory 110, and the linked list status table module 130 cooperate to output the instruction. If the multi-threaded storage unit 100 does not include the scheduler 150 and the second storage unit, a monitoring circuit may be included in the controller 120 to control the output of the instruction in the first memory 110 based on the monitoring signal of the monitoring circuit.

[0082] In this embodiment, the process of reading instructions from the first memory 110 may include: the controller 120, in response to the output of the instruction from the second memory 140, determining whether the first memory 110 stores instructions for the thread corresponding to the second memory 140; if not, determining that the thread has no new instructions and waiting for new instructions. If the first memory 110 stores instructions for the thread corresponding to the second memory 140, the controller 120 may also be configured to obtain a read pointer from the read address register 1322 of the thread corresponding to the instruction, output the instructions for the thread corresponding to the second memory 140 from the first memory 110 to the second memory 140 based on the read pointer, and update the read pointer to the address of the next node of the output instruction in the first memory 110.

[0083] Similar to the write process, the address of the instruction is determined from the node address register 1312 based on the read pointer in the read address register 1322. The corresponding instruction in the first memory 110 is then controlled to be output based on the address. After the instruction is output, the record in the node address register 1312 is modified, the pointer field corresponding to the instruction is deleted, and the pointer field originally pointing to the node is modified to the next pointer field pointed to by the node. At the same time, the read pointer recorded in the read address register 1322 is changed to the pointer field of the next node to be read. In addition, as mentioned in the previous embodiment, the state vector register 1311 is updated.

[0084] Thus, through the read address register 1322 and the write address register 1321, the output and write status of instructions are accurately recorded in a manner similar to a linked list, thereby enabling the multi-threaded storage unit 100 to control the storage and output of instructions based on the principle of a linked list structure. Unlike conventional array-based methods of arranging associated items, which often require data access to be converted between different arrangement orders, linked lists do not require linked lists and allow the insertion and removal of nodes at any position on the table. This can fully utilize computer memory space and eliminate the need to independently allocate large amounts of storage capacity for different threads to store instructions. This reduces the chip area occupied by the memory storing instructions, and also reduces the chip area occupied when the memory is not fully utilized.

[0085] It should be distinguished that the present application implements the principle of the linked list in a hardware manner, using the first memory 110 to store the data domain and the linked list status table module 130 to store the pointer domain, so that the storage of instructions can be temporarily stored and output in a manner similar to a linked list, rather than storing the instructions as a linked list.

[0086] Based on the same inventive concept, an embodiment of the present application further provides a multi-threaded storage method, which is applied to the multi-threaded storage unit provided in any of the above embodiments. Please refer to Figure 5, which is a flow chart of the multi-threaded storage method provided in one embodiment of the present application. The multi-threaded storage method includes:

[0087] S110, receiving a deposit instruction.

[0088] In this embodiment, the instruction to be stored may be an instruction corresponding to any thread.

[0089] S120: Store the instruction to be stored into a linked list in the first memory.

[0090] In this embodiment, the first memory 110 is used to store instructions corresponding to different threads as a data field of a linked list;

[0091] S130 , in response to the storing of the instruction to be stored in the first memory, generating a storage record of the instruction to be stored in the first memory.

[0092] In this embodiment, the storage record includes the address of the instruction to be stored in the first memory 110, and the address is used to represent the pointer field of the node in the linked list.

[0093] In one embodiment, the multi-thread storage unit includes multiple second memories 140, each of which is connected to the first memory and the linked list status table module 130. The second memories 140 are used to temporarily store and output instructions; wherein the number of second memories 140 matches the maximum number of parallel threads, and different second memories 140 are used to temporarily store instructions corresponding to different threads. The method further includes: determining whether the second memory 140 corresponding to the thread to be stored is idle; if the second memory 140 is not idle, storing the instruction to be stored in the first memory 110; if the second memory 140 corresponding to the thread to be stored is idle, storing the instruction to be stored in the second memory 140; if any second memory 140 is idle, outputting the instruction of the thread corresponding to the second memory 140 in the first memory 110 to the second memory 140.

[0094] In one embodiment, the linked list status table module 130 includes a status table submodule 131; the status table submodule 131 includes a state vector register 1311, and the state vector register 1311 is used to record the idle status of each storage row of the first memory 110; each storage row of the first memory 110 is used to store the data fields of different nodes of the linked list, and S110 includes: in response to receiving the instruction to be stored, determining the idle storage row of the first memory 110 based on the state vector register 1311; storing the instruction to be stored in the idle storage row; in response to the storage of the instruction to be stored in the idle storage row, updating the record of the idle storage row to a non-idle state.

[0095] In one embodiment, the linked list status table module 130 also includes a pointer table submodule 132; the pointer table submodule 132 includes multiple write address registers 1321, different write address registers 1321 correspond to different threads, and the write pointer recorded in the write address register 1321 is the address of the last inserted node in the first memory 110; the status table submodule 131 also includes a node address register 1312, and the node address register 1312 is used to record the address of each node inserted into the linked list in the first memory 110; S130 includes: determining the write address register 1321 of the thread corresponding to the instruction to be stored from the pointer table submodule 132, determining the address of the last inserted node in the node address register 1312 according to the write address register 1321 of the corresponding thread, and updating the address of the free storage row in the first register at the address of the last inserted node in the node address register 1312; updating the pointer field of the last inserted node recorded in the write address register 1321 of the thread corresponding to the instruction to the address of the free storage row in the first register.

[0096] In one embodiment, the multi-thread storage unit further includes a scheduler 150, which is connected to the first memory 110 and the linked list status table module 130, and the scheduler 150 is used to schedule the output of instructions in the second memory 140; the pointer table submodule 132 further includes a plurality of read address registers 1322, and different read address registers 1322 correspond to different threads; the read pointer recorded in the read address register 1322 is the pointer field of the next node output from the first memory 110; after S130, the method further includes: in response to the output of the instruction in the second memory 140, determining whether the first memory 110 stores the instruction of the thread corresponding to the second memory 140; if the first memory 110 stores the instruction of the thread corresponding to the second memory 140, obtaining the read pointer from the read address register 1322 of the thread corresponding to the instruction, outputting the instruction of the thread corresponding to the second memory 140 from the first memory 110 to the second memory 140 according to the read pointer, and updating the read pointer to the address of the next node of the output instruction in the first memory 110.

[0097] In one embodiment, the method further includes: in response to the output of the instructions of the thread corresponding to the second memory 140 from the first memory 110 , updating the storage row of the instructions of the thread corresponding to the second memory 140 to a free storage row.

[0098] In one embodiment, S130 includes: obtaining the first address of the node in the first memory 110 and the second address of the node after the preset position; updating the pointer field of the node before the preset position to the first address; and updating the pointer field of the preset node to the second address.

[0099] The functions implemented by the multi-threaded storage method and the multi-threaded storage unit are similar and will not be described in detail here.

[0100] Based on the same inventive concept, an embodiment of the present application further provides a chip, which includes the multi-threaded storage unit provided by any of the aforementioned embodiments.

[0101] In this embodiment, the chip may be a chip capable of performing multi-threaded work, for example, the chip may be a chip including a shader.

[0102] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which may include the chip provided by the aforementioned embodiment. The electronic device may be a device including a multi-threaded working device.

[0103] The technical features of the above embodiments can be freely combined without conflict, and the embodiments obtained by the combination are included in the protection scope of this application.

[0104] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0105] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A multi-threaded storage unit, characterized in that, it includes: A first memory for storing the instructions corresponding to different threads as the data fields of a linked list; A controller connected to the first memory, the controller is used to receive the instruction to be stored and store the instruction to be stored in the first memory; A linked list status table module, connected to the first memory, for generating a storage record of the instruction to be stored in the first memory in response to the storage of the instruction to be stored in the first memory, the storage record includes the address of the instruction to be stored in the first memory, and the address is used to represent the pointer field of the node in the linked list.

2. The multi-threaded storage unit according to claim 1, characterized in that, it further includes: A plurality of second memories, each of the second memories is connected to the first memory and to the linked list status table module, and the second memory is used to temporarily store and output instructions; wherein, the number of the second memories matches the maximum parallel number of the threads, and different second memories are used to temporarily store instructions corresponding to different threads; The controller is specifically used to judge whether the second memory corresponding to the thread of the instruction to be stored is idle; The controller is used to store the instruction to be stored in the first memory when the second memory is not idle; The controller is further used to store the instruction to be stored in the second memory when the second memory corresponding to the thread of the instruction to be stored is idle; The controller is further used to output the instruction of the thread corresponding to the second memory in the first memory to the second memory when any second memory is idle.

3. The multi-threaded storage unit according to claim 2, characterized in that, The linked list status table module includes a status table sub-module; the status table sub-module includes a status vector register, and the status vector register is used to record the idle status of each storage row of the first memory; each storage row of the first memory is respectively used to store the data fields of different nodes of the linked list; The controller is further used to determine the idle storage row of the first memory based on the status vector register in response to the reception of the instruction to be stored; the controller is further used to store the instruction to be stored in the idle storage row; The status vector register is further used to update the record of the idle storage row to a non-idle state in response to the storage of the instruction to be stored in the idle storage row.

4. The multi-threaded storage unit according to claim 3, characterized in that, The linked list status table module further includes a pointer table sub-module; the pointer table sub-module includes a plurality of write address registers, different write address registers correspond to different threads, and the write pointer recorded by the write address register is the address of the previous inserted node in the first memory; The status table sub-module further includes a node address register, and the node address register is used to record the addresses of the nodes inserted into the linked list in the first memory. The controller is further configured to determine, from the pointer table sub-module, the write address register corresponding to the thread of the instruction to be stored, determine, according to the write address register of the corresponding thread, the address of the previous inserted node in the node address register, and update, at the address of the previous inserted node in the node address register, the address of the free storage row in the first register; In addition, the controller is further configured to update the pointer field of the previous inserted node recorded in the write address register of the instruction corresponding thread to the address of the free storage row in the first register.

5. The multi-threaded storage unit according to claim 3, wherein, the multi-threaded storage unit further includes a scheduler, connected to the first memory and the linked list status table module, and the scheduler is configured to schedule the output of instructions in the second memory; the pointer table sub-module further includes a plurality of read address registers, and different read address registers correspond to different threads; the read pointer recorded by the read address register is the pointer field of the next node output from the first memory; the controller is further configured to, in response to the output of an instruction in the second memory, determine whether the first memory stores an instruction corresponding to the thread of the second memory; the controller is further configured to, when the first memory stores an instruction corresponding to the thread of the second memory, obtain a read pointer from the read address register of the instruction corresponding thread, output, according to the read pointer, the instruction corresponding to the thread of the second memory from the first memory to the second memory, and update the read pointer to the address of the next node of the output instruction in the first memory.

6. The multi-threaded storage unit according to claim 3, wherein, the status vector register is further configured to, in response to the output of an instruction corresponding to the thread of the second memory from the first memory, update the storage row of the instruction corresponding to the thread of the second memory to a free storage row.

7. The multi-threaded storage unit according to any one of claims 1-6, wherein, the instruction to be stored is inserted into a preset position of the linked list in the form of a node of the linked list; the linked list status table module is specifically configured to: obtain a first address of the node corresponding to the instruction to be stored in the first memory and a second address of the node after the preset position; update the pointer field of the node before the preset position to the first address; update the pointer field of the node corresponding to the preset position to the second address.

8. A chip, wherein, it includes: the multi-threaded storage unit according to any one of claims 1-7.

9. An electronic device, wherein, it includes: the chip according to claim 8.

10. A multi-threaded storage method, wherein, applied to the multi-threaded storage unit according to any one of claims 1-7, the multi-threaded storage method includes: receiving an instruction to be stored; storing the instruction to be stored into a linked list in a first memory, and the first memory is configured to store instructions corresponding to different threads as data fields of the linked list; In response to the storage of the instruction to be stored in the first memory, generate a storage record of the instruction to be stored in the first memory, where the storage record includes the address of the instruction to be stored in the first memory, and the address is used to represent the pointer field of a node in the linked list.

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