Product sum arithmetic unit

Abstract

Provided is a product sum calculator which consumes little energy and has high calculation accuracy. A product sum arithmetic unit (1) is configured from: a resistive digital-to-analog conversion unit (11) that is provided with a plurality of RDACs and that converts digital values of each element of an input vector into analog voltages and outputs the analog voltages; a capacitive digital-to-analog conversion unit (12), which is provided with a plurality of CDACs, to which the analog voltage output from the resistive digital-to-analog conversion unit (11) is inputted, and which sets a capacitance ratio corresponding to the digital value of each element of the matrix between input and output terminals and between the output terminal and ground; a successive approximation-type analog-to-digital conversion unit (13) provided with a plurality of successive approximation-type ADCs for converting the voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion unit (12) into a digital value and outputting the digital value; and a consumption current control unit (14) for controlling the consumption current of the resistive digital-to-analog conversion unit (11), the output from the successive comparison analog-to-digital conversion unit (13) being an output vector.

Description

Technical Field

[0001] The present invention relates to a product-sum calculator. More specifically, it relates to a product-sum calculator using a Digital to Analog Converter (DAC) and an Analog to Digital Converter (ADC). Background Art

[0002] Digital operations are based on product-sum operations. In addition, neuron operations are performed in AI processors that have been highly competitive in recent years (for example, refer to Non-Patent Document 1). Figure 8 It is a conceptual diagram of neuron operations in an AI processor. In addition, a large number of layers are required in neuron operations, but only the basic input layer, hidden layer, and output layer are shown in Figure 8 .

[0003] As shown in Figure 8 , product-sum operations are performed between layers in neuron operations. As an example, the operation between the input layer and the hidden layer is shown. If the vector of the input layer is set as X and the coupling coefficient matrix is set as W (0) , the vector Y of the hidden layer is represented by the following Equation 1.

[0004] [Equation 1]

[0005] Y = W (0) ·X

[0006] It is known that when focusing on one element y j of the output layer in the above Equation 1, the product-sum operation process is represented by the following Equation 2.

[0007] [Equation 2]

[0008]

[0009] In a neuron processor, when the number of nodes in each layer is N, N 2 product-sum operations are required in each layer. For example, in image recognition with 100×100 pixels, N = 10 4 , N 2 = 10 8 , and 100 million product-sum operations are required for each layer. Therefore, it has become an urgent problem to increase the operation speed of the neuron processor while reducing the energy consumption of the operation of the neuron processor.

[0010] Figure 9FIG. is a diagram showing the structure of a conventional product-sum calculator using a digital circuit. As Figure 9 shown, in a typical conventional digital product-sum calculator, the input X is input to each flip-flop (F / F) via a bus. Further, in Figure 9 the product-sum calculator shown, multipliers (MUL) are arranged two-dimensionally, and each element of the input X and each element of the input W are input to each multiplier, and the multiplication of each element of the input X and each element of the input W is performed in the multiplier. Then, the multiplication outputs are sequentially input to an adder (ADD) via a bus, and cumulative addition is performed.

[0011] On the other hand, in the above-described conventional digital product-sum calculator, there are problems with the operation speed and power consumption of the multiplier, and the operation speed and power consumption of the cumulative addition. In particular, since the outputs of the multipliers are sequentially sent to the cumulative adder via a bus, there are problems such as a slow operation speed and high power consumption of the cumulative adder.

[0012] In response to this, the present inventor has proposed a technique for reducing power consumption and increasing the operation speed by performing operations in an analog circuit (see Patent Document 1). Figure 10 FIG. is a block diagram showing the structure of the product-sum calculator described in Patent Document 1. In Figure 10 the product-sum calculator 100 shown, there are provided: a voltage output digital-to-analog conversion unit 101 having a plurality of DACs; a capacitive digital-to-analog conversion unit 102 having a plurality of capacitive digital-to-analog converters (CDACs); and an analog-to-digital conversion unit 103 having a plurality of ADCs.

[0013] In this product-sum calculator 100, for example, two input digital value strings are used as inputs, one input is converted into a voltage string using a resistive digital-to-analog converter (RDAC), and the other input is input to a capacitive digital-to-analog converter (CDAC). Then, multiplication is performed by the CDAC with the voltage as the analog input, simultaneous addition is performed by commonly connecting the outputs of the plurality of CDACs, and a digital output value is obtained by performing analog-to-digital conversion of the voltage at this node in the ADC.

[0014] Prior Art Documents

[0015] Patent Documents

[0016] Patent Document 1: International Publication No. 2021 / 171880

[0017] Non-Patent Documents

[0018] Non-Patent Document 1: Kodai Ueyoshi, et al., "FPGA implementation of a scalable and highly parallel architecture for restricted Boltzmann machines," Circuits and Systems, 2016, vol. 7, no. 9, p. 2132-2141 Summary of the Invention

[0019] Problems to be Solved by the Invention

[0020] Compared with the product-sum calculator using a digital arithmetic unit, the product-sum calculator described in Patent Document 1 can operate with low energy and high speed. However, a constant current steadily flows through the RDAC, so it does not always operate with the minimum power consumption. In addition, in the conventional product-sum calculator using this analog circuit, there are also problems such as an increase in power consumption due to analog-to-digital conversion above the required resolution in the ADC, and a voltage attenuation generated at the output terminal due to the parasitic capacitance at the output terminal of the CDAC, resulting in an ADC gain error and thus deteriorating the operation accuracy.

[0021] Therefore, an object of the present invention is to provide a product-sum calculator with low power consumption and high operation accuracy.

[0022] Solutions to the Problems

[0023] As a result of investigations by the present inventors to solve the above problems, the following insights were obtained. First, it was found that by providing a current consumption control unit for controlling the current consumption in the RDAC to control the generation period of the output voltage, and providing a conversion number control unit for controlling the number of successive comparisons in the successive approximation type ADC and setting it to the number of successive comparisons corresponding to the required resolution, the power consumption can be reduced. In addition, it was found that regarding the operation accuracy, by providing a reference voltage control unit in the ADC to control the reference voltage or providing a coefficient control unit and a multiplier to multiply the conversion value of the ADC by a coefficient, the generation of gain error can be suppressed to improve the operation accuracy. Then, the present inventors completed the present invention based on these insights.

[0024] That is, the product-sum calculator according to the present invention includes: a resistive digital-to-analog conversion unit including a plurality of resistive digital-to-analog converters configured to convert digital values of respective elements of an input vector into analog voltages and output them; a capacitive digital-to-analog conversion unit including a plurality of capacitive digital-to-analog converters, the capacitive digital-to-analog conversion unit being input with the analog voltages output from the resistive digital-to-analog conversion unit and setting a capacitance ratio corresponding to the digital value of each element of the matrix between the input / output terminals and between the output terminal and the ground; a successive approximation analog-to-digital conversion unit including a plurality of successive approximation analog-to-digital converters configured to convert the voltage of a node commonly connected to the output terminals of the capacitive digital-to-analog conversion unit into a digital value and output it; and a current consumption control unit configured to control the current consumption of the resistive digital-to-analog conversion unit, wherein the output from the successive approximation analog-to-digital conversion unit is set as an output vector.

[0025] The current consumption control unit may also control, for example, the generation period of the analog voltage output from the resistive digital-to-analog converter.

[0026] The product-sum calculator of the present invention may further include a conversion number control unit configured to control the number of successive approximations in the successive approximation analog-to-digital conversion unit.

[0027] The product-sum calculator of the present invention may further include a reference voltage control unit configured to control the reference voltage of the successive approximation analog-to-digital conversion unit. In this case, a capacitor for sampling an input signal as the reference voltage control unit may be connected to a connection portion between the capacitive digital-to-analog converter and the input terminal of the comparator in the successive approximation analog-to-digital conversion unit, and the capacitance value of the capacitor for sampling the input signal may be controllable.

[0028] The product-sum calculator of the present invention may further include: an adder configured to add an offset value to the output from the successive approximation analog-to-digital conversion unit; and an offset control unit configured to control the offset value.

[0029] The product-sum calculator of the present invention may further include: a multiplier configured to multiply the output from the successive approximation analog-to-digital conversion unit by a coefficient; and a coefficient control unit configured to control the coefficient.

[0030] Advantages of the Invention

[0031] According to the present invention, compared with a conventional product-sum calculator using an analog circuit, power consumption can be reduced and calculation accuracy can be improved, so that a product-sum calculator capable of operating with lower energy and performing high-precision calculations can be realized. Description of the Drawings

[0032] Figure 1 This is a diagram showing the structure of the product-sum calculator according to the first embodiment of the present invention.

[0033] Figure 2 A to C of [] are waveform diagrams showing methods for reducing the consumption current of each RDAC of the resistive digital-to-analog conversion unit 11.

[0034] Figure 3 A of [] is a circuit diagram showing the structure of the successive approximation type ADC, Figure 3 B of [] is a conceptual diagram showing a method for reducing the power consumption of the successive approximation type ADC.

[0035] Figure 4 This is a circuit diagram showing a structural example of the reference voltage control unit 16.

[0036] Figure 5 This shows the ability to control Figure 4 This is a circuit diagram showing a structural example of a structure capable of controlling the capacitance value of the capacitor βC shown.

[0037] Figure 6 This is a diagram showing the structure of the product-sum calculator according to the second embodiment of the present invention.

[0038] Figure 7 This is a characteristic diagram showing the deterioration of the operation accuracy and its compensation.

[0039] Figure 8 This is a conceptual diagram of neuron operations in an AI processor.

[0040] Figure 9 This is a block diagram showing the structure of a conventional product-sum calculator using a digital circuit.

[0041] Figure 10 This is a diagram showing the structure of the product-sum calculator described in Patent Document 1. Detailed Embodiment

[0042] Next, a mode for implementing the present invention will be described in detail with reference to the drawings. In addition, the present invention is not limited to the embodiments to be described below.

[0043] (First Embodiment)

[0044] First, the product-sum calculator according to the first embodiment of the present invention will be described. Figure 1 This is a diagram showing the structure of the product-sum calculator of this embodiment. As Figure 1As shown, in the product-sum calculator 1 of the present embodiment, there are provided: a resistive digital-to-analog conversion unit 11 including a plurality of RDACs; a capacitive digital-to-analog conversion unit 12 including a plurality of CDACs; a successive approximation analog-to-digital conversion unit 13 including a plurality of successive approximation ADCs; and a current consumption control unit 14 that controls the current consumption of each RDAC of the resistive digital-to-analog conversion unit 11.

[0045] In addition, in the product-sum calculator 1 of the present embodiment, a conversion number control unit 15, a reference voltage control unit 16, a multiplier 17, a coefficient control unit 18, etc. are provided as needed. Among them, the conversion number control unit 15 controls the successive approximation number of the successive approximation ADC, the reference voltage control unit 16 controls the reference voltage of the successive approximation ADC, the multiplier 17 multiplies the output of the successive approximation ADC by a coefficient, and the coefficient control unit 18 controls the coefficient.

[0046] [Resistive digital-to-analog conversion unit 11]

[0047] The resistive digital-to-analog conversion unit 11 is composed of a plurality of RDACs. A vector X with a plurality of digital values as elements is input to each RDAC of the digital-to-analog conversion unit 11 through a bus. Moreover, in each RDAC, the digital value of each element of the vector X is converted into an analog voltage and output.

[0048] [Capacitive digital-to-analog conversion unit 12]

[0049] The capacitive digital-to-analog conversion unit 12 is composed of a plurality of CDACs, and the CDACs are arranged two-dimensionally. An analog voltage (output voltage) output from the resistive digital-to-analog conversion unit 11 and a matrix W with a plurality of digital values as elements are input to each CDAC of the capacitive digital-to-analog conversion unit 12. Moreover, each CDAC sets a capacitance ratio corresponding to the digital value of each element of the matrix W between the input-output terminals and between the output terminal and the ground.

[0050] [Successive approximation analog-to-digital conversion unit 13]

[0051] The successive approximation analog-to-digital conversion unit 13 is composed of a plurality of successive approximation ADCs. The voltage of a node commonly connected to each output terminal of the capacitive digital-to-analog conversion unit 12 is input to the successive approximation analog-to-digital conversion unit 13, and each successive approximation ADC converts this voltage into a digital value and outputs it.

[0052] [Current consumption control unit 14]

[0053] The current consumption control unit 14 controls the current consumption of each RDAC of the resistive digital-to-analog conversion unit 11. The method of controlling the current consumption is not particularly limited. For example, the current consumption of each RDAC can be controlled by adjusting the generation period of the analog voltage (output voltage) output from the resistive digital-to-analog converter 11.

[0054] Figure 2 A to Figure 2 C of shows a waveform diagram of a method for reducing the current consumption of each RDAC of the resistive digital-to-analog conversion unit 11, and shows the situation when the input data to the RDAC is switched. As Figure 2 shown in A of, during the reset period T RST of the CDAC, the voltage of the common output terminal of the CDAC is zero. When a signal is input to the RDAC after the reset is released, current flows through the RDAC, and the voltage of the common output terminal of the CDAC rises and converges toward the final value. Since the time T1 is determined according to the normal operation clock cycle, as Figure 2 shown in B of, the current flowing through the RDAC continues to flow during this period.

[0055] On the other hand, since the response is the step response of an RC circuit, when the set voltage is V s and its time constant is τ, the error voltage V e is represented by the following equation 3.

[0056] [Equation 3]

[0057] V2 = V S e -t / τ

[0058] According to the above equation 3, it can be seen that if the time t is set to about 6τ, the error can be made 1 / 2 of the 8-bit accuracy. Let this settling time be T2. If the ADC samples the signal at time T2, it is not necessary to generate the voltage of the common output terminal of the CDAC thereafter. Therefore, as Figure 2 shown in C of, if the current of the RDAC is cut off after the settling time reaches T2, the current consumption of the RDAC can be reduced. At this time, the simplest method of cutting off the current in the RDAC is the method of selecting all the input terminals to be grounded.

[0059] By providing the current consumption control unit 14 that controls the current consumption of each RDAC of the resistive digital-to-analog conversion unit 11 in this way, the power consumption of the multiplier-accumulator 1 can be reduced.

[0060] [Conversion times control unit 15]

[0061] The conversion times control unit 15 controls the number of successive comparisons in the successive approximation type analog-to-digital conversion unit 13. Figure 3Figure A shows a circuit diagram of the structure of the successive approximation type ADC of the successive approximation type analog-digital conversion section 13. Figure 3 Figure B shows a conceptual diagram of the power consumption reduction method. As Figure 3 shown in Figure A, the successive approximation type analog-digital conversion section 13 is composed of a capacitor array C, switches S, a comparator, and SAR logic. Among them, the capacitor array C is binary weighted, the switch S selects the voltage applied to each capacitor from the ground potential or the reference voltage, the comparator compares the voltages, and the SAR logic controls the successive approximation.

[0062] As Figure 3 shown in Figure B, in the successive approximation type analog-digital conversion section 13, the shift register sequentially selects switches S1 to S5 substantially synchronously with the clock, and determines the voltage selected by the switch according to the output state of the comparator. Therefore, the number of clocks corresponding to the resolution is input, and the consumed energy is proportional to the number of clocks. On the other hand, in the AI processor, the resolution of the multiply-accumulate operation is not necessarily constant. Generally speaking, high resolution is required in the layer close to the input, but low resolution is sufficient in the layer close to the output. Therefore, the power consumption of the multiply-accumulate unit 1 can be reduced by controlling the number of successive approximation times of the successive approximation type ADC to be more in the case of high resolution and less in the case of low resolution by using the conversion number control section 15.

[0063] [Reference voltage control section 16]

[0064] The reference voltage control section 16 controls the reference voltage of each successive approximation type ADC in the successive approximation type analog-digital conversion section 13 to minimize the gain error of the ADC. Figure 4 Figure is a circuit diagram showing a structural example of the reference voltage control section 16. In addition to the method of directly controlling the reference voltage of the successive approximation type analog-digital conversion section 13 itself, the control of the reference voltage can also be achieved as follows: As Figure 4 shown, a capacitor βC (a capacitor with a capacitance ratio of β) that samples the input signal as the reference voltage control section 16 is connected to the connection part of the input terminal of the comparator 21 and a capacitive digital-analog converter (DAC) that is provided in the successive approximation type analog-digital conversion section 13 and is used to generate a voltage difference between the input signal and the comparison voltage and is binary weighted.

[0065] In the case of adopting the Figure 4 shown circuit structure, first, close the switch S 10 , and use the switches S 11 , S 12 …S n+10 of each capacitor of the capacitive DAC to select the input signal V inp or the input signal V innAnd sample the input signal. Then, turn off switch S 10 and connect the capacitor C / 2 of the capacitive DAC to the input signal V RP or the input signal V RN , and connect the remaining capacitors C / 4…C / 2 N-1 to ground GND. In this case, the potential difference (V a -V b ) at the input terminal of comparator 21 during the most significant bit (MSB) comparison is represented by Equation 4 below.

[0066] [Equation 4]

[0067]

[0068] Thus, since the reference voltage is reduced to 1 / (1 + β), the gain of the ADC can be increased and the gain error can be reduced. And by providing the reference voltage control unit 16 with such a structure, it is possible to reduce the voltage attenuation generated at the output terminal due to the parasitic capacitance at the output terminal of the CDAC without increasing the power consumption, and reduce the arithmetic error resulting therefrom.

[0069] Here, accuracy is required for the capacitance ratio β. Figure 5 is a circuit diagram showing a structural example capable of controlling the capacitance value of the capacitance βC shown in Figure 4 . For example, in the reference voltage control unit 16, a capacitor bank as shown in Figure 5 is provided. This capacitor bank includes a plurality of capacitances (βC / 2 to βC / 64) weighted in binary and a plurality of switches (S 21 to S 26 ). By controlling each switch S 21 to S 26 using a switch control signal, the gain error of the ADC can be minimized. In addition, although a structure weighted in binary is shown in Figure 5 , the present invention is not limited to this structure. By providing such a reference voltage control unit 16, the reference voltage can be controlled and the arithmetic accuracy of the product-sum calculator 1 can be improved.

[0070] [Multiplier 17 / Coefficient Control Unit 18]

[0071] The multiplier 17 multiplies the output from the successive approximation type analog-digital conversion unit 13 by a coefficient, and the coefficient control unit 18 controls the coefficient used in the multiplier 17. By multiplying by the coefficient generated in the coefficient control unit 18 using the multiplier 17, the arithmetic gain error can be reduced to improve the arithmetic accuracy of the product-sum calculator 1.

[0072] In addition, it is not necessary to have all of the aforementioned comparison count control unit 15, reference voltage control unit 16, multiplier 17, and coefficient control unit 18, and the conversion count control unit 15 may be omitted as appropriate. Additionally, it is sufficient to provide any one of the reference voltage control unit 16, multiplier 17, and coefficient control unit 18.

[0073] As described in detail above, in the product-sum calculator of the present embodiment, the current consumption of the resistive DAC is controlled by the current consumption control unit, so that the power consumption can be reduced compared to a conventional product-sum calculator using an analog circuit. Additionally, by providing a reference voltage control unit and / or a multiplier and coefficient control unit, etc., to reduce the gain error, the operation accuracy can be improved compared to a conventional product-sum calculator using an analog circuit. As a result, according to the present invention, it is possible to realize a product-sum calculator that can operate with lower energy and perform high-precision operations.

[0074] (Second Embodiment)

[0075] Next, a product-sum calculator according to a second embodiment of the present invention will be described. Figure 6 FIG. shows the structure of the product-sum calculator of the present embodiment. In addition, in Figure 6 the same reference numerals are given to the structures that are the same as those of the product-sum calculator 1 shown in Figure 1 , and in the present embodiment, detailed descriptions of these structures are omitted.

[0076] As shown in Figure 6 , in the product-sum calculator 10 of the present embodiment, in addition to a resistive digital-to-analog conversion unit 11, a capacitive digital-to-analog conversion unit 12, a successive approximation analog-to-digital conversion unit 13, a current consumption control unit 14, a conversion count control unit 15, a reference voltage control unit 16, a multiplier 17, and a coefficient control unit 18, an adder 19 for compensating for the offset of the successive approximation ADC and an offset control unit 20 are provided.

[0077] [Adder 19 / Offset Control Unit 20]

[0078] The adder 19 adds an arbitrary value to the output value from the successive approximation analog-to-digital conversion unit 13 to perform offset compensation, and the offset control unit 20 controls the value added in the adder 19.

[0079] Figure 7 FIG. is a characteristic diagram showing the deterioration of the operation accuracy and its compensation, and shows the output value obtained by normalizing the full-scale value of the ADC with respect to the ideal output voltage of the CDAC. As shown in Figure 7 , ideally, if the full-scale voltage of the RDAC is set to V FSIf this voltage is used as the reference voltage for the ADC, the normalized output of the ADC is 1, but in reality, there is an offset error e off and a gain of α - e less than 1 off . The reason is that parasitic capacitance is applied to the common output terminal of the CDAC due to wiring or the like, and the voltage at the common output terminal is divided by the capacitance. The deviation of the normalized output from 1 becomes an arithmetic error, so it is necessary to correct it.

[0080] Therefore, in the multiplier - adder 10 of the present embodiment, first, the offset control unit 20 is used to detect the offset error e off , and the adder 19 is used to add the offset error e to the output values of the respective successive - approximation ADCs from the successive - approximation analog - to - digital conversion unit 13 off for offset compensation. Next, the gain error is corrected. As a method for correcting the gain error, there are a method of providing a reference voltage control unit 16 to control the reference voltage of the successive - approximation ADC, and a method of providing a multiplier 17 and a coefficient control unit 18 and multiplying the output value offset - compensated by the adder 19 and the offset control unit 20 by 1 / (α - e off ) as a coefficient.

[0081] In the multiplier - adder of the present embodiment, the output from the successive - approximation analog - to - digital conversion unit is offset - compensated and the gain error is corrected, so the accuracy of the multiplier - adder can be improved. In addition, the structures and effects other than the above in the present embodiment are the same as those of the first embodiment described above.

[0082] In addition, the present invention can also adopt the following structure.

[0083] 〔1〕

[0084] A multiplier - adder having:

[0085] A resistive digital - to - analog conversion unit including a plurality of resistive digital - to - analog converters for converting the digital values of the respective elements of the input vector into analog voltages and outputting them;

[0086] A capacitive digital - to - analog conversion unit including a plurality of capacitive digital - to - analog converters. The capacitive digital - to - analog conversion unit is input with the analog voltage output from the resistive digital - to - analog conversion unit, and sets a capacitance ratio corresponding to the digital value of each element of the matrix between the input - output terminals and between the output terminal and the ground;

[0087] A successive - approximation analog - to - digital conversion unit including a plurality of successive - approximation analog - to - digital converters for converting the voltage of a node commonly connected to the respective output terminals of the capacitive digital - to - analog conversion unit into a digital value and outputting it; and

[0088] A current consumption control unit that controls the current consumption of the resistive digital-to-analog conversion unit,

[0089] wherein the output from the successive approximation analog-to-digital conversion unit is set as an output vector.

[0090] 〔2〕

[0091] The product-sum calculator according to 〔1〕, wherein,

[0092] the current consumption control unit controls the generation period of the analog voltage output from the resistive digital-to-analog converter.

[0093] 〔3〕

[0094] The product-sum calculator according to 〔1〕 or 〔2〕, wherein,

[0095] it further has a conversion number control unit that controls the number of successive comparisons in the successive approximation analog-to-digital conversion unit.

[0096] 〔4〕

[0097] The product-sum calculator according to any one of 〔1〕 to 〔3〕, wherein,

[0098] it further has a reference voltage control unit that controls the reference voltage of the successive approximation analog-to-digital conversion unit.

[0099] 〔5〕

[0100] The product-sum calculator according to 〔4〕, wherein,

[0101] a capacitor that samples the input signal and serves as the reference voltage control unit is connected to the connection part between the capacitive digital-to-analog converter and the input terminal of the comparator in the successive approximation analog-to-digital conversion unit.

[0102] 〔6〕

[0103] The product-sum calculator according to 〔5〕, wherein,

[0104] the capacitance value of the capacitor that samples the input signal can be controlled.

[0105] 〔7〕

[0106] The product-sum calculator according to any one of 〔1〕 to 〔6〕, wherein,

[0107] it further has: an adder that adds an offset value to the output from the successive approximation analog-to-digital conversion unit; and an offset control unit that controls the offset value.

[0108] 〔8〕

[0109] The product-sum calculator according to any one of 〔1〕 to 〔7〕, wherein,

[0110] it further includes: a multiplier that multiplies the output from the successive comparison type analog-to-digital conversion unit by a coefficient; and a coefficient control unit that controls the coefficient.

[0111] Description of Reference Numerals

[0112] 1, 10, 100: product-sum calculators; 11: resistance type digital-to-analog conversion unit; 12, 102: capacitance type digital-to-analog conversion units; 13: successive comparison type analog-to-digital conversion unit; 14: current consumption control unit; 15: conversion times control unit; 16: reference voltage control unit; 17: multiplier; 18: coefficient control unit; 19: adder; 20: offset control unit; 21: comparator; 101: voltage output digital-to-analog conversion unit; 103: analog-to-digital conversion unit.

Claims

1. An accumulation and summation calculator, comprising: A resistive digital-to-analog conversion section having a plurality of resistive digital-to-analog converters for converting the digital values of the respective elements of an input vector into analog voltages and outputting them; A capacitive digital-to-analog conversion section having a plurality of capacitive digital-to-analog converters. The capacitive digital-to-analog conversion section is input with the analog voltages output from the resistive digital-to-analog conversion section, and sets capacitance ratios corresponding to the digital values of the respective elements of the matrix between the input-output terminals and between the output terminal and the ground; A successive approximation type analog-to-digital conversion section having a plurality of successive approximation type analog-to-digital converters for converting the voltage of a node commonly connected to the respective output terminals of the capacitive digital-to-analog conversion section into a digital value and outputting it; and A current consumption control section for controlling the current consumption of the resistive digital-to-analog conversion section, Among them, wherein the output from the successive approximation type analog-to-digital conversion section is set as an output vector.

2. The accumulation and summation calculator according to claim 1, wherein the current consumption control section controls the generation period of the analog voltages output from the resistive digital-to-analog converters.

3. The accumulation and summation calculator according to claim 1, wherein it further has a conversion number control section for controlling the number of successive approximations in the successive approximation type analog-to-digital conversion section.

4. The accumulation and summation calculator according to claim 1, wherein it further has a reference voltage control section for controlling the reference voltage of the successive approximation type analog-to-digital conversion section.

5. The accumulation and summation calculator according to claim 4, wherein a capacitor for sampling an input signal as the reference voltage control section is connected to the connection portion between the capacitive digital-to-analog converter and the input terminal of the comparator in the successive approximation type analog-to-digital conversion section.

6. The accumulation and summation calculator according to claim 5, wherein the capacitance value of the capacitor for sampling the input signal can be controlled.

7. The accumulation and summation calculator according to claim 1, wherein it further has: an adder for adding an offset value to the output from the successive approximation type analog-to-digital conversion section; and an offset control section for controlling the offset value.

8. The accumulation and summation calculator according to claim 1 or 7, wherein it further has: a multiplier for multiplying the output from the successive approximation type analog-to-digital conversion section by a coefficient; and a coefficient control section for controlling the coefficient.

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