Circuit for carrying out stress test on grid electrode of power transistor

Abstract

The embodiment of the invention relates to a circuit for stress testing of a power transistor gate. A power electronic circuit is provided that includes at least one power transistor, a gate of the at least one power transistor is coupled to a control circuit, and a source of the at least one power transistor is coupled to a first contact pad, where the control circuit is coupled to a second contact pad, and wherein the first contact pad and the second contact pad are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing of the gate of the power transistor, and configured to be coupled to each other when the power transistor and the control circuit are packaged.

Description

Technical Field

[0001] The present description relates generally to the field of power electronic circuits including power transistors, and in particular to DC-DC converters or direct current to direct current converters. Background Art

[0002] During the production of power circuits such as DC-DC converters, the power transistors of these circuits (for example, forming the switching units in the case of converters) are tested in order to discard circuits containing transistors that do not meet the required specifications and to use circuits including transistors that meet these specifications. One such test is called a gate stress test and involves applying a high voltage, called a stress voltage, between the gate and the source of the power transistor being tested. For example, this stress voltage can be equal to 11 V and can be applied for a duration of up to 200 ms. For PMOS transistors, the stress voltage applied between the gate and the source of the transistor is negative to avoid PBTI type degradation (positive bias temperature instability).

[0003] This stress voltage is much higher than the nominal supply voltage applied during "normal" switching or operational use of these transistors, for example 5 V or 7 V. This stress test of the gates of power transistors makes it possible to identify the presence of defects in the tested transistors (for example in their gate oxides) that could lead to significant leakage currents after a short period of transistor use (for example after about a year). Leakage in transistors with such defects thus appears during the stress test, and power circuits including these faulty transistors can therefore be identified and discarded without having to wait for such leakage to appear during use.

[0004] During stress testing, other circuit components coupled to the connections to which the stress voltage is applied (such as components of the control circuit of the power transistor) are protected from being damaged by the stress voltage. For example, where the switching circuit includes a CMOS inverter, this protection can be achieved by adding an additional transistor coupled to a resistor at the output of the inverter.

[0005] Furthermore, dedicated internal contact pads are used to measure leakage current during stress testing of transistors, and for applying stress voltages to power transistors on the low side of the circuit.

[0006] Finally, since the drains of the power transistors on the high and low sides of the circuit are coupled to the same contact pad from which the output signals of the power transistors are recovered, the power transistors on the high and low sides of the power circuit cannot be tested simultaneously. Summary of the Invention

[0007] There is a need to provide a solution that does not have at least some of the disadvantages of existing solutions.

[0008] One embodiment overcomes some or all of the disadvantages of known solutions and provides a power electronic circuit comprising at least one power transistor, a gate of the at least one power transistor being coupled to a control circuit, and a source of the at least one power transistor being coupled to a first contact pad, wherein the control circuit is coupled to a second contact pad, and wherein the first contact pad and the second contact pad are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate of the power transistor, and configured to be coupled to each other when the power transistor and the control circuit are packaged.

[0009] According to one embodiment, the power transistor and the control circuit are high-side components of a power electronic circuit, and the first contact pad and the second contact pad are configured such that when the power electronic circuit is in a configuration for stress testing the gate of the power transistor, a different electrical supply potential is applied to each of the first contact pad and the second contact pad.

[0010] According to one embodiment, the power transistor and the control circuit are low-side components of a power electronic circuit, and the first contact pad and the second contact pad are configured such that when the power electronic circuit is in a configuration for stress testing a gate of the power transistor, a different electrical reference potential is applied to each of the first contact pad and the second contact pad.

[0011] According to one embodiment:

[0012] A power transistor referred to as the first power transistor and a control circuit referred to as the first control circuit are high-side components of the power electronic circuit, and

[0013] The power electronic circuit further includes a second power transistor, a gate of the second power transistor is coupled to the second control circuit, and a source of the second power transistor is coupled to the third contact pad, the second control circuit is coupled to the fourth contact pad, the second power transistor and the second control circuit correspond to low-side components of the power electronic circuit, and

[0014] The first contact pad and the second contact pad are configured such that when the power electronic circuit is in a configuration for stress testing the gate of the first power transistor and the gate of the second power transistor, a different electrical supply potential is applied to each of the first contact pad and the second contact pad, and

[0015] The third contact pad and the fourth contact pad are configured to be decoupled from each other and to apply a different electrical reference potential to each of the third contact pad and the fourth contact pad when the power electronic circuit is in a configuration for stress testing the gate of the first power transistor and the gate of the second power transistor, and are configured to be coupled to each other when the first power transistor and the second power transistor and the first control circuit and the second control circuit are packaged.

[0016] According to one embodiment, the drain of the first power transistor is coupled to the first switching pad, and the drain of the second power transistor is coupled to the second switching pad, and the first switching pad and the second switching pad are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate of the first power transistor and the gate of the second power transistor, and are configured to be coupled to each other when the first power transistor and the second power transistor and the first control circuit and the second control circuit are packaged.

[0017] According to one embodiment, the control circuit, or each of the first and second control circuits, includes a CMOS inverter, the output of the CMOS inverter being coupled to the gate of the power transistor or the gate of one of the first and second power transistors, and / or the power transistor, or each of the first and second power transistors, corresponds to a MOSFET.

[0018] According to one embodiment, a power electronic circuit includes a package component.

[0019] According to one embodiment, the power electronic circuit further comprises a first electrical connector electrically coupling the first contact pad and the second contact pad together, and when the power electronic circuit comprises a third contact pad and a fourth contact pad, the second electrical connector couples the third contact pad and the fourth contact pad together.

[0020] According to one embodiment, a power electronic circuit includes a first switching pad and a second switching pad and a third electrical connector coupling the first switching pad and the second switching pad together.

[0021] According to one embodiment, the power electronic circuit is a DC-DC converter.

[0022] A method for realizing and packaging at least one power electronic circuit is also provided, the method comprising at least the following steps:

[0023] Implementing the power electronic circuit as described above;

[0024] performing stress testing on gate(s) of(s) power transistor(s) of a power electronic circuit;

[0025] The power transistor(s) and control circuit(s) of the power electronic circuit are packaged.

[0026] According to an embodiment, stress testing the gate(s) of the power transistor(s) includes measuring a leakage current on the first contact pad and / or the third contact pad.

[0027] According to one embodiment, packaging (multiple) power transistors and (multiple) control circuits includes: executing a first electrical connector to electrically couple a first contact pad and a second contact pad of a power electronic circuit together, and, when the power electronic circuit includes a third contact pad and a fourth contact pad, executing a second electrical connector to couple the third contact pad and the fourth contact pad of the power electronic circuit together.

[0028] According to one embodiment, packaging the power transistor(s) and the control circuit(s) further comprises implementing a third electrical connector to couple together the first switching pad and the second switching pad of the power electronic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above-mentioned features and advantages and other features and advantages will be described in detail in the following description of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0030] Figure 1 schematically illustrates an example portion of a power electronics circuit in a configuration for stress testing the gates of power transistors of the circuit, according to one specific embodiment;

[0031] Figure 2 schematically illustrates an example of a portion of a power electronic circuit after interconnecting contact pads of the circuit according to a specific embodiment; and

[0032] Figure 3 A power electronic circuit according to a specific embodiment is schematically illustrated, the components of which are packaged. DETAILED DESCRIPTION

[0033] The same features have been designated by the same reference numerals in the various figures. In particular, common structural and / or functional features between the various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0034] For the sake of clarity, only the operations and elements that are helpful for understanding the embodiments described herein are illustrated and described in detail. Specifically, various elements and components of the power electronics circuit are not described in detail. Those skilled in the art will be able to implement these elements in detail from the description given herein.

[0035] Unless otherwise specified, when reference is made to two elements being connected together, this means a direct connection without any intermediate elements other than conductors, and when reference is made to two elements being coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements. Furthermore, the term "coupled" is used herein to refer to electrical coupling between multiple electrical and / or electronic components (assemblies, circuits, etc.). The same applies to the term "decoupled."

[0036] In the following disclosure, unless otherwise indicated, when reference is made to absolute position qualifiers, such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as terms "above", "below", "higher", "lower", etc., or to orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figures according to the orientation during normal use.

[0037] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, and preferably within 5%.

[0038] According to a specific embodiment, the power electronic circuit 100 is combined with Figure 1 Only some of the elements and components of circuit 100 are described below and in Figure 1 Visible above.

[0039] The circuit 100 includes electrical and / or electronic elements or components on a high-side portion of the circuit 100, to which at least one electrical supply potential of the circuit 100 is intended to be applied. The circuit 100 also includes electrical and / or electronic elements or components on a low-side portion of the circuit 100, to which at least one electrical reference potential of the circuit 100 (e.g., serving as ground) is intended to be applied.

[0040] In the depicted example embodiment, the circuit 100 includes one or more first power transistors 102 and one or more first control circuits 104 as part of the high side of the circuit 100. The first control circuit 104 is configured to control the switching of the first power transistors 102. When the circuit 100 includes several first power transistors 102, the gate of each of these first power transistors 102 is coupled to an output of the first control circuit 104 dedicated to controlling that transistor.

[0041] The circuit 100 also includes one or more second power transistors 106 and one or more second control circuits 108 as part of the low side of the circuit 100. The second control circuit 108 is configured to control the switching of the second power transistors 106. When the circuit 100 includes several second power transistors 106, the gate of each of these second power transistors 106 is coupled to an output of the second control circuit 108 dedicated to controlling that transistor.

[0042] exist Figure 1 In FIG. 1 , a single first power transistor 102, a single first control circuit 104, a single second power transistor 106, and a single second control circuit 108 are shown. The features described below for each of these components may also be applied to the circuit 100 in FIG. Figure 1 Other power transistors and control circuits are not shown.

[0043] In the depicted example embodiment, the power transistors 102 , 106 and the control circuit transistors 104 , 108 are MOSFETs. Alternatively, other types of transistors may be used to form the power transistors 102 , 106 and / or the transistors of the control circuits 104 , 108 .

[0044] exist Figure 1 In the example shown, the first power transistor 102 corresponds to a PMOS transistor, and the gate of the first power transistor 102 is coupled to the first control circuit 104. More specifically, in the described example embodiment, the gate of the first power transistor 102 is coupled to the output of the first CMOS inverter 109 of the first control circuit 104 (which output is coupled to the drains of the NMOS and PMOS transistors of the first CMOS inverter 109). Figure 1 In the example shown, the input of the first CMOS inverter 109 (which is coupled to the gates of the NMOS and PMOS transistors of the first CMOS inverter 109 ) is coupled to two inverters 110 , 112 coupled in series with each other.

[0045] The source of the first power transistor 102 is coupled to the first contact pad 114, and the first control circuit 104 is coupled to the second contact pad 116. Figure 1 In the example shown, the source of the PMOS transistor of the first CMOS inverter 109 is coupled to the second contact pad 116. In this example, the source of the NMOS transistor of the first CMOS inverter 109 is coupled to the floating ground 118. Finally, the drain of the first power transistor 102 is coupled to another contact pad, referred to as the first switching pad 120.

[0046] exist Figure 1In the example shown, the second power transistor 106 corresponds to an NMOS transistor, and the gate of the second power transistor 106 is coupled to the second control circuit 108. More specifically, in the described example embodiment, the gate of the second power transistor 106 is coupled to the output of the second CMOS inverter 119 of the second control circuit 108 (which output is coupled to the drains of the NMOS and PMOS transistors of the second CMOS inverter 119). Figure 1 In the example shown, the input of the second CMOS inverter 119 , which is coupled to the gates of the NMOS and PMOS transistors of the second CMOS inverter 119 , is coupled to an inverter 122 .

[0047] The source of the second power transistor 106 is coupled to the third contact pad 124, and the second control circuit 108 is coupled to the fourth contact pad 126. Figure 1 In the example shown, the source of the NMOS transistor of the second CMOS inverter 119 is coupled to a fourth contact pad 126. In this example, the source of the PMOS transistor of the second CMOS inverter 119 is coupled to a floating supply potential 128. Finally, the drain of the second power transistor 106 is coupled to another contact pad, referred to as a second switching pad 130.

[0048] exist Figure 1 In the example shown, the components of circuit 100 have not yet been packaged. Circuit 100 is therefore in a configuration in which connections between pads 114 and 116, between pads 124 and 126, and between pads 120 and 130 have not yet been made, and is therefore in a configuration that enables stress testing of the gates of power transistors 102 and 106. In this test configuration, first contact pad 114 and second contact pad 116 are decoupled from each other. Therefore, when stress testing the power transistors, different electrical supply potentials can be applied to each of first contact pad 114 and second contact pad 116, enabling a supply voltage to be applied to first control circuit 104 that is lower than the stress voltage applied between the gate and source of first power transistor 102, thereby avoiding damage to first control circuit 104 caused by the stress voltage applied to first control circuit 104.

[0049] For example, during stress testing of the first power transistor 102, a first electrical supply potential, for example equal to 11 V, can be applied to the first contact pad 114, and a second electrical supply potential lower than the first electrical supply potential (e.g., equal to 5 V) can be applied to the second contact pad 116. The potential of the floating ground 118 can be equal to 0 V. In this case, by applying a potential corresponding to a logic "1" (e.g., equal to 5 V) at the input of the inverter 110, the potential obtained at the output of the first CMOS inverter 109 and applied to the gate of the first power transistor 102 is zero. During stress testing of the first power transistor 102, another electrical supply potential equal to the first potential can be applied to the first switching pad 120.

[0050] Similarly, in this stress test configuration, the third contact pad 124 and the fourth contact pad 126 are decoupled from each other. Therefore, when stress testing the power transistor, different electrical reference potentials can be applied to each of the third contact pad 124 and the fourth contact pad 126, so that a supply voltage lower than the stress voltage applied between the gate and source of the second power transistor 106 can be applied to the second control circuit 108, as with the components on the high side of the circuit 100.

[0051] For example, during stress testing of the second power transistor 106, a first reference potential equal to -6 V may be applied to the third contact pad 124, and a second reference potential higher than the first reference potential (e.g., equal to 0 V) may be applied to the fourth contact pad 126. The floating supply potential 128 may be equal to 5 V. In this case, by applying a potential corresponding to a logic "1" (e.g., equal to 5 V) at the input of the inverter 122, the potential obtained at the output of the second CMOS inverter 119 and applied to the gate of the second power transistor 106 is equal to 5 V. During stress testing of the second power transistor 106, another electrical reference potential equal to the first electrical reference potential may be applied to the second switching pad 130.

[0052] In this test configuration, if Figure 1 As shown, the first switching pad 120 and the second switching pad 130 are thus decoupled from each other. Stress testing of the first power transistor 102 and the second power transistor 106 can thus be performed simultaneously.

[0053] During stress testing of the power transistors 102, 106, leakage current from the first power transistor 102 may be measured on the first contact pad 114, and / or leakage current from the second power transistor 106 may be measured on the third contact pad 124. Alternatively, the first power transistor 102 may include a Kelvin source connection, allowing any leakage current to be measured, in which case the output of the first CMOS inverter 109 is set to a high impedance configuration during stress testing of the transistor, and / or the second power transistor 106 may include a Kelvin source connection, allowing any leakage current to be measured, in which case the output of the second CMOS inverter 119 is set to a high impedance configuration during stress testing of the transistor.

[0054] The above-described implementation of stress testing the gates of the power transistors 102, 106 allows revealing whether one or more of these power transistors 102, 106 has a fault that generates a leakage current. In the presence of such a fault, the circuit 100 is discarded and not used. Due to the structure of the circuit 100, stress testing the power transistors 102, 106 can be performed without subjecting the control circuits 104, 108 to the high stress voltages used during these tests, and thus protecting them from these voltages without having to resort to additional components dedicated to protecting the control circuits 104, 108. In addition, since the first switching pad 120 and the second switching pad 130 are not coupled to each other during the stress testing of the power transistors 102, 106, these transistors can be tested simultaneously during the same stress testing phase. In addition, with this configuration of the circuit 100, there is no need to provide contact pads dedicated to measuring any leakage current and / or applying stress voltages. Finally, since there are no electronic components dedicated to protecting the control circuits 104, 108, the performance of the circuit 100, in particular its operating speed, is not altered by the presence of these protection components.

[0055] Circuit 100 is also suitable for stress testing the drains of power transistors 102 and 106. Furthermore, because contact pads 114 and 116, 124 and 126, and 120 and 130 are disconnected when the components of circuit 100 are not packaged, these tests can be performed in parallel on power transistors 102 and 106.

[0056] After stress testing the gates of the power transistors 102, 106 has been achieved, the components of the circuit 100 are packaged. In the example described here, the packaging is performed so that the following are coupled together:

[0057] a first contact pad 114 and a second contact pad 116;

[0058] a third contact pad 124 and a fourth contact pad 126;

[0059] The first switching pad 120 and the second switching pad 130 .

[0060] Figure 2 The components of the circuit 100 are schematically illustrated after the contact pads 114, 116, 120, 124, 126, and 130 have been interconnected during packaging of the components of the circuit 100. In addition to the components of the circuit 100 described above, the circuit 100 also includes analog logic components and digital logic components, which are collectively designated by the reference numeral 202 for the high side of the circuit 100 and by the reference numeral 204 for the low side of the circuit 100. Output signals from these components are sent as inputs to the control circuits 104, 108 via level shifter circuits 206, 208, enabling, in particular, control of the control circuits 104, 108. These components are also packaged.

[0061] The implemented package forms a first electrical connector 210 that couples the first contact pad 114 and the second contact pad 116. The implemented package also forms a second electrical connector 212 that couples the third contact pad 124 and the fourth contact pad 126. Figure 2 In the example shown, the package further forms a third electrical connector 214 that couples the first switching pad 120 and the second switching pad 130. Furthermore, in the exemplary embodiment described, the package further forms a fourth electrical connector 216 for applying a reference potential to the first control circuit 104 (via the floating ground 118) and the component 202, and a fifth electrical connector 218 for applying a supply potential to the second control circuit 108 (via the floating supply potential 128) and the component 204.

[0062] According to an exemplary embodiment, the electrical connectors 210 to 218 are of the DCI type (“Direct Copper Interconnect”), enabling low-resistance connections to the pads 114, 116, 120, 124, 126, and 130. Such connections between the electrical connectors 210 to 218 and the pads 114 and 116, 124 and 126, and 120 and 130 may be made at the panel level or PLP (“Panel Level Process” or “Panel Level Packaging”).

[0063] As an alternative to the above-described embodiments, the components of the high side and / or the low side of the circuit 100 may be different from those previously described.

[0064] Figure 3An example embodiment in which the power electronic circuit 100 corresponds to a step-down DC-DC converter is schematically illustrated. In the figure, a package element 200 of the circuit 100, such as a package or any other packaging device suitable for the circuit 100, is symbolically represented. Various components other than those described above are not described in detail.

[0065] The power electronic circuit 100 may be particularly suitable for use in the automotive field.

[0066] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined and that other variations will be readily apparent to those skilled in the art.

[0067] Finally, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional description provided above.

[0068] A power electronic circuit (100) can be summarized as including: at least one power transistor (102, 106), the gate of the at least one power transistor (102, 106) being coupled to a control circuit (104, 108), and the source of the at least one power transistor (102, 106) being coupled to a first contact pad (114, 124), wherein the control circuit (104, 108) is coupled to a second contact pad (116, 126), and wherein the first and second contact pads (114, 116, 124, 126) are configured to be decoupled from one another when the power electronic circuit (100) is in a configuration for stress testing the gate of the power transistor (102, 106), and are configured to be coupled to one another when the power transistor (102, 106) and the control circuit (104, 108) are packaged.

[0069] The power transistor (102) and the control circuit (104) may be high-side components of the power electronic circuit (100), and the first and second contact pads (114, 116) may be configured such that a different electrical supply potential is applied to each of the first and second contact pads (114, 116) when the power electronic circuit (100) is in a configuration for stress testing the gate of the power transistor (102).

[0070] The power transistor (106) and the control circuit (108) may be low-side components of the power electronic circuit (100), and the first and second contact pads (124, 126) may be configured such that a different electrical reference potential is applied to each of the first and second contact pads (124, 126) when the power electronic circuit (100) is in a configuration for stress testing the gate of the power transistor (106).

[0071] The power transistor (102) referred to as the first power transistor and the control circuit (104) referred to as the first control circuit may be high-side components of the power electronic circuit (100), and the power electronic circuit (100) may further include a second power transistor (106), the gate of the second power transistor (106) may be coupled to the second control circuit (108), and the source of the second power transistor (106) may be coupled to the third contact pad (124), the second control circuit (108) is coupled to the fourth contact pad (126), the second power transistor (106) and the second control circuit (108) correspond to low-side components of the power electronic circuit (100), and the first contact pad and the second contact pad (114, 116) may be configured such that in the power electronic circuit (1 00) is in a configuration for stress testing the gates of the first power transistor and the second power transistor (102, 106), different electrical supply potentials are applied to each of the first contact pad and the second contact pad (114, 116), and the third contact pad and the fourth contact pad (124, 126) can be configured to be decoupled from each other and to apply different electrical reference potentials to each of the third contact pad and the fourth contact pad when the power electronic circuit (100) is in a configuration for stress testing the gates of the first power transistor and the second power transistor (102, 106), and to be coupled to each other when the first power transistor and the second power transistor (102, 106) and the first control circuit and the second control circuit (104, 108) are packaged.

[0072] The drain of the first power transistor (102) may be coupled to the first switching pad (120) and the drain of the second power transistor (106) may be coupled to the second switching pad (130), and the first and second switching pads (120, 130) may be configured to be decoupled from each other when the power electronic circuit (100) is in a configuration for stress testing the gates of the first and second power transistors (102, 106), and to be coupled to each other when the first and second power transistors (102, 106) and the first and second control circuits (104, 108) are packaged.

[0073] The control circuit (104, 108), or each of the first and second control circuits (104, 108), may include a CMOS inverter (109, 119), the output of the CMOS inverter may be coupled to the gate of the power transistor (102, 106) or the gate of one of the first and second power transistors (102, 106), and / or the power transistor (102, 106) or one of the first and second power transistors (102, 106) corresponds to a MOSFET.

[0074] A power electronic circuit (100) may include a package component (200).

[0075] The power electronic circuit (100) may further include a first electrical connector (210) electrically coupling the first and second contact pads (114, 116) together, and when the power electronic circuit (100) may include third and fourth contact pads (124, 126), a second electrical connector (212) coupling the third and fourth contact pads (124, 126) together.

[0076] The power electronic circuit (100) may include first and second switching pads (120, 130) and a third electrical connector (214) coupling the first and second switching pads (120, 130) together.

[0077] The power electronic circuit (100) may correspond to a DC-DC converter.

[0078] A method for realizing and packaging at least one power electronic circuit (100) can be summarized as comprising at least the following steps: realizing a power electronic circuit (100) according to the above; performing a stress test on gate(s) of power transistor(s) (102, 106) of the power electronic circuit (100); and packaging the power transistor(s) (102, 106) and control circuit(s) (104, 108) of the power electronic circuit (100).

[0079] Stress testing the gate(s) of the power transistor(s) (102, 106) may include measuring leakage current on the first contact pad (114) and / or the third contact pad (124).

[0080] Packaging the power transistor(s) (102, 106) and the control circuit(s) (104, 108) may include implementing a first electrical connector (210) to electrically couple together first and second contact pads (114, 116) of the power electronic circuit (100), and when the power electronic circuit (100) includes third and fourth contact pads (124, 126), implementing a second electrical connector (212) to couple together the third and fourth contact pads (124, 126) of the power electronic circuit (100).

[0081] Packaging the power transistor(s) (102, 106) and the control circuit(s) (104, 108) may also include implementing a third electrical connector (214) to couple together the first switching pad and the second switching pad (120, 130) of the power electronic circuit (100).

[0082] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally speaking, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A power electronic circuit comprising: a first contact pad; a second contact pad; control circuit; as well as A power transistor, the power transistor having: a gate coupled to the control circuit, and a source coupled to the first contact pad, wherein the control circuit is coupled to the second contact pad, and wherein the first contact pad and the second contact pad are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate of the power transistor, and wherein the first contact pad and the second contact pad are configured to be coupled to each other when the power transistor and the control circuit are packaged.

2. The power electronic circuit of claim 1 , wherein the power transistor and the control circuit are high-side components of the power electronic circuit, and the first contact pad and the second contact pad are configured to receive different electrical supply potentials when the power electronic circuit is in the configuration for stress testing the gate of the power transistor.

3. The power electronic circuit of claim 1 , wherein the power transistor and the control circuit are low-side components of the power electronic circuit, and wherein the first contact pad and the second contact pad are configured to receive different electrical reference potentials when the power electronic circuit is in the configuration for stress testing the gate of the power transistor.

4. The power electronic circuit according to claim 1, wherein: The power transistor is a first power transistor, and the control circuit is a first control circuit, and the first power transistor and the first control circuit are high-side components of the power electronic circuit, and The power electronic circuit comprises: A second power transistor, the second power transistor having: is coupled to the gate of the second control circuit, and is coupled to a source of the third contact pad, wherein the second control circuit is coupled to a fourth contact pad, and the second power transistor and the second control circuit are low-side components of the power electronic circuit, and The first contact pad and the second contact pad are configured to receive different electrical supply potentials when the power electronic circuit is in a configuration for stress testing the gate of the first power transistor and the gate of the second power transistor, and The third contact pad and the fourth contact pad are configured to be decoupled from each other and receive different electrical reference potentials when the power electronic circuit is in a configuration for stress testing the gate of the first power transistor and the gate of the second power transistor, and the third contact pad and the fourth contact pad are configured to be coupled to each other when the first power transistor and the second power transistor and the first control circuit and the second control circuit are packaged.

5. The power electronic circuit of claim 4 , wherein the drain of the first power transistor is coupled to a first switching pad, and the drain of the second power transistor is coupled to a second switching pad, and wherein the first switching pad and the second switching pad are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate of the first power transistor and the gate of the second power transistor, and wherein the first switching pad and the second switching pad are configured to be coupled to each other when the first power transistor and the second power transistor and the first control circuit and the second control circuit are packaged. 6 . The power electronic circuit of claim 1 , wherein the control circuit comprises a CMOS inverter having an output coupled to the gate of the power transistor, or the power transistor is a MOSFET.

7. The power electronic circuit of claim 4 , wherein each of the first control circuit and the second control circuit comprises a CMOS inverter having an output coupled to a gate of one of the first power transistor and the second power transistor, or each of the first power transistor and the second power transistor is a MOSFET.

8. The power electronic circuit (100) according to claim 1, comprising: Package components.

9. The power electronic circuit according to claim 8, comprising: A first electrical connector electrically couples the first contact pad with the second contact pad.

10. The power electronic circuit according to claim 4, comprising: A second electrical connector couples the third contact pad with the fourth contact pad.

11. The power electronic circuit according to claim 9, comprising: a first switching pad and a second switching pad; as well as A third electrical connector couples the first switching pad with the second switching pad.

12. A DC-DC converter comprising: A power electronic circuit, comprising: a first contact pad; a second contact pad; control circuitry; and A power transistor, the power transistor having: a gate coupled to the control circuit, and a source coupled to the first contact pad, wherein the control circuit is coupled to the second contact pad, and wherein the first contact pad and the second contact pad are configured to be decoupled from each other when the power electronic circuit is in a configuration for stress testing the gate of the power transistor, and wherein the first contact pad and the second contact pad are configured to be coupled to each other when the power transistor and the control circuit are packaged.

13. The DC-DC converter of claim 12 , wherein the power transistor and the control circuit are high-side components of the power electronic circuit, and the first contact pad and the second contact pad are configured to receive different electrical supply potentials when the power electronic circuit is in the configuration for stress testing the gate of the power transistor.

14. The DC-DC converter of claim 12 , wherein the power transistor and the control circuit are low-side components of the power electronics circuit, and wherein the first contact pad and the second contact pad are configured to receive different electrical reference potentials when the power electronics circuit is in the configuration for stress testing the gate of the power transistor.

15. The DC-DC converter according to claim 12, wherein: The power transistor is a first power transistor, and the control circuit is a first control circuit, and the first power transistor and the first control circuit are high-side components of the power electronic circuit, and The power electronic circuit comprises: A second power transistor, the second power transistor having: is coupled to the gate of the second control circuit, and is coupled to a source of the third contact pad, wherein the second control circuit is coupled to a fourth contact pad, and the second power transistor and the second control circuit are low-side components of the power electronic circuit, and The first contact pad and the second contact pad are configured to receive different electrical supply potentials when the power electronic circuit is in a configuration for stress testing the gate of the first power transistor and the gate of the second power transistor, and The third contact pad and the fourth contact pad are configured to be decoupled from each other and receive different electrical reference potentials when the power electronic circuit is in a configuration for stress testing the gate of the first power transistor and the gate of the second power transistor, and the third contact pad and the fourth contact pad are configured to be coupled to each other when the first power transistor and the second power transistor and the first control circuit and the second control circuit are packaged.

16. The DC-DC converter of claim 15 , wherein the drain of the first power transistor is coupled to a first switching pad, and the drain of the second power transistor is coupled to a second switching pad, and wherein the first switching pad and the second switching pad are configured to be decoupled from each other when the power electronics circuit is in a configuration for stress testing the gate of the first power transistor and the gate of the second power transistor, and wherein the first switching pad and the second switching pad are configured to be coupled to each other when the first power transistor and the second power transistor and the first control circuit and the second control circuit are packaged.

17. A method comprising: Performing a stress test on a gate of a power transistor of a power electronic circuit, wherein the power electronic circuit comprises: a first contact pad; a second contact pad; control circuitry; and A power transistor, the power transistor having: a gate coupled to the control circuit, and a source coupled to the first contact pad, wherein the control circuit is coupled to the second contact pad; decoupling the first contact pad and the second contact pad from each other when the power electronic circuit is in a configuration for stress testing the gate of the power transistor; and When the power transistor and the control circuit are packaged, the first contact pad and the second contact pad are coupled to each other.

18. The method according to claim 17, wherein stress testing the gate of the power transistor comprises: A leakage current on the first contact pad or a leakage current on the third contact pad is measured.

19. The method of claim 17, wherein packaging the power transistor and the control circuit comprises: A first electrical connection is performed, the first electrical connection electrically coupling the first contact pad and the second contact pad of the power electronic circuit, and, when the power electronic circuit includes a third contact pad and a fourth contact pad, a second electrical connection is performed, the second electrical connection coupling the third contact pad and the fourth contact pad together.

20. The method of claim 19, wherein packaging the power transistor and the control circuit comprises: A third electrical connection is performed, coupling the first switching pad and the second switching pad of the power electronic circuit together.

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