Feedforward regulation circuit system and method for regulating power supply by using feed-forward regulation circuit system

Abstract

The invention relates to a circuit system (200) for regulating a power supply, comprising: a feed-forward amplifier (100) comprising a clock generator (10) comprising a switching detector circuit (12) for generating a feed-forward enable signal upon detection of a switched input clock signal, and a load circuit (20) for generating a current during a function demand, wherein the load circuit (20) comprises a feed-forward pass gate for receiving a feed-forward enable signal, load circuitry (24), a variable bias voltage controller, and a level shifter (22) for controlling the feed-forward pass gate.

Description

Technical Field

[0001] The present invention generally relates to high-speed CMOS clock circuits and particularly addresses challenges related to power regulation in such circuits. Background Art

[0002] In modern digital systems, a key function of high-speed CMOS clock circuits is to synchronize various components for seamless operation. However, the relentless pursuit of increased clock frequency and reduced power consumption poses challenges in maintaining a stable power supply, especially in the face of manufacturing process variations.

[0003] Traditional clock circuits often struggle to adapt to process-dependent fluctuations, leading to potential timing errors and performance degradation. Therefore, there is a need for a creative approach to power regulation that transcends the limitations imposed by manufacturing processes, ensuring both stability and optimal circuit functionality. These requirements underscore the core focus of current technological advancements.

[0004] In high-speed CMOS clock circuits, there have been some solutions provided for analog feed-forward systems, some of which are discussed below.

[0005] US2012 / 0121274 A1 discloses a receiver designed for an optical communication system, aimed at correcting distortion in a received signal. The system incorporates a clock recovery mechanism that employs both a feedback system and a feed-forward system. The feed-forward loop includes a phase detector and a delay element for delaying the output of the distortion correction system. Notably, the feedback loop operates at a significantly lower bandwidth compared to the feed-forward path. The patent also outlines methods for optimizing tap weights and obtaining initial tap weights.

[0006] US2022 / 0163988 A1 discloses a digital comparator coupled to a set of pull-up resistors and a set of pull-down resistors, where both sets of resistors are connected to the output terminal of a low dropout (LDO) regulator. Specifically, the digital comparator is equipped with an edge detector module, a continuous double-edge detector module, and a continuous triple-edge detector module. The edge detector module is designed to take two clock signals as inputs. After being processed by these three modules, the comparator adjusts the pull-up or pull-down state of the resistors at the output terminal of the LDO regulator based on the rising and falling edges of the received clock signals.

[0007] However, the above references and other conventional techniques are still struggling to address some challenges, thus facilitating the objectives and features of the present invention to solve these problems. Notably, industries such as computer architecture face challenges associated with voltage droop and overshoot. Therefore, there is an urgent need for a solution that is customized to overcome these specific problems and aims to improve the performance of high-speed CMOS clock circuits for better operation. Summary of the Invention

[0008] A simplified overview of the present invention is given below to provide a basic understanding of some aspects of the present invention. This overview is not an extensive review of the present invention. Its sole purpose is to present some concepts of the present invention in a simplified form as a prelude to the more detailed description presented later.

[0009] An object of the present invention is to effectively counteract the power supply voltage droop during the dynamic current requirement by switching the activation of the feedforward based on the input clock.

[0010] Another object of the present invention is to utilize a customized level shifter having thin-gate transistors and thick-gate transistors to ensure an effective voltage domain transition and enhance voltage stability.

[0011] Another object of the present invention is to use a fixed bias reference in the system without any periodic calibration or real-time calibration.

[0012] Correspondingly, these objectives can be achieved by following the teachings of the present invention. The present invention discloses a circuit system for regulating power supply, comprising: a feedforward amplifier including a clock generator and a load circuit for generating current during functional requirements; wherein the clock generator includes a switching detector circuit for generating a feedforward enable signal when detecting a switched input clock signal; wherein the load circuit includes a feedforward transmission gate for receiving the feedforward enable signal, a load circuit system, a variable bias voltage controller, and a level shifter for controlling the feedforward transmission gate.

[0013] The present invention also relates to a method for regulating the power supply of a circuit system using a feedforward amplifier, comprising the following steps: activating the feedforward transmission gate of the load circuit; detecting a switched input clock signal by the switching detector circuit; generating a feedforward enable signal when the switched input signal is detected; and deactivating the feedforward enable signal when the input clock signal is not switched.

[0014] By carefully reading the detailed description provided below and appropriately referring to the accompanying drawings, the foregoing and other objectives, features, aspects, and advantages of the present invention will be better understood. Brief Description of the Drawings

[0015] In order to be able to understand in detail the above features of the present invention, the present invention briefly outlined above has been described in more specific terms by way of examples, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the present invention and should not be considered as limiting the scope of the present invention, since the present invention may admit other equivalent embodiments.

[0016] These and other features, benefits, and advantages of the present invention will become apparent by reference to the following textual drawings, in which like reference numerals refer to like structures in the various views, wherein:

[0017] Figure 1 Shows an overall scheme of a feed - forward amplifier according to an embodiment of the present invention;

[0018] Figure 2 Is a schematic diagram of feed - forward enable signal generation according to an embodiment of the present invention;

[0019] Figure 3 Is a detailed schematic diagram of a switching detector circuit according to an embodiment of the present invention;

[0020] Figure 4 Shows internal waveforms of a switching detector circuit for switching detection signal generation according to an embodiment of the present invention;

[0021] Figure 5 Is a circuit of a level shifter having customized low - voltage (LV, Low Voltage) CMOS combinational logic before level conversion to a high - voltage (HV, High Voltage) domain according to an embodiment of the present invention;

[0022] Figure 6 Is a schematic diagram of a process - tracking feed - forward bias signal according to an embodiment of the present invention;

[0023] Figure 7 Is to regulate the VCC voltage level of the power supply rail in response to a burst - idle - burst condition;

[0024] Figure 8 Is a flowchart of the entire process of a circuit system according to an embodiment of the present invention;

[0025] Figure 9 Is the result of comparing VCC voltage levels with and without feed - forward according to an embodiment of the present invention;

[0026] Figure 10A Is the result of the VCC voltage level with process - tracking bias according to an embodiment of the present invention;

[0027] Figure 10B Is the result of the VCC voltage level without process - tracking bias according to an embodiment of the present invention; and

[0028] Figure 11 This is the result of the power supply rejection ratio (PSRR) capability on the feed-forward power rail according to an embodiment of the present invention. Detailed implementation manners

[0029] Although the present invention is described herein by way of examples using embodiments and illustrative drawings, those skilled in the art will recognize that the present invention is not limited to the embodiments of the described drawings and is not intended to represent the proportions of various components. Additionally, for ease of illustration, some components that may form part of the present invention may not be shown in some of the drawings, and such omissions do not in any way limit the described embodiments. It should be understood that the drawings and detailed description are not intended to limit the present invention to the specific forms disclosed, but rather the present invention covers all modifications, equivalents, and alternatives falling within the scope of the present invention defined by the appended claims. As used throughout the specification, the word "may" is used in a permissive sense (i.e., meaning having the possibility) rather than in a mandatory sense (i.e., meaning must). Additionally, unless otherwise mentioned, the word "a" or "an" means "at least one", and the word "plural" means "one or more". Furthermore, the terms and phrases used herein are for descriptive purposes only and should not be construed as limiting the scope. Languages such as "comprising", "including", "having", "containing", or "involving" and their variations are intended to be construed broadly and include the subject matter listed thereafter, equivalents, and additional unrecited subject matter, and are not intended to exclude other additives, components, wholes, or steps. Similarly, for applicable legal purposes, the term "comprising" is considered synonymous with the terms "including" or "containing". Any discussion of documents, acts, materials, devices, articles, etc. included in the specification is merely for providing the background of the present invention. There is no implication or indication that any or all of these matters form part of the prior art base or are common general knowledge in the field related to the present invention.

[0030] In the present disclosure, whenever a composition, element, or group of elements is preceded by the transitional phrase "comprising", it should be understood that we also contemplate the same composition, element, or group of elements where the transitional phrases "consisting of", "consisting", "selected from the group consisting of", "including", or "being" precede the recitation of the composition, element, or group of elements, and vice versa.

[0031] The present invention will now be described by way of various embodiments with reference to the accompanying drawings, in which the reference numerals used in the drawings correspond to the same elements throughout the description. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the following detailed description, numerical values and ranges are provided for various aspects of the described embodiments. These values and ranges are provided by way of example only and are not intended to limit the scope of the claims. Additionally, many materials are identified as being suitable for various aspects of the embodiments. These materials are provided by way of example only and are not intended to limit the scope of the invention.

[0032] Referring Figures 1 to 11 to the accompanying drawings shown, the present invention will now be described in more detail.

[0033] A first embodiment of the present invention relates to a circuit system 200 for regulating a power supply, comprising: a feedforward amplifier 100 including a clock generator 10 and a load circuit 20 for generating current during a functional demand; wherein the clock generator 10 includes a switching detector circuit 12 for generating a feedforward enable signal upon detecting a switched input clock signal; wherein the load circuit 20 includes a feedforward transmission gate for receiving the feedforward enable signal, a load circuit system 24, a variable bias voltage controller, and a level shifter 22 for controlling the level of the feedforward transmission gate. Figure 1 The feedforward amplifier 100 of the present invention is described in Figure 2 The clock signal during the generation of the feedforward enable signal is shown.

[0034] A second embodiment of the present invention relates to a process for regulating the power supply of a circuit system 200 using the feedforward amplifier 100 of the present invention, comprising the steps of: activating the feedforward transmission gate of the load circuit 20; detecting a switched input clock signal by the switching detector circuit 12; generating a feedforward enable signal when the switched input clock signal is detected, and deactivating the feedforward enable signal when the input clock signal is not switched.

[0035] According to an embodiment of the present invention, since the feedforward amplifier 100 is connected to a reference voltage tracker having the same bandgap voltage as the input voltage of the regulator, changes in the bandgap do not affect the performance and calibration of the feedforward circuit. This connection relationship is shown in Figure 8

[0036] According to an embodiment of the present invention, the circuit system 200 is a CMOS clock circuit. Additionally, the circuit system 200 provides a solution for the feedforward amplifier 100 that can counteract voltage drops and overshoots scaled with different process corners, thereby reducing area usage and calibration time. Figure 6 An overview of this configuration is shown in​

[0037] According to an embodiment of the present invention, the switching detector circuit 12 includes a delay unit for delaying signal propagation and managing synchronization between different clock domains, as Figure 3 shown. For example, as long as a logic "1" is generated from an "OR" gate between the phase 0 and 90 input clocks, the output of the switching detector circuit 12 will transition to logic "1" through a shorter "ON" path. The "OFF" path generated by the delay unit only drives the falling edge and pre-sets the internal node whenever the input clock is logic "1". This eliminates the risk of triggering a logic "false" signal of logic "0" if the delayed falling edge pairs with a logic "0" pulse of the "OR" gate output. Subsequently, a resulting switching detection signal is generated by combining the "ON" path for faster enabling and the "OFF" path for disabling, as Figure 4 shown.

[0038] According to an embodiment of the present invention, the level shifter 22 of the circuit system is a hybrid level shifter, including a combination of thin-gate transistors and thick-gate transistors for controlling the gates of the PMOS switches of the feed-forward transmission gates. The combinational logic is customized to be single-stage to reduce the total delay of the circuit, as Figure 5 shown.

[0039] According to an embodiment of the present invention, a switching input clock signal is detected by the following steps: based on an input clock transition signal; generating an output signal based on the transitioned signal, the output signal indicating the presence of the switching input clock. These steps generate an output signal representing the presence of the switching input clock and deactivate the feed-forward enable signal when the input clock does not switch.

[0040] Furthermore, in an embodiment of the present invention, the method further includes a level conversion from low voltage to high voltage when generating the feed-forward enable signal. The pull-down network for the high-voltage level shifter uses thin-gate NMOS to allow for faster conversion and lower delay. The low-voltage power supply is also used as the gate bias for the thin-gate NMOS to avoid electrical overloading of the thin-gate device when exposed to high voltage. The output stage also has a thin-gate NMOS pull-down assist, which acts as a parallel path to ground to accelerate the falling edge of the output signal. As a result, the on-time of the local feed-forward transmission gate PMOS can be significantly reduced.

[0041] Hereinafter, embodiments of the present invention will be provided for a more detailed explanation. Through these embodiments, the advantages of the present invention can be more easily understood and put into practice. However, it should be understood that the following embodiments do not limit the scope of the present invention in any way.

[0042] Circuit Description

[0043]

[0044]

[0045] Embodiment

[0046] Example 1: Feedforward implementation

[0047] In the context discussed subsequently, the desired characteristics are achieved by using a variable bias voltage to regulate the feedforward transfer gate, enabling rapid current provision when needed, as Figure 6 shown. This design choice addresses the delay in regulating the rail response to dynamic current demands, alleviating the burst-idle-burst condition that could otherwise distort the regulated power supply with significant voltage drops and overshoots. In essence, the feedforward mechanism meets all current requirements, allowing the feedforward amplifier to maintain its idle current state and ensuring stability in the regulated power rail without interruption.

[0048] The process tracking reference voltage is actively monitored on the feedforward amplifier 100, thereby eliminating the need to adjust the amplifier size in response to process variations. Refer to Figure 7 , where this architectural approach saves a significant amount of area that would otherwise be required to accommodate various current demands. It also relaxes the strict requirements on the regulator bandwidth performance. Additionally, Figure 7 it is emphasized that both the regulator and the process tracking reference utilize the same bandgap voltage as their input, effectively mitigating the impact of bandgap variations on the performance calibration of the feedforward circuit. Notably, it is shown that by using the feedforward amplifier 100, the voltage drop observed on the regulated rail in the "no feedforward" waveform is eliminated, resulting in a significant reduction from 80 mV to less than 5 mV, which represents a 16-fold reduction, as Figure 9 shown.

[0049] Furthermore, Figure 10A it is shown that in the case of incorporating the process tracking reference, the regulated power rail experiences variations within ±3 mV without having to size-adjust the changes to the feedforward amplifier 100. In contrast, in the absence of the process tracking bias, as Figure 10B shown, the VCC voltage level exhibits a change of approximately 180 mV from the fast corner to the slow corner, forcing the size of the feedforward amplifier 100 to increase by a factor of 20 to 30 times.

[0050] Example 2: PSRR capability on feedforward power rails

[0051] After incorporating the feedforward feature, a comprehensive evaluation is performed to assess the system's response to power supply variations, known as the power supply rejection ratio (PSRR). In this configuration, the PSRR depends on the size and voltage settings of the NMOS (a type of component used for current supply). As Figure 11As shown, the PSRR remains robust, maintaining at least -20 dB levels under various operating scenarios including fast, normal, or slow conditions.

[0052] Notably, unlike using a direct pull-up switch that does not inherently address the PSRR issue, this design avoids the need for many capacitors to handle the PSRR problem. This not only saves space but also prevents excessive strain on the internal regulator, thereby reducing the risk of instability. This approach highlights the advantageous aspects of the feed-forward design, emphasizing its improved PSRR performance and its ability to circumvent issues associated with other configurations.

[0053] The present invention overcomes the disadvantages of the prior art by providing a process for optimizing a high-speed CMOS clock circuit using a feed-forward regulated power supply. The optimization method of the present invention helps to counteract voltage drops and overshoots scaled with different process corners, thereby reducing area usage and calibration time.

[0054] Although embodiments of the present invention have been illustrated and described, it is obvious that the present invention is not limited to these embodiments. Many modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art without departing from the scope of the present invention as set forth in the claims.

Claims

1. A circuit system (200) for regulating power supply, characterized in that: A feedforward amplifier (100) comprising a clock generator (10), and a load circuit (20) for generating a current during a functional demand; Wherein, the clock generator (10) includes a switching detector circuit (12) for generating a feedforward enable signal when a switching input clock signal is detected; The load circuit (20) includes a feedforward transfer gate for receiving a feedforward enable signal, a load circuit system (24), a variable bias voltage controller, and a level converter (22) for controlling the feedforward transfer gate.

2. The circuit system (200) of claim 1, wherein: The feedforward amplifier (100) is connected to a reference voltage tracker having the same bandgap voltage as that of the regulator as an input voltage.

3. The circuit system (200) of claim 1, wherein: The circuit system is a CMOS clock circuit.

4. The circuit system (200) of claim 1, wherein: The switching detector circuit (12) includes a delay unit.

5. The circuit system (200) of claim 1, wherein: The level shifter (24) is a hybrid level shifter comprising a combination of thin gate transistors and thick gate transistors.

6. A method for regulating a power supply of a circuit system (200) using a feedforward amplifier (100) according to any one of claims 1 to 5, It is characterized by the following steps: activating a feedforward transfer gate of a load circuit (20); detecting a switching input clock signal by a switching detector circuit (12); generating a feedforward enable signal when a switching input clock signal is detected; as well as When the input clock signal is not switching, the feedforward enable signal is deactivated; When a feedforward enable signal is generated, the feedforward amplifier (100) generates a current.

7. The method according to claim 6, wherein: Detecting a switching input clock signal includes the following steps: Transition signal based on input clock; An output signal is generated based on the translated signal, the output signal indicating the presence of a switching input clock. 8 . The method of claim 6 , further comprising level shifting from a low voltage to a high voltage when generating the feedforward enable signal.

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