A dynamic control method and system for a power management chip based on hybrid modulation

Abstract

The application provides a power management chip dynamic control method and system based on hybrid modulation. Wherein, the method intercepts opcode sequence feature identifiers through a chip built-in instruction decoding unit, activates a current detection unit to collect a transient power supply loop power fluctuation curve; in a time sequence alignment module, aligns and associates the opcode identifiers with the power curve according to timestamps, and constructs a load behavior feature library; adjusts the magnetic flux control current through a driving circuit, so that the medium reaches a preset magnetic flux saturation degree before load transition; decomposes instruction stream segments, matches the instruction stream with the magnetic flux control current in waveform similarity, detects specific instruction combination modes; based on the detection results and the magnetic flux saturation degree, writes control parameters to the modulation logic unit, and switches the working state combination of the step-down and step-up hybrid conversion mode. The application improves the transient response speed and energy transmission efficiency of the power management chip in the video rendering burst load scene.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip dynamic control, and particularly relates to a power management chip dynamic control method and system based on hybrid modulation. BACKGROUND

[0002] When a mobile computing device performs a high dynamic load task, a power management system needs to respond to the processor from the idle state to the full load running in the millisecond level time. Such a scene requires the power chip to meet three core demands at the same time: accurately predicting the burst current demand triggered by the graphics processor instruction set; dynamically optimizing the transient energy transmission efficiency of the power conversion path; and maintaining the output voltage stable within the ±3% tolerance band to avoid rendering frame loss.

[0003] The current mainstream scheme adopts an adaptive PID control architecture based on load current feedforward, which dynamically adjusts the pulse width modulation frequency of the switching power supply by high-speed sampling the current change rate of the processor power supply loop and combining the pre-stored load-frequency response mapping table. When the rising edge of the current is detected to exceed the threshold, a multi-stage compensation mechanism is triggered: first, the future power consumption trend is predicted according to the historical load curve, then the output duty cycle of the PID controller is corrected by dynamically scaling the proportional coefficient, and finally the switching loss is reduced by optimizing the conduction timing of the synchronous rectifier in the step-down topology.

[0004] The response delay of the architecture is limited by the current sampling frequency and the PID calculation period. In the microsecond level load switching scene of the video rendering in which the vertex shader and the texture sampler work alternately, the output voltage will still have a transient drop. The fundamental defect lies in the complete decoupling of the power path control and the processor instruction set - the current feedforward signal only reflects the load change that has occurred, and cannot predict the calculation task sequence in the instruction pipeline, resulting in that the energy transmission optimization lags behind the actual load demand. At the same time, the fixed structure of the PID parameters cannot adapt to the nonlinear load transition characteristics in the rendering pipeline, and frequent duty cycle correction further aggravates the switching loss of the power transistor, causing the peak energy efficiency of the system to decrease. SUMMARY

[0005] The present application provides a power management chip dynamic control method and system based on hybrid modulation to solve the problem of insufficient transient response speed and energy transmission efficiency in the prior art.

[0006] In a first aspect, the present application provides a power management chip dynamic control method based on hybrid modulation, comprising:

[0007] The chip built-in instruction decoding unit synchronously intercepts the opcode sequence feature identifier in the operation code sequence in the continuous time window in the processor instruction pipeline, and activates the chip internal current detection unit to collect the transient power fluctuation curve of the processor power supply loop in the time window in parallel;

[0008] timestamping the operation code sequence identifier and the transient power fluctuation curve in the chip configuration timing alignment module, extracting the repeatedly occurring load change pattern feature group in the association result, and constructing a load behavior feature library containing a plurality of power consumption transition trajectories;

[0009] According to the prediction mode matching the current operation code segment in the load behavior feature library, the magnetic flux control current flowing through the energy storage medium of the magnetically coupled double winding is adjusted by the chip internal driving circuit, so that the energy storage medium enters a preset magnetic flux saturation degree before the load transition occurs.

[0010] The instruction stream segment currently executed by the decomposition processor is processed, and the instruction stream segment is waveform similarity matched with the adjusted magnetic flux control current in the chip mode matching unit. Based on the matching result, the specific instruction combination mode triggered by the video rendering operation is detected.

[0011] Based on the detection result of the specific instruction combination mode and the magnetic flux saturation degree of the energy storage medium, a control parameter is written to the chip modulation logic unit, and the working state combination of the mixed energy conversion mode of step-down and step-up is selectively switched according to the control parameter.

[0012] Optionally, according to the prediction mode matching the current operation code segment in the load behavior feature library, the magnetic flux control current flowing through the energy storage medium of the magnetically coupled double winding is adjusted by the chip internal driving circuit, so that the energy storage medium enters a preset magnetic flux saturation degree before the load transition occurs.

[0013] From the load behavior feature library, a prediction mode matching the current operation code segment is extracted, and the prediction mode is analyzed to obtain a magnetic flux saturation target value, a minimum current duration required to reach the magnetic flux saturation target value, and an expected load transition occurrence starting time point;

[0014] Query the magnetic circuit characteristic mapping table pre-stored in the chip non-volatile unit, and according to the magnetic flux saturation target value and the temperature parameter of the energy storage medium, output the corresponding direct current bias current value and current climbing rate parameter through the magnetic circuit characteristic mapping table;

[0015] Based on the starting time point and the minimum current duration, the current adjustment start time is calculated, and the stepwise current output sequence controlled by the current climbing rate parameter is triggered by the programmable delay unit of the chip internal driving circuit at the current adjustment start time;

[0016] The stepped current output sequence is applied to the main magnetic circuit control end of the magnetic coupling double-winding, the induced voltage differential value of the main magnetic circuit control end is monitored according to the direct current bias current value, and when the monitoring value is stable within a preset threshold range, it is determined that the energy storage medium reaches the target magnetic flux saturation degree.

[0017] Optionally, the instruction stream fragment currently executed by the decomposition processor is subjected to waveform similarity matching with the adjusted magnetic flux control current in the chip mode matching unit, and a specific instruction combination mode triggered by a video rendering operation is detected based on a matching result, including:

[0018] An instruction stream fragment currently executed by the processor is intercepted according to a fixed time window, a distribution position and an execution time sequence relationship of a graphics processing special operation code in the instruction stream fragment are identified, and an instruction event pulse sequence waveform is generated according to the distribution position and the execution time sequence relationship, wherein a vertex shader start operation code is marked as a positive pulse, and a texture sampling operation code is marked as a negative pulse.

[0019] An actual adjustment waveform of the adjusted magnetic flux control current in the fixed time window is synchronously acquired, and a turning point position and a turning direction exceeding a preset change rate threshold in the actual adjustment waveform are extracted.

[0020] The instruction event pulse sequence waveform is matched with the turning point position and the turning direction on a time axis, and when a time deviation between a vertex shader start pulse and a positive pulse turning point is less than a set threshold during the matching process, it is determined that the matching is successful.

[0021] When the number of successful matches reaches two consecutive video rendering frame periods, it is confirmed that the specific instruction combination mode triggered by the vertex shading intensive calculation and the texture sampling alternately is detected.

[0022] Optionally, based on a detection result of the specific instruction combination mode and a magnetic flux saturation degree of the energy storage medium, a control parameter is written to a chip modulation logic unit, and a working state combination of a step-down and step-up mixed energy conversion mode is selectively switched according to the control parameter, including:

[0023] An alternating time feature of a vertex shading intensive calculation stage and a texture sampling stage in the specific instruction combination mode is analyzed, and a mode switching time sequence parameter set is generated in combination with the magnetic flux saturation degree value.

[0024] According to an instruction density level of the vertex shading intensive calculation stage and the magnetic flux saturation degree value, a minimum voltage gain coefficient and a maximum switching frequency threshold required by a step-up mode are calculated.

[0025] Based on a storage access frequency of the texture sampling stage and a magnetic flux saturation degree decay rate, a duty cycle adjustment range and a synchronous rectification trigger condition of a step-down mode are limited.

[0026] write the integrated control parameter package to the chip modulation logic unit, through the integrated control parameter package, complete the calculation process of the minimum voltage gain coefficient and the maximum switching frequency threshold in the vertex shading intensive calculation stage, and switch to the defined process of the step-down mode in the texture sampling stage.

[0027] Optionally, the operation code sequence feature identifier is time-stamped and associated with the transient power fluctuation curve in the chip configured timing alignment module, the repeatedly appearing load change mode feature group in the associated result is extracted, and a load behavior feature library containing a multi-level power transition trajectory is constructed, including:

[0028] At each collection time, the operation code sequence feature identifier is marked with a corresponding timestamp, and the same timestamp is marked for the sampling points of the transient power fluctuation curve;

[0029] Based on the corresponding timestamp and the same timestamp, the associated section containing the operation code fragment combination and the power consumption change profile in the corresponding time period is generated by intercepting a continuous time period according to the video rendering instruction cycle;

[0030] In a plurality of video rendering instruction cycles, the associated section is compared, and when the same operation code fragment combination repeatedly appears during the comparison process, the load change mode feature group corresponding to the repeatedly appearing operation code fragment combination is extracted;

[0031] According to the amplitude value of the transition point sequence, the multi-level power transition trajectory is divided, and the operation code fragment combination and the multi-level power transition trajectory are stored in the load behavior feature library with a multi-level index structure.

[0032] Optionally, the instruction stream fragment currently executed by the processor is intercepted according to a fixed time window, the distribution position and execution timing relationship of the graphics processing dedicated operation code in the instruction stream fragment are identified, and the instruction event pulse sequence waveform is generated according to the distribution position and execution timing relationship, wherein the vertex shader start operation code is marked as a positive pulse, and the texture sampling operation code is marked as a negative pulse, including:

[0033] A fixed time window synchronized with the instruction cycle of the graphics processor is set, and an instruction stream fragment executed by the processor in the fixed time window is captured;

[0034] The first occurrence position of the vertex shader start operation code and the continuous distribution coordinates of the texture sampling operation code in the instruction stream fragment are identified by a hardware decoding unit, and the time interval sequence between operation codes is recorded to represent the execution timing relationship;

[0035] generating a baseline level at the start point of the fixed time window, generating a positive rectangular pulse when the first occurrence position is detected, wherein the pulse width is determined by the time interval sequence;

[0036] generating a negative rectangular pulse at the occurrence position of the continuous distribution coordinate, the start time of the negative rectangular pulse is dynamically offset according to the execution timing relationship, the pulse amplitude is proportional to the number of samplings, and the baseline level is maintained during the no-operation code period, and the positive rectangular pulse and the negative rectangular pulse constitute an instruction event pulse sequence waveform.

[0037] Optionally, the current adjustment start time is calculated based on the start time point and the minimum current duration, and a stepwise current output sequence controlled by the current ramp-up rate parameter is triggered at the current adjustment start time by a programmable delay unit of a chip internal driving circuit, including:

[0038] The start time point is taken as a reference, the minimum current duration is offset forward and a protection time margin is superimposed, and a current adjustment start time is calculated;

[0039] A countdown trigger signal of the current adjustment start time is set in the programmable delay unit, and the current ramp-up rate parameter is synchronously loaded to a staircase waveform generator;

[0040] When the countdown trigger signal is zeroed, a stepwise current output sequence is generated by the staircase waveform generator according to the current ramp-up rate parameter;

[0041] The stepwise current output sequence is output to a main magnetic circuit control end by a power amplification stage of a driving circuit, and a transient voltage suppression pulse is injected when each step is switched.

[0042] In a second aspect, the present application provides a hybrid modulation-based power management chip dynamic control system, including:

[0043] The intercepting module is configured to intercept, through a chip built-in instruction decoding unit, an operation code sequence feature identifier in a continuous time window in a processor instruction pipeline in parallel, and activate a chip internal current detection unit to collect a transient power fluctuation curve of a processor power supply loop in the time window;

[0044] The constructing module is configured to align and associate, in a timing alignment module configured by the chip, the operation code sequence feature identifier and the transient power fluctuation curve according to a time stamp, extract a repeatedly occurring load change mode feature group in an association result, and construct a load behavior feature library containing multiple power consumption transition tracks.

[0045] An adjusting module is configured to adjust, according to a prediction mode matched with a current operation code segment in the load behavior feature library, a magnetic flux control current flowing through an energy storage medium of a magnetic coupling double winding by a chip internal driving circuit, so that the energy storage medium enters a preset magnetic flux saturation degree before a load transition occurs.

[0046] A matching module is configured to decompose an instruction stream segment currently executed by a processor, perform waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in a chip mode matching unit, and detect a specific instruction combination mode triggered by a video rendering operation based on a matching result.

[0047] A switching module is configured to write, based on a detection result of the specific instruction combination mode and a magnetic flux saturation degree of the energy storage medium, a control parameter to a chip modulation logic unit, and selectively switch a working state combination of a mixed energy conversion mode of voltage reduction and voltage increase according to the control parameter.

[0048] In a third aspect, the present application provides a computing device, comprising a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component, and realize the dynamic control method of the power management chip based on the mixed modulation as described in the first aspect.

[0049] In a fourth aspect, the present application provides a computer storage medium, which stores a computer program; when the computer program is executed by a computer, the dynamic control method of the power management chip based on the mixed modulation as described in the first aspect is realized.

[0050] The application synchronously intercepts the opcode sequence feature identifier in the continuous time window in the processor instruction pipeline through the chip built-in instruction decoding unit, and activates the chip internal current detection unit to collect the transient power fluctuation curve of the processor power supply loop in the time window; in the chip configured time alignment module, the opcode sequence feature identifier is aligned and associated with the transient power fluctuation curve according to the time stamp, the repeatedly appearing load change mode feature group in the association result is extracted, and a load behavior feature library containing a multi-stage power transition track is constructed; according to the prediction mode matching the current opcode segment in the load behavior feature library, the magnetic flux control current flowing through the energy storage medium of the magnetic coupling double winding is adjusted through the chip internal driving circuit, so that the energy storage medium enters a preset magnetic flux saturation degree before the load transition occurs; the instruction stream segment currently executed by the processor is decomposed, the instruction stream segment is matched with the adjusted magnetic flux control current in the chip mode matching unit according to the waveform similarity, and the specific instruction combination mode triggered by the video rendering operation is detected based on the matching result; based on the detection result of the specific instruction combination mode and the magnetic flux saturation degree of the energy storage medium, a control parameter is written to the chip modulation logic unit, and the working state combination of the mixed energy conversion mode of step-down and step-up is selectively switched according to the control parameter.

[0051] The technical scheme of the application has the following beneficial effects:

[0052] The millisecond-level space-time synchronization of the processor instruction features and the physical state of the power supply loop is realized, and the original data basis for load behavior analysis is established; the multi-stage power transition track mode specific to the video rendering scene is extracted, and the decision basis for predicting the burst load is formed; the magnetic flux saturation degree of the magnetic coupling double winding energy storage medium is dynamically optimized according to the instruction feature prediction result, and the transient energy transmission capability is improved; the timing feature matching of the vertex shading / texture sampling instruction stream and the magnetic flux control current is performed, and the rendering pipeline stage switching time is accurately identified; the instruction mode and the magnetic circuit state parameter are coupled, the step-down-step-up conversion mode combination is adapted, and the energy efficiency ratio of different rendering stages is optimized.

[0053] Further, the prediction mode matching the current opcode is extracted from the load behavior feature library, the magnetic flux saturation target value, the minimum current duration and the load transition starting time point are analyzed, the temperature compensated DC bias current value and the climbing rate parameter are output by querying the magnetic circuit characteristic mapping table, the stepwise current sequence is triggered at the starting time point based on the time point calculation, and the magnetic flux saturation degree is verified by applying to the magnetic circuit control end and through the induced voltage differential value. The preventive closed-loop control of the magnetic coupling power path is realized, the energy storage medium accurately enters the target magnetic flux state before the video rendering burst load occurs, the transient voltage drop is suppressed, and the switching loss is reduced.

[0054] These aspects or other aspects of the application will be more apparent in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] Figure 1 A flow chart of a method for dynamic control of a power management chip based on hybrid modulation provided by the present application is shown;

[0057] Figure 2 A schematic diagram of the structure of a power management chip dynamic control system based on hybrid modulation provided by the present application is shown;

[0058] Figure 3 A schematic structural diagram of a computing device provided by the present application is shown. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0060] In some of the processes described in the specification and claims of this application and the above-mentioned figures, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to being different types.

[0061] While existing power management solutions employ load current feedforward and adaptive PID control architectures, their fundamental flaw lies in the complete decoupling of power path regulation from the processor instruction set. Current sampling signals can only capture load changes that have already occurred, but cannot predict the sequence of computational tasks about to be triggered in the instruction pipeline, such as the microsecond-level switch from vertex shader to texture sampling in video rendering. This causes energy transfer optimization to always lag behind actual demand. Furthermore, fixed-parameter PID control struggles to adapt to the nonlinear transition characteristics of the rendering pipeline, and frequent duty cycle corrections exacerbate switching losses, resulting in instantaneous output voltage drops and insufficient peak energy efficiency, a core pain point.

[0062] To solve the above problems, the application provides a power management chip dynamic control method based on instruction stream characteristics and magnetic circuit state cooperation, which is characterized by establishing a four-dimensional closed loop of processor instruction set-power consumption characteristics-magnetic coupling power path-modulation strategy. By decoding the operation code sequence of the graphics processor and synchronously correlating the transient power consumption waveform, a load behavior characteristic library dedicated to the video rendering scene is constructed. The load transition point is predicted by using the library, and the magnetic flux saturation of the magnetic coupling double-winding medium is dynamically adjusted, so that the energy transmission path enters an optimized state before the burst load occurs. Finally, the waveform matching of the instruction stream and the magnetic flux current accurately triggers the step-down-step-up mode switching. The method identifies the task sequence in advance through the opcode characteristics, responds in advance, dynamically adjusts the magnetic flux saturation to improve the transient energy transmission efficiency, and switches the conversion strategy based on the vertex / texture instruction combination mode to suppress voltage fluctuations. The voltage drop and energy efficiency decline caused by instruction decoupling in the prior art are fundamentally solved, and the power quality and system stability under high dynamic load scenes are guaranteed.

[0063] The technical solution of the application can be applied to the burst load scene of the notebook computer CPU / GPU.

[0064] The technical solutions in the embodiments of the application will be described clearly and completely in the embodiments of the application combined with the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the application.

[0065] Figure 1 A flowchart of a power management chip dynamic control method based on hybrid modulation is provided for the embodiments of the application, as shown in Figure 1 The method comprises the following steps.

[0066] 101, synchronously intercept the opcode sequence characteristic identifiers in the continuous time window in the processor instruction stream pipeline through the built-in instruction decoding unit of the chip, and activate the internal current detection unit of the chip to collect the transient power fluctuation curve of the processor power supply loop in the time window in parallel;

[0067] In the above scheme, the time window is a fixed time length segment synchronized with the rendering period of the graphics processor, which is used to intercept the time and space units of the instruction stream and power consumption data. The opcode sequence characteristic identifier is an encoding set for feature compression of the continuous operation codes in the instruction pipeline, which generates an 8-bit feature code by extracting the type, sequence and interval information of the video rendering dedicated instruction, reflecting the instruction combination rule. The transient power fluctuation curve is the current and time change trajectory obtained on the processor power supply loop at a sampling rate of 200 million times per second, which captures the microsecond-level current transition triggered by instruction execution.

[0068] In the embodiments of the present application, first, a fixed-length time window is automatically started by the instruction decoding unit built in the chip when a screen refresh signal (such as the rising edge of a vertical synchronization signal) is detected, and the window is synchronized with the rendering period of the graphics processor and used to simultaneously capture the instruction sequence and the power consumption data; for example, when the screen refresh signal triggers, the decoding unit immediately starts to continuously read the instructions in the processor instruction pipeline at a period of 2 microseconds.

[0069] Secondly, within the time window, the decoding unit scans the instruction stream, identifies the instruction types dedicated to video rendering (such as a start drawing instruction or a texture sampling instruction), and compresses the types, order and interval information of these consecutive instructions into a short 8-bit binary code according to the preset rules, which is called a feature identifier; for example, a start drawing instruction can be mapped to binary '01', and a texture sampling instruction is mapped to '10', thereby generating a feature code reflecting the combination rules of the instructions.

[0070] Then, the system activates the current detection unit in parallel, collects the current value on the processor power supply line at a sampling rate of 20 million times per second within the same time window, converts these analog current changes into digital waveforms, and particularly captures the transient events of the current sharp fluctuations (i.e. the microsecond-level transition of the current change rate exceeding 10 amperes per second); for example, when the texture sampling instruction is executed, it can cause the current to drop by 5 amperes within 100 nanoseconds, and here the change rate needs to be calculated: 100 nanoseconds equal to 0.1 microseconds, so the change rate is 5 amperes divided by 0.1 microseconds, equal to 50 amperes per second, which exceeds the threshold of 10 amperes per second, so it is recorded as a transient power fluctuation curve with a time stamp.

[0071] Finally, the system aligns the feature identifier and the corresponding power curve according to the time stamp accurate to nanoseconds, and writes them into adjacent storage areas in the memory to form a data packet associated with the instructions and the power consumption, ensuring that the subsequent modules can be accessed synchronously; for example, the feature identifier is stored in memory addresses 0x2000 to 0x2001, and the power curve is stored in 0x2002 to 0x2020, so that when the analysis module is called, the instruction features and power consumption changes can be directly associated. The whole process is closely linked from signal triggering to data storage, achieving efficient synchronization.102、In the timing alignment module configured in the chip, the operation code sequence feature identifier is aligned and associated with the transient power fluctuation curve according to the time stamp, the repeatedly occurring load change mode feature group in the association result is extracted, and a load behavior feature library containing multiple power transition tracks is constructed;

[0072] Optionally, step 102 can specifically include:

[0073] 1021. marking a corresponding time stamp for the operation code sequence feature identifier at each acquisition time, and marking the same time stamp for the sampling points of the transient power fluctuation curve;

[0074] 1022. based on the corresponding time stamp and the same time stamp, generating a correlation segment containing operation code segment combination and its corresponding power consumption change profile in a continuous time period by intercepting the video rendering instruction cycle;

[0075] 1023. comparing the correlation segment in a plurality of continuous video rendering instruction cycles, and when detecting the same operation code segment combination repeatedly appearing in the comparison process, extracting the load change mode feature group corresponding to the repeatedly appearing operation code segment combination;

[0076] 1024. dividing the multi-level power consumption transition trajectory according to the amplitude value of the transition point sequence, and storing the operation code segment combination and the multi-level power consumption transition trajectory into the load behavior feature library with a multi-level index structure.

[0077] In the above scheme, the time sequence alignment module is a chip internal hardware unit, which realizes the accurate matching of the operation code identifier and the power consumption curve time stamp through the nanosecond clock counter. The load change mode feature group is a set composed of the repeatedly appearing operation code combination and the triggered power consumption transition event, which reflects the periodic load law of the video rendering scene. The multi-level power consumption transition trajectory is a power consumption mutation path divided according to the amplitude, and the binding relationship of the operation code combination and the transition feature is stored. The operation code segment combination is an ordered set of the video rendering special instruction sequence in a fixed time period. The power consumption change profile is the form feature of the current value changing with time in the associated time period, including the rising slope, peak position and falling rate. The transition point sequence is a set of mutation points in the profile exceeding the set change rate threshold sorted by time, which marks the load state switching. The multi-level index structure is a storage architecture layered according to the transition amplitude, which supports fast retrieval of the trajectory through the operation code combination.

[0078] In the embodiment of the present application, when the chip captures the operation code feature identifier (i.e. the short code representing a specific graphics instruction combination) and the transient power fluctuation curve (i.e. the record of the rapid change of the power consumption of the processor), the primary task of the time sequence alignment module is to label them with a time label accurate to one billionth of a second (nanosecond), to ensure that each point on the identifier and the power consumption curve can strictly correspond in time; for example, when the system identifies an operation code combination representing "start drawing graphics" (such as internal code 0xC1), it will record the current time stamp (such as "125 nanoseconds") at the same moment, freeze and record the current current value (such as 28.6 amperes) at the same moment, and give it the same "125 nanoseconds" time label.

[0079] Then, the system cuts the instruction identifiers and power consumption data with timestamps into continuous segments based on the natural rhythm of screen refresh (e.g. 16.7 milliseconds per cycle), each segment containing a complete sequence of instructions (e.g. "start drawing, process texture, generate pixel points") and the complete shape of power consumption change (i.e. power consumption change profile) in a period of time.

[0080] Subsequently, the system continuously observes multiple screen refresh cycles (e.g. three consecutive cycles) to find the same instruction combination repeatedly appearing in these segments; whenever the same instruction combination is found to repeatedly appear in multiple cycles, the system checks the power consumption change profile corresponding to the instruction combination to find the points where the current suddenly changes drastically (i.e. the transition point where the current change rate exceeds 10 amperes per second), and records the time and current value of these mutation points; for example, if in three consecutive refresh cycles, the current suddenly increases by more than 25 amperes after 3.5 milliseconds and for a very short time (e.g. 100 nanoseconds), the system extracts the sequence of time points (e.g. [3.5001 milliseconds, 3.5001 milliseconds, 3.5001 milliseconds]) and the corresponding sequence of current values (e.g. [28 amperes, 27.9 amperes, 28.2 amperes]).

[0081] Finally, the system classifies the mutation point current values according to their range size (amplitude) (e.g. less than 10 amperes is classified as level 1, 10 to 30 amperes is classified as level 2, and greater than 30 amperes is classified as level 3), and then binds the repeatedly appearing instruction combination with the power consumption mutation trajectory of that level (e.g. amplitude around 25 amperes belongs to level 2 trajectory) it triggers, and stores it in an organized feature database; this database, like a multi-layer directory, can easily find the corresponding power consumption mutation level by instruction combination; for example, after binding the instruction combination "[0xC1, 0xD8]" (representing a specific sequence of graphics processing instructions) with the level 2 power consumption mutation trajectory, it is stored in the level 2 area of the database (e.g. address 0x5000-0x501F), and the system can know that when executing this instruction combination, the power consumption will usually experience a moderate mutation.

[0082] The overall scheme of step 102 above achieves accurate spatiotemporal association of instruction features and power consumption data through timestamp synchronization mechanism, extracts key transition features in repetitive load patterns based on video rendering frame cycles, and constructs a hierarchical index feature library with scene adaptability. This scheme breaks through the limitations of decoupling instructions and power consumption in traditional power control, establishes a prediction model from processor opcodes to energy transmission characteristics, provides high-precision decision basis for advanced optimization of magnetic circuit state, and significantly improves the dynamic response capability in burst load scenarios.

[0083] 103、According to the predicted mode matched with the current operation code segment in the load behavior characteristic library, the magnetic flux control current flowing through the energy storage medium of the magnetic coupling double winding is adjusted by the chip internal driving circuit, so that the energy storage medium enters a preset magnetic flux saturation degree before the load transition occurs.

[0084] Optionally, step 103 can specifically include the following steps:

[0085] 1031、Extract the predicted mode matched with the current operation code segment from the load behavior characteristic library, and analyze the predicted mode to obtain a magnetic flux saturation target value, a minimum current duration required to reach the magnetic flux saturation target value, and a starting time point of an expected load transition occurrence;

[0086] 1032、Query the magnetic circuit characteristic mapping table pre-stored in the chip non-volatile unit, and output corresponding direct current bias current value and current ramp rate parameter through the magnetic circuit characteristic mapping table according to the magnetic flux saturation target value and temperature parameter of the energy storage medium;

[0087] 1033、Based on the starting time point and the minimum current duration, calculate the current adjustment start time, and trigger the stepwise current output sequence controlled by the current ramp rate parameter at the current adjustment start time through the programmable delay unit of the chip internal driving circuit;

[0088] Wherein, step 1033 can specifically include the following process: taking the starting time point as the reference, offsetting the minimum current duration and superimposing a protection time margin, calculating the current adjustment start time; Set the countdown trigger signal of the current adjustment start time in the programmable delay unit, and load the current ramp rate parameter to the ladder waveform generator at the same time; When the countdown trigger signal is zero, generate a stepwise current output sequence through the ladder waveform generator according to the current ramp rate parameter; The stepwise current output sequence is output to the main magnetic circuit control end through the power amplifier stage of the driving circuit, and a transient voltage suppression pulse is injected when each step is switched.

[0089] 1034、Apply the stepwise current output sequence to the main magnetic circuit control end of the magnetic coupling double winding, and monitor the induced voltage differential value of the main magnetic circuit control end according to the direct current bias current value, when the monitoring value is stable within a preset threshold range, it is determined that the energy storage medium reaches the target magnetic flux saturation degree.

[0090] In the above scheme, the prediction mode is a set of magnetic circuit control parameters associated with the opcode fragment retrieved from the load behavior feature library, containing the target magnetic state and time constraints. The magnetic flux saturation target value is the proportion of the relative maximum capacity of the magnetic flux in the magnetically coupled double-winding medium, which determines the transient energy transmission capability. The stepped current output sequence is a current output waveform that gradually increases in amplitude at fixed time intervals, used for progressive magnetization of the magnetic circuit. The magnetic circuit characteristic mapping table is a two-dimensional lookup table that stores the correspondence between magnetic flux saturation and current parameters at different temperatures, calibrated by experiments. The programmable delay unit is an internal configurable timer of the chip, supporting the generation of trigger signals with nanosecond-level precision. The induced voltage differential value is the rate of change of the voltage across the magnetic coupling winding, reflecting the physical quantity of the magnetic flux accumulation speed.

[0091] In the embodiments of the present application, first, when the chip needs to handle an impending load change (load transition), it will use a historical experience (load behavior feature library) to predict and prepare in advance. The specific process is as follows: First, the chip will check the currently running instruction combination fragment (for example, a combination of an opcode named "vertex shader opcode 0xC1" and a texture sampling code named "0xD8"), just like using a specific key to find a matching record in the experience library. After finding the matching record, the chip will interpret three key information from it: the first is the target magnetic flux saturation (i.e. the "full" degree that the energy storage medium hopes to reach, such as the record showing that it needs to reach 85% saturation, which is represented by the value 0x55), the second is the shortest power-on time required to reach this saturation (such as the record showing that it needs to be powered on for at least 200 microseconds, represented by the value 0x00C8), and the third is the predicted starting time point of the load change (such as predicting that it will occur after 300 microseconds, represented by the value 0x0000012C).

[0092] Next, the chip will combine the current temperature situation (such as reading the internal temperature sensor value of the chip as 65°C, represented by the value 0x41) to form a query code (0x55+0x41=0x5541) by splicing the target saturation value (85%) obtained earlier. The chip will use this query code to query a pre-stored internal reference table (magnetic circuit characteristic mapping table) that records the required current parameters at different saturation and temperature. Through this query, the chip can obtain two specific parameters: one is the required DC current reference value (DC bias current value), and the other is the speed at which the current needs to rise (current ramp rate parameter).

[0093] Then, the chip needs to calculate when to start adjusting the current to ensure that the energy storage medium reaches the target saturation just before the predicted load change occurs. The calculation method is: subtract the shortest time required to reach saturation (200 microseconds) from the predicted load change start time point (300 microseconds), and additionally subtract a reserved safety buffer time (such as 20 microseconds), so as to obtain the absolute time point at which the current adjustment must start (calculation example: 300 microseconds-200 microseconds-20 microseconds=80 microseconds). A programmable timer (programmable delay unit) inside the chip will be set to this calculated time point (80 microseconds later) to send a start signal. When this timer counts down to zero, it will trigger a current waveform generator (step waveform generator) to generate a current output sequence that increases step by step like a staircase (for example, this sequence may contain 5 steps, each step increases the current by 0.7 amperes, and each step maintains for 2 microseconds) according to the current rise speed parameter obtained by looking up the table previously. At the same time, in order to reduce the interference during current switching, a short transient voltage suppression pulse is applied each time the current step jumps. This current step sequence is applied to the control coil of the energy storage medium (the control end of the main magnetic circuit of the magnetically coupled double-winding).

[0094] Finally, in order to confirm whether the energy storage medium has really reached the target saturation, the chip will continuously monitor the rate of change of the induced voltage across the control coil (induced voltage differential value). When the monitored voltage change rate becomes very small and stable within a preset small fluctuation range (such as three consecutive measurements, each with an interval of 150 nanoseconds, the voltage change rate remains within ±5 millivolts per second), the chip determines that the energy storage medium has successfully reached the preset target magnetic flux saturation and is ready to cope with the upcoming load transition.

[0095] The overall scheme of step 103 above realizes the advanced closed-loop regulation of the energy storage medium state through precise mapping of instruction characteristics to magnetic circuit parameters and temperature adaptive compensation. Combined with time-accurate step charging and physical quantity feedback verification, it breaks through the limitations of traditional power management in responding to load mutations after the fact, significantly enhances the timeliness and stability of energy transmission in video rendering and other burst load scenarios, and provides reliable protection for hybrid modulation strategies.

[0096] 104, decompose the instruction stream segment currently executed by the processor, perform waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in the chip mode matching unit, and detect a specific instruction combination mode triggered by the video rendering operation based on the matching result;

[0097] Optionally, step 104 can specifically include the following steps:

[0098] 1041、according to the distribution position and the execution time sequence relationship, generating an instruction event pulse sequence waveform, wherein a vertex shader start operation code is marked as a positive pulse and a texture sampling operation code is marked as a negative pulse;

[0099] The step 1041 can specifically include the following processes: setting a fixed time window synchronized with a GPU instruction cycle, capturing an instruction stream fragment executed by a processor in the fixed time window; identifying, by a hardware decoding unit, a first occurrence position of a vertex shader start operation code and a continuous distribution coordinate of a texture sampling operation code in the instruction stream fragment, and recording a time interval sequence between the operation codes to represent an execution time sequence relationship; generating a baseline level at a starting point of the fixed time window, generating a positive rectangular pulse when the first occurrence position is detected, wherein a pulse width is determined by the time interval sequence; generating a negative rectangular pulse at the occurrence position of the continuous distribution coordinate, wherein a starting time of the negative rectangular pulse is dynamically offset according to the execution time sequence relationship, a pulse amplitude is proportional to a sampling number, and a no-operation code period maintains the baseline level, and the positive rectangular pulse and the negative rectangular pulse constitute an instruction event pulse sequence waveform.

[0100] 1042、synchronously acquiring an actual adjustment waveform of the adjusted magnetic flux control current in the fixed time window, and extracting a turning point position and a turning direction of the actual adjustment waveform that exceed a preset change rate threshold;

[0101] 1043、matching the instruction event pulse sequence waveform with the turning point position and the turning direction on a time axis, and determining that the matching is successful when a time deviation between a vertex shader start pulse and a turning point of the positive pulse in the matching process is less than a set threshold.

[0102] 1044、when a number of times of successful matching reaches two continuous video rendering frame periods, confirming that a specific instruction combination mode triggered by vertex shader intensive calculation and texture sampling alternation is detected.

[0103] In the above scheme, the instruction event pulse sequence waveform is a voltage pulse signal with a time sequence feature converted from a graphics processing operation code, and reflects a dynamic waveform of an instruction execution sequence. The turning point position and the turning direction are space-time coordinates of a mutation point with a change rate exceeding a set threshold in a current waveform, and mark a magnetic circuit state switching direction, wherein a positive direction is magnetic charging acceleration and a negative direction is demagnetization starting. The fixed time window is a collection unit locked with a GPU rendering clock, and ensures that a time-space reference of instructions and currents is uniform. The change rate threshold is a threshold value for determining a current mutation, and filters normal fluctuations of a magnetic circuit.

[0104] In the embodiments of the present application, firstly, through step 1041, a fixed time interval is set to capture the instruction stream fragment being executed by the processor, just like intercepting a small piece of code execution record; then, in these fragments, the positions and sequences of special instruction types related to graphics processing are identified, such as when the instruction of starting a vertex shader is detected, it is marked as an upward jumping voltage signal, and when the instruction of texture sampling is detected, it is marked as a downward jumping voltage signal, and the width of these signals is determined according to the time interval between the instructions, and finally a voltage waveform reflecting the dynamic changes of the instructions is formed, which is similar to a high-low pulse sequence on a time line; for example, in a 2 microsecond time window, the system scans three vertex instructions and five texture instructions, according to the time points of the instructions, the first vertex instruction generates a +3V pulse at time 0.1 microsecond, the width is based on the instruction execution period such as 0.5 microsecond, and at the same time each texture instruction generates a -2V pulse with a width of 50 nanoseconds, and the other idle time remains 0V, thus a regular pulse curve is synthesized.

[0105] Next, through step 1042, the actual change waveform of the magnetic flux control current adjusted in the same time interval is obtained at the same time, which is like measuring the fluctuation of the current; the current waveform is analyzed, the change rate of adjacent sampling points is calculated, the current difference between two consecutive points is divided by the time interval, and the position points whose change rate exceeds the preset limit value are found, which are the turning points, the change direction upward is positive, indicating that the current increases rapidly, and the change direction downward is negative, indicating that the current decreases rapidly; for example, using a high-precision sampler to sample the current value every 50 nanoseconds, 40 data points are obtained in a 2 microsecond window, and after calculating the change rate, two turning points are found: the first point is at time 0.3 microsecond with a change rate of +20A / microsecond, which exceeds the threshold of 15A / microsecond, and is marked as a positive turning point; the second point is at time 1.5 microsecond with a change rate of -18A / microsecond, and is marked as a negative turning point.

[0106] Then, through step 1043, the generated instruction pulse waveform is matched with the current turning points on the time axis, and it is checked whether the pulse point of the vertex instruction occurs at a time point close to the current positive turning point, if the time deviation of the two is less than the set tolerance value, it is determined that the single matching is successful; for example, on the time axis, the rising edge of the first vertex pulse is taken as the reference zero point, such as the vertex pulse at 0.1 microsecond, and the closest current positive turning point at 0.3 microsecond, the time difference is calculated as 0.2 microsecond, but the system only tolerates a difference ≤100 nanoseconds to be judged as successful, so this time does not match; in another example, if the pulse is at 0.4 microsecond and the turning point is at 0.35 microsecond, the difference is 50 nanoseconds, which is less than 100 nanoseconds, so a matching flag is generated; for the entire time window, the matching state of all vertex pulses is verified one by one, and only when all the vertex pulses match, the overall matching is confirmed.

[0107] Finally, the number of successful matches is counted by step 1044, and according to the continuous requirements of the video rendering period, only when the number of successful matches reaches a certain number within a set frame period, it is confirmed that the pattern of vertex shading and texture sampling instruction alternation is detected; for example, in a 60Hz video rendering, every 16.7 milliseconds, 8 detection windows are divided, and at least 15 successful matches are required within 33.4 milliseconds of two consecutive frames to trigger confirmation; the specific calculation is as follows: 16 windows for two frames, 16 actual successful matches, more than 15 threshold, then mark that the pattern is detected.

[0108] The overall scheme of step 104 described above dynamically associates the space-time characteristics of instruction flow and magnetic current change, accurately identifies the calculation-storage load alternation pattern specific to the video rendering scene. This scheme breaks through the limitations of decoupling software instructions and hardware states in traditional power control, establishes a collaborative perception mechanism from processor operation to energy transmission behavior, provides high-reliability decision basis for dynamic switching of hybrid modulation strategy, and significantly improves the energy efficiency adaptation accuracy and system stability in burst load scenarios.

[0109] 105、Based on the detection result of the specific instruction combination pattern and the magnetic flux saturation of the energy storage medium, write control parameters to the chip modulation logic unit, and selectively switch the working state combination of the buck-boost hybrid energy conversion mode according to the control parameters.

[0110] Optionally, step 105 can specifically include the following steps:

[0111] 1051, analyze the alternating time characteristics of the vertex shading intensive calculation stage and the texture sampling stage in the specific instruction combination pattern, and generate a pattern switching time sequence parameter set combined with the magnetic flux saturation value;

[0112] 1052, according to the instruction density level of the vertex shading intensive calculation stage and the magnetic flux saturation value, calculate the minimum voltage gain coefficient and the maximum switching frequency threshold required for the boost mode;

[0113] 1053, based on the storage access frequency of the texture sampling stage and the magnetic flux saturation decay rate, limit the duty cycle adjustment range and synchronous rectification trigger condition of the buck mode;

[0114] 1054, write an integrated control parameter package to the chip modulation logic unit, and through the integrated control parameter package, complete the calculation process of the minimum voltage gain coefficient and the maximum switching frequency threshold in the vertex shading intensive calculation stage, and at the same time, switch to the limited process of the buck mode in the texture sampling stage.

[0115] In the above scheme, the mode switching timing parameter set is a collection of time constraints including boost / buck mode activation time window, transition protection interval, etc., dynamically generated by the instruction phase feature and the magnetic flux state. The minimum voltage gain coefficient is the amplification multiple of the output voltage relative to the input voltage in boost mode, dynamically adjusted according to the calculated load demand. The synchronous rectification trigger condition is the judgment rule for the control body diode to conduct in buck mode, preventing inductive current from flowing backward. The instruction density level is the load intensity level (low / medium / high) divided by the number of vertex operation codes appearing in a unit of time. The magnetic flux saturation decay rate is the percentage of magnetic flux decline per unit of time, reflecting the speed of energy release. The comprehensive control parameter package is a data structure integrating timing / electrical / protection parameters, supporting direct loading of hardware registers.

[0116] In the embodiments of the present application, first, the time characteristics of different stages in the detected specific instruction mode are analyzed, such as the start and end time points of vertex intensive calculation and texture sampling, and the time interval difference between them is calculated. At the same time, the time parameter group for controlling the power mode switching is generated in combination with the magnetic flux saturation of the energy storage medium. For example, when it is found that the vertex calculation stage starts at 200 microseconds, the texture sampling stage starts at 390 microseconds, and the interval between the two stages is 190 microseconds; at this time, if the magnetic flux saturation reaches 85%, which exceeds the threshold of 80%, the system will extend the end time of the vertex stage by 10 microseconds to 400 microseconds, and set a 20-microsecond protection buffer period, and finally output the complete time control parameters: the boost mode time window is 200-400 microseconds, the buck mode time window is 420-510 microseconds, the mode switching buffer period is 20 microseconds, and the 400-420 microseconds. Subsequently, the minimum voltage boost multiple required by the boost mode is calculated according to the instruction intensity of the vertex calculation stage, that is, the frequency of instruction occurrence per unit time and the current magnetic flux saturation, that is, the lowest multiple of the output voltage amplification of the input voltage, and the highest working frequency limit of the switching circuit. For example, in the vertex calculation stage, 9 instructions per microsecond are detected, which belongs to the high density level, and the voltage gain coefficient is 1.28 according to the preset rule, that is, the voltage needs to be boosted by 28%; at the same time, the current magnetic flux saturation is 85%, the basic frequency is 1MHz, the unit adjustment amount is 0.1MHz / %, and the maximum switching frequency threshold is calculated: 1MHz+(85-80)×0.1=1.5MHz, which guarantees the safe frequency of the power supply. At the same time, the memory access frequency in the texture sampling stage is counted, that is, the number of memory accesses per unit time, and the switching time proportion range of the buck mode and the special conditions for preventing current backflow are determined in combination with the magnetic flux saturation decline rate. For example, the memory is accessed 12 times per second in the sampling stage, so the switching time proportion lower limit is 12x2%=24%; at the same time, it is detected that the magnetic flux decreases at a rate of 5% / second, which exceeds the threshold of 4% / second, and the access frequency meets the standard, and the synchronous rectification trigger condition is set as "only when the inductance current is zero is the conduction allowed", which avoids the damage of the circuit caused by current backflow. Finally, all the parameters are integrated and packaged by 1054, written into the chip power control unit, and the power supply mode is automatically switched according to the instruction stage. For example, the time window parameters, voltage gain 1.28, frequency upper limit 1.5MHz, switching time proportion 24%, and current zero trigger condition are packaged into a 32-byte data packet; the data packet is written into the power control register address 0x5000 through the internal bus at a high speed, and when the processor starts vertex calculation, the boost mode is automatically enabled, the voltage is amplified by 1.28 times, the frequency does not exceed 1.5MHz, when switching to texture sampling, the buck mode is automatically converted, the switching conduction time is not less than 24%, and the protection mechanism is activated when the current is zero.

[0117] Here is a complete example for steps 101~105:

[0118] When a laptop's graphics processor (GPU) is performing a high-load task such as rendering a 4K video, the chip executes a smart power management process to smoothly handle the dramatic fluctuation of current.

[0119] The whole process starts with monitoring the GPU's current workload: upon the arrival of the start signal of screen refresh (the rising edge of vertical sync signal), the chip starts a very short 2-microsecond timing window to "snap" the instruction that the GPU is processing at that moment. For example, at the 3.5-millisecond mark, it identifies a critical "draw object shape" instruction (vertex shader opcode 0xC1), and gives this instruction group a specific identification code 0x5A. Meanwhile, the chip's internal current meter (using a tiny 50-micro-ohm resistor to measure the main power supply line) captures the current's sudden surge from 12.8 amperes to 41.3 amperes, with a change rate exceeding 30 million amperes per second, and the chip records the waveform of this dramatic current jump.

[0120] Then comes the experience database building: the chip tags both the identified instruction code 0x5A and the monitored 41.3-ampere current peak with the same time marker (3,500,000 nanoseconds). It analyzes the data of the consecutive three video frame periods (about 3.5 milliseconds to 5.0 milliseconds) and finds a pattern: every time that specific instruction code 0x5A appears, 100 nanoseconds later, the current will definitely increase dramatically by more than 25 amperes, with a magnitude between 25 and 40 amperes. Thus, the chip stores this "see 0x5A instruction code, 100 nanoseconds later, there will be a large current demand" experience pattern, along with the current change magnitude information, into its "behavior characteristic database".

[0121] The third step is prediction and preparation in advance: when the chip sees that specific 0x5A opcode again in the current instruction stream, it immediately retrieves the corresponding experience data from the "behavior feature library": it needs to let the internal energy storage material reach an "85% full" state (saturation 85%) in advance, which requires a minimum of 180 microseconds of continuous power (minimum current time 180 ps), and predicts that this large current demand will occur 200 microseconds later (expected transition point TS = 200 ps). Considering that the current temperature of the chip is 70°C, it queries an internal storage reference table (magnetic path mapping table) and obtains two key parameters: a 3.8 ampere reference current (bias current 3.8 A) needs to be provided, and the current rise rate needs to be set to 0.8 million amperes per second (climb rate 0.8 A ps). The chip calculates the optimal timing to start adjusting the current: the predicted large current demand point (200 microseconds later) minus the minimum time required for preparation (180 microseconds) minus a 20-microsecond safety buffer, the result is that it must start immediately (0 microseconds later). The current generator inside the chip is immediately triggered to generate a current that increases step by step like a staircase: starting from 1.9 amperes, increasing by 0.8 amperes each step (because the rate is 0.8 A ps), so the second step is 2.7 amperes (1.9 + 0.8), the third step is 3.5 amperes (2.7 + 0.8), the fourth step is 4.3 amperes (3.5 + 0.8), and the fifth step reaches 5.1 amperes (4.3 + 0.8). The chip continuously monitors the voltage change rate across the energy storage material coil, and when it finds that this change rate becomes very slow and stable within a small range of plus or minus 4 millivolts per second, it confirms that the energy storage material has successfully reached the pre-set 85% "full" state.

[0122] The fourth step is to verify the prediction model: at a later time period (10.0 ms to 12.0 ms), the chip disassembles the instruction stream and identifies that the "draw shape" instruction (0xC1) generates a +3V control pulse at 10.2 ms, and the "apply texture" instruction (0xD8) generates a -2V pulse at 11.1 ms. At the same time, it captures that the current of the control energy storage material experiences a sharp upward turn (slope +28 A / μs, 28 million amperes per second increase) at 10.2001 ms and a sharp downward turn (slope -19 A / μs, 19 million amperes per second decrease) at 11.1003 ms. The chip checks the time matching: the predicted "draw shape" pulse is at 10.2000 ms, and the actual current turn is at 10.2001 ms, with only a 100 nanosecond difference, which meets the chip's error standard (≤100 ns). After continuously analyzing multiple video frame periods (total duration 33.4 ms), the success rate of the high degree of time matching between this instruction pulse and the sharp current turn reaches 94%, thus confirming that the chip's previous prediction that the alternating execution of the "draw shape" and "apply texture" instructions will trigger a specific current pattern is reliable.

[0123] Finally, dynamic optimization of power supply: the chip analyzes the "draw shape" phase (occurring 200 microseconds to 380 microseconds after the screen refresh signal) in detail: the instruction is very intensive (900 million instructions per second) during this period, and the energy storage material maintains a "full" state of 87%. The chip calculates that it needs to increase the voltage gain by 26% (boost gain 1.26) during this phase, but limits the frequency of power switching to no more than 620 kHz (switching frequency limit 620 kHz). In the subsequent "apply texture" phase (380 microseconds to 500 microseconds after the refresh signal): access to storage is very frequent (1,400 million times per second), and the "full" level of the energy storage material decreases at a rate of 5.3% per second (magnetic flux decay rate 5.3% / μs). Therefore, the chip sets the minimum ratio of power output during this phase to no less than 28% (duty cycle lower limit 28%), and requires that the power supply state be switched at the moment when the current is zero (synchronous rectification condition "current zero crossing"). The chip packages all these optimization parameters (such as boost period: 200-380 μs, and drop period: 380-500 μs, as well as specific gain values, frequency upper limit, minimum output ratio, and synchronous switching flag) and sends them to the control module responsible for power regulation at the precise moment of 200 microseconds after the screen refresh signal. In this way, during the "draw shape" phase, the power system stabilizes in the boost voltage mode, working at a fixed frequency of 620 kHz per second; and during the "apply texture" phase, it automatically switches to the drop voltage mode and intelligently adjusts the power output ratio between 28% and 80% according to actual needs. This dynamic adjustment mechanism ensures that the GPU is both efficient and stable in power supply during high-intensity rendering.

[0124] The application realizes preventive dynamic regulation of the power management chip in the video rendering burst load scene through deep coordination of instruction features and magnetic circuit state. It breaks through the passive response limitation of traditional schemes to the load change that has occurred, establishes a closed-loop control chain from processor opcode analysis to energy transmission path optimization: based on instruction-level load prediction, the state of the magnetic coupling medium is optimized in advance, the rendering pipeline stage is accurately identified through instruction-current waveform matching, and finally the dynamic adaptation of mixed modulation strategy and computing task is realized. This scheme significantly improves the transient response speed and energy transmission efficiency, effectively suppresses voltage fluctuations, and ensures the system stability and energy efficiency balance in high dynamic load scenarios.

[0125] Figure 2 A structure diagram of a dynamic control system of a power management chip based on mixed modulation is provided for the embodiment of the application, as shown in Figure 2 The system comprises:

[0126] The intercepting module 31 is used to synchronize and intercept opcode sequence feature identifiers in a continuous time window in the processor instruction pipeline through the chip built-in instruction decoding unit, and activate the chip internal current detection unit to collect the transient power fluctuation curve of the processor power supply loop in the time window in parallel;

[0127] The construction module 32 is used to align and associate the opcode sequence feature identifiers with the transient power fluctuation curve in the time stamp in the chip configured timing alignment module, extract the repeatedly appearing load change mode feature group in the association result, and construct a load behavior feature library containing multiple power transition tracks;

[0128] The adjustment module 33 is used to adjust the magnetic flux control current flowing through the energy storage medium of the magnetic coupling double-winding through the chip internal drive circuit according to the prediction mode matching the current opcode segment in the load behavior feature library, so that the energy storage medium enters a preset magnetic flux saturation degree before the load transition occurs;

[0129] The matching module 34 is used to decompose the instruction stream segment currently executed by the processor, and perform waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in the chip mode matching unit, and detect the specific instruction combination mode triggered by the video rendering operation based on the matching result;

[0130] The switching module 35 is used to write control parameters to the chip modulation logic unit based on the detection result of the specific instruction combination mode and the magnetic flux saturation degree of the energy storage medium, and selectively switch the working state combination of the mixed energy conversion mode of step-down and step-up according to the control parameters.

[0131] Figure 2 The dynamic control system of the power management chip based on mixed modulation can performFigure 1 The implementation principle and technical effects of the dynamic control method of the power management chip based on hybrid modulation according to the embodiment are not described again. The specific manner in which each module and unit in the dynamic control system of the power management chip based on hybrid modulation according to the embodiment performs operations has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0132] In one possible design, Figure 2 The dynamic control system of the power management chip based on hybrid modulation according to the embodiment can be implemented as a computing device, such as a computer. Figure 3 As shown, the computing device can include a storage component 41 and a processing component 42.

[0133] The storage component 41 stores one or more computer instructions, wherein the one or more computer instructions are called and executed by the processing component 42.

[0134] The processing component 42 is configured to perform the above Figure 1 The embodiment provides a dynamic control method of a power management chip based on hybrid modulation.

[0135] The processing component 42 can include one or more processors to execute computer instructions to complete all or part of the steps in the above method. Of course, the processing component can also be one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components, for executing the above method.

[0136] The storage component 41 is configured to store various types of data to support the operation of the terminal. The storage component can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0137] Of course, the computing device can also include other components, such as an input / output interface, a display component, a communication component, etc.

[0138] The input / output interface provides an interface between the processing component and the peripheral interface module, which can be an output device, an input device, etc.

[0139] The communication component is configured to facilitate wired or wireless communication between the computing device and other devices, etc.

[0140] Wherein, the computing device can be a physical device or an elastic computing host provided by a cloud computing platform, at this time the computing device can be referred to as a cloud server, and the processing component, the storage component and the like can be a basic server resource rented or purchased from the cloud computing platform.

[0141] The embodiment of the application further provides a computer storage medium, which stores a computer program, and the computer program can realize the above-mentioned Figure 1 The embodiment shown in the figure is a dynamic control method of a power management chip based on hybrid modulation.

[0142] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-mentioned system, device and unit can refer to the corresponding processes in the foregoing method embodiments, and will not be described here.

[0143] The device embodiments described above are only schematic, wherein the units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment scheme. Those skilled in the art can understand and implement without creative labor.

[0144] Through the description of the foregoing embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software and necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, server, or network device, etc.) execute the method described in each embodiment or some part of the embodiment.

[0145] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the application, and not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the application.

Claims

1. A dynamic control method for a power management chip based on hybrid modulation, characterized in that: include: The chip's built-in instruction decoding unit synchronously intercepts the opcode sequence feature identifier within a continuous time window in the processor's instruction pipeline, and simultaneously activates the chip's internal current detection unit to collect the transient power consumption fluctuation curve of the processor's power supply circuit within the time window; In a timing alignment module configured in the chip, the opcode sequence feature identifier is associated with the transient power consumption fluctuation curve according to timestamp alignment, a load change pattern feature group that appears repeatedly in the association result is extracted, and a load behavior feature library containing multi-level power consumption transition trajectories is constructed; According to the prediction pattern matching the current operation code fragment in the load behavior feature library, the magnetic flux control current flowing through the energy storage medium of the magnetically coupled dual winding is adjusted by the chip internal drive circuit so that the energy storage medium reaches a preset magnetic flux saturation before the load transition occurs; Decomposing an instruction stream segment currently executed by the processor, performing waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in a chip pattern matching unit, and detecting a specific instruction combination pattern triggered by a video rendering operation based on the matching results; Based on the detection result of the specific instruction combination mode and the magnetic flux saturation of the energy storage medium, writing control parameters to the chip modulation logic unit, and selectively switching the working state combination of the buck and boost hybrid energy conversion modes according to the control parameters; The method comprises: adjusting the magnetic flux control current flowing through the energy storage medium of the magnetically coupled dual-winding by the internal driving circuit of the chip according to the prediction pattern matching the current operation code segment in the load behavior feature library, so that the energy storage medium reaches a preset magnetic flux saturation before the load transition occurs. Extracting a prediction pattern matching the current operation code segment from the load behavior feature library, parsing the prediction pattern to obtain a magnetic flux saturation target value, a minimum current duration required to achieve the magnetic flux saturation target value, and a start time point at which a load transition is expected to occur; querying a magnetic circuit characteristic mapping table pre-stored in a non-volatile unit of the chip, and outputting a corresponding DC bias current value and current ramp rate parameter through the magnetic circuit characteristic mapping table according to the magnetic flux saturation target value and the temperature parameter of the energy storage medium; Calculating a current regulation start time based on the starting time point and the minimum current duration, and triggering a step-type current output sequence controlled by the current ramp rate parameter at the current regulation start time through a programmable delay unit of an internal chip driving circuit; The stepped current output sequence is applied to the main magnetic circuit control end of the magnetically coupled dual winding, and the induced voltage differential value of the main magnetic circuit control end is monitored according to the DC bias current value. When the monitored value is stable within a preset threshold range, it is determined that the energy storage medium has reached the target magnetic flux saturation.

2. The method according to claim 1, characterized in that The processor decomposes an instruction stream segment currently executed by the processor, performs waveform similarity matching between the instruction stream segment and the adjusted magnetic flux control current in a chip pattern matching unit, and detects a specific instruction combination pattern triggered by a video rendering operation based on the matching result, including: intercepting an instruction stream segment currently being executed by the processor according to a fixed time window, identifying the distribution position and execution timing relationship of graphics processing-specific opcodes in the instruction stream segment, and generating an instruction event pulse train waveform based on the distribution position and execution timing relationship, wherein the vertex shader activation opcode is marked as a positive pulse and the texture sampling opcode is marked as a negative pulse; Synchronously acquiring an actual regulation waveform of the flux control current after regulation within the fixed time window, and extracting a turning point position and a turning direction exceeding a preset rate of change threshold in the actual regulation waveform; Matching the command event pulse sequence waveform with the turning point position and turning direction on the time axis, and determining that the match is successful when the time deviation between the vertex shader start pulse and the positive pulse turning point during the matching process is less than a set threshold; When the number of successful matches reaches two consecutive video rendering frame cycles, it is confirmed that a specific instruction combination pattern triggered by the alternation of vertex shading intensive calculations and texture sampling is detected.

3. The method according to claim 1, characterized in that The detection result of the specific instruction combination mode and the magnetic flux saturation of the energy storage medium are used to write control parameters to the chip modulation logic unit, and the working state combination of the step-down and step-up hybrid energy conversion modes is selectively switched according to the control parameters, including: Analyze the alternating time characteristics of the vertex shading intensive calculation phase and the texture sampling phase in the specific instruction combination mode, and combine the magnetic flux saturation value to generate a mode switching timing parameter set; Calculating a minimum voltage gain coefficient and a maximum switching frequency threshold required for a boost mode according to the instruction density level of the vertex shading intensive calculation phase and the magnetic flux saturation value; Based on the memory access frequency and the magnetic flux saturation decay rate in the texture sampling phase, the duty cycle adjustment range and the synchronous rectification triggering condition of the buck mode are limited; A comprehensive control parameter package is written to the chip modulation logic unit, and the calculation process of the minimum voltage gain coefficient and the maximum switching frequency threshold is completed through the comprehensive control parameter package in the vertex shading intensive calculation stage, while the limitation process of switching to the buck mode in the texture sampling stage is completed.

4. The method according to claim 1, wherein The timing alignment module configured in the chip aligns and associates the operation code sequence feature identifier with the transient power consumption fluctuation curve according to the timestamp, extracts the load change pattern feature group that appears repeatedly in the association result, and constructs a load behavior feature library containing multi-level power consumption transition trajectories, including: Marking a corresponding timestamp for the operation code sequence feature identifier at each acquisition moment, and synchronously marking the same timestamp for the sampling points of the transient power consumption fluctuation curve; Based on the corresponding timestamp and the same timestamp, intercepting continuous time periods according to video rendering instruction cycles to generate associated segments including opcode segment combinations and power consumption change profiles within corresponding time periods; Comparing the associated segments in a plurality of consecutive video rendering instruction cycles, and when the same opcode segment combination is detected to be repeated during the comparison process, extracting a load change pattern feature group corresponding to the repeated opcode segment combination; The multi-level power consumption transition trajectory is divided according to the amplitude value of the transition point sequence, and the operation code segment combination and the multi-level power consumption transition trajectory are bound and stored in a load behavior feature library with a multi-level index structure.

5. The method according to claim 2, characterized in that The method includes intercepting an instruction stream segment currently executed by the processor according to a fixed time window, identifying the distribution position and execution timing relationship of graphics processing-specific opcodes in the instruction stream segment, and generating an instruction event pulse sequence waveform based on the distribution position and execution timing relationship, wherein the vertex shader activation opcode is marked as a positive pulse and the texture sampling opcode is marked as a negative pulse, including: Setting a fixed time window synchronized with a graphics processor instruction cycle, and capturing instruction stream segments executed by the processor within the fixed time window; Identifying, by a hardware decoding unit, the first occurrence position of a vertex shader activation opcode and the continuously distributed coordinates of texture sampling opcodes in the instruction stream fragment, and recording a time interval sequence between the opcodes to characterize an execution timing relationship; generating a baseline level at a starting point of the fixed time window and generating a positive rectangular pulse when the first occurrence position is detected, wherein the pulse width is determined by the time interval sequence; A negative rectangular pulse is generated at the appearance position of the continuous distribution coordinates, the starting time of the negative rectangular pulse is dynamically offset according to the execution timing relationship, the pulse amplitude is proportional to the number of sampling times, the baseline level is maintained during the period without operation code, and the positive rectangular pulse and the negative rectangular pulse constitute an instruction event pulse sequence waveform.

6. The method according to claim 1, characterized in that The step of calculating the current regulation start time based on the starting time point and the minimum current duration, and triggering the stepped current output sequence controlled by the current ramp rate parameter at the current regulation start time through a programmable delay unit of an internal chip driving circuit, includes: Taking the starting time point as a reference, the minimum current duration is shifted forward and a protection time margin is added to calculate the current regulation start time; Setting the countdown trigger signal for the current regulation start-up moment in the programmable delay unit, and synchronously loading the current climbing rate parameter to the step waveform generator; When the countdown trigger signal returns to zero, a step current output sequence is generated by the step waveform generator according to the current climbing rate parameter; The step-type current output sequence is output to the main magnetic circuit control end through the power amplifier stage of the driving circuit, and a transient voltage suppression pulse is injected when each step is switched.

7. A power management chip dynamic control system based on hybrid modulation, used to execute a power management chip dynamic control method based on hybrid modulation according to any one of claims 1 to 6, characterized in that: include: An interception module is used to synchronously intercept the opcode sequence feature identifier within a continuous time window in the processor instruction pipeline through the chip's built-in instruction decoding unit, and in parallel activate the chip's internal current detection unit to collect the transient power consumption fluctuation curve of the processor power supply circuit within the time window; A construction module is used to align and associate the operation code sequence feature identifier with the transient power consumption fluctuation curve according to timestamps in a timing alignment module configured by the chip, extract the load change pattern feature group that repeatedly appears in the association result, and construct a load behavior feature library containing multi-level power consumption transition trajectories; a regulating module, configured to regulate, based on a prediction pattern in the load behavior feature library that matches the current operation code segment, the magnetic flux control current flowing through the energy storage medium of the magnetically coupled dual windings through an internal chip driving circuit, so that the energy storage medium reaches a preset magnetic flux saturation before a load transition occurs; a matching module configured to decompose instruction stream segments currently executed by the processor, perform waveform similarity matching between the instruction stream segments and the adjusted flux control current in a chip pattern matching unit, and detect specific instruction combination patterns triggered by video rendering operations based on the matching results; A switching module is used to write control parameters to the chip modulation logic unit based on the detection results of the specific instruction combination mode and the magnetic flux saturation of the energy storage medium, and selectively switch the working state combination of the buck and boost hybrid energy conversion modes according to the control parameters.

8. A computing device, characterized in that It includes a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component to implement a dynamic control method for a power management chip based on hybrid modulation as described in any one of claims 1 to 6.

9. A computer storage medium, characterized in that A computer program is stored, and when the computer program is executed by a computer, a dynamic control method for a power management chip based on hybrid modulation according to any one of claims 1 to 6 is implemented.

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