A light-emitting chip reliability screening method and system

Abstract

The present application discloses a method and system for screening the reliability of light-emitting chips, which uses a composite stress action of temperature cycling and dynamic current to accelerate chip aging, collects multiple optical and electrical performance parameter change values ​​in real time as failure parameters, calculates the failure risk index based on these parameters, and compares it with the failure risk threshold to determine whether the chip is qualified. In addition, the PCA algorithm is used to analyze key degradation characteristics, construct a failure-sensitive parameter set, and dynamically optimize and update the failure risk threshold using a transfer learning framework. The present application significantly shortens the chip reliability screening cycle and improves production efficiency; multi-parameter monitoring and nonlinear degradation path capture can more quickly and accurately identify reliability defects in chips; at the same time, through the application of the PCA algorithm and the transfer learning framework, the accuracy and reliability of the screening are further improved, providing strong support for chip design and optimization.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device testing technology, and in particular to a light-emitting chip reliability screening method and system. Background Art

[0002] In the field of LiDAR technology, reliability screening of the Vertical-Cavity Surface-Emitting Laser (VCSEL) chips used in LiDAR is crucial. As a core sensor in fields such as autonomous driving and robotic navigation, LiDAR's performance stability is directly related to system safety and reliability. As a key component of LiDAR, the long-term performance stability of VCSEL chips is essential for ensuring the proper functioning of LiDAR. Therefore, early reliability screening is a key step in ensuring chip quality.

[0003] However, existing high-temperature aging tests have significant drawbacks. They use only a single temperature stress to induce chip aging, resulting in long test cycles and inability to meet the rapid screening requirements of large-scale LiDAR production. Furthermore, single-stress testing struggles to simulate the complex environments chips face in real-world operating conditions and cannot effectively simulate complex failure mechanisms such as material interface failure caused by temperature cycling shock, leading to discrepancies between test results and actual usage.

[0004] Furthermore, traditional VCSEL chip screening methods rely primarily on fixed thresholds for electro-optical performance parameters, such as the optical power attenuation rate. However, VCSEL chip failure results from the coupling of multiple physical fields: optical, electrical, and thermal. Traditional single-parameter threshold methods cannot capture nonlinear degradation paths, making it difficult to quickly identify potential reliability defects in the chip, posing a risk to the long-term stable operation of LiDAR. Summary of the Invention

[0005] The purpose of this application is to provide a light-emitting chip reliability screening method and system, which can improve the above-mentioned problems.

[0006] The embodiment of the present application is implemented as follows:

[0007] In a first aspect, the present application provides a light-emitting chip reliability screening method, comprising the following steps:

[0008] A composite stress mode of temperature cycling and dynamic current is used to perform aging tests on the light-emitting chip to be tested.

[0009] During the aging test, at least two optical performance parameter change values ​​and / or electrical performance parameter change values ​​of the light-emitting chip to be tested are collected in real time as failure parameters;

[0010] Calculating a failure risk index of the light-emitting chip to be tested based on the failure parameter;

[0011] The failure risk index and the failure risk threshold are compared. If the failure risk index is greater than or equal to the failure risk threshold, the light-emitting chip to be tested is judged to be unqualified; if the failure risk index is less than the failure risk threshold, the light-emitting chip to be tested is judged to be qualified.

[0012] It can be understood that the main innovation of this application lies in proposing a reliability screening method for light-emitting chips (such as VCSEL chips). Through the combined stress of temperature cycling and dynamic current, the chip aging process is accelerated, and the changes in multiple optical and electrical performance parameters are collected in real time to calculate the failure risk index. This method can simulate the complex environment faced by chips under actual working conditions, effectively stimulate the potential defects of the chip through composite stress, and make the screening process closer to actual usage. Using this light-emitting chip reliability screening method, the screening cycle for qualified light-emitting chips is significantly shortened to 15% to 20% of traditional methods, thereby improving production efficiency. Secondly, through multi-parameter monitoring and nonlinear degradation path capture, reliability defects in the chip can be identified more quickly and accurately, ensuring the long-term stable operation of systems such as lidar and reducing the safety risks caused by chip failure.

[0013] In an optional embodiment of the present application, the composite stress action mode of temperature cycling and dynamic current includes: adjusting the ambient temperature of the light-emitting chip to be tested according to a preset temperature cycling strategy, and applying a dynamic current to the light-emitting chip to be tested according to a preset dynamic current application strategy.

[0014] In an optional embodiment of the present application, the preset temperature cycling strategy includes adjusting the ambient temperature of the light-emitting chip under test according to a preset temperature cycling range, a preset number of temperature cycles, and a preset temperature adjustment rate. The preset temperature cycling range, the preset number of temperature cycles, and the preset temperature adjustment rate are determined based on research on temperature environments in actual application scenarios of the light-emitting chip under test and thermal stability test data of the light-emitting chip under test, and according to the experience of those skilled in the art.

[0015] In an optional embodiment of the present application, the dynamic current application strategy includes: using a pulse current superimposed on a DC bias current to form a composite current and applying it to the light-emitting chip to be tested.

[0016] In an optional embodiment of the present application, the failure parameters include at least two of the following: the wavelength drift of the light-emitting chip to be tested; the change rate of the near-field light spot divergence angle of the light-emitting chip to be tested; the series resistance growth rate of the light-emitting chip to be tested; and the change in quantum efficiency of the light-emitting chip to be tested.

[0017] The wavelength drift of the light-emitting chip to be tested is closely related to the degradation of the quantum well structure inside the light-emitting chip, and indicates the temperature sensitivity of the active area. The degradation of the quantum well structure inside the chip will cause the temperature sensitivity of the active area to change, which in turn causes the output laser wavelength to change. By accurately measuring the wavelength of the laser output by the chip and comparing it with the initial wavelength, the wavelength drift can be obtained. The specific collection method may include: using a high-precision spectrum analyzer to perform spectral analysis on the laser output by the chip at different aging stages and accurately measure its wavelength. The wavelength measured at each stage is calculated with the initial wavelength to obtain the wavelength drift.

[0018] The rate of change of the near-field light spot divergence angle of the light-emitting chip to be tested, and the sensitivity of the rate of change of the near-field light spot divergence angle to reflecting damage to the optical resonant cavity of the chip. Damage to the optical resonant cavity of the light-emitting chip will affect the propagation characteristics of the laser, causing changes in the near-field light spot divergence angle. By monitoring the changes in the near-field light spot divergence angle, the damage to the optical resonant cavity of the chip can be reflected. The specific acquisition method may include: using a high-resolution light spot analyzer to image and analyze the near-field light spot output by the chip. During the aging test, the divergence angle of the near-field light spot is measured regularly, and the ratio of the difference between two adjacent measurement results to the previous measurement result is calculated to obtain the rate of change of the near-field light spot divergence angle.

[0019] The series resistance growth rate of the light-emitting chip to be tested is related to the ohmic contact degradation. Ohmic contact degradation will increase the series resistance of the chip. By measuring the series resistance of the chip at different aging stages and calculating its growth rate, the degree of degradation of the ohmic contact can be evaluated. Specific collection methods may include: using a four-probe test method or a volt-ampere characteristic test method to measure the series resistance of the chip. Before the aging test, the initial series resistance of the chip is measured first. During the aging process, the series resistance of the chip is measured regularly, and the ratio of the difference between the current series resistance and the initial series resistance to the initial series resistance is calculated to obtain the series resistance growth rate.

[0020] The quantum efficiency of the light-emitting chip to be tested changes, and the quantum efficiency characterizes the radiative recombination efficiency. Quantum efficiency characterizes the radiative recombination efficiency, that is, the ability of the chip to convert photons generated by the recombination of electron-hole pairs into output lasers. The performance degradation of the chip will affect the quantum efficiency. By measuring the change in quantum efficiency, the change in the radiative recombination efficiency of the chip can be evaluated. The specific collection method may include: using an integrating sphere and an optical power meter to measure the output light power of the chip, and using a current source to measure the injected current of the chip. According to the definition of quantum efficiency, the quantum efficiency of the chip is obtained by calculating the ratio of the output light power to the injected current. During the aging test, the quantum efficiency of the chip is measured regularly, and the difference between the current quantum efficiency and the initial quantum efficiency and the ratio of the initial quantum efficiency are calculated to obtain the quantum efficiency change.

[0021] Understandably, this application utilizes more dimensional failure parameters (such as wavelength drift, rate of change of near-field spot divergence angle, series resistance growth rate, and quantum efficiency change) for screening and evaluation. This advantage lies in its ability to more comprehensively and accurately reflect chip performance degradation. Multi-parameter monitoring can capture chip performance under different failure mechanisms, such as quantum well structure degradation, optical resonant cavity damage, ohmic contact degradation, and changes in radiative recombination efficiency, thereby more quickly and accurately identifying potential reliability defects. This approach improves screening accuracy and efficiency, providing a strong guarantee for the long-term stable operation of systems such as LiDAR.

[0022] In an optional embodiment of the present application, the calculating the failure risk index of the light-emitting chip to be tested based on the failure parameter includes:

[0023] A characteristic matrix of failure parameters is established based on the failure parameters:

[0024] ;

[0025] in, represents the feature matrix, represents the wavelength drift of the light-emitting chip to be tested, represents the rate of change of the near-field light spot divergence angle of the light-emitting chip to be tested, represents the series resistance growth rate of the light-emitting chip to be tested, Represents the change in quantum efficiency of the light-emitting chip to be tested;

[0026] The failure risk index of the light-emitting chip to be tested is calculated based on the characteristic matrix according to the following formula:

[0027] ;

[0028] in, represents the failure risk index, A first characteristic weight coefficient representing the wavelength shift amount, The second characteristic weight coefficient representing the rate of change of the near-field light spot divergence angle, The third characteristic weight coefficient representing the series resistance growth rate, The fourth characteristic weight coefficient representing the change in quantum efficiency, represents the time decay factor, Represents time.

[0029] In an optional embodiment of the present application, the first feature weight coefficient, the second feature weight coefficient, the third feature weight coefficient, and the fourth feature weight coefficient are all inferred based on the Bayesian hyperparameter tuning algorithm using historical failure data of the same model chip of the light-emitting chip to be tested.

[0030] In an optional embodiment of the present application, before calculating the failure risk index, the light-emitting chip reliability screening method also includes: collecting the failure parameters and corresponding actual usage time of the same model chips of the light-emitting chip to be tested at different aging stages to form a first historical failure database; based on the first historical failure database, using a preset mathematical model to fit the value of the time attenuation factor.

[0031] In an optional embodiment of the present application, the failure risk threshold is a failure risk threshold dynamically optimized and updated based on a transfer learning framework; before comparing the failure risk index and the failure risk threshold, the light-emitting chip reliability screening method further includes: collecting the failure parameters of the same type of chips of the light-emitting chips to be tested produced in different batches to form a second historical failure database; using a machine learning algorithm to learn the second historical failure database and transfer learning the failure parameters of other related types of chips to form a failure risk threshold prediction model; setting the failure risk threshold of the light-emitting chip to be tested through the failure risk threshold prediction model.

[0032] It can be understood that, on the one hand, dynamically optimizing and updating the failure risk threshold based on a transfer learning framework can fully integrate historical failure parameters of the same chip model from different batches, as well as transfer learning failure parameters from other related chip models, to form a failure risk threshold prediction model, which can then be used to set the failure risk threshold for the light-emitting chip under test. This approach dynamically adjusts the threshold based on historical failure data, effectively addressing the model generalization problem caused by batch process variations, enabling the screening method to better adapt to the characteristics of different chip batches, and improving the accuracy and reliability of screening. On the other hand, transfer learning, such as transferring the failure modes of automotive-grade 905nm VCSELs to industrial-grade 850nm devices, can share failure knowledge from different but related devices, providing more reference information for industrial-grade devices. This enhances the model's ability to identify failure risks in different scenarios, improves the robustness and comprehensiveness of predictions, and ultimately improves the overall effectiveness of light-emitting chip reliability screening.

[0033] In an optional embodiment of the present application, the light-emitting chip reliability screening method further includes: analyzing key degradation features corresponding to the failure parameters through a principal component analysis (PCA) algorithm, and constructing a failure sensitive parameter set based on the key degradation features.

[0034] It can be understood that this application uses the PCA algorithm to analyze the key degradation characteristics corresponding to the failure parameters and constructs a failure-sensitive parameter set based on this. This approach has significant beneficial effects. PCA can extract the main components in the data, remove noise and redundant information, and make the screening process more focused on the parameters that have the greatest impact on chip reliability. By constructing a failure-sensitive parameter set, potential reliability defects in the chip can be identified more quickly and accurately, improving screening efficiency. At the same time, this method also helps to deeply understand the mechanism of chip failure and provide strong support for subsequent chip design and optimization.

[0035] In a second aspect, the present application discloses a light-emitting chip reliability screening system, comprising: a central control system, a temperature cycling system, a dynamic current application power supply, a failure parameter acquisition system, and a failure analysis module;

[0036] The central control system is configured to control the temperature cycle system and the dynamic current application power supply, and perform an aging test on the light-emitting chip to be tested by adopting a composite stress action mode of temperature cycle and dynamic current;

[0037] The failure parameter acquisition system is configured to acquire at least two optical performance parameter change values ​​and / or electrical performance parameter change values ​​of the light-emitting chip to be tested in real time during the aging test as failure parameters;

[0038] The failure analysis module is configured to calculate a failure risk index of the light-emitting chip to be tested based on the failure parameters; compare the failure risk index with a failure risk threshold dynamically optimized and updated based on a transfer learning framework; and if the failure risk index is greater than or equal to the failure risk threshold, judge that the light-emitting chip to be tested is unqualified; and if the failure risk index is less than the failure risk threshold, judge that the light-emitting chip to be tested is qualified.

[0039] In an optional embodiment of the present application, the composite stress action mode of temperature cycling and dynamic current includes: adjusting the ambient temperature of the light-emitting chip to be tested according to a preset temperature cycling strategy, and applying a dynamic current to the light-emitting chip to be tested according to a preset dynamic current application strategy.

[0040] In an optional embodiment of the present application, the preset temperature cycle strategy includes: adjusting the ambient temperature of the light-emitting chip to be tested according to a preset temperature cycle range, a preset number of temperature cycles and a preset temperature adjustment rate; the dynamic current application strategy includes: using a pulse current superimposed on a DC bias current to form a composite current and apply it to the light-emitting chip to be tested.

[0041] In an optional embodiment of the present application, the failure parameters include at least two of the following: the wavelength drift of the light-emitting chip to be tested; the change rate of the near-field light spot divergence angle of the light-emitting chip to be tested; the series resistance growth rate of the light-emitting chip to be tested; and the change in quantum efficiency of the light-emitting chip to be tested.

[0042] In an optional embodiment of the present application, the failure analysis module is specifically configured to perform the following steps: establishing a feature matrix of failure parameters based on the failure parameters:

[0043] ;

[0044] in, represents the feature matrix, represents the wavelength drift of the light-emitting chip to be tested, represents the rate of change of the near-field light spot divergence angle of the light-emitting chip to be tested, represents the series resistance growth rate of the light-emitting chip to be tested, Represents the change in quantum efficiency of the light-emitting chip to be tested;

[0045] The failure risk index of the light-emitting chip to be tested is calculated based on the characteristic matrix according to the following formula:

[0046] ;

[0047] in, represents the failure risk index, A first characteristic weight coefficient representing the wavelength shift amount, The second characteristic weight coefficient representing the rate of change of the near-field light spot divergence angle, The third characteristic weight coefficient representing the series resistance growth rate, The fourth characteristic weight coefficient representing the change in quantum efficiency, represents the time decay factor, Represents time.

[0048] In an optional embodiment of the present application, the first feature weight coefficient, the second feature weight coefficient, the third feature weight coefficient, and the fourth feature weight coefficient are all inferred based on the Bayesian hyperparameter tuning algorithm using historical failure data of the same model chip of the light-emitting chip to be tested.

[0049] In an optional embodiment of the present application, before calculating the failure risk index, the failure analysis module is specifically further configured to collect the failure parameters and corresponding actual usage time of the same model chip of the light-emitting chip to be tested at different aging stages to form a first historical failure database; based on the first historical failure database, a preset mathematical model is used to fit the value of the time attenuation factor.

[0050] In an optional embodiment of the present application, the failure risk threshold is a failure risk threshold dynamically optimized and updated based on a transfer learning framework; the failure analysis module is specifically further configured to collect the failure parameters of the same type of chips of the light-emitting chip to be tested produced in different batches to form a second historical failure database; a machine learning algorithm is used to learn the second historical failure database and transfer learning of the failure parameters of other related types of chips to form a failure risk threshold prediction model; the failure risk threshold of the light-emitting chip to be tested is set by the failure risk threshold prediction model.

[0051] In an optional embodiment of the present application, the failure analysis module is further configured to analyze key degradation features corresponding to the failure parameters through a component algorithm, and construct a failure sensitive parameter set according to the key degradation features.

[0052] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, optional embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 This is a flow chart of a light-emitting chip reliability screening method provided by the present application;

[0055] Figure 2 This is a structural diagram of a light-emitting chip reliability screening method system provided in this application. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0057] First, as Figure 1As shown, the present application provides a light-emitting chip reliability screening method, which includes the following steps S1 to S4. Among them, S1, S2, etc. are only step identifiers, and the execution order of the method is not necessarily in ascending order. For example, step S2 can be executed first and then step S1. This application does not impose any restrictions.

[0058] S1. Perform aging test on the light-emitting chip to be tested using a composite stress mode of temperature cycling and dynamic current.

[0059] In an optional embodiment of the present application, the composite stress action mode of temperature cycling and dynamic current includes: adjusting the ambient temperature of the light-emitting chip to be tested according to a preset temperature cycling strategy, and applying a dynamic current to the light-emitting chip to be tested according to a preset dynamic current application strategy.

[0060] In an optional embodiment of the present application, the preset temperature cycling strategy includes adjusting the ambient temperature of the light-emitting chip under test according to a preset temperature cycling range, a preset number of temperature cycles, and a preset temperature adjustment rate. The preset temperature cycling range, the preset number of temperature cycles, and the preset temperature adjustment rate are determined based on research into temperature environments in actual application scenarios of the light-emitting chip under test and thermal stability test data of the light-emitting chip under test, and based on the experience of those skilled in the art.

[0061] For example, when conducting reliability screening for VCSEL chips used in lidar (LiDAR), based on actual application scenario temperature environment research and combined with chip material thermal stability test data, a temperature cycle range of -40°C to 125°C can be set, with five cycles and a ramp rate of ≥ 20°C / min. LiDAR is widely used in autonomous vehicles, drones, robotics, and other fields, where the chips are exposed to a wide range of ambient temperatures. When starting a car outdoors in cold winter weather, the external ambient temperature can drop to -40°C or even lower; while local temperatures near the engine compartment or after prolonged operation can rise to around 125°C. By conducting temperature research in actual use scenarios and setting a temperature cycle range of -40°C to 125°C, we can maximize the simulation of the extreme temperature environments the chip may face in real-world applications, ensuring that test results are highly relevant to actual application conditions. Furthermore, in real-world applications, temperature fluctuations can be rapid and drastic. For example, if a car moves from a cold environment to a parking lot in direct sunlight within a short period of time, the chip temperature will rise rapidly. Setting the heating and cooling rate to ≥20℃ / min can simulate this rapid temperature change, accelerate the aging process of the chip during rapid temperature changes, and expose potential defects earlier.

[0062] This temperature cycling range screening, which closely mirrors actual applications, can effectively identify chips with unstable performance or potential defects under extreme temperature conditions, improving their reliability in real-world applications and reducing the risk of chip failure due to temperature fluctuations. Rapid temperature ramping can shorten test cycles and improve testing efficiency. Furthermore, by accelerating the aging process, performance degradation or failure of chips under rapidly changing temperatures can be detected earlier, enabling timely improvements and optimizations and reducing post-market quality risks.

[0063] In an optional embodiment of the present application, the dynamic current application strategy includes: using a pulse current superimposed on a DC bias current to form a composite current and applying it to the light-emitting chip to be tested.

[0064] For example, when conducting reliability screening of VCSEL chips used in lidar, a pulse current with a duty cycle of 30% to 80% can be superimposed with a bias DC of 0.8×Ith to 1.2×Ith based on the pulse width and chip characteristics to form a composite current that is applied to the light-emitting chip to be tested.

[0065] It can be understood that this dynamic current loading method can more accurately evaluate the performance and reliability of the chip in actual work. By simulating the actual working current, it is possible to discover problems such as performance degradation and heat generation that may occur in the chip under dynamic current drive, and to optimize and improve them in advance, thereby improving the stability and life of the chip in actual applications. In addition, during the manufacturing and use of the chip, there may be some interface defects, such as active area degradation, oxide layer cracking, process degradation, solder joint fatigue, etc. These defects may not appear immediately under normal working conditions, but under the combined effect of dynamic current and temperature changes, their development will be accelerated. The current fluctuations and heat changes generated by the dynamic current loading method will generate additional stress on the chip interface, causing interface defects to appear earlier.

[0066] S2. In the aging test, at least two optical performance parameter change values ​​and / or electrical performance parameter change values ​​of the light-emitting chip to be tested are collected in real time as failure parameters.

[0067] In an optional embodiment of the present application, the failure parameters include at least two of the following: the wavelength drift of the light-emitting chip to be tested; the rate of change of the near-field light spot divergence angle of the light-emitting chip to be tested; the growth rate of the series resistance of the light-emitting chip to be tested; and the change in the quantum efficiency of the light-emitting chip to be tested.

[0068] The wavelength drift of the light-emitting chip under test is closely related to the degradation of the chip's internal quantum well structure and indicates the temperature sensitivity of the active region. Degradation of the chip's internal quantum well structure can alter the temperature sensitivity of the active region, leading to changes in the output laser wavelength. The wavelength drift can be determined by accurately measuring the wavelength of the chip's output laser and comparing it with the initial wavelength. Specific acquisition methods include using a high-precision spectrum analyzer to perform spectral analysis on the chip's laser output at different aging stages and accurately measure its wavelength. The wavelength measured at each stage is then compared with the initial wavelength to determine the wavelength drift.

[0069] The rate of change of the near-field light spot divergence angle of the light-emitting chip under test, and the sensitivity of the rate of change of the near-field light spot divergence angle to damage to the chip's optical resonant cavity. Damage to the optical resonant cavity of the light-emitting chip will affect the propagation characteristics of the laser, causing changes in the near-field light spot divergence angle. By monitoring changes in the near-field light spot divergence angle, the damage to the chip's optical resonant cavity can be reflected. Specific acquisition methods may include: using a high-resolution light spot analyzer to image and analyze the near-field light spot output by the chip. During the aging test, the divergence angle of the near-field light spot is measured regularly, and the ratio of the difference between two adjacent measurement results to the previous measurement result is calculated to obtain the rate of change of the near-field light spot divergence angle.

[0070] The growth rate of the series resistance of the light-emitting chip to be tested, and the growth rate of the series resistance are related to the degradation of the ohmic contact. The degradation of the ohmic contact will increase the series resistance of the chip. By measuring the series resistance of the chip at different aging stages and calculating its growth rate, the degree of degradation of the ohmic contact can be evaluated. Specific collection methods may include: using a four-probe test method or a volt-ampere characteristic test method to measure the series resistance of the chip. Before the aging test, the initial series resistance of the chip is measured first. During the aging process, the series resistance of the chip is measured regularly, and the ratio of the difference between the current series resistance and the initial series resistance to the initial series resistance is calculated to obtain the series resistance growth rate.

[0071] The quantum efficiency of the light-emitting chip to be tested changes, and the quantum efficiency characterizes the radiative recombination efficiency. Quantum efficiency characterizes the radiative recombination efficiency, that is, the ability of the chip to convert photons generated by the recombination of electron-hole pairs into output lasers. The performance degradation of the chip will affect the quantum efficiency. By measuring the change in quantum efficiency, the change in the radiative recombination efficiency of the chip can be evaluated. The specific collection method may include: using an integrating sphere and an optical power meter to measure the output light power of the chip, and using a current source to measure the injected current of the chip. According to the definition of quantum efficiency, the quantum efficiency of the chip is obtained by calculating the ratio of the output light power to the injected current. During the aging test, the quantum efficiency of the chip is measured regularly, and the difference between the current quantum efficiency and the initial quantum efficiency and the ratio of the initial quantum efficiency are calculated to obtain the change in quantum efficiency.

[0072] Understandably, this application utilizes more dimensional failure parameters (such as wavelength drift, rate of change of near-field spot divergence angle, series resistance growth rate, and quantum efficiency change) for screening and evaluation. This advantage lies in its ability to more comprehensively and accurately reflect chip performance degradation. Multi-parameter monitoring can capture chip performance under different failure mechanisms, such as quantum well structure degradation, optical resonant cavity damage, ohmic contact degradation, and changes in radiative recombination efficiency, thereby more quickly and accurately identifying potential reliability defects. This approach improves screening accuracy and efficiency, providing a strong guarantee for the long-term stable operation of systems such as LiDAR.

[0073] S3. Calculate the failure risk index of the light-emitting chip to be tested based on the failure parameters.

[0074] In an optional embodiment of the present application, calculating the failure risk index of the light-emitting chip to be tested based on the failure parameter includes:

[0075] Establish the characteristic matrix of failure parameters based on failure parameters:

[0076] ;

[0077] in, represents the feature matrix, Represents the wavelength drift of the light-emitting chip to be tested, Represents the rate of change of the near-field light spot divergence angle of the light-emitting chip to be tested, Represents the series resistance growth rate of the light-emitting chip to be tested, Represents the change in quantum efficiency of the light-emitting chip to be tested;

[0078] The failure risk index of the light-emitting chip to be tested is calculated based on the characteristic matrix according to the following formula:

[0079] ;

[0080] in, represents the failure risk index, The first characteristic weight coefficient representing the wavelength shift, The second characteristic weight coefficient representing the rate of change of the near-field spot divergence angle, The third characteristic weight coefficient representing the growth rate of series resistance, The fourth characteristic weight coefficient representing the change in quantum efficiency, represents the time decay factor, Represents time.

[0081] In an optional embodiment of the present application, the first feature weight coefficient, the second feature weight coefficient, the third feature weight coefficient, and the fourth feature weight coefficient are all inferred based on the Bayesian hyperparameter tuning algorithm using historical failure data of the same model of chips as the light-emitting chip to be tested.

[0082] The Bayesian hyperparameter tuning algorithm is an optimization method based on Bayesian theory, used to automatically adjust hyperparameters in machine learning models or algorithms. This algorithm constructs a probabilistic model between hyperparameters and model performance and continuously updates the posterior distribution of model parameters using historical data to find the optimal hyperparameter combination. In the reliability screening of light-emitting chips, the Bayesian hyperparameter tuning algorithm can scientifically infer the characteristic weight coefficients of each failure parameter based on historical failure data for the same chip model, improving the accuracy of failure risk index calculation and optimizing the screening process.

[0083] The Bayesian hyperparameter tuning algorithm is used to determine the weight coefficients for the first, second, third, and fourth features. This algorithm analyzes historical failure data for the same type of light-emitting chip under test, which contains variations in various failure parameters at different aging stages. Based on this data, the algorithm iteratively optimizes and finds the optimal combination of weight coefficients, ensuring that the failure risk index calculated using these weight coefficients most accurately reflects the actual failure risk of the chip.

[0084] As you can see, by leveraging historical failure data for the same chip model and the Bayesian hyperparameter tuning algorithm, we can more scientifically and accurately determine the weighting coefficients for each failure parameter. This not only improves the accuracy of failure risk index calculations but also makes the screening process more automated and intelligent, reducing the impact of human intervention and subjective judgment. This approach also helps optimize the screening process, improves screening efficiency, and provides strong support for chip quality control.

[0085] In an optional embodiment of the present application, before calculating the failure risk index, the light-emitting chip reliability screening method also includes: collecting failure parameters of the same model of chips of the light-emitting chip to be tested at different aging stages and the corresponding actual usage time to form a first historical failure database; based on the first historical failure database, using a preset mathematical model to fit the value of the time attenuation factor.

[0086] The time decay factor is a parameter that reflects the rate at which chip performance degrades over time. It is used to quantify the rate of performance degradation during the aging process and has a significant impact on the calculation of the failure risk index. Based on the first historical failure database, the failure parameters and actual usage duration of the same chip model at different aging stages are compiled. Next, a preset mathematical model (such as an exponential decay model) is selected, using the failure parameters and time as inputs. Using optimization algorithms such as least squares or maximum likelihood estimation, the optimal value of the time decay factor is fitted to ensure that the model's predictions are most consistent with the actual data.

[0087] As can be understood, this embodiment, by constructing a first historical failure database and fitting a time decay factor, makes the calculation of the failure risk index more accurate, more accurately reflecting the performance degradation of the chip in actual use. This helps to identify potential reliability defects in advance, reduce the flow of substandard chips into the market, and improve product quality and customer satisfaction. It also optimizes the screening process and improves production efficiency.

[0088] S4. Compare the failure risk index and the failure risk threshold. If the failure risk index is greater than or equal to the failure risk threshold, determine that the light-emitting chip to be tested is unqualified. If the failure risk index is less than the failure risk threshold, determine that the light-emitting chip to be tested is qualified.

[0089] In an optional embodiment of the present application, the failure risk threshold is a failure risk threshold that is dynamically optimized and updated based on a transfer learning framework; before comparing the failure risk index and the failure risk threshold, the light-emitting chip reliability screening method also includes: collecting failure parameters of the same type of chips to be tested produced in different batches to form a second historical failure database; using a machine learning algorithm to learn the second historical failure database and transfer learning the failure parameters of other related types of chips to form a failure risk threshold prediction model; setting the failure risk threshold of the light-emitting chip to be tested through the failure risk threshold prediction model.

[0090] It can be understood that, on the one hand, dynamically optimizing and updating the failure risk threshold based on a transfer learning framework can fully integrate historical failure parameters of the same chip model from different batches, as well as transfer learning failure parameters from other related chip models, to form a failure risk threshold prediction model, which can then be used to set the failure risk threshold for the light-emitting chip under test. This approach dynamically adjusts the threshold based on historical failure data, effectively addressing the model generalization problem caused by batch process variations, enabling the screening method to better adapt to the characteristics of different chip batches, and improving the accuracy and reliability of screening. On the other hand, transfer learning, such as transferring the failure modes of automotive-grade 905nm VCSELs to industrial-grade 850nm devices, can share failure knowledge from different but related devices, providing more reference information for industrial-grade devices. This enhances the model's ability to identify failure risks in different scenarios, improves the robustness and comprehensiveness of predictions, and ultimately improves the overall effectiveness of light-emitting chip reliability screening.

[0091] In an optional embodiment of the present application, the light-emitting chip reliability screening method further includes: analyzing key degradation features corresponding to failure parameters through a principal component analysis (PCA) algorithm, and constructing a failure sensitive parameter set based on the key degradation features.

[0092] It can be understood that this application uses the PCA algorithm to analyze the key degradation characteristics corresponding to the failure parameters and constructs a failure-sensitive parameter set based on this. This approach has significant beneficial effects. PCA can extract the main components in the data, remove noise and redundant information, and make the screening process more focused on the parameters that have the greatest impact on chip reliability. By constructing a failure-sensitive parameter set, potential reliability defects in the chip can be identified more quickly and accurately, improving screening efficiency. At the same time, this method also helps to deeply understand the mechanism of chip failure and provide strong support for subsequent chip design and optimization.

[0093] Second, as Figure 2 As shown, the present application discloses a light-emitting chip reliability screening system, including: a central control system 10 , a temperature cycle system 20 , a dynamic current application power supply 30 , a failure parameter acquisition system 40 , and a failure analysis module 50 .

[0094] The central control system 10 is configured to control the temperature cycle system 20 and the dynamic current application power supply 30, and perform an aging test on the light-emitting chip to be tested by adopting a composite stress action mode of temperature cycle and dynamic current;

[0095] The failure parameter acquisition system 40 is configured to acquire at least two optical performance parameter change values ​​and / or electrical performance parameter change values ​​of the light-emitting chip to be tested in real time during the aging test as failure parameters;

[0096] The failure analysis module 50 is configured to calculate the failure risk index of the light-emitting chip to be tested based on the failure parameters; compare the failure risk index with the failure risk threshold dynamically optimized and updated based on the transfer learning framework; if the failure risk index is greater than or equal to the failure risk threshold, the light-emitting chip to be tested is judged to be unqualified; if the failure risk index is less than the failure risk threshold, the light-emitting chip to be tested is judged to be qualified.

[0097] In an optional embodiment of the present application, the composite stress action mode of temperature cycling and dynamic current includes: adjusting the ambient temperature of the light-emitting chip to be tested according to a preset temperature cycling strategy, and applying a dynamic current to the light-emitting chip to be tested according to a preset dynamic current application strategy.

[0098] In an optional embodiment of the present application, the preset temperature cycle strategy includes: adjusting the ambient temperature of the light-emitting chip to be tested according to a preset temperature cycle range, a preset number of temperature cycles and a preset temperature adjustment rate; the dynamic current application strategy includes: using a pulse current superimposed on a DC bias current to form a composite current applied to the light-emitting chip to be tested.

[0099] In an optional embodiment of the present application, the failure parameters include at least two of the following: the wavelength drift of the light-emitting chip to be tested; the rate of change of the near-field light spot divergence angle of the light-emitting chip to be tested; the growth rate of the series resistance of the light-emitting chip to be tested; and the change in the quantum efficiency of the light-emitting chip to be tested.

[0100] In an optional embodiment of the present application, the failure analysis module 50 is specifically configured to perform the following steps: establishing a characteristic matrix of failure parameters based on the failure parameters:

[0101] ;

[0102] in, represents the feature matrix, Represents the wavelength drift of the light-emitting chip to be tested, Represents the rate of change of the near-field light spot divergence angle of the light-emitting chip to be tested, Represents the series resistance growth rate of the light-emitting chip to be tested, Represents the change in quantum efficiency of the light-emitting chip to be tested;

[0103] The failure risk index of the light-emitting chip to be tested is calculated based on the characteristic matrix according to the following formula:

[0104] ;

[0105] in, represents the failure risk index, The first characteristic weight coefficient representing the wavelength shift, The second characteristic weight coefficient representing the rate of change of the near-field spot divergence angle, The third characteristic weight coefficient representing the growth rate of series resistance, The fourth characteristic weight coefficient representing the change in quantum efficiency, represents the time decay factor, Represents time.

[0106] In an optional embodiment of the present application, the first feature weight coefficient, the second feature weight coefficient, the third feature weight coefficient, and the fourth feature weight coefficient are all inferred based on the Bayesian hyperparameter tuning algorithm using historical failure data of the same model of chips as the light-emitting chip to be tested.

[0107] In an optional embodiment of the present application, before calculating the failure risk index, the failure analysis module 50 is specifically configured to collect failure parameters of the same type of chips of the light-emitting chip to be tested at different aging stages and the corresponding actual usage time to form a first historical failure database; based on the first historical failure database, a preset mathematical model is used to fit the value of the time attenuation factor.

[0108] In an optional embodiment of the present application, the failure risk threshold is a failure risk threshold dynamically optimized and updated based on a transfer learning framework; the failure analysis module 50 is specifically further configured to collect failure parameters of the same type of chips to be tested produced in different batches to form a second historical failure database; a machine learning algorithm is used to learn the second historical failure database and transfer learning of failure parameters of other related types of chips to form a failure risk threshold prediction model; and the failure risk threshold of the light-emitting chip to be tested is set by the failure risk threshold prediction model.

[0109] In an optional embodiment of the present application, the failure analysis module 50 is further configured to analyze key degradation features corresponding to the failure parameters through a component algorithm, and construct a failure sensitive parameter set according to the key degradation features.

[0110] The specific implementation of the above-mentioned light-emitting chip reliability screening system is similar to the light-emitting chip reliability screening method, and will not be repeated here.

[0111] This application focuses on reliability screening methods for light-emitting chips (such as VCSEL chips) and includes three core innovations:

[0112] (1) Stress loading mechanism: The synergistic effect of temperature cycling and dynamic current stress is used to accelerate the early appearance of chip interface defects (such as oxide layer cracking and solder joint fatigue), which is closer to actual working conditions and improves screening efficiency.

[0113] (2) Degradation feature extraction algorithm: Based on the feature dimensionality reduction technology of principal component analysis (PCA), the failure sensitive parameter set under the coupling of optical-electrical-thermal multi-physical fields is extracted, focusing on key degradation features and improving screening accuracy.

[0114] (3) Dynamic threshold judgment system: Introducing a transfer learning framework, the judgment threshold (R_critical) is dynamically optimized using historical failure data to adapt to the characteristics of different batches of chips, ensuring the robustness and extensiveness of the screening. This method significantly shortens the screening cycle and ensures the long-term stable operation of systems such as lidar.

[0115] The application has achieved remarkable results, mainly in three aspects:

[0116] (1) The screening cycle is greatly shortened to only 15% to 20% of the traditional method, which greatly improves production efficiency.

[0117] (2) The accuracy rate of identifying potentially failed components exceeds 90%, effectively ensuring product quality.

[0118] (3) Screening costs were reduced by more than 40%, thanks to the optimization of test time and the improvement of data calculation efficiency. This application uses innovative methods to achieve efficient, accurate and low-cost chip reliability screening.

[0119] The terms "first," "second," "the first," or "the second" used in various embodiments of the present disclosure may modify various components regardless of order and / or importance, but these terms do not limit the corresponding components. The above terms are configured solely for the purpose of distinguishing an element from other elements. For example, a first user device and a second user device represent different user devices, even though both are user devices. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0120] When one element (for example, a first element) is referred to as being “(operably or communicably) coupled” or “(operably or communicably) coupled to” or “connected to” another element (for example, a second element), it should be understood that the one element is directly connected to the other element or that the one element is indirectly connected to the other element via yet another element (for example, a third element). Conversely, it should be understood that when an element (for example, a first element) is referred to as being “directly connected” or “directly coupled” to another element (the second element), there is no element (for example, a third element) interposed therebetween.

[0121] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0122] The above description is merely an optional embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also encompass other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the above-mentioned inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

[0123] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0124] The above description is merely an optional embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also encompass other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the above-mentioned inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

[0125] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for screening the reliability of a light-emitting chip, characterized in that: include: A composite stress mode of temperature cycling and dynamic current is used to perform aging tests on the light-emitting chip to be tested. During the aging test, at least two optical performance parameter change values ​​and / or electrical performance parameter change values ​​of the light-emitting chip to be tested are collected in real time as failure parameters; Calculating a failure risk index of the light-emitting chip to be tested based on the failure parameter; The failure risk index and the failure risk threshold are compared. If the failure risk index is greater than or equal to the failure risk threshold, the light-emitting chip to be tested is judged to be unqualified; if the failure risk index is less than the failure risk threshold, the light-emitting chip to be tested is judged to be qualified.

2. The light-emitting chip reliability screening method according to claim 1, characterized in that: The composite stress action mode of temperature cycling and dynamic current includes: adjusting the ambient temperature of the light-emitting chip to be tested according to a preset temperature cycling strategy, and applying a dynamic current to the light-emitting chip to be tested according to a preset dynamic current application strategy.

3. The light-emitting chip reliability screening method according to claim 2, characterized in that: The preset temperature cycle strategy includes: adjusting the ambient temperature of the light-emitting chip to be tested according to a preset temperature cycle range, a preset number of temperature cycles and a preset temperature adjustment rate; The dynamic current application strategy includes: using a pulse current to superimpose a DC bias current to form a composite current and apply it to the light-emitting chip to be tested.

4. The light-emitting chip reliability screening method according to claim 1, characterized in that: The failure parameters include at least two of the following: The wavelength drift of the light-emitting chip to be tested; The near-field light spot divergence angle change rate of the light-emitting chip to be tested; The series resistance growth rate of the light-emitting chip to be tested; The quantum efficiency of the light-emitting chip to be tested changes.

5. The light-emitting chip reliability screening method according to claim 4, characterized in that: The calculating the failure risk index of the light-emitting chip to be tested based on the failure parameter includes: A characteristic matrix of failure parameters is established based on the failure parameters: ； in, represents the feature matrix, represents the wavelength drift of the light-emitting chip to be tested, represents the rate of change of the near-field light spot divergence angle of the light-emitting chip to be tested, represents the series resistance growth rate of the light-emitting chip to be tested, Represents the change in quantum efficiency of the light-emitting chip to be tested; The failure risk index of the light-emitting chip to be tested is calculated based on the characteristic matrix according to the following formula: ； in, represents the failure risk index, A first characteristic weight coefficient representing the wavelength shift amount, The second characteristic weight coefficient representing the rate of change of the near-field light spot divergence angle, The third characteristic weight coefficient representing the series resistance growth rate, The fourth characteristic weight coefficient representing the change in quantum efficiency, represents the time decay factor, Represents time.

6. The light-emitting chip reliability screening method according to claim 5, characterized in that: The first feature weight coefficient, the second feature weight coefficient, the third feature weight coefficient, and the fourth feature weight coefficient are all inferred based on a Bayesian hyperparameter tuning algorithm using historical failure data of chips of the same model as the light-emitting chip to be tested.

7. The light-emitting chip reliability screening method according to claim 5, characterized in that: Before calculating the failure risk index, the light-emitting chip reliability screening method further includes: Collecting the failure parameters of the same type of chips of the light-emitting chip to be tested at different aging stages and the corresponding actual usage time to form a first historical failure database; According to the first historical failure database, a preset mathematical model is used to fit the value of the time decay factor.

8. The light-emitting chip reliability screening method according to claim 1, characterized in that: The failure risk threshold is the failure risk threshold that is dynamically optimized and updated based on the transfer learning framework; Before comparing the failure risk index and the failure risk threshold, the light-emitting chip reliability screening method further includes: Collecting the failure parameters of the same type of the light-emitting chips to be tested produced in different batches to form a second historical failure database; Using a machine learning algorithm to learn the second historical failure database and transfer learning the failure parameters of other related chip models to form a failure risk threshold prediction model; The failure risk threshold of the light-emitting chip to be tested is set using the failure risk threshold prediction model.

9. The light-emitting chip reliability screening method according to any one of claims 1 to 8, characterized in that: The light-emitting chip reliability screening method further includes: analyzing key degradation features corresponding to the failure parameters through a component algorithm, and constructing a failure sensitive parameter set according to the key degradation features.

10. A light-emitting chip reliability screening system, characterized in that: include: Central control system, temperature circulation system, dynamic current application power supply, failure parameter acquisition system, failure analysis module; The light-emitting chip reliability screening system is configured to execute the light-emitting chip reliability screening method according to any one of claims 1 to 9.

Images