SOC-oriented IP storage unit verification method and device, medium, program product and terminal

Abstract

The invention provides an SOC-oriented IP storage unit verification method and device, a medium, a program product and a terminal, and the method comprises the steps: obtaining the performance parameters of each storage unit, and storing the performance parameters in a parameter document through a script file; based on this, an environment building file and a verification data file are automatically generated. An SOC verification environment comprising a chip top layer and an IP verification module is constructed, the chip top layer is integrated with a plurality of IP modules and corresponding storage units thereof, and each storage unit is connected with the IP verification module. And a trigger signal is generated and sent to the IP verification module, and simulation verification based on the verification data file is started. According to the method, the problem of automation of verification of the storage unit in the SOC is solved, and the defects of low efficiency and error proneness of traditional manual parameter configuration are overcome. The verification efficiency is remarkably improved, human errors are reduced, and unified verification of various storage units is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a method, device, medium, program product, and terminal for verifying an IP storage unit for a SOC. Background Art

[0002] In the field of semiconductor integrated circuit design and manufacturing, design verification of multifunctional chips, especially testing and verification of embedded memory cells, is a critical step in ensuring chip functionality and reliability. As a highly integrated system-on-chip (SoC), it integrates multiple functional modules and peripheral interfaces. The correctness and performance of its circuit design directly affect the quality and reliability of the final product.

[0003] When it comes to memory verification in SoC chips, the industry currently generally uses memory access testing methods based on customized C programs. During the chip design verification phase, verification engineers need to develop dedicated test programs tailored to the memory architecture characteristics of a specific chip. These programs simulate diverse read and write operation scenarios, including accessing different memory addresses, writing multiple data patterns, and complex read and write timing combinations, in order to effectively identify potential design flaws.

[0004] However, this traditional verification approach has significant technical limitations. First, manually writing test programs significantly increases the workload of test vector generation and test environment configuration. Second, this approach struggles to fully verify the characteristics of different memory cells. Especially when faced with diverse project requirements, verification of different memory cell types often lacks systematic planning and in-depth analysis, which can easily lead to functional defects after tape-out, making it difficult to meet the increasingly stringent reliability and performance requirements of modern embedded systems. Summary of the Invention

[0005] In view of the shortcomings of the existing technology mentioned above, the purpose of this application is to provide a SOC-oriented IP storage unit verification method, device, medium, program product and terminal, which are used to solve the problems faced by existing SoC storage verification technology, such as incomplete test coverage, high degree of manual intervention and low verification efficiency.

[0006] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides an IP storage unit verification method for SOC, comprising: obtaining performance parameters of each storage unit; storing the performance parameters in a parameter document file through a script file, and generating an environment construction file and a verification data file based on the parameter document file; constructing a SOC storage unit verification environment based on the environment construction file and the verification data file; the SOC storage unit verification environment includes a chip top layer and an IP verification module; the chip top layer includes multiple IP modules and their corresponding storage units; the IP module is communicatively connected to its corresponding storage unit, and each storage unit is communicatively connected to the IP verification module; generating a trigger signal and sending the trigger signal to the IP verification module, so that the IP verification module performs simulation verification operations on each storage unit based on the verification data file.

[0007] In some embodiments of the first aspect of the present application, the process of causing the IP verification module to perform a simulation verification operation on each storage unit based on the verification data file includes: determining the interface type of the current storage unit; if the current storage unit is a dual-port, synchronously performing a write operation and a read operation of the data, and after the read and write operations are completed, performing consistency verification on the written data and the read data; otherwise, performing a write operation on the data, and after the write is completed, performing a read operation on the data, and performing consistency verification on the written data and the read data; and / or, determining whether the current storage unit supports a byte selection control function; if the byte selection control function is supported, writing test data to the current storage unit in byte units, reading data from the storage unit in byte units, and performing consistency verification on the written data and the read data; and / or, determining whether the current storage unit includes a test port function; if the current storage unit includes a test port, writing randomly generated verification data to the test port, reading data from the test port, and performing consistency verification on the written data and the read data; if all consistency verification operations pass, the current storage unit passes verification; if any consistency verification operation fails, the current storage unit fails verification.

[0008] In some embodiments of the first aspect of the present application, the verification data file includes a forced signal assignment file, a test stimulus file, and a C language test vector.

[0009] In some embodiments of the first aspect of the present application, the performance parameters are stored in a parameter document file through a script file, and the environment build file and the verification data file are generated based on the parameter document file. The process includes the following steps: storing the performance parameters in an Excel spreadsheet through Python; generating an environment build file, a forced signal assignment file, a test stimulus file, and a C language test vector through Python based on the performance parameters; and deploying the environment build file, the forced signal assignment file, the test stimulus file, and the C language test vector to the SOC storage unit verification environment directory.

[0010] In some embodiments of the first aspect of the present application, each storage unit is communicatively connected to the IP verification module, including: the IP verification module assigns the driving stimulus signal to the input port of each storage unit based on the forced signal assignment file, and connects the output port of each storage unit to the IP verification module.

[0011] In some embodiments of the first aspect of the present application, the process of generating a trigger signal and sending the trigger signal to the IP verification module also includes the following steps: after the SOC system is powered on, setting the clock of the storage unit to the on state; generating a trigger signal and sending the trigger signal to the IP verification module, and setting the on-chip CPU to sleep mode at the same time.

[0012] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides an IP storage unit verification device for SOC, including: a data acquisition module: used to obtain the performance parameters of each storage unit; an environment construction module: used to store the performance parameters in a parameter document file through a script file, and generate an environment construction file and a verification data file based on the parameter document file; based on the environment construction file and the verification data file, a SOC storage unit verification environment is constructed; the SOC storage unit verification environment includes a chip top layer and an IP verification module; the chip top layer includes multiple IP modules and their corresponding storage units; the IP module is communicatively connected to its corresponding storage unit, and each storage unit is communicatively connected to the IP verification module; a storage unit verification module: used to generate a trigger signal and send the trigger signal to the IP verification module, so that the IP verification module performs simulation verification operations on each storage unit based on the verification data file.

[0013] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the SOC-oriented IP storage unit verification method when the computer program is executed by a processor.

[0014] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes computer program code. When the computer program code is run on a computer, the computer implements the SOC-oriented IP storage unit verification method.

[0015] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the SOC-oriented IP storage unit verification method.

[0016] As described above, the present invention's SOC-oriented IP memory cell verification method, apparatus, medium, program product, and terminal have the following beneficial effects: By acquiring the performance parameters of each memory cell, these parameters are stored in a parameter document file using a script file, and an environment construction file and verification data file are generated based on this file. Furthermore, using these generated files, a SOC memory cell verification environment is constructed, comprising a top-level chip layer and an IP verification module. The top-level chip layer includes multiple IP modules and their corresponding memory cells, which are communicatively connected to their corresponding memory cells, and each memory cell is connected to the IP verification module. Finally, a trigger signal is generated and sent to the IP verification module, initiating a memory cell simulation verification operation based on the verification data file. This solves the problem of automating the verification of a large number of memory cells in SOCs, overcoming the shortcomings of manual intervention in traditional verification through automatic parameter extraction and automatic environment construction. This significantly improves the automation and efficiency of SOC memory cell verification, effectively reduces human error during the verification process, and enables unified management and verification of multiple types of memory cells. This method is suitable for memory cell functional verification scenarios in complex SOC designs, and has broad application value, particularly in the field of large-scale integrated circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flow chart of an embodiment of a SOC-oriented IP storage unit verification method of the present application is shown.

[0018] Figure 2 The flowchart of the execution of the script file in the first embodiment of the SOC-oriented IP storage unit verification method of the present application is shown.

[0019] Figure 3 A schematic diagram of the structure of the SOC storage unit verification environment in an embodiment of the SOC-oriented IP storage unit verification method of the present application is shown.

[0020] Figure 4 The figure shows the structure of the IP verification module in the first embodiment of the SOC-oriented IP storage unit verification method of the present application.

[0021] Figure 5 The flowchart of the execution of the simulation verification operation in the first embodiment of the SOC-oriented IP storage unit verification method of the present application is shown.

[0022] Figure 6 The flowchart shows the execution flow chart of the C program during the verification process in an embodiment of the SOC-oriented IP storage unit verification method of the present application.

[0023] Figure 7 A structural diagram of an embodiment of an IP storage unit verification device for SOC of the present application is shown.

[0024] Figure 8 A structural diagram of an embodiment of an IP storage unit verification terminal for SOC of the present application is shown. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0026] Before further explaining the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are subject to the following interpretations:

[0027] <1> SOC system (System on Chip) is an integrated circuit that integrates all necessary components of a complete electronic system (such as processor, memory, interface, etc.) on a single chip, and is often used in embedded systems.

[0028] <2> IP module (Intellectual Property Module): A pre-designed, verified and reusable hardware or software component used to be integrated into SOC design to shorten the design cycle.

[0029] <3> IP Module Memory: A memory unit integrated within or closely connected to an IP module that stores data or instructions required for the operation of the IP module.

[0030] <4> IP Verification Module VIP (Verification IP): A hardware and software component specifically used to verify the functionality of a specific IP module, including reference models, stimulus generators, etc., for automated testing and verification.

[0031] <5> Dual-Port: A memory cell with two independent access ports, allowing simultaneous reading and / or writing, improving data throughput.

[0032] <6> Single-Port: A memory cell with only one access port and can be accessed by only one circuit at any given time.

[0033] <7> CPU Sleep Mode: This mode places the CPU in an inactive, low-power state to prevent the CPU from performing any read or write operations on the memory during verification. This prevents CPU activity from interfering with the verification process and improves the accuracy of test results.

[0034] <8> Scripting Language: In hardware verification environments, a scripting language is a programming language used to automate test tasks. It is interpreted and easy to learn and use. Its main uses include generating test bench files and C-language test vectors for verifying memory cells, IP blocks, or SoCs; parsing verification logs; automating verification processes; and configuring and controlling simulation tools. Common scripting languages include Python, Perl, Tcl, Ruby, and Shell scripts. System Verilog (with DPI-C) can also call C / C++ to achieve similar functionality.

[0035] <9> Stimulus Signal: In the context of memory cell verification, stimulus signals refer to input signals generated by a verification platform (e.g., VIP, Testbench) and applied to the memory cell (DUT). The purpose of these signals is to simulate the various operating and environmental conditions that the memory cell may encounter in actual applications, triggering its internal state transitions and functional execution. Stimulus signals can be various combinations of addresses, data, and control signals (e.g., read / write enable, clock signals, reset signals, etc.) to verify the read / write functionality, timing characteristics, and correctness of the memory cell in different operating modes. The design and generation of stimulus signals is a key step in the verification process, and their quality directly affects the coverage and effectiveness of verification.

[0036] <10> Testbench: A test environment used to verify the correctness of hardware designs. It includes stimulus generators, DUTs, reference models, etc. and is written in the Hardware Verification Language (HVL).

[0037] <11> Chip Top (Chip_Top): The highest level of SOC design, the top module that connects all IP modules in the SOC, handles interconnection, clock distribution, etc., and is the entrance to chip design.

[0038] To facilitate understanding of the embodiments of this application, first Figure 1 Detailed description. Figure 1 The following is a flow chart of a method for verifying an IP storage unit for a SOC according to an embodiment of the present invention. The method for verifying an IP storage unit for a SOC according to this embodiment mainly includes the following steps:

[0039] Step S11: Acquire performance parameters of each storage unit.

[0040] In one embodiment of the present application, different types of IP modules are equipped with corresponding storage units, each with its own unique features in terms of function and architecture. For example, the processor IP typically includes an instruction cache, a data cache, a register stack, and a stack memory, wherein the instruction and data caches are typically 32-64KB, using a multi-way group associative structure, and the register stack contains general-purpose and special-function registers. The graphics processing IP is equipped with a dedicated texture cache, frame cache, and shader registers. These storage units support high bandwidth, parallel computing, and complex graphics rendering tasks. The network communication IP relies on packet caches, transceiver buffers, and protocol status registers. These storage units support high-speed data transmission and complex communication protocol processing. The peripheral control IP mainly uses register map storage, interrupt vector table, and clock reset control register for system configuration, status management, and interrupt response. The dedicated accelerator IP is equipped with microcode storage, intermediate result cache, and configuration registers to support the efficient execution of complex algorithms.

[0041] Furthermore, the performance parameters include depth, width, and port path. Specifically, depth represents the capacity and storage space size of the storage unit. For storage units of different IPs, the depth ranges from tens of KB to several MB, indicating the scale of data processing by the storage unit. Width represents the data path bandwidth of the storage unit, expressed in bits, ranging from 32 bits to 512 bits, which determines the data transmission throughput and parallel processing capability. Port path represents the connection mechanism of the storage unit in the SoC, mainly including bus interface type (such as AXI4), data transmission channel (such as DMA), interrupt connection, clock synchronization mechanism, data flow control, and access priority management.

[0042] It should be noted that the SOC (System on Chip) system on chip involved in this application does not specifically refer to a certain type of system on chip, but covers a wide range of integrated circuit systems. Such SOC systems include but are not limited to microcontroller units (MCUs), and complex system-level chips that integrate multiple functional modules such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory controllers, and various peripheral interfaces. The technical solution of this application is applicable to various types of SOCs. As long as the SOC contains a storage unit that needs to be verified, the verification method of this application can be used for automated testing and verification. Therefore, the scope of application of this application is not limited to a specific SOC architecture or functional module combination, but aims to provide a general and efficient storage unit verification solution.

[0043] Step S12: storing the performance parameters in a parameter document file through a script file, and generating an environment construction file and a verification data file based on the parameter document file.

[0044] In one embodiment of the present application, the verification data file includes a forced signal assignment file, a test stimulus file, and a C language test vector.

[0045] In this embodiment, the verification data file includes a forced signal assignment file, a test stimulus file, and C language test vectors. The forced signal assignment file controls the internal signal states of the storage unit, sets the initial state, data storage path, and access constraints of the storage unit, and provides a signal control mechanism for verifying the performance of the storage unit in different operating scenarios. Through forced signal assignment, the operating environment of storage units such as processor IP cache, graphics IP texture cache, and network communication IP buffer can be simulated, and the changing characteristics of key storage signals can be captured. The test stimulus file is used to verify the functionality of the storage unit and contains predefined input sequences and timing parameters for different IP storage units. By simulating operating scenarios such as processor data reading and writing, graphics texture loading, and network packet transmission, it covers the depth, width, and port path characteristics of the storage unit. The test stimulus file is used to verify the response behavior and performance boundaries of the storage unit under diverse input conditions. The C language test vector presents a collection of test data for the storage unit in a high-level language. Describing test scenarios and data sequences in C language provides a flexible test solution for storage unit verification. The C language test vector describes the access logic of the storage unit and can be converted into the test data required for low-level verification, which is used to verify complex SoC storage architectures and data flow conversion.

[0046] In one embodiment of the present application, the performance parameters are stored in a parameter document file through a script file, and the environment build file and the verification data file are generated based on the parameter document file. The process includes the following steps: storing the performance parameters in an Excel spreadsheet through Python; generating an environment build file, a forced signal assignment file, a test stimulus file, and a C language test vector through Python based on the performance parameters; and deploying the environment build file, the forced signal assignment file, the test stimulus file, and the C language test vector to the SOC storage unit verification environment directory.

[0047] Figure 2 The flowchart of the process of generating the environment files required for verification storage, port forced signal assignment files, driver stimulus files, and C language test vectors through script files in this embodiment is shown. Preferably, the script file is Python. Specifically, the following steps are performed through the Python script: based on the verification environment of the SOC system, the storage unit properties of each IP module in the SOC are defined, including the width and depth of the storage unit and the corresponding port path in the SOC. In particular, in order to improve the reusability between different projects, these properties are written into Excel tables and stored in specific folders. It is worth noting that, considering that the absolute path of the IP is generally defined in the SOC environment, the port path of the storage unit is expressed as a relative path relative to the IP, which can avoid frequent changes between different projects.

[0048] Furthermore, a Python script is used to store performance parameters in an Excel file, facilitating centralized processing and management of these parameters. Based on the stored performance parameters, a Python script generates read and write stimulus signals in System Verilog to simulate the actual operational behavior of the storage unit. During this process, to ensure the integrity and consistency of verification, the script also generates and associates forced assignment paths for each storage unit. A forced assignment path refers to a path within the verification environment that sets a forced assignment for a specific signal, allowing key signals to be precisely controlled and assigned values during the verification process.

[0049] Next, the Python script generates C language test vector files, which are used to drive various logic modules in the verification process, ensuring that the hardware modules within the SoC system respond according to the preset behaviors. Finally, the script automatically deploys the generated environment build files, forced signal assignment files, test bench files, and C language test vectors to the SoC's verification environment directory.

[0050] It's worth noting that Python scripting plays a key role in defining and optimizing the structure and processes of the SoC verification environment. It not only rapidly generates various verification files but also ensures their consistency and logic. During the IP memory unit verification process, verification files generated for different modules are organized and stored in the corresponding SoC environment directories. This eliminates manual verification operations and significantly improves the reusability and scalability of the SoC verification environment.

[0051] Step S13: Based on the environment construction file and verification data file, a SOC storage unit verification environment is constructed; the SOC storage unit verification environment includes a chip top layer and an IP verification module; the chip top layer includes multiple IP modules and their corresponding storage units; the IP modules are communicatively connected to their corresponding storage units, and each storage unit is communicatively connected to the IP verification module.

[0052] Figure 3 The structural diagram of the SOC storage unit verification environment in an embodiment of the present application is shown. The SOC storage unit verification environment adopts a layered architecture to build a complete verification closed loop, including two core parts: the chip top layer (Chip_Top) and the IP verification module (VIP, Verification IP), and includes the following connection relationship: Testbench serves as the top-level control platform, initializes the working mode of VIP through the configuration interface, and sends the test scenario parameter Rdata (including test mode, data mode, address range, timing parameters, etc.) to define the specific content of the verification. At the same time, Testbench receives the verification status and error report returned by VIP through MemoryInterface Force, which is used to monitor the verification process and obtain results. Among them, Memory Interface Force memory interface control is a method for Testbench to directly access and control the Memory interface in Chip_Top, which is used to receive the verification status and error report of VIP. Subsequently, VIP injects the stimulus signal (including address bus, data bus and control signals such as WE / RE / CS) into the Memory interface in Chip_Top through the read-write stimulus file, performs actual read and write operations on the storage unit, and monitors the response data and status signal output by Memory in real time to determine whether the function of the storage unit meets expectations.

[0053] Furthermore, Chip_Top contains multiple IP modules and their corresponding memory cells. Each memory module is connected to its corresponding IP core via standard interfaces such as AHB / AXI. During verification, reading and writing stimulus files bypasses some IP logic, allowing the VIP to directly establish communication connections with each memory cell while maintaining the normal connection of basic signals such as clock and reset. This ultimately forms a complete closed-loop verification mechanism: After the stimulus generated by the VIP is processed by the memory, the output data is collected by the VIP and compared to the expected value in real time. A verification result report is generated, and the testbench summarizes the verification results of all memory cells. This architecture not only verifies the independent function of each memory cell, but also ensures its correct integration into the SoC system, achieving comprehensive verification coverage from the module level to the system level.

[0054] This verification method comprises three main components: Testbench, the verification platform; Chip_top, the chip code representing the design under test; and the VIP stimulus model, which generates test stimuli. Building on the conventional SoC verification environment, this verification method uses Python to automatically generate three key verification files: a forced signal assignment file (used to force test stimuli onto memory cell ports); stimulus files required for memory testing; and test vectors written in C, thereby creating an efficient verification process. The forced signal assignment file establishes a bidirectional connection between the VIP and the memory cells: on the one hand, the stimulus signals generated by the VIP are transmitted to the memory cell input ports; on the other hand, the memory output is fed back to the VIP input ports, forming a closed-loop test loop. This architecture enables the verification system to automatically complete key functions such as signal driving, data detection, connection verification, and verification of memory attributes (such as capacity and bit width). The key advantage of this method lies in the automated generation of verification files using Python scripts, which not only significantly improves verification efficiency but also comprehensively verifies the physical connection correctness and functional characteristics of all memory cells in the SoC, providing strong assurance for the reliability of the chip's memory system.

[0055] Figure 4The structural diagram of VIP in one embodiment of the present application is shown. The VIP in this embodiment is built based on the Universal Verification Methodology (UVM) framework and uses the Sequence component to control the generation of the stimulus signal. In order to improve management efficiency, Sequencer and Driver are encapsulated as an Agent to coordinate the generation and transmission of the stimulus signal. In this architecture, the original implementation of Sequencer and Driver does not need to be modified. The generation process of the stimulus signal depends on a pre-written Python script and automatically generates a corresponding number of Sequences based on the number of storage modules to be tested in the predefined Excel file, and instantiates the corresponding Agent. Among them, Sequence refers to the stimulus file used to verify the function of the storage unit. Each stimulus file corresponds to a storage unit to be tested (Device Under Test, DUT).

[0056] In one embodiment of the present application, each storage unit is communicatively connected to the IP verification module, including: the IP verification module assigns the driving stimulus signal to the input port of each storage unit based on the forced signal assignment file, and connects the output port of each storage unit to the IP verification module.

[0057] In this embodiment, a direct communication connection is established between the storage unit and the IP verification module to ensure an effective verification process. Specifically, the IP verification module uses a forced signal assignment file (Force File) to load the driving stimulus signal to the input port of each storage unit. These stimulus signals can include read and write commands, address information, and control signals (such as write enable, read enable, etc.), thereby accurately stimulating the various functions of the storage unit. At the same time, the output port of the storage unit is connected to the IP verification module so that the return data generated by the storage unit after the operation is performed can be monitored and collected in real time. Through such an architecture, the IP verification module can effectively implement functional testing and status feedback of the storage unit, ensuring that the performance and correctness of the verification of each storage unit can be accurately reflected during the verification process.

[0058] Step S14: generating a trigger signal and sending the trigger signal to the IP verification module, so as to enable the IP verification module to perform a simulation verification operation on each storage unit based on the verification data file.

[0059] In one embodiment of the present application, the process of causing the IP verification module to perform a simulation verification operation on each storage unit based on the verification data file includes: determining the interface type of the current storage unit; if the current storage unit is a dual-port, synchronously performing a write operation and a read operation of the data, and after the read and write operations are completed, performing consistency verification on the written data and the read data; otherwise, performing a write operation on the data, and after the write is completed, performing a read operation on the data, and performing consistency verification on the written data and the read data; and / or, determining whether the current storage unit supports a byte selection control function; if the byte selection control function is supported, writing test data to the current storage unit in byte units, reading data from the storage unit in byte units, and performing consistency verification on the written data and the read data; and / or, determining whether the current storage unit includes a test port function; if the current storage unit includes a test port, writing randomly generated verification data to the test port, reading data from the test port, and performing consistency verification on the written data and the read data; if all consistency verification operations pass, the current storage unit passes verification; if any consistency verification operation fails, the current storage unit fails verification.

[0060] Figure 5 The following figure shows a flow chart of the simulation verification operation of the IP storage unit in this embodiment. In this process, the IP verification module (VIP) first waits for the trigger signal sent from the processor core, and then performs a verification test on the current storage unit after receiving the signal. First, the interface type of the current storage unit to be tested is determined. If the current storage unit is a dual-port type, the VIP will perform data write and read operations simultaneously. This concurrent operation can more comprehensively test the performance and stability of the dual-port storage unit under parallel access conditions. After the read and write operations are completed, the VIP will automatically perform consistency verification on the written data and the read data to determine whether the two are completely matched.

[0061] If the memory cell is not a dual-port type, VIP performs verification operations sequentially. It first writes randomly generated data to the memory cell until the entire storage space is filled. Then, it reads data from the memory cell and compares it with the previously written data. This sequential read and write test effectively verifies the data integrity and stability of single-port memory cells.

[0062] VIP then determines whether the current storage unit supports byte-select control. If so, random data is written to the storage unit byte by byte, then read out the data byte by byte, and data consistency is verified. This step is specifically used to test the performance of the storage unit when accessing at the byte level, and is particularly important for application scenarios that require fine-grained access control. If the storage unit does not support byte-select control, this test is skipped.

[0063] The VIP then determines whether the current storage unit includes a test port. Many storage unit designs include a dedicated test port to facilitate testing. If the current storage unit has this capability, the VIP writes randomly generated verification data to the test port, then reads the data from the port and performs consistency verification. This test verifies the correctness of the storage unit's test port and provides a foundation for subsequent product testing. If the test port is not available, this test is skipped.

[0064] Finally, VIP makes a comprehensive assessment of all consistency verification results. If all verification operations pass (i.e., all written and read data are completely consistent), the current storage unit is considered to have passed verification and possesses the expected functionality and performance. If any verification operation fails (data inconsistency occurs), VIP will mark the current storage unit as having failed verification and further analyze the cause of the failure to determine whether there is a problem with the design itself or a mismatch between the initially defined file and the actual implementation. This multi-level, multi-angle verification approach can comprehensively evaluate the various functions of the storage unit, ensuring that the storage unit can operate stably and reliably in actual applications.

[0065] In one embodiment of the present application, the process of generating a trigger signal and sending the trigger signal to the IP verification module also includes the following steps: after the SOC system is powered on, setting the clock of the storage unit to the on state; generating a trigger signal and sending the trigger signal to the IP verification module, and setting the on-chip CPU to sleep mode.

[0066] like Figure 6 The figure shows a flow chart of generating a trigger signal and sending it to the IP verification module (VIP) in this embodiment. This chart illustrates the complete process from system power-up to verification completion in a SOC (system-on-chip) environment. First, the SOC system is powered on and completes the boot process. After system boot, the process enters the clock configuration phase, where the clocks of each IP module and its corresponding memory unit are enabled and configured. This operation provides the necessary timing support for the subsequent verification process, ensuring that the memory unit can respond to external commands in a timely manner. After clock configuration is complete, the system generates a trigger signal and sends it to the IP verification module, activating the VIP to begin accessing the memory unit for functional verification. Simultaneously, the flow chart shows that the on-chip CPU is placed in sleep mode (Wait For Interrupt, WFI). It is worth noting that placing the CPU in correction mode simultaneously prevents the CPU from performing any read or write operations on the memory during verification, thereby preventing CPU activity from interfering with the verification process and improving the accuracy of test results.

[0067] Furthermore, the generation of trigger signals is implemented through C programs compiled based on the RISC-V or ARM architecture. C programs for memory cell verification usually contain specific memory-mapped register access instructions, which generate VIP trigger signals by writing to predefined control registers. RISC-V and ARM architectures support efficient memory access and atomic operation instructions, allowing verification programs to precisely control SOC internal bus transactions and generate trigger signals in a deterministic manner. At the same time, these architectures can quickly switch to low-power modes, such as putting the CPU into sleep mode through the WFI (wait for interrupt) instruction, thereby optimizing system power consumption and avoiding CPU interference with memory cell testing. In the process of generating trigger signals, the C program first configures the clock register, then writes a specific value to the trigger control register, and finally executes the WFI instruction to put the CPU into sleep mode. This series of operations ensures the accuracy of trigger signal generation and provides a reliable foundation for subsequent VIP access and verification of memory cells.

[0068] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0069] Figure 7 FIG is a schematic block diagram of an IP storage unit verification device 700 for SOC provided in an embodiment of the present application. Figure 7 As shown, the device includes a data acquisition module 701, an environment construction module 702 and a storage unit verification module 703.

[0070] Data acquisition module 701: used to obtain performance parameters of each storage unit;

[0071] Environment construction module 702: used to store the performance parameters in a parameter document file through a script file, and generate an environment construction file and a verification data file based on the parameter document file; based on the environment construction file and the verification data file, construct a SOC storage unit verification environment; the SOC storage unit verification environment includes a chip top layer and an IP verification module; the chip top layer includes multiple IP modules and their corresponding storage units; the IP modules are communicatively connected to their corresponding storage units, and each storage unit is communicatively connected to the IP verification module;

[0072] The storage unit verification module 703 is configured to generate a trigger signal and send the trigger signal to the IP verification module, so as to enable the IP verification module to perform a simulation verification operation on each storage unit based on the verification data file.

[0073] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0074] It should also be understood that the division of modules in the embodiments of the present application is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of the present application may be integrated into a single processor, or may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0075] Figure 8 : is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Figure 8 As shown, the electronic terminal includes: at least one processor 801, a memory 802, at least one network interface 803 and a user interface 805. The various components in the device are coupled together via a bus system 804. It is understood that the bus system 804 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 804 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 8 Various buses are labeled as bus systems.

[0076] The user interface 805 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0077] It will be appreciated that the memory 802 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM) or a programmable read-only memory (PROM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memories.

[0078] The memory 802 in the embodiment of the present invention is used to store various categories of data to support the operation of the electronic terminal 800. Examples of such data include: any executable program for operating on the electronic terminal 800, such as an operating system 8021 and an application 8022; the operating system 8021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 8022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The SOC-oriented IP storage unit verification method provided in the embodiment of the present invention can be included in the application 8022.

[0079] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by processor 801. Processor 801 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in processor 801 or by software instructions. The above processor 801 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 801 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 801 can be a microprocessor or any conventional processor. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory. The processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0080] In an exemplary embodiment, the electronic terminal 800 may be configured to execute the aforementioned method using one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0081] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, which, when running on a computer, enables the computer to execute the SOC-oriented IP storage unit verification method of any of the embodiments shown above.

[0082] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores program code. When the program code runs on a computer, the computer executes the SOC-oriented IP storage unit verification method of any of the embodiments shown above.

[0083] As used in this specification, the terms "component," "module," "system," and the like are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component on a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0084] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0085] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0086] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0087] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0088] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0089] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (program) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. Available media can be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0090] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0091] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0092] In summary, the present application provides an IP storage unit verification method, device, medium, program product and terminal for SOC, which obtains the performance parameters of each storage unit and stores them in a parameter document using a script file. Based on this, an environment construction file and a verification data file are automatically generated. A SOC verification environment including a chip top layer and an IP verification module is constructed. The chip top layer integrates multiple IP modules and their corresponding storage units, and each storage unit is connected to the IP verification module. A trigger signal is generated and sent to the IP verification module to start simulation verification based on the verification data file. The present application solves the automation problem of storage unit verification in SOC and overcomes the inefficiency and error-proneness of traditional manual configuration parameters. It significantly improves verification efficiency, reduces human errors, and realizes unified verification of multiple storage units. It is particularly suitable for complex SOC designs and is widely used in the field of large-scale integrated circuits. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0093] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A SOC-oriented IP storage unit verification method, characterized in that: include: Obtain performance parameters of each storage unit; Storing the performance parameters in a parameter document file through a script file, and generating an environment construction file and a verification data file based on the parameter document file; Based on the environment construction file and the verification data file, a SOC storage unit verification environment is constructed; the SOC storage unit verification environment includes a chip top layer and an IP verification module; the chip top layer includes multiple IP modules and their corresponding storage units; the IP modules are communicatively connected to their corresponding storage units, and each storage unit is communicatively connected to the IP verification module; A trigger signal is generated and sent to an IP verification module, so as to cause the IP verification module to perform a simulation verification operation on each storage unit based on the verification data file.

2. The SOC-oriented IP storage unit verification method according to claim 1, characterized in that: The process of causing the IP verification module to perform a simulation verification operation on each storage unit based on the verification data file includes: Determine the interface type of the current storage unit; if the current storage unit is dual-port, perform data write and read operations simultaneously, and after the read and write operations are completed, perform consistency verification on the written data and the read data; otherwise, perform data write operations, and after the write is completed, perform data read operations, and perform consistency verification on the written data and the read data; and / or, determining whether the current storage unit supports a byte selection control function; if the byte selection control function is supported, writing test data into the current storage unit in byte units, reading data from the storage unit in byte units, and performing consistency verification on the written data and the read data; and / or, determining whether the current storage unit includes a test port function; if the current storage unit includes a test port, writing randomly generated verification data to the test port, reading data from the test port, and performing consistency verification on the written data and the read data; If all consistency verification operations pass, the current storage unit passes the verification; if any consistency verification operation fails, the current storage unit fails the verification.

3. The SOC-oriented IP storage unit verification method according to claim 1, characterized in that: The verification data file includes a forced signal assignment file, a test stimulus file, and a C language test vector.

4. The SOC-oriented IP storage unit verification method according to claim 3, characterized in that: The process of storing the performance parameters in a parameter document file through a script file and generating an environment construction file and a verification data file based on the parameter document file is as follows: Storing the performance parameters in an Excel spreadsheet via Python; Based on the performance parameters, generate environment build files, mandatory signal assignment files, test stimulus files, and C language test vectors through Python; Deploy the environment build file, the forced signal assignment file, the test stimulus file, and the C language test vector to the SOC storage unit verification environment directory.

5. The SOC-oriented IP storage unit verification method according to claim 3, characterized in that: Each storage unit is communicatively connected to the IP verification module, including: the IP verification module assigns a driving stimulus signal to an input port of each storage unit based on the mandatory signal assignment file, and connects an output port of each storage unit to the IP verification module.

6. The SOC-oriented IP storage unit verification method according to claim 1, characterized in that: The process of generating a trigger signal and sending the trigger signal to the IP verification module further includes the following steps: After the SOC system is powered on, setting the clock of the storage unit to an on state; A trigger signal is generated and sent to the IP verification module, and the on-chip CPU is set to a sleep mode.

7. A SOC-oriented IP storage unit verification device, characterized in that: include: Data acquisition module: used to obtain the performance parameters of each storage unit; Environment building module: used to store the performance parameters into a parameter document file through a script file, and generate an environment building file and a verification data file based on the parameter document file; Based on the environment construction file and the verification data file, a SOC storage unit verification environment is constructed; the SOC storage unit verification environment includes a chip top layer and an IP verification module; the chip top layer includes multiple IP modules and their corresponding storage units; the IP modules are communicatively connected to their corresponding storage units, and each storage unit is communicatively connected to the IP verification module; Storage unit verification module: used to generate a trigger signal and send the trigger signal to the IP verification module, so that the IP verification module performs a simulation verification operation on each storage unit based on the verification data file.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the SOC-oriented IP storage unit verification method according to any one of claims 1 to 6 is implemented.

9. A computer program product, characterized in that The computer program product includes computer program codes, and when the computer program codes are run on a computer, the computer is enabled to implement the SOC-oriented IP storage unit verification method according to any one of claims 1 to 6.

10. An electronic terminal comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the SOC-oriented IP storage unit verification method according to any one of claims 1 to 6.

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