DRAM sensitive amplifier based on offset voltage of capacitance compensation bit line, amplification circuit and chip

Abstract

The invention relates to the technical field of DRAM circuit design, in particular to a DRAM sensitive amplifier based on offset voltage of a capacitance compensation bit line, an amplifying circuit and a chip. The invention discloses a DRAM (Dynamic Random Access Memory) sensitive amplifier based on offset voltage of a capacitance compensation bit line. The DRAM sensitive amplifier comprises a signal amplification part and a pre-charging circuit part, wherein the signal amplification part comprises nine NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N8 and N12, three PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P3 and a capacitor C0. According to the invention, the offset voltage of the bit line is compensated by using the capacitor C0, so that the offset voltage is effectively eliminated, and the reading precision is improved. According to the invention, the NMOS tube N8 is switched on to carry out short circuit on the C0 during signal amplification, so that the signal amplification process is accelerated, and the power consumption of the circuit is reduced. The problems that an existing traditional DRAM sensitive amplifier is large in offset voltage and high in power consumption are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of DRAM circuit design, and more specifically, to: 1. a DRAM sense amplifier (SCOCSA) based on capacitor compensation of bit line offset voltage; 2. an amplifier circuit constructed based on the SCOCSA; and 3. a sense amplifier chip designed based on the SCOCSA. Background Art

[0002] Dynamic random access memory (DRAM) is an indispensable component of modern computer systems, and its performance directly impacts the speed and stability of the entire system. With the continuous advancement of semiconductor technology, DRAM storage density and capacity continue to increase, but this also places higher demands on the read and write speed and reliability of storage cells.

[0003] The sense amplifier plays a crucial role in DRAM read and write operations. It amplifies the weak charge signal in the memory cell and converts it to a logic level of "0" or "1." Sense amplifier performance parameters primarily include read speed, sensing yield, offset voltage, and power consumption. Offset voltage and power consumption are key performance factors to consider, as offset voltage affects DRAM read accuracy. Low power consumption is a key trend in DRAM circuit design.

[0004] For existing traditional DRAM sense amplifiers, the symmetrical transistors in the left and right inverters may have inconsistent size parameters, resulting in unequal threshold voltages for the left and right pairs of transistors. This leads to differences in the threshold reversal points of the left and right inverters in the cross-coupled feedback amplifier structure, which in turn causes bit line voltage imbalance and leads to erroneous reading of DRAM data. In actual use, it has been found that the power consumption of existing traditional DRAM sense amplifiers is also relatively high. Summary of the Invention

[0005] Based on this, it is necessary to provide a DRAM sense amplifier, amplifier circuit, and chip based on capacitor compensation for bit line offset voltage to address the problems of large offset voltage and high power consumption of existing traditional DRAM sense amplifiers.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] In a first aspect, the present invention provides a DRAM sense amplifier based on capacitance compensation for bit line offset voltage, comprising: a signal amplification section and a pre-charging circuit section.

[0008] The signal amplifier section includes: 9 NMOS transistors N1 to N8, N12, 3 PMOS transistors P1 to P3, and 1 capacitor C0. Among them, the gate of P1 is connected to the gate of N1, the source of N3, and the drain of N7; the drain of P1 is connected to the gate of P2, the drain of N1, the drain of N3, the drain of N5, the drain of N8, and one end of C0; the source of P1 is connected to the source of P2 and the drain of P3; the drain of P2 is connected to the drain of N2, the drain of N4, the drain of N6, and the source of N7; the gate of P3 is connected to the control signal T5, and the source is connected to the power supply VDD; the source of N1 is connected to the The source and drain of N12; the gate of N2 is connected to the other end of C0, the source of N4, and the source of N8; the gate of N3 is connected to the control signal OC; the gate of N4 is connected to the control signal T1; the gate of N5 is connected to the control signal T3, and the source is connected to the bit line BL; the gate of N6 is connected to T3, and the source is connected to the bit line BLB; the gate of N7 is connected to the control signal T2; the gate of N8 is connected to T3; the gate of N12 is connected to the control signal T4, and the source is connected to the ground VSS.

[0009] The precharge circuit is connected to BL and BLB and is used to precharge the voltage of BL and BLB to VDD / 2.

[0010] The implementation of the DRAM sense amplifier based on capacitance compensation of bit line offset voltage is in accordance with the method or process of an embodiment of the present disclosure.

[0011] In a second aspect, the present invention discloses an amplifier circuit, comprising: a DRAM storage unit 1, a DRAM storage unit 2, and a DRAM sensitive amplifier based on capacitance compensation for bit line offset voltage as disclosed in the first aspect.

[0012] DRAM storage unit 1 is used to store 0 or 1. DRAM storage unit 2 is used to store 0 or 1.

[0013] A DRAM sense amplifier based on capacitance compensation of a bit line offset voltage is used to read a DRAM storage cell 1 or a DRAM storage cell 2.

[0014] The implementation of such an amplifier circuit is based on the method or process of an embodiment of the present disclosure.

[0015] In a third aspect, the present invention discloses a sense amplifier chip, which adopts the circuit layout of the DRAM sense amplifier based on capacitance compensation of bit line offset voltage disclosed in the first aspect.

[0016] The implementation of the sense amplifier chip is based on the method or process of the embodiment of the present disclosure.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The present invention provides a newly designed DRAM sense amplifier that uses capacitor C0 to compensate for the bit line offset voltage, effectively eliminating the offset voltage and improving reading accuracy. By turning on NMOS transistor N8 to short-circuit C0 during signal amplification, the signal amplification process is accelerated and circuit power consumption is reduced.

[0019] 2. The present invention provides an amplifier circuit constructed based on a newly designed DRAM sense amplifier. The amplifier circuit first stores the offset voltage in capacitor C0 during the precharge and offset compensation stages. Then, during the potential balancing stage, the voltages of the left and right nodes are balanced to prevent the impact of different node voltages on the bit line voltage difference, thereby completing the compensation of the offset voltage. Then, during the sharing and main amplification stages, capacitor C0 is short-circuited by turning on NMOS transistor N8, and the cross-coupling structure formed by N1, N2, P1, and P2 is used to effectively and quickly amplify the voltage difference between BL and BLB to achieve reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A circuit diagram of a DRAM sense amplifier based on capacitance compensation for bit line offset voltage provided in Example 1 of the present invention;

[0022] Figure 2 A circuit diagram of an amplifier circuit provided in Example 1 of the present invention;

[0023] Figure 3 for Figure 2 Circuit state diagram of the amplifier circuit when it is in the precharge and offset compensation stages;

[0024] Figure 4 for Figure 2 Circuit state diagram when the amplifier circuit is in the potential equilibrium stage;

[0025] Figure 5 for Figure 2 A circuit state diagram of a DRAM storage unit when the amplifier circuit is in the shared and main amplification stages;

[0026] Figure 6 for Figure 2 The signal timing change diagram of the amplifier circuit;

[0027] Figure 7A circuit diagram of a conventional DRAM sense amplifier provided in Example 2 of the present invention;

[0028] Figure 8 A comparison diagram of offset voltage simulation provided in Example 2 of the present invention;

[0029] Figure 9 This is a power consumption simulation comparison chart provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0031] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] Example 1

[0034] First, see Figure 1 , which is a circuit structure diagram of a DRAM sense amplifier (ie, SCOCSA) based on capacitance compensation for bit line offset voltage provided in the first embodiment.

[0035] For SCOCSA, it can be divided into signal amplification part and pre-charge circuit part according to its function.

[0036] 1. The signal amplifier part is the core part of SCOCSA, which includes: 9 NMOS tubes N1~N8, N12, 3 PMOS tubes P1~P3, and 1 capacitor C0.

[0037] like Figure 1 As shown, the connection relationship of each component is as follows:

[0038] The gate of P1 is connected to the gate of N1, the source of N3, and the drain of N7;

[0039] The drain of P1 is connected to the gate of P2, the drain of N1, the drain of N3, the drain of N5, the drain of N8, one end of C0 (corresponding to Figure 1 L node in );

[0040] The source of P1 is connected to the source of P2 and the drain of P3;

[0041] The drain of P2 is connected to the drain of N2, the drain of N4, the drain of N6, and the source of N7;

[0042] The gate of P3 is connected to the control signal T5, and the source is connected to the power supply VDD;

[0043] The source of N1 is connected to the source of N2 and the drain of N12;

[0044] The gate of N2 is connected to the other end of C0 (corresponding to Figure 1 R node in), source of N4, source of N8;

[0045] The gate of N3 is connected to the control signal OC;

[0046] The gate of N4 is connected to the control signal T1;

[0047] The gate of N5 is connected to the control signal T3, and the source is connected to the bit line BL;

[0048] The gate of N6 is connected to T3, and the source is connected to the bit line BLB;

[0049] The gate of N7 is connected to the control signal T2;

[0050] The gate of N8 is connected to T3;

[0051] The gate of N12 is connected to the control signal T4, and the source is connected to the ground VSS.

[0052] It should be noted that P1, N1, and N3 constitute inverter 1; P2, N2, N4, and N8 constitute inverter 2; and inverter 1 and inverter 2 together constitute a cross-coupled amplification structure.

[0053] 2. The precharge circuit is connected to BL and BLB and is used to precharge the voltage of BL and BLB to VDD / 2.

[0054] In this embodiment 1, the pre-charge circuit is recommended to adopt Figure 1The design shown includes three NMOS transistors, N9 to N11. Specifically, the gates of N9, N10, and N11 are connected to control signal VBLP; the sources of N9 and N11 are connected to bit line BL; the drains of N9 and N10 are connected to control signal VEQ; and the drains of N10 and N11 are connected to bit line BLB.

[0055] It should be noted that when the pre-charge circuit is working, VBLP is set to a high level (N9~N11 is turned on), VEQ is set to VDD / 2, so that the voltage of BL and BLB is pre-charged to VDD / 2 (VEQ charges BL through N9 and charges BLB through N10, and BL and BLB are short-circuited through N11 to maintain VDD / 2).

[0056] Of course, the pre-charging circuit may also adopt other designs, but it is necessary to ensure that it can pre-charge the voltage of BL and BLB to VDD / 2.

[0057] Secondly, see Figure 2 Based on the above SCOCSA, an amplifier circuit is constructed, namely a SCOCSA utilization circuit. The amplifier circuit includes: SCOCSA, DRAM storage unit 1, and DRAM storage unit 2.

[0058] DRAM storage cell 1 is used to store 0 or 1. DRAM storage cell 2 is used to store 0 or 1. SCOCSA is used to read DRAM storage cell 1 or DRAM storage cell 2.

[0059] DRAM storage unit 1 and DRAM storage unit 2 may adopt a common 1T1C structure.

[0060] See Figure 2 DRAM storage cell 1 includes: an NMOS transistor NM1 and a capacitor C1. NM1's drain is connected to BL, and its gate is connected to word line WL1. C1's first end is connected to NM1's source, and its second end is connected to VDD / 2. DRAM storage cell 2 includes: an NMOS transistor NM2 and a capacitor C2. NM2's drain is connected to BLB, and its gate is connected to word line WL2. C2's second end is connected to NM2's source, and its second end is connected to VDD / 2.

[0061] It should be noted that WL1 and WL2 cannot be turned on at the same time to prevent damage to the data in the DRAM storage unit.

[0062] The above disclosed amplifier circuit is used to perform data reading operation, and its working sequence includes: pre-charge and offset compensation stage, potential balance stage, sharing and main amplification stage.

[0063] In general, in the precharge and offset compensation stages, C0 stores the voltages of the nodes L and R on both sides; in the potential balance stage, C0 controls the voltage change of node R; in the sharing and main amplification stages, C0 is short-circuited, and the amplifier circuit relies on the cross-coupling structure to amplify the bit line voltage difference.

[0064] The following is a detailed explanation of the principles of each stage:

[0065] 1) During the precharge and offset compensation phase:

[0066] VBLP is set to a high level (generally set to 1.5*VDD), and N9~N11 are turned on; VEQ is set to VDD / 2, and the voltage of BL and BLB is pulled up to VDD / 2 to complete the pre-charge.

[0067] T4 is set to a high level (generally set to 1.5*VDD), T5 is set to a low level (generally set to 0), N12 and P3 are turned on; OC is set to a high level (generally set to 1.5*VDD), T1 is set to a high level (generally set to 1.5*VDD), N3 and N4 are turned on; the input and output of inverter 1 are short-circuited, and the gate and drain of N2 are short-circuited; then P1, N1, P2, and N2 are turned on (the source of P1 is connected to VDD, and the source of N1 is connected to VSS, then P1 and N1 are turned on; the gate of P2 is connected to the drain of P1, and the gate and drain of N2 are short-circuited. At this time, the gate of P2 and the gate of N2 are both in the saturation region, so that P2 and N2 are turned on), and the other tubes remain cut off (that is, N5~N8, NM1~NM2 are cut off). At this time, the amplifier circuit appears as follows Figure 3 If the circuit state is , C0 becomes an offset voltage storage unit and stores the voltages of nodes L and R.

[0068] It should be noted that the voltage V at node L at this time L The voltage V at node R R The voltage difference ΔV between them is the offset voltage.

[0069] 2) In the potential equilibrium stage:

[0070] T4 is set to low level (generally set to 0), T5 is set to high level (generally set to 1.5*VDD), N12 and P3 are cut off, inverters 1 and 2 are not working; OC is set to high level (generally set to 1.5*VDD), T2 is set to high level (generally set to 1.5*VDD), N3 and N7 are turned on; the other tubes remain cut off (that is, N1, N2, N4~N6, N8~N11, P1~P2, NM1~NM2 are cut off), and the amplifier circuit appears as follows Figure 4 The circuit state is as follows: Node L and node R are voltage balanced, thereby avoiding the influence of different node voltages on the bit line voltage. Since the C0 voltage cannot change suddenly, the voltage V' of node R at this time Ris the voltage V' at node L L and the sum of ΔV (i.e. V' R =V' L +ΔV), thus completing the compensation of the offset voltage.

[0071] 3) In the sharing and main amplification phase, there are four situations:

[0072] 301, if DRAM storage cell 1 is read and DRAM storage cell 1 stores "1", WL1 is set to a high level (usually set to 1.5*VDD), NM1 is turned on, C1 and BL share charge, so that the voltage of BL rises and becomes greater than BLB, and a positive voltage difference to be amplified appears between BL and BLB;

[0073] T4 is set to a high level (generally set to 1.5*VDD), T5 is set to a low level (generally set to 0), N12 and P3 are turned on; T2 is set to a high level (generally set to 1.5*VDD), T3 is set to a high level (generally set to 1.5*VDD), N5~N8 are turned on; then, P1, N1, P2, N2 are turned on, and the other tubes remain cut off (N3, N4, N9~N11, NM2 are cut off). At this time, the amplifier circuit appears as follows Figure 5 In the circuit state, inverters 1 and 2 work and form a cross-coupled negative feedback amplifier structure, amplifying the positive voltage difference between BL and BLB to the swing amplitude - that is, the BL voltage is amplified to VDD and the BLB voltage is pulled down to 0, then reading the BL potential will obtain the reading result "1".

[0074] 302, if DRAM storage cell 1 is read and DRAM storage cell 1 stores "0", WL1 is set to a high level (usually set to 1.5*VDD), NM1 is turned on, and C1 and BL share charge, so that the voltage of BL drops and becomes lower than BLB, and a negative voltage difference to be amplified appears between BL and BLB;

[0075] T4 is set to a high level (generally set to 1.5*VDD), T5 is set to a low level (generally set to 0), N12 and P3 are turned on; T2 is set to a high level (generally set to 1.5*VDD), T3 is set to a high level (generally set to 1.5*VDD), N5~N8 are turned on; then, P1, N1, P2, N2 are turned on, and the other tubes remain cut off (N3, N4, N9~N11, NM2 are cut off). At this time, the amplifier circuit appears as follows Figure 5 In the circuit state, inverters 1 and 2 work and form a cross-coupled negative feedback amplifier structure, amplifying the negative voltage difference between BL and BLB to the swing amplitude - that is, the BL voltage is pulled down to 0 and the BLB voltage is pulled up to VDD, then reading the BL potential will obtain the reading result "0".

[0076] 303, if DRAM storage cell 2 is read and DRAM storage cell 2 stores "1", WL2 is set to a high level (usually set to 1.5*VDD), NM2 is turned on, and C2 and BLB share charge. In this way, the voltage of BLB rises and becomes greater than BL, and a negative voltage difference to be amplified appears between BL and BLB;

[0077] T4 is set to a high level (generally set to 1.5*VDD), T5 is set to a low level (generally set to 0), N12 and P3 are turned on; T2 is set to a high level (generally set to 1.5*VDD), T3 is set to a high level (generally set to 1.5*VDD), N5~N8 are turned on; then, P1, N1, P2, N2 are turned on, and the remaining tubes remain cut off (N3, N4, N9~N11, NM1 are cut off), inverters one and two work, and form a cross-coupled negative feedback amplifier structure, which amplifies the negative voltage difference between BL and BLB to the swing amplitude - that is, the BL voltage is pulled down to 0 and the BLB voltage is pulled up to VDD, then reading the BLB potential will get the reading result "1".

[0078] 304, if DRAM storage cell 2 is read and DRAM storage cell 2 stores "0", WL2 is set to a high level (usually set to 1.5*VDD), NM2 is turned on, and C2 and BLB share charge. In this way, the voltage of BLB drops and becomes lower than BL, and a positive voltage difference to be amplified appears between BL and BLB;

[0079] T4 is set to a high level (generally set to 1.5*VDD), T5 is set to a low level (generally set to 0), N12 and P3 are turned on; T2 is set to a high level (generally set to 1.5*VDD), T3 is set to a high level (generally set to 1.5*VDD), N5~N8 are turned on; then, P1, N1, P2, N2 are turned on, and the remaining tubes remain cut off (N3, N4, N9~N11, NM1 are cut off), inverters one and two work, and form a cross-coupled negative feedback amplifier structure, amplifying the positive voltage difference between BL and BLB to the swing amplitude - that is, the BL voltage is pulled up to VDD and the BLB voltage is pulled down to 0, then reading the BLB potential will get the reading result "0".

[0080] It should be noted that in the above-mentioned sharing and main amplification stages, C0 will be short-circuited by the turned-on N8, which can accelerate the feedback amplification speed of the cross-coupled negative feedback amplification structure and amplify the BL and BLB voltages to the swing amplitude in a shorter time, thereby reducing power consumption.

[0081] In order to facilitate the understanding of the above stages, the timing change diagram of each signal at each stage is drawn by taking the reading of DRAM storage unit 1 as an example, as shown in the figure: Figure 6 shown.

[0082] In addition, this embodiment 1 simultaneously discloses a sense amplifier chip, which adopts the circuit layout of the SCOCSA disclosed above and is packaged into a chip mode, which makes it easier to promote and apply the above circuit.

[0083] The sensitive amplifier chip has at least 8 pins: pin 1 is used to connect to BL; pin 2 is used to connect to BLB; pin 3 is used to connect to OC; pin 4 is used to connect to T1; pin 5 is used to connect to T2; pin 6 is used to connect to T3; pin 7 is used to connect to T4; and pin 8 is used to connect to T5.

[0084] It should be noted that if the pre-charge circuit adopts Figure 1 If the specific design is to be determined, the sensitive amplifier chip needs to add two pins: pin nine is used to connect VBLP; pin ten is used to connect VEQ.

[0085] Of course, SCOCSA can also be designed as a module—if it is designed as a module, the corresponding pins can be designed as terminals. After all, the cost of designing as a chip is very high. If it is designed as a module, it will also be convenient for technicians in the field to quickly use SCOCSA. They only need to refer to the product manual and connect the wiring terminals of the module, without having to solder individual components to connect the SCOCSA circuit itself.

[0086] Example 2

[0087] This embodiment 2 is intended to verify the performance of the SCOCSA proposed in embodiment 1. Figure 1 The SCOCSA circuit design is simulated and introduced as follows Figure 7 The conventional DRAM sense amplifier (SA for short, which has the problems mentioned in the background art) is shown for comparison.

[0088] 1. Under simulation conditions (Corner: mismatch; Temperature: 27℃; VDD: 1.2V), the offset voltage of SCOCSA and SA under different bit line capacitances was investigated. The variation curves are shown in the figure below. Figure 8 As shown. Figure 8 It can be seen that under the same bit line capacitance, the offset voltage of SCOCSA is much lower than that of SA; and as the bit line capacitance increases, the offset voltage of SA decreases but still remains high, while the offset voltage of SCOCSA only increases slightly and remains much lower than that of SA.

[0089] 2. Under simulation conditions (Corner: TT; Temperature: 27°C; VDD: 1.2V), the power consumption comparison of SCOCSA and SA when reading data under different bit line capacitances is investigated. The change curves are shown as follows: Figure 9As shown. Figure 9 It can be seen that under the same bit line capacitance, the power consumption of SCOCSA is less than that of SA; and as the bit line capacitance increases, the power consumption of SCOCSA increases less than that of SA.

[0090] In summary, the SCOCSA proposed in Example 1 can effectively compensate for the bit line offset voltage, significantly reduce the impact of the offset voltage, and maintain low power consumption.

[0091] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A DRAM sense amplifier based on capacitance compensation for bit line offset voltage, characterized in that: include: The signal amplification part includes: 9 NMOS transistors N1 to N8, N12, 3 PMOS transistors P1 to P3, and 1 capacitor C0; Among them, the gate of P1 is connected to the gate of N1, the source of N3, and the drain of N7; the drain of P1 is connected to the gate of P2, the drain of N1, the drain of N3, the drain of N5, the drain of N8, and one end of C0; the source of P1 is connected to the source of P2 and the drain of P3; the drain of P2 is connected to the drain of N2, the drain of N4, the drain of N6, and the source of N7; the gate of P3 is connected to the control signal T5, and the source is connected to the power supply VDD; the source of N1 is connected to the The source and drain of N12; the gate of N2 is connected to the other end of C0, the source of N4, and the source of N8; the gate of N3 is connected to the control signal OC; the gate of N4 is connected to the control signal T1; the gate of N5 is connected to the control signal T3, and the source is connected to the bit line BL; the gate of N6 is connected to T3, and the source is connected to the bit line BLB; the gate of N7 is connected to the control signal T2; the gate of N8 is connected to T3; the gate of N12 is connected to the control signal T4, and the source is connected to the ground VSS; as well as The precharge circuit is connected to BL and BLB and is used to precharge the voltage of BL and BLB to VDD / 2.

2. The DRAM sense amplifier based on capacitance compensation for bit line offset voltage according to claim 1, characterized in that: The pre-charge circuit includes: 3 NMOS tubes N9~N11; The gates of N9, N10, and N11 are connected to the control signal VBLP; The source of N9 and the source of N11 are connected to the bit line BL; The drain of N9 and the source of N10 are connected to the control signal VEQ; The drain of N10 and the drain of N11 are connected to the bit line BLB; When the precharge circuit is working, VBLP is set to a high level, N9 to N11 are turned on, and VEQ is set to VDD / 2, so that the voltage of BL and BLB is precharged to VDD / 2.

3. An amplifier circuit, characterized in that: include: DRAM storage unit 1, which is used to store 0 or 1; DRAM storage unit 2, which is used to store 0 or 1; as well as The DRAM sense amplifier based on capacitance compensation for bit line offset voltage as claimed in claim 1 or 2 is used to read DRAM storage cell 1 or DRAM storage cell 2.

4. The amplifier circuit according to claim 3, wherein: DRAM storage unit 1 includes: 1 NMOS transistor NM1, 1 capacitor C1; The drain of NM1 is connected to BL, and the gate is connected to word line WL1; The first end of C1 is connected to the source of NM1, and the second end is connected to VDD / 2; DRAM storage unit 2 includes: 1 NMOS transistor NM2, 1 capacitor C2; The drain of NM2 is connected to BLB, and the gate is connected to word line WL2; The first end of C2 is connected to the source of NM2, and the second end is connected to VDD / 2; Among them, WL1 and WL2 are not turned on at the same time.

5. The amplifier circuit according to claim 4, characterized in that: The working sequence of the amplifier circuit includes: a pre-charge and offset compensation stage, a potential balance stage, a sharing and main amplification stage.

6. The amplifier circuit according to claim 5, characterized in that: During the precharge and offset compensation stages, N1 to N4, N9 to N12, and P1 to P3 are turned on, and N5 to N8 and NM1 to NM2 are turned off.

7. The amplifier circuit according to claim 6, characterized in that: In the potential balance stage, N3 and N7 are turned on, and N1, N2, N4~N6, N8~N12, P1~P3, and NM1~NM2 are turned off.

8. The amplifier circuit according to claim 7, characterized in that: During the sharing and mastering phases: If DRAM storage unit 1 is to be read, NM1, N1, N2, N5-N8, N12, P1-P3 are turned on, and N3, N4, N9-N11, and NM2 are turned off; If DRAM storage unit 2 is to be read, NM2 is turned on, N1, N2, N5-N8, N12, P1-P3 are turned on, and N3, N4, N9-N11, and NM1 are turned off.

9. A sensitive amplifier chip, characterized in that: A circuit layout of a DRAM sense amplifier based on capacitance compensation for bit line offset voltage as claimed in claim 1 or 2 is adopted.

10. The sense amplifier chip according to claim 9, characterized in that: The pins of the sense amplifier chip include: Pin 1, which is used to connect BL; Pin 2, which is used to connect to BLB; Pin 3, which is used to connect OC; Pin 4, which is used to connect T1; Pin 5, which is used to connect T2; Pin six, which is used to connect T3; Pin seven, which is used to connect T4; as well as Pin eight is used to connect T5.

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