Charge pump circuit and memory

Abstract

The embodiment of the invention discloses a charge pump circuit and a memory. The charge pump circuit comprises a switched capacitor module. The switched capacitor module comprises a voltage transformation capacitor, a charge transmission tube and an output switch tube. And the charge transmission tube is configured to transmit charges from the first voltage source to the first polar plate of the voltage transformation capacitor. And the output switch tube is configured to transmit charges on the first polar plate of the voltage transformation capacitor to the output end of the charge pump circuit. The leakage current of the charge transmission tube in the closed state is lower than the leakage current of the output switch tube in the closed state. And when the charge pump circuit is in an idle state, the charge transmission tube is kept in a closed state under the action of the control end voltage.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a charge pump circuit and a memory. Background Art

[0002] Charge pump circuits can provide a supply voltage higher or lower than the power supply voltage and can be integrated into integrated circuit systems. Within these systems, charge pump circuits consume significant power, making the design of low-power integrated circuits challenging. Therefore, reducing the power consumption of charge pump circuits has become a pressing issue. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a charge pump circuit and a memory, which can reduce power consumption and improve power consumption efficiency.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] An embodiment of the present disclosure provides a charge pump circuit, which includes: a switching capacitor module; the switching capacitor module includes: a transformer capacitor, a charge transfer tube and an output switch tube; the first end of the charge transfer tube is connected to a first voltage source, and the second end of the charge transfer tube is connected to the first plate of the transformer capacitor; the charge transfer tube is configured to transfer charge from the first voltage source to the first plate of the transformer capacitor; the first end of the output switch tube is connected to the first plate of the transformer capacitor, and the second end of the output switch tube is connected to the output end of the charge pump circuit; the output switch tube is configured to transfer the charge on the first plate of the transformer capacitor to the output end of the charge pump circuit; wherein the leakage current of the charge transfer tube in the off state is lower than the leakage current of the output switch tube in the off state; when the charge pump circuit is in an idle state, the charge transfer tube remains in a closed state under the action of the control terminal voltage.

[0006] In some embodiments of the present disclosure, the charge pump circuit also includes: a clock signal generation module; the clock signal generation module includes: a first clock generation unit; the first clock generation unit outputs a first clock signal; the control terminal voltage of the charge transfer tube is controlled by the first clock signal; wherein, when the charge pump circuit is in an idle state, the first clock signal is set to a first level, and the charge transfer tube remains in a closed state under the action of the control terminal voltage.

[0007] In some embodiments of the present disclosure, the first clock generation unit includes: a main path, configured to generate and transmit the first clock signal; a control unit, arranged on the main path, configured to set the first clock signal to a first level when the charge pump circuit is in an idle state.

[0008] In some embodiments of the present disclosure, the control unit includes: a first logic gate; a first input end of the first logic gate receives a first control signal or an inverted signal of the first control signal; a second input end of the first logic gate and an output end of the first logic gate are connected to the main path; wherein, when the charge pump circuit is in an idle state or a running state, the first control signal maintains different levels respectively.

[0009] In some embodiments of the present disclosure, the control unit further includes: a driving unit; the driving unit includes: at least one inverter; the driving unit is connected to the first input end of the first logic gate.

[0010] In some embodiments of the present disclosure, the clock signal generation module further includes: a second clock generation unit; the second clock generation unit generates a second clock signal; and the second plate voltage of the variable capacitor is controlled by the second clock signal.

[0011] In some embodiments of the present disclosure, the number of the charge transfer tubes is two; the number of the first clock signals is two; the control terminal voltage of each of the charge transfer tubes is controlled by a corresponding first clock signal; the number of the variable capacitors is two; the number of the second clock signals is two; the second plate voltage of each of the variable capacitors is controlled by a corresponding second clock signal; wherein, when the charge pump circuit is in operation, the two first clock signals are inverted and non-overlapping, and the two second clock signals are inverted and non-overlapping.

[0012] In some embodiments of the present disclosure, the charge pump circuit further includes: a setting module; the setting module is connected between the control end of the charge transfer tube and the discharge source; the setting module is configured to connect the control end of the charge transfer tube to the discharge source when the charge pump circuit is in an idle state.

[0013] In some embodiments of the present disclosure, the setting module includes: a discharge switch tube and a setting control unit; the output end of the setting control unit outputs a setting control signal; the first end of the discharge switch tube is connected to the control end of the charge transfer tube; the second end of the discharge switch tube is connected to the discharge source; the control end of the discharge switch tube is connected to the output end of the setting control unit to receive the setting control signal; wherein, when the charge pump circuit is in an idle state or a running state, the setting control signal maintains different levels respectively.

[0014] In some embodiments of the present disclosure, a first input terminal of the setting control unit receives a first control signal; a second input terminal of the setting control unit is connected to a second voltage source; a third input terminal of the setting control unit is connected to a ground terminal; when the charge pump circuit is in an idle state or a running state, the first control signal maintains different levels respectively; when the charge pump circuit is in an idle state, the difference between the voltage value of the setting control signal and the voltage value of the discharge source is equal to the voltage value of the second voltage source.

[0015] In some embodiments of the present disclosure, the setting control unit includes: an inverter, a first capacitor, a first MOS transistor, a second MOS transistor, and a third MOS transistor; the inverter receives the first control signal; the inverter generates a first setting enable signal and a second setting enable signal; the first setting enable signal and the second setting enable signal are inverted to each other; the first plate of the first capacitor receives the second setting enable signal; the gate of the first MOS transistor and the gate of the second MOS transistor receive the first setting enable signal; the first end of the first MOS transistor, the first end of the second MOS transistor, and the control end of the third MOS transistor are connected; the second end of the first MOS transistor is grounded, and the first end of the third MOS transistor is connected to the second voltage source; or, the second end of the first MOS transistor is connected to the second voltage source, and the first end of the third MOS transistor is grounded; the second plate of the first capacitor, the second end of the second MOS transistor, and the second end of the third MOS transistor are all connected to the output end of the setting control unit.

[0016] An embodiment of the present disclosure further provides a memory, which includes the charge pump circuit described in the above solution.

[0017] It is understood that when the charge pump circuit is in an idle state, that is, when the charge pump circuit does not need to change the output voltage, the output switch tube with lower leakage current is kept in a closed state. This can effectively reduce reverse leakage in the charge transfer path, more effectively maintain the output voltage, reduce the frequency of the charge pump circuit being turned on, and thus effectively reduce the power consumption of the charge pump circuit and improve the power consumption efficiency of the charge pump circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the structure of the switch capacitor module of the charge pump circuit provided in the embodiment of the present disclosure Figure 1 ;

[0019] Figure 2 Schematic diagram of the structure of the switch capacitor module of the charge pump circuit provided in the embodiment of the present disclosure Figure 2 ;

[0020] Figure 3Schematic diagram of the structure of the clock signal generation module of the charge pump circuit provided in the embodiment of the present disclosure Figure 1 ;

[0021] Figure 4 Schematic diagram of the structure of the clock signal generation module of the charge pump circuit provided in the embodiment of the present disclosure Figure 2 ;

[0022] Figure 5 A schematic diagram of a waveform of a clock signal of a charge pump circuit provided in an embodiment of the present disclosure;

[0023] Figure 6 A schematic diagram of the structure of the set module of the charge pump circuit provided in the embodiment of the present disclosure Figure 1 ;

[0024] Figure 7 A schematic diagram of the structure of the set module of the charge pump circuit provided in the embodiment of the present disclosure Figure 2 ;

[0025] Figure 8 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions of this application are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting this application. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0027] In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. The terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that the specific order or sequence of "first / second / third" may be interchanged where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing this application only and are not intended to limit this application.

[0029] The embodiment of the present disclosure provides a charge pump circuit, including a switched capacitor module, which includes variable voltage capacitors C3 and C4, charge transfer transistors M1 and M2, and output switch transistors M3 and M4.

[0030] It should be noted that Figure 1 and Figure 2 The figure shows a switched capacitor module in an embodiment of the present disclosure. Figure 1 The switched capacitor module 11 shown is applied to a positive voltage charge pump circuit. Figure 2 The switched capacitor module 12 shown is applied to a negative voltage charge pump circuit.

[0031] In the embodiments of the present disclosure, reference Figure 1 The switched capacitor module 11 includes two charge transfer paths: a first charge transfer path formed by a charge transfer tube M1 and an output switch tube M3, and a second charge transfer path formed by a charge transfer tube M2 and an output switch tube M4. The two charge transfer paths are used to transfer positive charge to the output end of the charge pump circuit, thereby gradually increasing the output voltage Vout of the charge pump circuit to the target value. The first end of the charge transfer tube M1 is connected to the first voltage source Vcc, and the second end of the charge transfer tube M1 is connected to the first plate of the variable capacitor C3; the first end of the output switch tube M3 is connected to the first plate of the variable capacitor C3, and the second end of the output switch tube M3 is connected to the output end of the charge pump circuit. Correspondingly, the first end of the charge transfer tube M2 is connected to the first voltage source Vcc, and the second end of the charge transfer tube M2 is connected to the first plate of the variable capacitor C4; the first end of the output switch tube M4 is connected to the first plate of the variable capacitor C4, and the second end of the output switch tube M4 is connected to the output end of the charge pump circuit.

[0032] Continue to refer Figure 1 When the charge pump circuit is in operation, the charge transfer tubes M1 and M2 are periodically turned on by their gate voltages Aga and Agb; thus, the first voltage source Vcc periodically transfers positive charges to the first plates of the variable capacitors C3 and C4. Then, the positive charges on the first plates of the variable capacitors C3 and C4 are respectively transferred to the output end of the charge pump circuit through the output switch tubes M3 and M4; thus, the output voltage Vout of the charge pump circuit can be gradually increased to the target value. Figure 1 In the charge pump circuit shown, the capacitor is used as a boost capacitor to realize the boost function of the charge pump.

[0033] Accordingly, reference Figure 2The switched capacitor module 12 includes two charge transfer paths: a first charge transfer path consisting of a charge transfer tube M1 and an output switch tube M3, and a second charge transfer path consisting of a charge transfer tube M2 and an output switch tube M4. The two charge transfer paths are used to transfer negative charge to the output end of the charge pump circuit, thereby gradually reducing the output voltage Vout of the charge pump circuit to a target value. The first end of the charge transfer tube M1 is connected to the first voltage source Vss (i.e., the ground end Vss), and the second end of the charge transfer tube M1 is connected to the first plate of the variable capacitor C3; the first end of the output switch tube M3 is connected to the first plate of the variable capacitor C3, and the second end of the output switch tube M3 is connected to the output end of the charge pump circuit. Correspondingly, the first end of the charge transfer tube M2 is connected to the first voltage source Vss (i.e., the ground end Vss), and the second end of the charge transfer tube M2 is connected to the first plate of the variable capacitor C4; the first end of the output switch tube M4 is connected to the first plate of the variable capacitor C4, and the second end of the output switch tube M4 is connected to the output end of the charge pump circuit.

[0034] Continue to refer Figure 2 When the charge pump circuit is in operation, the charge transfer tubes M1 and M2 are periodically turned on by their gate voltages Aga and Agb; thus, the first voltage source Vss periodically transfers negative charges to the first plates of the variable capacitors C3 and C4. Then, the negative charges on the first plates of the variable capacitors C3 and C4 are respectively transferred to the output end of the charge pump circuit through the output switch tubes M3 and M4; thus, the output voltage Vout of the charge pump circuit can be gradually reduced to the target value. Figure 2 In the charge pump circuit shown, the capacitor serves as a step-down capacitor to implement the step-down function of the charge pump.

[0035] In the embodiments of the present disclosure, reference Figure 1 or Figure 2 The on-times of charge transfer tubes M1 and M2 are complementary; that is, when charge transfer tube M1 is on, charge transfer tube M2 is off, and conversely, when charge transfer tube M1 is off, charge transfer tube M2 is on. Therefore, the charge transfer times of the two charge transfer paths in the switched capacitor module are also complementary. This allows the charge pump circuit to operate during both the rising and falling cycles of the clock signal, ensuring uninterrupted charge transfer to the charge pump circuit's output, improving efficiency.

[0036] In the embodiments of the present disclosure, reference Figure 1 or Figure 2, the leakage current of the charge transfer transistor M1 or M2 in the off state is lower than the leakage current of the output switch transistor M3 or M4 in the off state. When the charge pump circuit is in the idle state, that is, when the charge pump circuit does not need to change the output voltage Vout, the charge transfer transistor M1 remains in the off state under the action of the control terminal voltage Aga, and the charge transfer transistor M2 remains in the off state under the action of the control terminal voltage Agb.

[0037] It is understood that when the charge pump circuit is in an idle state, that is, when the charge pump circuit does not need to change the output voltage Vout, the output switches M3 and M4, which have lower leakage current, remain in a closed state. This effectively reduces reverse leakage in the charge transfer path, more effectively maintains the output voltage Vout, and reduces the frequency of the charge pump circuit being turned on. This effectively reduces the power consumption of the charge pump circuit and improves the power efficiency of the charge pump circuit.

[0038] In some embodiments of the present disclosure, reference Figure 1 or Figure 2 Charge transfer transistors M1 and M2 can use high-threshold-voltage transistors. A higher threshold voltage reduces the subthreshold conduction effect, thereby reducing leakage current. Threshold voltage is a relative term. Using high-threshold-voltage transistors for charge transfer transistors M1 and M2 means their threshold voltages are higher than those of other transistors in the charge pump. For example, this means the threshold voltages of charge transfer transistors M1 and M2 are higher than those of output switches M3 and M4.

[0039] In some embodiments of the present disclosure, reference Figure 1 or Figure 2 The leakage current of charge transfer tubes M1 and M2 can be reduced by changing their structures. The channel length of charge transfer tubes M1 and M2 can be increased, which suppresses the short channel effect and reduces leakage current. Charge transfer tubes M1 and M2 can use transistor structures with better gate control capabilities, such as gate-all-around transistors (GAA). This allows the transistors to be turned off more completely, reducing leakage current.

[0040] In the embodiments of the present disclosure, reference Figure 1 The gate of the charge transfer tube M1 is connected to the voltage source Vdd1 through the discharge transistor M11; at the same time, the gate of the charge transfer tube M2 is connected to the voltage source Vdd1 through the discharge transistor M12. The voltage value of the voltage source Vdd1 is greater than the voltage value of the first voltage domain Vcc. Figure 2The gate of charge transfer tube M1 is connected to ground Vss via discharge transistor M11. Meanwhile, the gate of charge transfer tube M2 is connected to ground Vss via discharge transistor M12. This way, when the gate voltage of charge transfer tubes M1 or M2 is too high or too low, the excess gate voltage can be discharged, thereby protecting charge transfer tubes M1 and M2 from gate breakdown.

[0041] In the embodiments of the present disclosure, reference Figure 1 or Figure 2 Charge transfer transistors M1 and M2, as well as output switch transistors M3 and M4, all utilize a floating substrate voltage. That is, the substrate voltages of charge transfer transistors M1 and M2, as well as those of output switch transistors M3 and M4, are not fixed but controllable. The substrate terminals of transistors M5 and M6 are connected to the substrate terminals of charge transfer transistors M1 and M2, providing a floating substrate voltage for these transistors. The substrate terminals of transistors M7 and M8 are connected to the substrate terminal of output switch transistor M3, providing a floating substrate voltage for this transistor. The substrate terminals of transistors M9 and M10 are connected to the substrate terminal of output switch transistor M4, providing a floating substrate voltage for this transistor. Using a floating substrate voltage allows for adjustable threshold voltages, ensuring efficient operation of the transistors at appropriate voltages. This improves the withstand voltage characteristics of the transistors, enhancing the reliability and stability of the circuit.

[0042] In the embodiments of the present disclosure, reference Figure 1 , transistors M13, M14 and M15 connect the terminals of the output switch tube M3 to the voltage source Vdd1; at the same time, transistors M16, M17 and M18 connect the terminals of the output switch tube M4 to the voltage source Vdd1. Figure 2 Transistors M13, M14, and M15 connect the terminals of output switch M3 to ground Vss. Meanwhile, transistors M16, M17, and M18 connect the terminals of output switch M4 to ground Vss. This precharges the terminals of output switches M3 and M4, reducing setup time and accelerating startup.

[0043] In some embodiments of the present disclosure, the charge pump circuit further includes: a clock signal generating module.

[0044] It should be noted that Figure 3 and Figure 4 The clock signal generation module in the embodiment of the present disclosure is shown. Figure 3 The clock signal generating module 21 shown is applied to a positive charge pump circuit. Figure 4 The clock signal generating module 22 shown is applied to a negative voltage charge pump circuit.

[0045] In the embodiments of the present disclosure, reference Figure 3 or Figure 4 The clock signal generation module includes: a first clock generation unit 210. The first clock generation unit 210 outputs first clock signals N and NF.

[0046] Combine Figure 1 or Figure 2 The control terminal voltage Aga of the charge transfer transistor M1 is controlled by the first clock signal NF, and the control terminal voltage Agb of the charge transfer transistor M2 is controlled by the first clock signal N. When the charge pump circuit is in an idle state, that is, when the charge pump circuit does not need to change the output voltage Vout, the first clock signals N and NF are set to the first level, and the charge transfer transistors M1 and M2 remain in the off state under the influence of the control terminal voltages Aga and Agb, respectively.

[0047] It should be noted that the first levels of the first clock signals N and NF can be high or low. Figure 3 In the embodiment, the first level of the first clock signal N and NF is a high level; Figure 4 In the embodiment, the first levels of the first clock signals N and NF are low levels.

[0048] It is understood that when the charge pump circuit is in an idle state, the first clock signals N and NF are set to a first level, causing the charge transfer transistors M1 and M2 to remain in an off state. This effectively reduces reverse leakage in the charge transfer path, more effectively maintains the output voltage Vout, and reduces the frequency of the charge pump circuit being turned on, thereby effectively reducing the power consumption of the charge pump circuit and improving the power consumption efficiency of the charge pump circuit.

[0049] In some embodiments of the present disclosure, reference Figure 3 or Figure 4 The first clock generation unit 210 includes a main path 211 and a control unit 212. The main path 211 is configured to generate and transmit first clock signals N and NF. The control unit 212 is disposed on the main path 211. The control unit 212 is configured to set the first clock signals N and NF to a first level when the charge pump circuit is in an idle state.

[0050] In some embodiments of the present disclosure, reference Figure 3 or Figure 4 The control unit 212 includes a first logic gate 213. The first input terminal of the first logic gate 213 receives the first control signal OSC_en or the inverted signal of the first control signal OSC_en. Figure 3 In the embodiment, the first logic gate 213 is a NAND gate, and the first input terminal of the first logic gate 213 receives the first control signal OSC_en. Figure 4 In the embodiment, the first logic gate 213 is a NOR gate, and a first input terminal of the first logic gate 213 receives an inverted signal of the first control signal OSC_en. A second input terminal of the first logic gate 213 and an output terminal of the first logic gate 213 are connected to the main path 211 .

[0051] In the embodiment of the present disclosure, when the charge pump circuit is in an idle state or a running state, the first control signal OSC_en maintains different levels respectively. That is, the level of the first control signal OSC_en is directly related to the state of the charge pump circuit, and the control signal for starting the charge pump circuit can be used as the first control signal OSC_en.

[0052] refer to Figure 3 When the charge pump circuit is in an idle state, the first control signal OSC_en maintains a low level, so that under the action of the NAND gate 213, the first clock signals NF and N are set to a low level; when the charge pump circuit is in an operating state, the first control signal OSC_en maintains a high level, so that under the action of the NAND gate 213, the first clock signals NF and N are generated by the main path 211.

[0053] Accordingly, reference Figure 4 When the charge pump circuit is in an idle state, the first control signal OSC_en maintains a low level, so that under the action of the NOR gate 213, the first clock signals NF and N are set to a high level; when the charge pump circuit is in an operating state, the first control signal OSC_en maintains a high level, so that under the action of the NOR gate 213, the first clock signals NF and N are generated by the main path 211.

[0054] In some embodiments of the present disclosure, reference Figure 3 or Figure 4 The control unit 212 further includes a driving unit 214. The driving unit 214 includes at least one inverter. The driving unit is connected to the first input terminal of the first logic gate.

[0055] exist Figure 3 In FIG, the driving unit 214 includes an even number of inverters, and the driving unit 214 can drive the first control signal OSC_en. Figure 4 In the embodiment, the driving unit 214 includes an odd number of inverters, and the driving unit 214 can drive and invert the first control signal OSC_en.

[0056] In some embodiments of the present disclosure, reference Figure 3 or Figure 4 The clock signal generating module further includes: a second clock generating unit 220. The second clock generating unit 220 generates the second clock signals P and PF. Figure 1 or Figure 2The second plate voltages of the variable capacitors C3 and C4 are controlled by the second clock signals P and PF, respectively.

[0057] In the embodiments of the present disclosure, reference Figure 3 or Figure 4 The clock signal generator 230 also receives the first control signal OSC_en. In response to the first control signal OSC_en, the clock signal generator 230 generates a square wave signal OSC_in. The square wave signal OSC_in is used to generate the first clock signals NF, N and the second clock signals PF, P.

[0058] In some embodiments of the present disclosure, Figure 1 and Figure 3 , or, combined Figure 2 and Figure 4 There are two charge transfer tubes, M1 and M2. There are two first clock signals, NF and N. The control terminal voltage of each charge transfer tube is controlled by a corresponding first clock signal. That is, the control terminal voltage Aga of the charge transfer tube M1 is controlled by the first clock signal NF, and the control terminal voltage Agb of the charge transfer tube M2 is controlled by the first clock signal N.

[0059] Combine Figure 1 and Figure 3 , or, combined Figure 2 and Figure 4 There are two variable capacitors, including C3 and C4. There are two second clock signals, including P and PF. The second plate voltage of each variable capacitor is controlled by a corresponding second clock signal. That is, the second plate voltage of variable capacitor C3 is controlled by the second clock signal P, and the second plate voltage of variable capacitor C4 is controlled by the second clock signal PF.

[0060] In the embodiments of the present disclosure, reference Figure 5 When the charge pump circuit is in operation, the two first clock signals NF and N are in phase opposition and do not overlap; that is, the changing edges of the two first clock signals NF and N are not aligned; specifically, the falling edge of the first clock signal NF precedes the rising edge of the first clock signal N, and the rising edge of the first clock signal NF lags behind the falling edge of the first clock signal N. Simultaneously, when the charge pump circuit is in operation, the two second clock signals P and PF are in phase opposition and do not overlap; that is, the changing edges of the two second clock signals P and PF are not aligned; specifically, the falling edge of the second clock signal PF precedes the rising edge of the second clock signal P, and the rising edge of the second clock signal PF lags behind the falling edge of the second clock signal P.

[0061] It is understandable that the changing edges of the clock signals (including the first clock signals NF, N and the second clock signals P, PF) determine the state switching of the devices controlled by them. If the changing edges of the clock signals are aligned, the devices will switch states at the same time. This may cause a sudden change in the output voltage Vout of the charge pump circuit, which is not conducive to the smooth operation of the charge pump circuit. Therefore, in the embodiment of the present disclosure, when the charge pump circuit is in the operating state, the two first clock signals NF and N are in phase opposition and do not overlap with each other, and the two second clock signals P and PF are in phase opposition and do not overlap with each other. In this way, the moments when the devices switch states can be staggered, avoiding sudden changes in the output voltage Vout of the charge pump circuit, which is conducive to the smooth operation of the charge pump circuit.

[0062] In some embodiments of the present disclosure, the charge pump circuit further includes: a setting module.

[0063] It should be noted that Figure 6 and Figure 7 The figure shows a setting module in an embodiment of the present disclosure. Figure 6 The setting module 31 shown is applied to a positive charge pump circuit. Figure 7 The illustrated setting module 32 is applied to a negative voltage charge pump circuit.

[0064] In the embodiments of the present disclosure, reference Figure 6 The setting module 31 is connected between the control end of the charge transfer tube M1 and the discharge source (ie, the first voltage source Vcc). At the same time, the setting module 31 is also connected between the control end of the charge transfer tube M2 and the discharge source (ie, the first voltage source Vcc).

[0065] In the present disclosure, continue to refer to Figure 6 The setting module 31 is configured to connect the control terminal of the charge transfer transistor M1 and the control terminal of the charge transfer transistor M2 to the first voltage source Vcc when the charge pump circuit is in the idle state. That is, when the charge pump circuit is in the idle state, the control terminal voltage Aga of the charge transfer transistor M1 and the control terminal voltage Agb of the charge transfer transistor M2 are set to the voltage of the first voltage source Vcc. At the same time, the first terminal voltage Asa of the charge transfer transistor M1 and the first terminal voltage Asb of the charge transfer transistor M2 are also set to the voltage of the first voltage source Vcc. In this way, the charge transfer transistors M1 and M2 can remain in the off state.

[0066] In the embodiments of the present disclosure, reference Figure 7 The setting module 32 is connected between the control end of the charge transfer tube M1 and the discharge source (ie, the ground end Vss). At the same time, the setting module 32 is also connected between the control end of the charge transfer tube M2 and the discharge source (ie, the ground end Vss).

[0067] In the present disclosure, continue to refer to Figure 7The setting module 32 is configured to connect the control terminals of the charge transfer transistors M1 and M2 to the ground terminal Vss when the charge pump circuit is in an idle state. That is, when the charge pump circuit is in an idle state, the control terminal voltage Aga of the charge transfer transistor M1 and the control terminal voltage Agb of the charge transfer transistor M2 are set to the voltage of the ground terminal Vss. At the same time, the first terminal voltage Asa of the charge transfer transistor M1 and the first terminal voltage Asb of the charge transfer transistor M2 are also set to the voltage of the ground terminal Vss. In this way, the charge transfer transistors M1 and M2 remain in a closed state.

[0068] It can be understood that when the charge pump circuit is in an idle state, the setting module sets the control terminal voltage of the charge transfer tubes M1 and M2 to the voltage of the first voltage source, so that the charge transfer tubes M1 and M2 remain in a closed state. In this way, the reverse leakage in the charge transfer path can be effectively reduced, the output voltage Vout can be more effectively maintained, and the frequency of the charge pump circuit being turned on can be reduced, thereby effectively reducing the power consumption of the charge pump circuit and improving the power consumption efficiency of the charge pump circuit.

[0069] In some embodiments of the present disclosure, the setting module includes: a discharge switch tube and a setting control unit.

[0070] In the embodiments of the present disclosure, reference Figure 6 The output terminal of the setting control unit 311 outputs the setting control signal G_en. The control terminals of the discharge switches M19 and M20 are connected to the output terminal of the setting control unit 311 and receive the setting control signal G_en. The first terminal of the discharge switch M19 is connected to the control terminal of the charge transfer transistor M1, and the second terminal of the discharge switch M19 is connected to the discharge source (i.e., the first voltage source Vcc). The first terminal of the discharge switch M20 is connected to the control terminal of the charge transfer transistor M2, and the second terminal of the discharge switch M20 is connected to the discharge source (i.e., the first voltage source Vcc).

[0071] When the charge pump circuit is in an idle state or a running state, the setting control signal G_en maintains different levels. Figure 6 In the embodiment, the set control signal G_en maintains a high level when the charge pump circuit is in an idle state, the discharge switch tubes M19 and M20 are turned on, and the control terminal voltage Aga of the charge transfer tube M1 and the control terminal voltage Agb of the charge transfer tube M2 are set to the voltage of the first voltage source Vcc; the set control signal G_en maintains a low level when the charge pump circuit is in an operating state, the discharge switch tubes M19 and M20 are turned off, and the set module 31 does not affect the operation of the switch capacitor module 11.

[0072] In the embodiments of the present disclosure, reference Figure 7The output terminal of the setting control unit 321 outputs the setting control signal G_enb. The control terminals of the discharge switches M19 and M20 are connected to the output terminal of the setting control unit 321 and receive the setting control signal G_enb. The first terminal of the discharge switch M19 is connected to the control terminal of the charge transfer transistor M1, and the second terminal of the discharge switch M19 is connected to the discharge source (i.e., ground Vss). The first terminal of the discharge switch M20 is connected to the control terminal of the charge transfer transistor M2, and the second terminal of the discharge switch M20 is connected to the discharge source (i.e., ground Vss).

[0073] When the charge pump circuit is in an idle state or in an operating state, the set control signal G_enb maintains different levels. Figure 7 In the embodiment, the set control signal G_enb maintains a low level when the charge pump circuit is in an idle state, the discharge switch tubes M19 and M20 are turned on, and the control terminal voltage Aga of the charge transfer tube M1 and the control terminal voltage Agb of the charge transfer tube M2 are set to the voltage of the ground terminal Vss; the set control signal G_enb maintains a high level when the charge pump circuit is in an operating state, the discharge switch tubes M19 and M20 are turned off, and the set module 32 does not affect the operation of the switch capacitor module 11.

[0074] In some embodiments of the present disclosure, reference Figure 6 or Figure 7 A first input terminal of the setting control unit 311 or 321 receives the first control signal OSC_en, a second input terminal of the setting control unit 311 or 321 is connected to the second voltage source Vdd1, and a third input terminal of the setting control unit 311 or 321 is connected to the ground terminal Vss. When the charge pump circuit is in an idle state or an operating state, the first control signal OSC_en maintains different levels.

[0075] In the embodiments of the present disclosure, reference Figure 6The setting control unit 311 includes an inverter, a first capacitor Ccoup, a first MOS transistor M21, a second MOS transistor M22, and a third MOS transistor M23. The inverter receives a first control signal OSC_en and generates a first setting enable signal P_en and a second setting enable signal P_enb; the first setting enable signal P_en and the second setting enable signal P_enb are mutually inverted. The first plate of the first capacitor Ccoup receives the second setting enable signal P_enb. The gates of the first MOS transistor M21 and the second MOS transistor M22 receive the first setting enable signal P_en. The first terminal of the first MOS transistor M21, the first terminal of the second MOS transistor M22, and the control terminal of the third MOS transistor M23 are connected. The second terminal of the first MOS transistor M21 is connected to the ground terminal Vss, and the first terminal of the third MOS transistor M23 is connected to the second voltage source Vdd1. The second plate of the first capacitor Ccoup, the second end of the second MOS transistor M22 and the second end of the third MOS transistor M23 are all connected to the output end of the setting control unit 311 .

[0076] In the embodiments of the present disclosure, reference Figure 6 When the charge pump circuit is in operation, the first control signal OSC_en is high. Consequently, the second set enable signal P_enb is low, and the first set enable signal P_en is high. Consequently, the second MOS transistor M22 is turned off, and the first MOS transistor M21 is turned on. Furthermore, the potential of the ground terminal Vss is transmitted through the first MOS transistor M21 to the control terminal of the third MOS transistor M23, turning on the third MOS transistor M23. Furthermore, the potential of the second voltage source Vdd1 is transmitted through the third MOS transistor M23 to the set control signal G_en. Consequently, the voltages across the first capacitor Ccoup are the second set enable signal P_enb (low, 0V) and the set control signal G_en (lower, Vdd1), respectively.

[0077] For further reference, Figure 6The charge pump circuit switches from an operating state to an idle state, and the first control signal OSC_en switches from a high level to a low level. Furthermore, the second set enable signal P_enb switches from a low level to a high level, and the first set enable signal P_en switches from a high level to a low level. This turns on the second MOS transistor M22, turning off the first MOS transistor M21. Simultaneously, the voltage at one end of the first capacitor Ccoup (the second set enable signal P_enb) changes from low to high, causing the voltage at the other end of the first capacitor Ccoup (the set control signal G_en) to couple to a high voltage (Vcc + Vdd1). Furthermore, the turned-on second MOS transistor M22 transmits the high-voltage set control signal G_en to the control terminal of the third MOS transistor M23, causing it to shut down. This blocks the high-voltage set control signal G_en from discharging to the second voltage source Vdd1, thereby maintaining the high voltage of the set control signal G_en over a long period of time. That is, when the charge pump circuit is in an idle state, the first control signal OSC_en is maintained at a low level, the difference between the voltage value of the set control signal G_en and the voltage value of the discharge source (i.e., the first voltage source Vcc) is equal to the voltage value of the second voltage source Vdd1, and the set control signal G_en can be maintained at a high voltage of Vcc+Vdd1.

[0078] Continue to refer Figure 6 When the charge pump circuit is in an idle state, even though the first terminals of the discharge switches M19 and M20 are connected to the first voltage source Vcc and have a higher voltage, the voltage at the control terminals of the discharge switches M19 and M20 (i.e., the set control signal G_en) can still be higher than the voltage at the first terminals of the discharge switches M19 and M20. Therefore, when the charge pump circuit is in an idle state, the discharge switches M19 and M20 can be fully turned on, ensuring that the control terminals of the charge transfer transistors M1 and M2 are fully conductive to the first voltage source Vcc. Consequently, the voltage Aga at the control terminal of the charge transfer transistor M1 and the voltage Agb at the control terminal of the charge transfer transistor M2 are set to the voltage of the first voltage source Vcc, keeping the charge transfer transistors M1 and M2 in an off state. This reduces reverse leakage in the charge transfer path, lowers the power consumption of the charge pump circuit, and improves the power efficiency of the charge pump circuit.

[0079] In the embodiments of the present disclosure, reference Figure 7The setting control unit 321 includes an inverter, a first capacitor Ccoup, a first MOS transistor M21, a second MOS transistor M22, and a third MOS transistor M23. The inverter receives a first control signal OSC_en. The inverter generates a first setting enable signal P_enb and a second setting enable signal P_en. The first setting enable signal P_enb and the second setting enable signal P_en are mutually inverted. The first plate of the first capacitor Ccoup receives the second setting enable signal P_en. The gate of the first MOS transistor M21 and the gate of the second MOS transistor M22 receive the first setting enable signal P_enb. The first terminal of the first MOS transistor M21, the first terminal of the second MOS transistor M22, and the control terminal of the third MOS transistor M23 are connected. The second terminal of the first MOS transistor M21 is connected to the second voltage source Vdd1, and the first terminal of the third MOS transistor M23 is connected to the ground terminal Vss. The second plate of the first capacitor Ccoup, the second end of the second MOS transistor M22 and the second end of the third MOS transistor M23 are all connected to the output end of the setting control unit 311 .

[0080] In the embodiments of the present disclosure, reference Figure 7 When the charge pump circuit is in operation, the first control signal OSC_en is high. Consequently, the second set enable signal P_en is high, and the first set enable signal P_enb is low. Consequently, the second MOS transistor M22 is turned off, and the first MOS transistor M21 is turned on. Furthermore, the potential of the second voltage source Vdd1 is transmitted through the first MOS transistor M21 to the control terminal of the third MOS transistor M23, turning on the third MOS transistor M23. Furthermore, the potential of the ground terminal Vss is transmitted through the third MOS transistor M23 to the set control signal G_en. Consequently, the voltages across the first capacitor Ccoup are the second set enable signal P_enb (high, Vdd1) and the set control signal G_en (low, Vss), respectively.

[0081] For further reference, Figure 7The charge pump circuit switches from an operating state to an idle state. The first control signal OSC_en switches from a high level to a low level. Furthermore, the second set enable signal P_en switches from a high level to a low level, and the first set enable signal P_enb switches from a low level to a high level. This turns on the second MOS transistor M22, turning off the first MOS transistor M21. Simultaneously, the voltage at one end of the first capacitor Ccoup (the second set enable signal P_en) changes from high to low, causing the voltage at the other end of the first capacitor Ccoup (the set control signal G_en) to couple to a lower negative voltage (-Vdd1). Consequently, the turned-on second MOS transistor M22 transmits the negative set control signal G_en to the control terminal of the third MOS transistor M23, causing it to turn off. This blocks the negative set control signal G_en from discharging to the ground terminal Vss, thus maintaining the negative voltage of the set control signal G_en over a long period of time. That is, when the charge pump circuit is in an idle state, the first control signal OSC_en is maintained at a low level, the difference between the voltage value of the set control signal G_en and the voltage value of the discharge source (i.e., the ground terminal Vss) is equal to the voltage value of the second voltage source Vdd1, and the set control signal G_en can be maintained at a negative voltage of -Vdd1.

[0082] Continue to refer Figure 7 When the charge pump circuit is in an idle state, even though the first terminals of the discharge switches M19 and M20 are connected to the ground terminal Vss and have a relatively low voltage, the voltage at the control terminals of the discharge switches M19 and M20 (i.e., the set control signal G_en) can still be lower than the voltage at the first terminals of the discharge switches M19 and M20. Consequently, when the charge pump circuit is in an idle state, the discharge switches M19 and M20 can be fully turned on, ensuring full conduction between the control terminals of the charge transfer transistors M1 and M2 and the ground terminal Vss. Consequently, the voltage Aga at the control terminal of the charge transfer transistor M1 and the voltage Agb at the control terminal of the charge transfer transistor M2 are set to the voltage of the ground terminal Vss, allowing the charge transfer transistors M1 and M2 to remain in an off state. This reduces reverse leakage in the charge transfer path, lowers the power consumption of the charge pump circuit, and improves the power efficiency of the charge pump circuit.

[0083] In the embodiments of the present disclosure, reference Figure 6 and Figure 7 To ensure that the set control signal G_en is not interfered with, the components of the set modules 31 and 32 can be placed away from other components or interference sources. Thus, when the charge pump circuit is in an idle state, the charge transfer transistors M1 and M2 can be stably turned off and are not easily affected by external interference.

[0084] In the embodiments of the present disclosure, reference Figure 6 and Figure 7The first MOS transistor M21, the second MOS transistor M22, and the third MOS transistor M23 can be devices with extremely low leakage (e.g., pA-level leakage); at the same time, the first capacitor Ccoup can be a device with a capacitance of tens or even hundreds of pF (e.g., a nicap capacitor). In this way, the charge on the first capacitor Ccoup is discharged very slowly due to leakage. Thus, when the charge pump circuit is in an idle state, the set control signal G_en can be maintained for a long time, thereby greatly reducing the number of start-up times of the charge pump circuit, reducing the power consumption of the charge pump circuit, and improving the power consumption efficiency of the charge pump circuit.

[0085] The present disclosure also provides a memory device, such as Figure 8 As shown, the memory 80 includes a charge pump circuit 70. The charge pump circuit 70 includes the technical features of the above embodiments.

[0086] In the disclosed embodiment, the memory 80 may include a dynamic random access memory, such as DDR (double data rate synchronous dynamic random access memory) or LPDDR (low power double data rate synchronous dynamic random access memory). The charge pump in the DDR or LPDDR system needs to maintain its line voltage capability. The charge pump circuit 70 provided in the disclosed embodiment can reduce reverse leakage, lower power consumption, and improve power efficiency, thereby helping to reduce the power consumption of the DDR or LPDDR system.

[0087] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0088] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0089] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A charge pump circuit, characterized in that: The charge pump circuit includes: a switch capacitor module; the switch capacitor module includes: a transformer capacitor, a charge transfer tube and an output switch tube; The first end of the charge transfer tube is connected to a first voltage source, and the second end of the charge transfer tube is connected to the first plate of the variable capacitor; the charge transfer tube is configured to transfer charge from the first voltage source to the first plate of the variable capacitor; The first end of the output switch tube is connected to the first plate of the variable capacitor, and the second end of the output switch tube is connected to the output end of the charge pump circuit; the output switch tube is configured to transfer the charge on the first plate of the variable capacitor to the output end of the charge pump circuit; Wherein, the leakage current of the charge transfer tube in the off state is lower than the leakage current of the output switch tube in the off state; When the charge pump circuit is in an idle state, the charge transfer tube remains in a closed state under the action of the control terminal voltage.

2. The charge pump circuit according to claim 1, wherein: The charge pump circuit further includes: a clock signal generating module; the clock signal generating module includes: a first clock generating unit; The first clock generating unit outputs a first clock signal; the control terminal voltage of the charge transfer tube is controlled by the first clock signal; Wherein, when the charge pump circuit is in an idle state, the first clock signal is set to a first level, and the charge transfer tube remains in a closed state under the action of the control terminal voltage.

3. The charge pump circuit according to claim 2, wherein: The first clock generating unit includes: a main path configured to generate and transmit the first clock signal; The control unit is provided on the main path and is configured to set the first clock signal to a first level when the charge pump circuit is in an idle state.

4. The charge pump circuit according to claim 3, wherein: The control unit includes: a first logic gate; The first input end of the first logic gate receives the first control signal or the inverted signal of the first control signal; the second input end of the first logic gate and the output end of the first logic gate are connected to the main path; Wherein, when the charge pump circuit is in an idle state or a running state, the first control signal maintains different levels respectively.

5. The charge pump circuit according to claim 4, wherein: The control unit further includes: a driving unit; the driving unit includes: at least one inverter; The driving unit is connected to the first input terminal of the first logic gate.

6. The charge pump circuit according to claim 2, wherein: The clock signal generating module further includes: a second clock generating unit; The second clock generating unit generates a second clock signal; the second plate voltage of the variable capacitor is controlled by the second clock signal.

7. The charge pump circuit according to claim 6, wherein: There are two charge transfer tubes; there are two first clock signals; the control terminal voltage of each charge transfer tube is controlled by a corresponding first clock signal; The number of the variable voltage capacitors is two; The number of the second clock signals is two; the second plate voltage of each of the variable capacitors is controlled by a corresponding second clock signal; Wherein, when the charge pump circuit is in operation, the two first clock signals are in opposite phases and do not overlap with each other, and the two second clock signals are in opposite phases and do not overlap with each other.

8. The charge pump circuit according to claim 1, wherein: The charge pump circuit further includes: a setting module; The setting module is connected between the control end of the charge transfer tube and the discharge source; The setting module is configured to connect the control terminal of the charge transfer tube to the discharge source when the charge pump circuit is in an idle state.

9. The charge pump circuit according to claim 8, wherein: The setting module includes: a discharge switch tube and a setting control unit; The output terminal of the setting control unit outputs a setting control signal; The first end of the discharge switch tube is connected to the control end of the charge transfer tube; the second end of the discharge switch tube is connected to the discharge source; the control end of the discharge switch tube is connected to the output end of the setting control unit to receive the setting control signal; Wherein, when the charge pump circuit is in an idle state or a running state, the setting control signal maintains different levels respectively.

10. The charge pump circuit according to claim 9, wherein: The first input terminal of the setting control unit receives a first control signal; the second input terminal of the setting control unit is connected to a second voltage source; and the third input terminal of the setting control unit is connected to a ground terminal; When the charge pump circuit is in an idle state or a running state, the first control signal maintains different levels respectively; When the charge pump circuit is in an idle state, a difference between a voltage value of the set control signal and a voltage value of the discharge source is equal to a voltage value of the second voltage source.

11. The charge pump circuit according to claim 10, wherein: The setting control unit includes: an inverter, a first capacitor, a first MOS transistor, a second MOS transistor and a third MOS transistor; The inverter receives the first control signal; the inverter generates a first set enable signal and a second set enable signal; the first set enable signal and the second set enable signal are inverted to each other; The first plate of the first capacitor receives the second set enable signal; The gate of the first MOS transistor and the gate of the second MOS transistor receive the first set enable signal; the first end of the first MOS transistor, the first end of the second MOS transistor and the control end of the third MOS transistor are connected; The second end of the first MOS transistor is grounded, and the first end of the third MOS transistor is connected to the second voltage source; or the second end of the first MOS transistor is connected to the second voltage source, and the first end of the third MOS transistor is grounded; The second plate of the first capacitor, the second end of the second MOS transistor, and the second end of the third MOS transistor are all connected to the output end of the setting control unit.

12. A memory, characterized in that: The memory comprises the charge pump circuit according to any one of claims 1 to 11.

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