Duty cycle calibration for phase locked loops

Abstract

This disclosure describes techniques relating to phase-locked loop (PLL) duty cycle calibration, i.e., duty cycle calibration for a phase-locked loop. In one embodiment, a circuit includes an amplifier to generate a level-converted clock having a duty cycle. The circuit also includes comparison logic coupled to an output of the amplifier, the comparison logic comparing the duty cycle to a target duty cycle and generating a difference. Tuning logic coupled to the amplifier adjusts the duty cycle based on the difference.

Description

Technical Field

[0001] The present disclosure relates to the technical field of phase-locked loops (PLLs), and in particular to a duty cycle calibration technology for phase-locked loops. Background Art

[0002] A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of the input signal. In many cases, the output signal generated by the PLL is a clock with a duty cycle. For some applications using a PLL, a certain duty cycle may be desired for the clock output by the PLL for reasons such as power consumption, signal integrity, heat dissipation, or clock frequency. In other applications, a precise duty cycle of the clock output by the PLL may be required due to design constraints. Summary of the Invention

[0003] One aspect of the present disclosure provides a circuit comprising: an amplifier to receive an oscillator clock having a first duty cycle and output a level-converted clock having a second duty cycle; tuning logic coupled to the amplifier; and comparison logic coupled between the output of the amplifier and the tuning logic, wherein the comparison logic is configured to generate a difference value based on a difference between the second duty cycle and a target duty cycle; and wherein the tuning logic is configured to adjust the second duty cycle generated by the amplifier based on the difference value.

[0004] Another aspect of the present disclosure provides a phase-locked loop, comprising: an oscillator for generating an oscillator clock having a first duty cycle; an amplifier coupled to the oscillator, wherein the amplifier is configured to receive the oscillator clock and output a level-converted clock having a second duty cycle; tuning logic coupled to the amplifier; and comparison logic coupled between an output of the amplifier and the tuning logic, wherein the comparison logic is configured to generate a difference value based on a difference between the second duty cycle and a target duty cycle; and wherein the tuning logic is configured to adjust the second duty cycle generated by the amplifier based on the difference value.

[0005] Another aspect of the present disclosure provides a method for operating a phase-locked loop circuit. The phase-locked loop circuit includes an amplifier, an oscillator coupled to the amplifier, tuning logic coupled to the amplifier, and comparison logic coupled between the amplifier and the tuning logic. The method for operating the PLL circuit includes: generating an oscillation clock having a first duty cycle by the oscillator; receiving the oscillation clock by the amplifier; outputting a level-converted clock having a second duty cycle by the amplifier; receiving the level-converted clock by the comparison logic; generating a difference value based on a comparison between the second duty cycle and a target duty cycle by the comparison logic; and adjusting the second duty cycle generated by the amplifier toward the target duty cycle by the tuning logic. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0007] Figure 1 Figure 1 is a simplified block diagram of a digital phase-locked loop (DPLL) used in some electronic devices.

[0008] Figure 2 is a block diagram illustrating a duty cycle tuning circuit within a phase-locked loop (PLL) according to one embodiment.

[0009] Figure 3 is a circuit diagram illustrating tuning logic and level shifters according to one embodiment.

[0010] Figure 4 is a circuit diagram illustrating comparison logic according to one embodiment.

[0011] Figure 5 A method of calibrating the duty cycle of a PLL according to one embodiment is shown. DETAILED DESCRIPTION

[0012] The following description sets forth many specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of various embodiments of circuits configured to calibrate the duty cycle in a phase-locked loop (PLL) as described herein. Such a PLL can be applied to Internet of Things (IoT) applications or any number of other applications such as home automation and security. However, it will be apparent to those skilled in the art that at least some embodiments can be implemented without these specific details. In other instances, well-known components, elements, or methods are not described in detail or presented in a simple block diagram format to avoid unnecessarily obscuring the subject matter described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the spirit and scope of the present embodiment.

[0013] References in the specification to "an embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" mean that a particular feature, structure, step, operation, or characteristic described in connection with the embodiment(s) is included in at least one embodiment. In addition, the appearance of the phrases "an embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" in various places in the specification do not necessarily refer to the same embodiment(s).

[0014] This specification includes reference to the accompanying drawings, which form part of the detailed description. The accompanying drawings show diagrams according to exemplary embodiments. These embodiments (which may also be referred to herein as "examples") are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0015] This paper describes techniques for calibrating the duty cycle of a phase-locked loop (PLL). In many PLL circuit applications, such as those in the Internet of Things (IoT), designers strive to generate a PLL output duty cycle as close to 50% as possible. Maintaining the duty cycle enables precise timing and frequency control, ensuring that high and low periods in the clock signal are equal, which enables reliable data transmission and synchronization between devices. In particular, maintaining a 50% duty cycle helps minimize power consumption in IoT devices and other applications, including battery-powered devices.

[0016] A conventional approach to implementing a clock with a 50% duty cycle involves designing a PLL at two ("2") times the target frequency and using a flip-flop-based divider to divide the frequency by two while ensuring that the high period of the output clock signal is equal to the low period of the output clock signal. However, using a flip-flop-based divider has significant power implications due to both dynamic power used during frequent switching and static power due to leakage current in the flip-flops that make up the divider.

[0017] Aspects and embodiments of the present disclosure introduce a power-efficient circuit for PLL duty cycle calibration, referred to herein as a duty cycle tuning circuit, that can control the duty cycle toward 50% or another target duty cycle without resorting to the inefficient and power-consuming method of doubling the PLL operating frequency. In various embodiments, the duty cycle tuning circuit includes comparison logic and tuning logic. The comparison logic compares the duty cycle of a signal output by the PLL with a target duty cycle. The tuning logic adjusts the duty cycle of the signal output by the PLL based on the output of the comparison logic. The tuning logic can adjust the duty cycle by modifying a bias voltage introduced into the signal output by the PLL. In some embodiments, a level shifter receives a first signal (e.g., a first clock) having a first duty cycle from an oscillator and level-shifts the first signal into a second signal having a second duty cycle. The second duty cycle can be compared to the target duty cycle by the comparison logic, thereby generating a difference. The tuning logic can use the difference to adjust the second duty cycle of the second signal generated by the level shifter.

[0018] Figure 1 FIG1 is a simplified block diagram of a digital phase-locked loop (DPLL) 100 used in certain electronic devices. As shown, DPLL 100 may include a phase detector (PD) and time-to-digital converter (TDC) 110, a digital loop filter (DLF) 120, an oscillator 130, a duty cycle tuning circuit 140, and a frequency divider 150 (e.g., a divide-by-N frequency divider), which are typically coupled together in a loop. In such a DPLL 100, the PD (of the PD & TDC 110) is adapted to detect the phase and frequency of an input reference clock (REFCLCK) and a feedback clock (FBCLK). Furthermore, in DPLL 100, the TDC of the PD & TDC 110 is configured to determine the time difference (e.g., phase error) between the reference frequency (Fref) of the input reference clock and the feedback frequency (Ffb) of the feedback clock.

[0019] The TDC of the PD&TDC 110 generates a multi-bit code that digitally encodes the time difference (e.g., quantized phase error) and is designed to trigger the oscillator 130 to adjust the output frequency (Fout) of the alternating current (AC) output signal of the DPLL 100. In some embodiments, the oscillator 130 is a digital oscillator (DCO). The oscillator 130 of the DPLL is typically implemented as a code-to-frequency circuit, wherein for each input code (e.g., a set of digital bits), the oscillator 130 has a unique output frequency. The DLF 120, coupled between the TDC and the oscillator 130, is configured to digitally filter the multi-bit code to ensure that each bit of the multi-bit code is accurately transmitted to the oscillator 130.

[0020] In at least some embodiments, the duty cycle tuning circuit 140 monitors and adjusts the duty cycle of the oscillating signal generated by the oscillator 130. To monitor the duty cycle, the duty cycle tuning circuit 140 can compare the duty cycle with a target duty cycle. If the duty cycle differs from the target duty cycle, the duty cycle tuning circuit 140 can change or modify the duty cycle to be as close to the target duty cycle as possible, for example, in a feedback control loop, which would refer to the Figures 2 to 5 Discuss in more detail.

[0021] Among various applications, DPLL 100 can be used in battery-powered consumer electronics, low-power wireless sensors, home automation systems, remote controls, and automotive memory control units (MCUs), for example, where low cost, low power, a reduced bill of materials (BOM), and smaller size are highly desirable. DLF 120 is typically implemented as an on-chip integrated loop filter to further keep the design smaller than its analog counterpart. Divider 150 divides the output frequency of the AC output signal by an integer value (N) to generate a feedback clock that flows back to PD&TDC 110. In some embodiments, when implementing duty cycle tuning circuit 140, divider 150 can be eliminated or the frequency division can be reduced to one-half ('2'). In this way, DPLL 100 does not need to be designed at twice the frequency so that divider 150 (or a different divider) can be used to adjust the frequency back to the original frequency with the tuned duty cycle. Therefore, the DPLL 100 is designed to operate in a feedback loop, where the time difference between the input reference clock and the feedback clock is minimized until "locked" to the frequency and phase of the input reference clock.

[0022] In many applications of DPLLs, the time it takes for the oscillator 130 to lock to the frequency / phase of the reference clock is called the lock time. The DPLL 100 typically goes through multiple iterations through the loop of the DPLL 100 for the oscillator 130 to finally achieve this lock.

[0023] Figure 2 is a block diagram illustrating a duty cycle tuning circuit 200 within a phase-locked loop (PLL) according to one embodiment. Circuit 200 may be an embodiment of duty cycle tuning circuit 140. In various embodiments, circuit 200 includes an oscillator 130 that generates an oscillating signal (e.g., an oscillator clock) that is sent to a level shifter 204. In one embodiment, oscillator 130 may be a ring oscillator. The oscillating signal may be a first clock signal. The first clock signal may be susceptible to variations in process, voltage, or temperature (PVT). PVT variations may be caused by factors such as manufacturing defects (e.g., semiconductor doping concentration, oxide thickness, etc.), power supply fluctuations, or temperature sensitivity. The first clock signal generated by oscillator 130 may have a first duty cycle that is also susceptible to PVT variations. Unless otherwise specified, when a duty cycle is expressed as a percentage (e.g., 52%), the duty cycle in this disclosure refers to the percentage at which the duty cycle is switched to "high." For example, a clock with a 75% duty cycle means a clock with a "high" duty cycle of 75% and a "low" duty cycle of 25%.

[0024] In some embodiments, the first clock signal is sent to a level shifter 204. The level shifter 204 may include one or more amplifiers and feedback resistors. The level shifter 204 may adjust the characteristics of the first clock signal toward a desired characteristic. For example, the level shifter may adjust one or more of the voltage level and the first duty cycle of the first clock signal. In some embodiments, it can be said that the level shifter 204 generates the second clock signal (e.g., a second oscillating signal) by adjusting the characteristics of the first duty cycle toward a desired characteristic. The level shifter 204 may adjust the characteristics of the first duty cycle by receiving a bias voltage from the tuning logic 202. In some embodiments, the tuning logic 202 may include a bias voltage generator. The bias voltage generator may generate a bias voltage that causes the level shifter 204 to adjust the first clock signal toward the desired characteristic. The bias voltage generator is explained in more detail below.

[0025] The bias voltage generator can generate a bias voltage based on the difference value provided by the comparison logic 206. The comparison logic 206 receives the second clock signal (e.g., the adjusted first clock signal) from the level shifter 204 and compares the second duty cycle of the second clock signal with the target duty cycle. The target duty cycle can be represented by a reference voltage (e.g., a direct current (DC) voltage). In some embodiments, the reference voltage can be a portion of the power supply voltage that corresponds to the target duty cycle. For example, if the target duty cycle is 50%, the reference voltage is half (or substantially half) of the power supply voltage. If the target duty cycle is 75%, the reference voltage is three-quarters of the power supply voltage.

[0026] The comparison logic 206 can compare the second duty cycle of the second clock signal to the target duty cycle by converting the second duty cycle to a DC voltage or a signal similar to a DC voltage (e.g., a DC voltage with negligible alternating current (AC) or noise). The comparison logic 206 can convert the second duty cycle to a first voltage by passing the second clock signal through a low-pass filter (LPF). The first voltage can be a portion of the power supply voltage corresponding to the second duty cycle, similar to how the reference voltage is a portion of the power supply voltage corresponding to the target duty cycle. Once the second duty cycle has been converted to the first voltage, the first voltage and the reference voltage are sent to the comparator.

[0027] Figure 33 is a circuit diagram 300 illustrating tuning logic 202 and level shifter 204 according to one embodiment. Level shifter 204 can be used to convert a first clock signal (e.g., an input signal) having a first amplitude received from an upstream oscillator into a second clock signal (e.g., an output signal) having a second amplitude. The second clock signal is then sent to downstream circuitry, such as comparison logic 206. In some embodiments, level shifter 204 can be an amplifier-based level shifter that uses (one or more) feedback resistors to set the gain and other operating characteristics of the amplifier. In these embodiments, level shifter 204 can include amplifier 302 and feedback resistor 304. Capacitor 306 can be coupled to the input of level shifter 204. Capacitor 306 can help prevent the DC bias of the upstream oscillator (e.g., oscillator 130) from reaching or being passed by amplifier 302.

[0028] When level shifting a clock signal from a first amplitude to a second amplitude, the duty cycle of the clock signal can be unintentionally changed in a variety of ways. First, the level shifter can be coupled to a capacitor to form a resistor-capacitor (RC) circuit. For example, as shown, amplifier 302, feedback resistor 304, and capacitor 306 can be coupled together to form an RC circuit. Therefore, the level-shifted clock signal generated by level shifter 204 can have a different frequency than the original clock signal received by level shifter 204. The change in frequency can change the duty cycle of the clock signal.

[0029] Second, a clock signal can be characterized as "high" or "low." Typically, a clock signal is "high" (e.g., enabled or on) when a predetermined voltage threshold is met, and is "low" (e.g., disabled or off) when the predetermined voltage threshold is not met. Thus, depending on the position of the predetermined voltage threshold (i) before and (ii) after the level shift, the proportion of the clock's duty cycle that is "high" may be modified unintentionally (or intentionally).

[0030] Third, a level shifter may introduce different delays for the rising edge (e.g., when the clock goes from "low" to "high") and the falling edge (e.g., when the clock goes from "high" to "low") of the clock signal. These delays can be caused by factors such as differences in the supply voltage and output side of the level shifter, the inherent capacitance of the level shifter, and the amount of time required to level shift from one voltage level to another. These delays can affect rising and falling edges differently, which can also affect the duty cycle of the level-shifted clock signal.

[0031] While the duty cycle of the level-shifted clock signal may be affected by any of the above examples, these examples are not exhaustive. Rather, the level shifter may affect the duty cycle of the level-shifted clock signal in a variety of ways, including the three examples above.

[0032] In some embodiments, it may be desirable to modify (e.g., change) the duty cycle of a clock signal via a level shifter. For example, the clock signal may have been generated by an oscillator (e.g., a ring oscillator) that is susceptible to some PVT variations. The duty cycle of such a clock signal may not be the same as or substantially similar to a target duty cycle (e.g., a target duty cycle). In these embodiments, it may be desirable to have the ability to intentionally modify the duty cycle to be the same as or substantially similar to the target duty cycle.

[0033] In the example shown, level shifter 204 level shifts a first clock signal (e.g., an input signal) having a first frequency and a first duty cycle into a second clock signal (e.g., an output signal) having a second frequency and a second duty cycle. Capacitor 306 is combined with level shifter 204 to create an RC circuit that causes the second frequency to be different from the first frequency. After level shifting the first clock signal to the second clock signal, the second duty cycle may not be the same as or substantially similar to the target duty cycle. This may be caused by (i) PVT variations caused by an upstream oscillator (e.g., oscillator 130) or (ii) the conversion from the first clock signal to the second clock signal.

[0034] In various embodiments, the tuning logic 202 is coupled to the level shifter 204 and is configured to adjust the second duty cycle of the second clock cycle based on a difference between the second duty cycle and the target duty cycle. The difference may be represented by a difference value. In some embodiments, the difference value may be based on the output of the comparison logic 206. In other embodiments, the comparison logic 206 may output the difference value. Figure 4 The comparison logic 206 is explained in more detail.

[0035] In some embodiments, the tuning logic 202 includes a low-power bias generator 308 configured to generate a bias voltage. In some embodiments, the feedback resistor 304 is a potentiometer (e.g., a trimmer potentiometer) that is tapped at various locations along the resistive component, thereby enabling the resistance of the feedback resistor to be adjusted. In at least some embodiments, the bias voltage generated by the low-power bias generator 308 is provided to the level shifter 204 at a tap location on the feedback resistor 304. The tap location can be adjusted based on the difference. For example, the low-power bias generator 308 can be coupled to a wiper terminal of the potentiometer. In another embodiment, the feedback resistor 304 can be adjusted based on the difference according to instructions from a controller (e.g., a microcontroller). The potentiometer can be iteratively adjusted (e.g., multiple times) until the second duty cycle (from the output of the comparison logic 206) is the same as or similar to the target duty cycle. Notwithstanding the above description regarding a potentiometer, any implementation that allows the low power bias generator 308 to be coupled to the feedback resistor 304 at an adjustable tap position may be used.

[0036] In some embodiments, the low-power bias generator 308 can generate and / or adjust a bias voltage based on the difference. For example, the bias voltage can be increased or decreased based on the difference. In some embodiments, a controller or other logic can increase or decrease the bias voltage based on the difference. The low-power bias generator 308 can iteratively increase or decrease the bias voltage until the second duty cycle is the same as or similar to the target duty cycle.

[0037] In some implementations, a combination of (i) adjusting the tap position at which the bias voltage is introduced into the feedback resistor 304 and (ii) adjusting the bias voltage based on the difference may be used.

[0038] Figure 4 is a circuit diagram illustrating comparison logic 206 according to one embodiment. In at least some embodiments, comparison logic 206 includes a reference voltage generator 402. Reference voltage generator 402 can receive a supply voltage of the circuit and generate a reference voltage that, when compared with the supply voltage, correlates with (e.g., corresponds to) a target duty cycle. In other words, the reference voltage can be a portion of the supply voltage that is proportional to the target duty cycle. For example, if the target duty cycle is 50%, reference voltage generator 402 generates a reference voltage that is half the supply voltage. As another example, if the target duty cycle is 75%, reference voltage generator 402 generates a reference voltage that is three-quarters the supply voltage.

[0039] In various embodiments, the comparison logic 206 further includes a low pass filter (LPF) 404. The LPF 404 may receive an oscillating signal from an upstream circuit system and output a first voltage. In some embodiments, the oscillating signal received by the LPF 404 is as described above with reference to Figures 2 to 3 In response to receiving the second clock signal, LPF 404 can be designed such that the first voltage, when compared to the power supply voltage, corresponds to the second duty cycle of the second clock signal. In other words, the first voltage can be a portion of the power supply voltage that is proportional to the second duty cycle. For example, if the second duty cycle is 25%, the first voltage is one-quarter of the power supply voltage. As another example, if the second duty cycle is 50%, the first voltage is half of the power supply voltage.

[0040] In some embodiments, once the first voltage is generated by passing the second clock signal through LPF 404, the reference voltage is compared to the first voltage at comparator 408. Comparator 408 determines whether the first voltage is (i) greater than, (ii) less than, or (iii) substantially equal to the reference voltage. In some embodiments, to determine (iii) substantially equal to the reference voltage, comparator 408 may determine that the first voltage is within a target voltage range around the reference voltage. In these embodiments, comparator 408 may include a hysteresis comparator or a Schmitt trigger. A hysteresis comparator may include a gap around the comparator's threshold to provide hysteresis, thereby preventing rapid switching of the output due to changes in the hysteresis comparator's input. For example, if the reference voltage is 50% of the power supply voltage, comparator 408 may determine that the first voltage is substantially equal to the reference voltage if the first voltage is not less than 48% and not greater than 52% of the power supply voltage. This, in turn, indicates that the target duty cycle is 50% and the second duty cycle of the second clock is between 48% and 52%. This example assumes that the error tolerance of the second duty cycle is within 2% of the target duty cycle. However, the error tolerance of the second duty cycle can be set to different values, such as 1%, 0.5% or 5%, depending on the requirements of the PLL.

[0041] If the comparator 408 determines that the first voltage is not substantially equal to the reference voltage, a difference value can be calculated based on the digital output 208. The digital output 208 represents the difference between the first voltage and the reference voltage, which in turn represents the difference between the second duty cycle and the target duty cycle. The comparator 408 can output the digital output 208. The digital output 208 can be the difference value. The difference value can be sent from the comparator 408 to the tuning logic 202. The tuning logic 202 can include a controller (e.g., a microcontroller) that receives the difference value and adjusts the second duty cycle of the second clock signal based on the difference value.

[0042] In some embodiments, comparator 408 is a low-offset comparator having a first input 410a and a second input 410b. Typically, a low-offset comparator is designed to have a very small input offset voltage, typically in the microvolt range, which enables it to accurately compare voltages that are very close to each other. This is different from a conventional comparator, which may have a higher input offset voltage, resulting in lower accuracy in detecting small differences between input voltages. Low-offset comparator 408 can be particularly useful in applications requiring high precision, such as in a PLL.

[0043] In at least some embodiments, comparison logic 206 also includes a switching circuit 406 that receives the reference voltage from reference voltage generator 402 and the first voltage from LPF 404. Comparison logic 206 may include switching circuit 406 to alternately switch the reference voltage and the first voltage between a first input 410a and a second input 410b. This may, for example, provide offset cancellation for comparison logic 206. Switching circuit 406 may be coupled to inputs 410a and 410b to reduce noise and improve the accuracy and overall resolution of the voltage comparison of comparator 408. For example, switching circuit 406 may reset or correct any voltage drift or surges. Each time the input of switching circuit 406 switches between the first voltage and the reference voltage, digital output 208 may invert. This inversion may be managed by a controller that receives digital output 208. For example, the controller may be a programmed processor, a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, or other logic responsible for inverting and optionally using the output voltage with an adjusted duty cycle. In some embodiments, such a controller or other circuitry that receives an output voltage with an adjusted duty cycle generates a stable clock from a relatively unstable signal. Other applications for the DPLL 100 include, but are not limited to, frequency synthesis, data recovery, jitter reduction, modulation and demodulation of other signals, and other frequency control and signal generation applications.

[0044] Figure 5 FIG. 5 shows a method 500 for calibrating the duty cycle of a signal within a PLL according to one embodiment. The method 500 may be performed by Figure 2 The circuit 200 together with Figures 3 and 4 The operations do not need to be performed in a specific order unless explicitly disclosed as requiring such order.

[0045] At operation 502 , the method 500 includes generating, by the oscillator 130 , an oscillating clock having a first duty cycle.

[0046] At operation 504 , the method 500 further includes receiving an oscillating clock by the amplifier 302 of the level shifter 204 .

[0047] At operation 506 , the method 500 further includes outputting, by the amplifier 302 of the level shifter 204 , the level shifted clock having the second duty cycle.

[0048] At operation 508 , the method 500 further includes receiving, by the comparison logic 206 , the level-shifted clock.

[0049] At operation 510 , the method 500 further includes generating, by the comparison logic 206 , a difference value based on the comparison of the second duty cycle to the target duty cycle.

[0050] At operation 512 , the method 500 further includes adjusting, by the tuning logic 202 , the second duty cycle generated by the amplifier toward the target duty cycle.

[0051] Various embodiments of the duty cycle of the calibration PLL internal signal described herein can include various operations. These operations can be performed and / or controlled by hardware components, digital hardware and / or firmware, and / or their combination. As used herein, the term "coupled to" can mean being directly connected to or indirectly connected through one or more intermediate components. Any signal provided by various on-chip buses can be time-multiplexed with other signals and provided by one or more public on-chip buses. In addition, the interconnection between circuit components or blocks can be shown as a bus or a single signal line. Each of the bus can alternatively be one or more single signal lines, and each of the single signal lines can alternatively be a bus.

[0052] Certain embodiments may be implemented by firmware instructions stored on a non-transitory computer-readable medium (e.g., such as volatile memory and / or non-volatile memory). These instructions may be used to program and / or configure one or more devices including a processor (e.g., a CPU) or its equivalent (e.g., such as a processing core, a processing engine, a microcontroller, etc.) so that when executed by (one or more) processors or their equivalents, the instructions cause (one or more) devices to perform the operations described herein for the USB-C mode conversion architecture. Non-transitory computer-readable storage media may include, but are not limited to, electromagnetic storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or other non-transitory types of media suitable for storing information, now known or later developed.

[0053] Although the operations of the circuit(s) and block(s) are shown and described herein in a particular order, in some embodiments, the order of operations of each circuit / block may be changed so that certain operations may be performed in reverse order, or so that certain operations may be performed at least partially simultaneously and / or in parallel with other operations. In other embodiments, instructions or sub-operations of different operations may be performed in an intermittent and / or alternating manner.

[0054] In the foregoing description, the present invention has been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The description and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A circuit comprising: an amplifier to receive an oscillator clock having a first duty cycle and output a level-shifted clock having a second duty cycle; tuning logic coupled to the amplifier; as well as comparison logic coupled between an output of the amplifier and the tuning logic, wherein the comparison logic is configured to generate a difference value based on a difference between the second duty cycle and a target duty cycle; and The tuning logic is configured to adjust the second duty cycle generated by the amplifier based on the difference.

2. The circuit according to claim 1, wherein The comparison logic includes a low pass filter (LPF) for receiving the level-shifted clock and generating a first voltage proportional to the second duty cycle, and wherein the comparison logic is for comparing the first voltage with a reference voltage associated with the target duty cycle.

3. The circuit according to claim 2, wherein The first voltage generated by the LPF is a first fraction of a power supply voltage, and wherein the first fraction corresponds to the second duty cycle.

4. The circuit according to claim 2, wherein The comparison logic also includes: a low-offset comparator comprising a first input terminal and a second input terminal, wherein the low-offset comparator is configured to compare a voltage at the first input terminal with a voltage at the second input terminal; and A switching circuit is coupled between the LPF and the low-offset comparator, wherein the switching circuit is configured to alternately switch the first voltage and the reference voltage between the first input terminal and the second input terminal.

5. The circuit according to claim 1, wherein The target duty cycle is comprised between 48% and 52%.

6. The circuit of claim 1 , further comprising a feedback resistor coupled between the output of the amplifier and the input of the amplifier, the feedback resistor being tapped to receive a bias voltage, and wherein The tuning logic is configured to generate the bias voltage based on the difference.

7. The circuit of claim 1 , further comprising a feedback resistor coupled between the output of the amplifier and the input of the amplifier, the feedback resistor being tapped to receive a bias voltage, and wherein The position at which the feedback resistor is tapped is adjusted based on the difference.

8. A phase-locked loop (PLL), comprising: an oscillator for generating an oscillator clock having a first duty cycle; an amplifier coupled to the oscillator, wherein the amplifier is configured to receive the oscillator clock and output a level-shifted clock having a second duty cycle; tuning logic coupled to the amplifier; and comparison logic coupled between an output of the amplifier and the tuning logic, wherein the comparison logic is configured to generate a difference value based on a difference between the second duty cycle and a target duty cycle; and The tuning logic is configured to adjust the second duty cycle generated by the amplifier based on the difference.

9. The PLL according to claim 8, wherein The comparison logic includes a low pass filter (LPF) for receiving the level-shifted clock and generating a first voltage proportional to the second duty cycle, and wherein the comparison logic is for comparing the first voltage with a reference voltage associated with the target duty cycle.

10. The PLL of claim 9, wherein: The first voltage generated by the LPF is a first portion of a power supply voltage, and wherein the first portion corresponds to the second duty cycle.

11. The PLL of claim 9, wherein: The comparison logic also includes: a low-offset comparator comprising a first input terminal and a second input terminal, wherein the low-offset comparator is configured to compare a voltage at the first input terminal with a voltage at the second input terminal; and A switching circuit is coupled between the LPF and the low-offset comparator, wherein the switching circuit is configured to alternately switch the first voltage and the reference voltage between the first input terminal and the second input terminal.

12. The PLL of claim 8, wherein: The target duty cycle is comprised between 48% and 52%.

13. The PLL of claim 8, further comprising a feedback resistor coupled between the output of the amplifier and the input of the amplifier, the feedback resistor being tapped to receive a bias voltage, and wherein The tuning logic is configured to generate the bias voltage based on the difference.

14. The PLL of claim 8, further comprising a feedback resistor coupled between the output of the amplifier and the input of the amplifier, the feedback resistor being tapped to receive a bias voltage, and wherein The position at which the feedback resistor is tapped is adjusted based on the difference.

15. The PLL of claim 8, wherein: The oscillator is a ring oscillator.

16. A method of operating a phase-locked loop (PLL) circuit, the circuit comprising an amplifier, an oscillator coupled to the amplifier, tuning logic coupled to the amplifier, and comparison logic coupled between the amplifier and the tuning logic, the method of operating the PLL circuit comprising: generating an oscillation clock having a first duty cycle by the oscillator; receiving the oscillation clock by the amplifier; outputting, by the amplifier, a level-converted clock having a second duty cycle; receiving, by the comparison logic, the level-converted clock; generating, by the comparison logic, a difference value based on a comparison of the second duty cycle with a target duty cycle; as well as The second duty cycle generated by the amplifier is adjusted toward the target duty cycle by the tuning logic.

17. The method according to claim 16, wherein: Generating the difference includes: Inputting the level-converted clock into a low-pass filter LPF; outputting a first voltage proportional to the second duty cycle from the LPF; and The first voltage is compared to a reference voltage associated with the target duty cycle.

18. The method according to claim 17, wherein The comparison logic further includes a switching circuit and a low-offset comparator, the low-offset comparator including a first input terminal and a second input terminal, and wherein comparing the first voltage to the reference voltage includes: comparing the voltage at the first input terminal and the voltage at the second input terminal by the low offset comparator; receiving, by the switching circuit, the first voltage and the reference voltage; and The switching circuit alternately switches the first voltage and the reference voltage between the first input terminal and the second input terminal.

19. The method according to claim 16, wherein The target duty cycle is comprised between 48% and 52%.

20. The method according to claim 16, wherein The PLL circuit also includes a feedback resistor coupled between the output of the amplifier and the input of the amplifier, the feedback resistor being tapped to receive a bias voltage, and wherein adjusting the second duty cycle toward the target duty cycle includes generating, by the tuning logic, the bias voltage based on the difference.

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