Vertical nonvolatile memory device and electronic device

Abstract

A vertical non-volatile memory device and an electronic device including the same are provided. The vertical nonvolatile memory device includes a plurality of cell strings, and each of the plurality of cell strings includes a channel layer, a charge tunneling layer disposed on the channel layer, a charge trapping layer disposed on the charge tunneling layer, a charge blocking layer disposed on the charge trapping layer, a gate electrode disposed on the charge blocking layer, and a boron nitride film disposed on the gate electrode, wherein the gate electrodes and the boron nitride films are alternately stacked.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0017538 filed on February 5, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a vertical nonvolatile memory device including a boron nitride film and an electronic apparatus including the vertical nonvolatile memory device. Background Art

[0004] Electronic devices and semiconductor devices are often manufactured by combining and connecting semiconductors with insulators and conductors. For example, after forming multiple unit devices on a semiconductor substrate, various integrated circuits can be manufactured by repeatedly stacking insulating layers and electrode lines on top.

[0005] However, in the process of manufacturing or operating the device, the temperature of the constituent layers may rise, and electric stress may occur due to the applied voltage / current. Accordingly, diffusion of materials (atoms) may occur between adjacent constituent layers, which may lead to degradation of device characteristics and reduction of reliability and durability. When the integration of the device increases, it may become more difficult to solve the problem due to the diffusion of materials between the constituent layers. In addition, even when there is no diffusion of materials, signal delays may occur due to mutual interference caused by the electric field between the wires of the device with high integration.

[0006] As the integration density of integrated circuits increases significantly, the distance between conductor patterns decreases. Consequently, parasitic capacitance between conductor patterns increases, which can lead to performance degradation in electronic devices. For example, parasitic capacitance can delay signal transmission in semiconductor devices. To reduce this parasitic capacitance, insulator materials with relatively low dielectric constants have been used as interlayer insulating films. Summary of the Invention

[0007] Some example embodiments provide a vertical nonvolatile memory device including a boron nitride film.

[0008] Some example embodiments provide electronic apparatuses including a vertical nonvolatile memory device including a boron nitride film.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented example embodiments of the disclosure.

[0010] According to an example embodiment of the present disclosure, a vertical non-volatile memory device includes a channel layer, a charge tunneling layer on the channel layer, a charge trapping layer on the charge tunneling layer, a charge blocking layer on the charge trapping layer, a gate electrode on the charge blocking layer, and a boron nitride film on the gate electrode, wherein the gate electrode and the boron nitride film are alternately stacked, and the boron nitride film has a dielectric constant of 4 or less and a Young's modulus of 60 GPa or greater at an operating frequency of 100 kHz.

[0011] The boron nitride film can have a thickness of 16 nm or less.

[0012] The boron nitride film may have a boron to nitrogen ratio of about 0.9 to about 1.1.

[0013] Boron nitride films can have a viscosity of approximately 1 g / cm 3 About 3g / cm 3 mass density.

[0014] Boron nitride films can have a 4mVcm -1 or larger breakdown field.

[0015] The boron nitride film may have a roughness of about 0.3 root mean square (RMS) to about 0.6 RMS.

[0016] The boron nitride film may have a hydrogen content of 10% or less.

[0017] The boron nitride film may have an amorphous structure or a nanocrystalline structure.

[0018] The charge blocking layer may include a first charge blocking layer and a second charge blocking layer, and the second charge blocking layer may include a fluorite-based material, a perovskite-based material, or a wurtzite-based material.

[0019] The fluorite-based material may include HfO 2 or ZrO 2 .

[0020] The fluorite-based material may further include a dopant, and the dopant includes at least one of Al, Ga, Co, Ni, Mg, In, La, Y, Nd, Sm, Er, Sr, Ba, Gd, Ge, N, or Si.

[0021] Perovskite-based materials may include materials having an ABO3 composition, where A and B are metallic elements.

[0022] The perovskite-based material may include at least one of PbZrO 3 , PbTiO 3 , BaTiO 3 , SrTiO 3 , or CaTiO 3 .

[0023] The wurtzite-based material may include at least one of AlN, GaN, InN, doped AlN, doped GaN, or doped InN.

[0024] The second charge blocking layer may have a thickness of about 1 nm to about 3 nm.

[0025] The vertical nonvolatile memory device may further include a diffusion preventing layer between the gate electrode and the charge blocking layer.

[0026] The diffusion prevention layer may include at least one of titanium (Ti), zirconium (Zr), vanadium (V), aluminum (Al), lanthanum (La), niobium (Nb) or tantalum (Ta), or include a nitride including at least one of titanium (Ti), zirconium (Zr), vanadium (V), aluminum (Al), lanthanum (La), niobium (Nb) or tantalum (Ta).

[0027] According to an example embodiment of the present disclosure, an electronic device includes a memory and a memory controller configured to control the memory to read data from the memory and / or write data on the memory, wherein the memory is a vertical non-volatile memory device including a plurality of cell strings, and each of the plurality of cell strings includes a channel layer, a charge tunneling layer on the channel layer, a charge trapping layer on the charge tunneling layer, a charge blocking layer on the charge trapping layer, a gate electrode on the charge blocking layer, and a boron nitride film on the gate electrode, wherein the gate electrode and the boron nitride film are alternately stacked, and wherein the boron nitride film has a dielectric constant of 4 or less at an operating frequency of 100 kHz and has a Young's modulus of 60 GPa or greater. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features and advantages of certain example embodiments of the present disclosure will become more apparent through the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a schematic view of a vertical nonvolatile memory device according to an example embodiment;

[0030] Figure 2 It is along Figure 1 a cross-sectional view of a memory string included in a vertical nonvolatile memory device taken along line AA′;

[0031] Figure 3 yes Figure 2 An enlarged view of area A;

[0032] Figures 4A to 4C is a cross-sectional view for illustrating a method of manufacturing a boron nitride film according to example embodiments;

[0033] Figure 5 and Figure 6 Each according to some exemplary embodiments Figure 2 An enlarged view of area A;

[0034] Figure 7 is a circuit diagram to which a vertical nonvolatile memory device is applied according to an example embodiment;

[0035] Figure 8 is a schematic block diagram of a display driver integrated circuit (DDI) and a display device including the DDI according to example embodiments;

[0036] Figure 9 is a block diagram of an electronic device according to an example embodiment;

[0037] Figure 10 is a block diagram of an electronic device according to an example embodiment;

[0038] Figure 11 is a conceptual diagram schematically illustrating a device architecture applicable to an electronic apparatus according to example embodiments; and

[0039] Figure 12 is a conceptual diagram schematically illustrating a device architecture applicable to an electronic apparatus according to another example embodiment. DETAILED DESCRIPTION

[0040] Reference will now be made in detail to some example embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this regard, the present example embodiments may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the disclosed example embodiments will be described below solely with reference to the accompanying drawings to explain various aspects. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Expressions such as "at least one of..." modify the entire list of elements when preceding a list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both represent A, B, C, or any combination thereof. Similarly, A and / or B represent A, B, or A and B.

[0041] Hereinafter, a vertical non-volatile memory device and an electronic device including the same according to various exemplary embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, like reference numerals denote like elements, and the dimensions of components in the drawings may be exaggerated for clarity and ease of explanation. While terms such as "first," "second," and the like may be used to describe various components, these components are not limited to these terms. These terms are used solely to distinguish one component from another.

[0042] Expressions used in the singular encompass expressions in the plural unless they have a significantly different meaning in the context. When a part "includes" an element, unless otherwise specified, another element may be further included rather than excluding the presence of another element. For ease of explanation, the size or thickness of the components in the drawings may be arbitrarily exaggerated. In addition, when a certain material layer is described as being arranged on a substrate or another layer, the material layer may be in contact with another layer, or a third layer may be present between the material layer and the other layer. In the embodiments, the materials constituting each layer are provided only as examples, and other materials may also be used.

[0043] Although the terms "same," "equal," or "identical" are used in the description of example embodiments, it should be understood that some imprecision may exist. Thus, when one element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0044] When the terms "about," "substantially," or "approximately" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. Furthermore, when the terms "about," "substantially," or "approximately" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but rather that the tolerance of the shape is within the scope of the present disclosure. Furthermore, regardless of whether a numerical value or shape is modified to "about" or "substantially," it should be understood that these values and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0045] Figure 1 is a schematic view of a vertical nonvolatile memory device according to example embodiments, Figure 2 It is along Figure 1 A cross-sectional view of a memory string included in a vertical nonvolatile memory device taken along line AA', and Figure 3 yes Figure 2 Magnified view of area A.

[0046] Reference Figure 1 , the vertical nonvolatile memory device 100 may include a plurality of cell strings CS arranged on a substrate 101. Each cell string CS may be arranged in a direction perpendicular to the substrate 101 (eg, Figure 1The plurality of cell strings CS may be arranged in various forms on the substrate 101. The gate electrodes 131 and the boron nitride films 132 may be alternately stacked on the substrate 101. The channel hole CH may penetrate the stack of the gate electrodes 131 and the boron nitride films 132 in a direction perpendicular to the substrate 101 (e.g., the z-axis direction). The channel hole CH may have, for example, a circular cross-section. However, the shape of the cross-section of the channel hole CH is not limited thereto.

[0047] In the cell string CS, a portion other than the gate electrode 131 and the boron nitride film 132 may also have a stacked structure of multiple cylindrical shells within the channel hole CH. However, the structure of the cell string CS is not limited thereto, and the cell string CS may have other shapes and structures.

[0048] The substrate 101 may include a single crystal silicon substrate, a compound semiconductor substrate, or a silicon-on-insulator (SOI) substrate. However, the present disclosure is not limited thereto. The substrate 101 may also include an impurity region due to doping, electronic devices such as transistors, and peripheral circuits for selecting and controlling memory cells for storing data.

[0049] refer to Figure 2 The cell string CS may include a plurality of memory cells MC stacked in a direction (z-axis direction) perpendicular to the substrate 101. The memory cell MC may be a basic unit cell for writing or deleting data.

[0050] The cell string CS may include a pillar 121 extending in a direction perpendicular to the substrate 101, a channel layer 122 arranged on the pillar 121, a charge tunneling layer 124 arranged on the channel layer 122, a charge trapping layer 126 arranged on the charge tunneling layer 124, a charge blocking layer CB arranged on the charge trapping layer 126, and a gate electrode 131 arranged on the charge blocking layer CB.

[0051] The pillar 121 may include, for example, silicon oxide, air, etc. However, the present disclosure is not limited thereto. Each of the channel layer 122 , the charge tunneling layer 124 , and the charge trap layer 126 may extend in a direction perpendicular to the substrate 101 and may be shared by a plurality of memory cells MC.

[0052] The channel layer 122 may include a semiconductor material. The channel layer 122 may include, for example, Si, Ge, SiGe, or a III-V semiconductor. In some example embodiments, the channel layer 122 may include, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) semiconductor material, a quantum dot, or an organic semiconductor. The oxide semiconductor may include, for example, InGaZnO. The 2D semiconductor material may include a transition metal dichalcogenide (TMD) or graphene, and the quantum dots may include colloidal quantum dots, a nanocrystal structure, etc. The 2D semiconductor material may refer to a semiconductor material having a 2D crystal structure and may have a single layer or a multilayer structure. The 2D material may have excellent electrical properties and may be a material suitable for various devices because it maintains high mobility even in nanometer-scale thickness without any significant change in electrical properties. Each layer comprising such a 2D semiconductor material may have an atomic-level thickness. The channel layer 122 may include one to ten 2D semiconductor material layers.

[0053] 2D semiconductor materials may include, for example, at least one of graphene, black phosphorus, or TMD. Graphene is a material having a hexagonal honeycomb structure of carbon atoms bonded in a 2D manner and may have higher electrical mobility and better thermal properties than silicon (Si). Graphene may also be chemically stable and have a wide surface area. Black phosphorus is a material in which black phosphorus atoms are bonded to each other in a 2D manner.

[0054] TMDs may be represented by, for example, MX2, where M represents a transition metal and X represents a chalcogen element. For example, M may include Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, or Re, and X may include S, Se, or Te. Thus, TMDs may include, for example, MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReS2, and the like.

[0055] The 2D semiconductor material may include CuS, which is a compound of Cu as a transition metal and S as a chalcogenide element. The 2D semiconductor material may be a chalcogenide material including a non-transition metal. The non-transition metal may include, for example, Ga, In, Sn, Ge, Pb, etc. In this case, the 2D semiconductor material may include a compound of a non-transition metal such as Ga, In, Sn, Ge, Pb, etc. and a chalcogenide element such as S, Se, Te, etc. For example, the 2D semiconductor material may include SnSe2, GaS, GaSe, GaTe, GeSe, In2Se3, InSnS2, etc. However, the aforementioned materials are merely examples, and other materials may be used as the 2D semiconductor material.

[0056] The channel layer 122 may further include a dopant. The dopant may include a p-type dopant and an n-type dopant. The p-type dopant may include a Group III element such as B, Al, Ga, In, etc., and the n-type dopant may include a Group V element such as P, As, Sb, etc.

[0057] The charge tunneling layer 124 may be a layer in which charge tunneling occurs, and may include, for example, silicon oxide or metal oxide. However, the present disclosure is not limited thereto.

[0058] The gate electrodes 131 may be stacked apart from each other in a direction perpendicular to the substrate 101, and the boron nitride film 132 may be disposed between the gate electrodes 131. The boron nitride film 132 may electrically separate the gate electrodes 131 so that each of the gate electrodes 131 is independently driven in units of memory cells MC. Figure 1 The source and drain electrodes are not shown, but Figure 2 Illustrated are a source electrode 110 and a drain electrode 140. The source electrode 110 may be disposed below the channel layer 122, and the drain electrode 140 may be disposed on the channel layer 122. The drain electrode 140 may be connected to a bit line (not shown).

[0059] although Figure 2 The source electrode 110 is illustrated as being connected to each cell string CS, but the source electrode 110 may be commonly connected to the cell strings CS. Figure 2 It is illustrated that the charge blocking layer CB includes a single layer for convenience, but the present disclosure is not limited thereto, and the charge blocking layer CB may include a plurality of layers.

[0060] Figure 3 yes Figure 2 Magnified view of area A.

[0061] The channel layer 122 may be arranged around a lateral surface of the pillar 121 , the charge tunneling layer 124 may be arranged around a lateral surface of the channel layer 122 , the charge capture layer 126 may be arranged around a lateral surface of the charge tunneling layer 124 , and the charge blocking layer CB may be arranged around a lateral surface of the charge capture layer 126 .

[0062] In addition, the gate electrodes 131 and the boron nitride films 132 may be alternately arranged along the side surface of the charge blocking layer CB. Each channel corresponding to the gate electrodes 131 may be formed in the channel layer 122 between the source electrode 110 and the drain electrode 140. When a certain voltage is applied to the gate electrode 131 from each memory cell MC, the charges flowing between the source electrode 110 and the drain electrode 140 in the channel layer 122 corresponding to the gate electrode 131 may pass through the charge tunneling layer 124 and may be trapped in the charge trapping layer 126 to store information.

[0063] The gate electrode 131 can control the corresponding channel layer 122, and the word line can be electrically connected to the gate electrode 131. The gate electrode 131 may include a metal material with excellent conductivity, a conductive oxide, a metal nitride, silicon doped with impurities, a 2D conductive material, etc. The metal material may include, for example, Au, Ti, TiN, TaN, W, Mo, WN, Pt, Nb, NbN, Ni, or any combination thereof. The conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc. However, this is merely an example, and the gate electrode 131 may include various other materials. The boron nitride film 132 may serve as a spacer for insulation between the gate electrodes 131. The boron nitride film 132 may be configured to have a dielectric constant of 4 or less and a Young's modulus of 60 GPa or greater at an operating frequency of 100 kHz. The boron nitride film 132 may include an amorphous structure or a nanocrystalline structure. The boron nitride film 132 may have a Young's modulus of, for example, approximately 60 GPa to approximately 100 GPa. The boron nitride film 132 may have a thickness d2 of 16 nm or less. The thickness d2 may be a thickness in the stacking direction of the gate electrode 131 and the boron nitride film 132 (eg, Figure 1 ( z-direction thickness in ). Since the boron nitride film 132 has a very thin thickness while having a relatively high Young's modulus, when the boron nitride film has a lattice structure with a very thin thickness during the manufacturing process of the vertical non-volatile memory device, the lattice structure can be supported due to the high Young's modulus. The boron nitride film 132 can have a thickness d2 of, for example, about 1 nm to about 16 nm. The boron nitride film 132 can have a thickness less than or equal to the thickness of the gate electrode 131. The ratio (d2 / d1) of the thickness d2 of the boron nitride film 132 to the thickness d1 of the gate electrode 131 can be about 0.5 to about 1. The ratio (d2 / d1) of the thickness d2 of the boron nitride film 132 to the thickness d1 of the gate electrode 131 can be about 0.7 to about 1. The ratio (d2 / d1) of the thickness d2 of the boron nitride film 132 to the thickness d1 of the gate electrode 131 can be about 0.8 to about 1.

[0064] The charge blocking layer CB may function as a barrier to charge transfer between the charge trap layer 126 and the gate electrode 131. One surface of the charge blocking layer CB may contact the charge trap layer 126, and the other surface of the charge blocking layer CB may contact the gate electrode 131.

[0065] The charge trap layer 126 can store inflowing charges. Charges (eg, electrons) present in the channel layer 122 can flow into the charge trap layer 126 by a tunnel effect, etc. The charges that have flowed into the charge trap layer 126 can be fixed in the charge trap layer 126.

[0066] A key reliability factor in vertical nonvolatile memory devices involves data retention (e.g., the property of storing charge for a long time in the charge trap layer 126). When the distance between memory cells MC is reduced to increase the memory density in the vertical nonvolatile memory device, transfer of the trapped charge between the memory cells MC may occur, which may lead to degradation of the charge retention property.

[0067] In a direction perpendicular to the charge trapping layer 126, charges can be transferred from the charge trapping layer 126 to the charge tunneling layer 124 via trapping-assisted tunneling or thermal radiation. The extent of this charge transfer can be determined by the conduction band offset (CBO) at the interface between the charge trapping layer 126 and the charge tunneling layer 124.

[0068] In a direction parallel to the charge trapping layer 126, charge transfer can occur by lateral migration due to the gradient of charge concentration. Charge transfer in a direction parallel to the charge trapping layer 126 can be controlled by Poole-Frenkel tunneling. The current density of Poole-Frenkel tunneling can be expressed by the Poole-Frenkel conduction equation (Equation 1):

[0069]

[0070] (J: current density, q: electron charge, μ: carrier mobility, N c : density of states in the conduction band, E: electric field, E T : trap energy, ε: dielectric constant, k: Boltzmann constant, T: temperature).

[0071] The charge transfer in the direction parallel to the charge trapping layer 126 due to Poole-Frenkel tunneling can be determined by the trap energy (E T ) and trap density (N T ) is determined. Trap energy refers to the voltage barrier that electrons can pass through to move from one atom to another in the material. That is, trap energy can refer to the depth of the trap state relative to the conduction band minimum (CBM) of the material. Trap density can refer to the number of charges trapped per unit volume. Trap density can be calculated by using a charge pump method. The charge retention characteristics in the direction parallel to the charge trapping layer 126 can be improved by high trap energy and high trap density.

[0072] The charge trapping layer 126 may include, for example, at least one of silicon nitride (SiN), gallium nitride (GaN), gallium oxide (GaO), hafnium oxide (HfO), scandium oxide (ScO), strontium oxide (SrO), zirconium oxide (ZrO), yttrium oxide (YO), tantalum oxide (TaO), barium oxide (BaO), or zinc sulfide (ZnS).

[0073] The charge trapping layer 126 may include a matrix and nanocrystals in the matrix. The matrix may include an amorphous metal oxynitride. The matrix may include a metal oxynitride having a dielectric constant greater than that of silicon nitride. For example, the matrix may include at least one of AlON, ZrON, LaON, AlSiON, HfAlON, LaSiON, AlZrON, LaAlON, HfAlON, or ZrSiON. However, the present disclosure is not limited thereto. For example, the nanocrystals may include at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, or ZrN. However, the present disclosure is not limited thereto.

[0074] Since the charge trap layer 126 includes an amorphous metal oxynitride in which nanocrystals having semiconductor characteristics are dispersed, the trap energy and trap density can be increased, and the charge retention characteristics can be improved by suppressing the transfer of trapped charges between memory cells MC. As a result, the threshold voltage can be reduced, resulting in improved memory operation characteristics.

[0075] The charge blocking layer CB can block or prevent charges from leaking to the boron nitride film 132 and the gate electrode 131 on the charge trapping layer 126. The charge blocking layer CB may include, for example, a first charge blocking layer 128 disposed on the charge trapping layer 126 and a second charge blocking layer 129 disposed on the first charge blocking layer 128. The first charge blocking layer 128 may be in direct contact with the charge trapping layer 126. However, the present disclosure is not limited thereto, and another layer may be disposed between the charge trapping layer 126 and the first charge blocking layer 128. The first charge blocking layer 128 may include silicon oxide, a metal oxide, or a metal nitride. However, the present disclosure is not limited thereto. The first charge blocking layer 128 may include at least one of aluminum oxide (AlO), magnesium oxide (MgO), aluminum nitride (AlN), or gallium nitride (GaN). The first charge blocking layer 128 may include, for example, SiO2 or Al2O3.

[0076] The second charge blocking layer 129 may include a ferroelectric material or an antiferroelectric material. A ferroelectric material is a material having ferroelectricity that maintains spontaneous polarization by aligning an electric dipole moment even when no electric field is applied thereto. A ferroelectric material can show spontaneous polarization by aligning permanent dipole moments in the same direction. Even in the absence of an external electric field, a ferroelectric material may have a residual polarization of a dipole. In addition, the polarization direction can be switched according to a domain unit by an external electric field. The threshold voltage of the vertical non-volatile memory device 100 can be changed according to the switching of the polarization direction of the ferroelectric material, for example, from the gate electrode 131 toward the channel layer 122 or from the channel layer 122 toward the gate electrode 131.

[0077] Antiferroelectric materials may contain an array of electric dipoles, but the remnant polarization can be zero or close to zero. In the absence of an electric field, adjacent dipoles are oriented in opposite directions and then offset from each other, and both the spontaneous polarization and the remnant polarization can be zero or close to zero. However, when an external electric field is applied, polarization characteristics or switching characteristics may sometimes appear.

[0078] The ferroelectric material may include a hafnium oxide material or an aluminum nitride material. The ferroelectric material may have a structure in which a dopant is implanted into a hafnium oxide-based material or a structure in which a dopant is implanted into an aluminum nitride-based material. When the ferroelectric material is a hafnium oxide-based material, the dopant may be Zr, La, Al, Si, or Y. When the ferroelectric material is a aluminum nitride-based material, the dopant may be B or Sc.

[0079] The ferroelectric material may include a ferroelectric material having at least one of, for example, a fluorite structure, a perovskite structure, or a wurtzite structure.

[0080] The ferroelectric material with a fluorite structure may include, for example, HfO2 or ZrO2. HfO2 or ZrO2 may have a tetragonal crystal structure or an orthorhombic crystal structure. The tetragonal crystal structure may have antiferroelectricity, and the orthorhombic crystal structure may have ferroelectricity. Undoped HfO2 may have a stable tetragonal crystal structure or an orthorhombic crystal structure, depending on the size of the grains. Undoped ZrO2 may have a stable tetragonal crystal structure. Undoped HfO2 or ZrO2 may include nanocrystals having a grain size of about 1 nm to about 3 nm. However, the present disclosure is not limited thereto.

[0081] Fluorite-based materials may include, for example, HfO2 or ZrO2 including a dopant. The dopant may include, for example, at least one of Al, Ga, Co, Ni, Mg, In, La, Y, Nd, Sm, Er, Sr, Ba, Gd, Ge, N, or Si. However, this is merely an example. Depending on the grain size and doping concentration, HfO2 or ZrO2 including a dopant may have a tetragonal crystal structure or an orthorhombic crystal structure containing antiferroelectricity. When the grain size is small and the doping concentration is high, the tetragonal crystal structure may be stable, and when the grain size is large and the doping concentration is low, the orthorhombic crystal structure may be stable.

[0082] The HfO 2 or ZrO 2 doped with a dopant may include nanocrystals having a larger grain size than undoped HfO 2 or ZrO 2. For example, the HfO 2 or ZrO 2 doped with a dopant may have a grain size of about 4 nm to about 7 nm or about 4 nm to about 5 nm. However, the present disclosure is not limited thereto.

[0083] The dopant concentration may vary depending on the type of dopant. For example, when the dopant is Si, the doping concentration may be from about 1 at% (atomic percentage) to about 5 at%. However, the present disclosure is not limited thereto.

[0084] The ferroelectric material having a perovskite structure may include a material having an ABO3 composition, wherein A and B each represent a metal element. The perovskite-based material may include, for example, at least one of PbZrO3, PbTiO3, BaTiO3, SrTiO3, or CaTiO3. However, the present disclosure is not limited thereto. Depending on the composition ratio of the constituent elements, the perovskite-based material may have a crystal structure of a tetragonal system containing antiferroelectricity or a crystal structure of an orthorhombic system containing ferroelectricity.

[0085] The wurtzite-based material may include undoped AlN, GaN, or InN, or may include AlN, GaN, or InN each including a dopant. The dopant may include at least one of boron (B) or scandium (Sc).

[0086] For example, the second charge blocking layer 129 may include hafnium zirconium oxide (HfZrO), and Zr / (Hf+Zr) may be about 20 at % to about 80 at %.

[0087] Figures 4A to 4C is a cross-sectional view for illustrating a method of manufacturing a boron nitride film according to example embodiments.

[0088] The substrate S may be prepared in a chamber (not shown). Figure 4AThe substrate S is shown only briefly, but intermediate structures of an integrated circuit on which a boron nitride film is to be formed may exist on the substrate S. The substrate S may include at least one of a Group IV semiconductor material, a semiconductor compound, an insulating material, and a metal. For example, the substrate S may include a Group IV semiconductor material such as Si, Ge, Sn, etc. The substrate S may include, for example, at least one of Si, Ge, C, Zn, Cd, Al, Ga, In, B, C, N, P, S, Se, As, Sb, Te, Ta, Ru, Rh, Ir, Co, Ta, Ti, W, Pt, Au, Ni, or Fe. In addition, the substrate S may also include N and F as a SiCOH-based composition and may include pores to reduce the dielectric constant. The substrate S may also include dopants. The aforementioned materials for the substrate S are merely examples.

[0089] The substrate S may be pre-treated before being placed in the chamber. For example, after being immersed in an organic solvent such as acetone, the substrate S may be cleaned using nitrogen gas. By performing plasma treatment on the surface of the cleaned substrate S using oxygen, hydrogen, NH3, etc., carbon impurities remaining on the surface may be removed. In addition, the substrate S may be immersed in an HF solution, and natural oxides may be removed. The remaining HF solution may then be removed using anhydrous and N2 gases.

[0090] After the cleaned substrate S is prepared in the chamber, carbon impurities remaining on the surface of the substrate S may be removed by performing plasma treatment on the surface of the substrate S in the chamber. For example, H2 plasma treatment may be performed on the surface of the substrate S at a temperature of approximately 200° C. to approximately 800° C. During the H2 plasma treatment performed on the surface of the substrate S, a flow rate of H2 may be controlled to be approximately 20 standard cubic centimeters (sccm) to approximately 200 sccm, and a plasma power may be maintained at approximately 20 W to approximately 100 W or approximately 30 W to approximately 100 W.

[0091] The process temperature for the growth of the boron nitride film may be 700°C or lower, which is lower than the temperature used in the chemical vapor deposition process. For example, in order to grow the boron nitride film into an amorphous state, the process temperature in the chamber may be about 400°C. In addition, the process pressure for the growth of the boron nitride film may be set to 2 Torr or less before increasing the process temperature. For example, the process pressure may be 10 -2 The processing pressure for growing nanocrystalline boron nitride films can be 10 mTorr or higher. For example, the processing pressure for growing nanocrystalline boron nitride films can be about 10 mTorr to about 1 Torr.

[0092] Then, a reaction gas can be injected into the chamber for the growth of the boron nitride film. The reaction gas can be a source of boron nitride for growing the boron nitride film, and can be a source comprising both nitrogen and boron, such as borazine (B3N3H6) or ammonia-borane (NH3-BH3). The reaction gas can include a nitrogen source comprising nitrogen and a boron source comprising boron. The nitrogen source can include at least one of ammonia (NH3) or nitrogen (N2), and the boron source can include at least one of BH3, BF3, BCl3, B2H6, (CH3)3B or (CH3CH2)3B.

[0093] The reaction gas may further include a carrier gas. The carrier gas may further include an inert gas. The inert gas may include, for example, at least one of argon, neon, nitrogen, helium, krypton, or xenon. The reaction gas may further include hydrogen. The mixing ratio of the reaction gas injected into the chamber may vary according to the growth conditions of the boron nitride film.

[0094] The flow rate of the gas for boron nitride may be lower than that of other reaction gases. In order to grow a boron nitride film by using plasma, the volume ratio between the boron nitride source and the inert gas may be, for example, about 1:10 to 1:5,000, or the volume ratio between the boron nitride source, the inert gas, and hydrogen may be, for example, about 1:10 to 5,000:10 to 5,000.

[0095] In order to form the nanocrystalline boron nitride film, the amount of the boron nitride source in the reaction gas needs to be relatively small, and for this reason, the flow rate of the boron nitride source flowing into the chamber may be relatively low. For example, the flow rate of the source of boron nitride can be approximately 0.03 sccm to approximately 1 sccm. For example, during the growth of the boron nitride film, the flow rate of the source of boron nitride can be controlled to 0.05 sccm, and the flow rate of the inert gas can be controlled to 50 sccm. The flow rate of hydrogen can be controlled to 20 sccm.

[0096] When the reaction gas flows into the chamber, the plasma power can be maintained at about 20W to about 100W or about 30W to about 100W, and the processing temperature can be maintained at about 200°C to about 800°C. The plasma device can be a device that provides plasma, including inductively coupled plasma, microwave plasma, capacitively coupled discharge plasma, electron cyclotron resonance plasma, helicon wave plasma, etc. However, the present disclosure is not limited to this. When an electric field is induced in the chamber of the plasma device, the induced electric field can generate plasma for growing a nanocrystalline boron nitride film.

[0097] Since the ratio of the source of boron nitride is lower than that of other reaction gases, the crystallinity of boron nitride may be weakened. Therefore, the boron nitride film 132 according to example embodiments may be formed in an amorphous or nano-scale crystal structure.

[0098] For example, an inductively coupled plasma device can provide a current generated by electromagnetic induction (e.g., a plasma supplied with energy by a magnetic field that varies with time). When power for generating plasma is applied from the plasma device to the interior of the chamber, an electric field can be induced within the chamber. When a reactive gas is injected and an electric field is induced, plasma can be formed for growing the boron nitride film 132.

[0099] Reference Figure 4B , nitrogen (N*) and boron (B*) activated by the plasma of the reaction gas obtained by mixing a carbon source, an inert gas, and hydrogen can be generated and adsorbed on the surface of the substrate S. Then, as the plasma of the inert gas continuously causes activation of the substrate S, the adsorption of activated nitrogen (N*) and activated boron (B*) on the surface of the substrate S can be accelerated. Activated nitrogen (N*) and activated boron (B*) can be adsorbed in an amorphous manner. Even when activated nitrogen and boron are bonded to each other, their amount may be very small, and therefore, nitrogen and boron can be adsorbed as nano-scale crystals.

[0100] Reference Figure 4C Since adsorption of activated nitrogen (N*) and activated boron (B*) on the surface of the substrate S is an accelerated event at low temperatures, the boron nitride film 132 may be grown on the surface of the substrate S. According to example embodiments, at low temperatures, for example, at 700° C. or lower, the boron nitride film BN may be directly grown on the surface of the substrate S by a low ratio of activated boron (B*) and activated nitrogen (N*), and the boron nitride film 132 may have weak crystallinity.

[0101] The boron nitride film 132 according to the example embodiment may be grown amorphously or may be grown as nano-scale crystals. Even when the amorphously formed boron nitride film 132 has crystals, their size may be 3 nm or less, and the boron nitride film 132 formed as nanocrystals may include crystals having a size of 100 nm or less. The boron nitride film 132 may have an amorphous structure or may include a nano-crystalline structure having a size of approximately 0.5 nm to approximately 100 nm.

[0102] Boron nitride film 132 may have a thickness d2 of 16 nm or less. Since boron nitride film 132 may include an amorphous material or nanocrystals, boron nitride film 132 may be thin.

[0103] After growth, the plasma can be turned off and the furnace can be slowly cooled. For example, the furnace can be cooled to room temperature by injecting 20 sccm of H2 gas into the chamber.

[0104] The device can be manufactured by forming another layer at the boron nitride film 132 manufactured by the aforementioned method. The manufactured boron nitride film can be transferred to another layer. A hydrofluoric acid transfer technique can be applied. However, the present disclosure is not limited thereto.

[0105] Because Figures 4A to 4C The boron nitride film 132 manufactured as shown is directly grown from activated nitrogen and boron having a low density at a low temperature, so the crystallinity may be low. When at least one of the process temperature and the process pressure is low, the amount of amorphous material may be high.

[0106] The ratio of nitrogen and the ratio of boron in the boron nitride film 132 may be substantially the same. The ratio of boron to nitrogen may be approximately 0.9 to approximately 1.1. Furthermore, the boron nitride film 132 may include hydrogen. However, the amount of hydrogen in the boron nitride film 132 may be relatively small. For example, the amount of hydrogen may be 10 at % or less. Since the boron nitride film 132 includes a small amount of hydrogen, the boron nitride film 132 may be chemically stable.

[0107] The boron nitride film 132 may have a dielectric constant (dielectric constant may refer to a relative dielectric constant relative to vacuum or air) of 4 or less at an operating frequency of about 100 kHz. For example, an amorphous boron nitride film (a-BN) may have a dielectric constant of 2.3 or less at an operating frequency of about 100 kHz, and a nanocrystalline boron nitride film (nc-BN) may have a dielectric constant of about 2.3 to about 4 at an operating frequency of about 100 kHz.

[0108] The boron nitride film 132 may have a Young's modulus of 60 GPa or greater. For example, the boron nitride film 132 may have a Young's modulus of about 60 GPa to about 200 GPa. For example, the boron nitride film 132 may have a Young's modulus of about 60 GPa to about 150 GPa. Since the boron nitride film 132 has excellent mechanical properties (such as Young's modulus), the physical / mechanical characteristics of the boron nitride film 132 can be maintained stable even at a thin thickness.

[0109] Furthermore, the mass density of the boron nitride film 132 according to example embodiments may vary depending on the dielectric constant of the boron nitride film 132. For example, the boron nitride film 132 may have a mass density of approximately 1 g / cm 2 About 3g / cm 2 The breakdown field of the boron nitride film 132 may be 4 MVcm -1 For example, the breakdown field of the boron nitride film 132 may be about 5 MVcm -1 to about 10 MVcm -1 .

[0110] The surface of the boron nitride film 132 may be smooth. For example, the surface roughness of the boron nitride film 132 may be about 0.3 root mean square (RMS) to about 0.6 RMS. The surface roughness of the boron nitride film 132 may be determined by the flow rate of the boron nitride source.

[0111] In order to obtain the characteristics of the boron nitride film 132, the boron nitride film 132 is deposited at a processing temperature of about 400° C. and a temperature of about 10 -4 The boron nitride film is grown on the Si substrate at a process pressure of 1000 Torr. However, the manufacturing process is not limited thereto.

[0112] By changing the conditions of the process for forming the boron nitride film 132 (e.g., process temperature, plasma power, etc.), the properties of the boron nitride film 132 can be slightly changed. When both the process temperature and the plasma power are low, an amorphous boron nitride film 132 can be formed. For example, when the process temperature is 200° C. and the plasma power is 20 W, an amorphous boron nitride film 132 can be formed. When the process temperature is higher than 200° C. and the plasma power is greater than 20 W, a nanocrystalline boron nitride film 132 can be formed.

[0113] Thus, even when the vertical nonvolatile memory device is miniaturized by employing the boron nitride film 132 having a low dielectric constant and a high Young's modulus as the insulating layer between the gate electrodes 131, the thickness of the insulating layer becomes thinner, but the structure of the device can remain stable.

[0114] Figure 5 1 shows an example of a variation of the structure of the second charge blocking layer 129. The second charge blocking layer 129 may be arranged to surround some surfaces of the gate electrode 131. For example, the second charge blocking layer 129 may surround three surfaces of the gate electrode 131. In this manner, the second charge blocking layer 129 may be independently arranged for each memory cell MC.

[0115] Figure 6 An example is shown in which a diffusion prevention layer 135 is further provided on the second charge blocking layer 129. The diffusion prevention layer 135 can mitigate or prevent reaction and diffusion between the interface of the gate electrode 131 and the boron nitride film 132, or between the gate electrode 131 and the charge trapping layer 126. The diffusion prevention layer 135 may include a material having a greater redox potential than the boron nitride film 132. The diffusion prevention layer 135 may include at least one of titanium (Ti), zirconium (Zr), vanadium (V), aluminum (Al), lanthanum (La), niobium (Nb), or tantalum (Ta), or may include a nitride including at least one of the foregoing elements (e.g., at least one of titanium (Ti), zirconium (Zr), vanadium (V), aluminum (Al), lanthanum (La), niobium (Nb), or tantalum (Ta)). The diffusion prevention layer 135 may include, for example, TiN or NbN.

[0116] Figure 7 is a circuit diagram including a vertical nonvolatile memory device according to an example embodiment. k*n cell strings CS may be arranged in a matrix and may be represented by CSij according to rows and columns (1≤i≤k, 1≤j≤n). Each cell string CSij may be connected to a bit line BL, a string select line SSL, a word line WL, and a common source line CSL.

[0117] Each cell string CSij may include a memory cell MC and a string selection transistor SST. The memory cell MC and the string selection transistor SST of each cell string CSij may be stacked in a height direction.

[0118] The rows of multiple cell strings CS can be connected to different string selection lines (SSL1 to SSLk). For example, the string selection transistors SST of the cell strings CS11 to CS1n can be commonly connected to the string selection line SSL1. The string selection transistors SST of the cell strings CSk1 to CSkn can be commonly connected to the string selection line SSLk.

[0119] The columns of the plurality of cell strings CS may be connected to different bit lines (BL1 to BLn), respectively. For example, the memory cells MC and string selection transistors SST of the cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and string selection transistors SST of the cell strings CS1n to CSkn may be commonly connected to the bit line BLn.

[0120] The rows of multiple cell strings CS can be connected to different common source lines (CSL1 to CSLk) respectively. For example, the string selection transistors SST of the cell strings CS11 to CS1n can be commonly connected to the common source line CSL1, and the string selection transistors SST of the cell strings CSk1 to CSkn can be commonly connected to the common source line CSLk.

[0121] Memory cells MC located at the same height from the string selection transistor SST or the substrate may be commonly connected to one word line WL, and memory cells MC located at different heights from each other may be respectively connected to different word lines ( WL1 to WLn).

[0122] The circuit structures illustrated in the accompanying drawings are merely examples. For example, the number of rows of cell strings CS may increase or decrease. When the number of rows of cell strings CS changes, the number of string select lines connected to the rows of cell strings CS and the number of cell strings CS connected to one bit line BL may also change. When the number of rows of cell strings CS changes, the number of common source lines connected to the rows of cell strings CS may also change.

[0123] The number of columns of cell strings CS may also increase or decrease. When the number of columns of cell strings CS changes, the number of bit lines BL connected to the columns of cell strings CS and the number of cell strings CS connected to one string selection line may also change.

[0124] The height of the cell string CS may also be increased or decreased. For example, the number of memory cells MC stacked in each cell string CS may be increased or decreased. When the number of memory cells MC stacked in each cell string CS changes, the number of word lines WL may also change. For example, the number of string selection transistors provided to each cell string CS may be increased. When the number of string selection transistors provided to each cell string CS changes, the number of string selection lines or common source lines may also change. When the number of string selection transistors SST increases, the string selection transistors SST may be stacked in the same manner as the memory cells MC.

[0125] For example, reading and writing can be performed in units of rows of cell strings CS. Cell strings CS can be selected as row units by a common source line CSL, and cell strings CS can be selected as row units by a string select line SSL. In addition, a voltage can be applied to at least two common source lines CSL as a unit. In some example embodiments, a voltage can be applied to all common source lines CSL as a unit.

[0126] Reading and writing can be performed by a page at a selected row of a cell string CS. A page can be a row of memory cells connected to one word line WL. At a selected row of a cell string CS, a memory cell can be selected by a word line WL in units of a page. For example, Figure 1 The gate electrode 131 may be connected to one of a word line WL and a string selection line SSL.

[0127] The memory cell MC may have a circuit structure in which a transistor including a gate electrode 131 , a boron nitride film 132 , and a channel layer 122 is connected to a charge trap layer 126 .

[0128] Such memory cells MC are continuously arranged in the vertical direction (z direction) to constitute a cell string CS. In addition, both ends of the cell string CS can be connected to a common source line CSL and a bit line BL, as shown in FIG. Figure 7 By applying voltage to the common source line CSL and the bit line BL, programming, reading, and erasing can be performed on a plurality of memory cells MC.

[0129] For example, when a memory cell MC is selected for writing, the gate voltage value of the memory cell can be adjusted so that no channel is formed in the selected memory cell (channel-off), and the gate voltage value of the unselected memory cells can also be adjusted to make the unselected memory cells channel-on. Therefore, charge can be tunneled through the charge tunneling layer 124 by the voltage applied to the common source line CSL and the bit line BL and can be stored in the charge trapping layer 126 of the selected memory cell MC. Then, the desired information 1 or 0 can be written to the selected memory cell MC.

[0130] Similar to the above, in a read operation, a selected cell can be read. That is, the gate voltage applied to the gate electrode 131 can be adjusted to channel-on the selected memory cell MC and channel-off the unselected memory cells MC. Then, the current flowing in the memory cell MC by the voltage Vread applied between the common source line CSL and the bit line BL can be measured to identify the memory cell state (1 or 0).

[0131] The vertical nonvolatile memory device 100 may have a structure in which cells are connected to each other in a vertical direction. When storing information, charges may diffuse in the vertical direction and move to adjacent cells to affect the operation of the adjacent cells.

[0132] In the vertical nonvolatile memory device according to example embodiments, since a boron nitride film can be applied as an insulating layer between gate electrodes 131 and the boron nitride film has a low dielectric constant and a high Young's modulus, the vertical nonvolatile memory device can be used in integrated circuits of various electronic devices to reduce parasitic capacitance. In addition, since the boron nitride film has excellent mechanical properties, including hardness and Young's modulus, its physical / mechanical characteristics can be maintained stable even at a thin thickness.

[0133] Since the vertical nonvolatile memory device according to example embodiments has the advantages described above, it may be applied to various electronic devices.

[0134] Figure 8 2 is a schematic block diagram of a display driver integrated circuit (DDI) 200 and a display device 220 including the DDI 200 according to an example embodiment. Figure 8DDI 200 may include a controller 202, a power supply circuit 204, a driver block 206, and a memory block 208. Controller 202 may receive and decode commands applied from a main processing unit (MPU) 222 and control each block of DDI 200 to operate according to the commands. Power supply circuit 204 may generate a driving voltage in response to control by controller 202. In response to control by controller 202, driver block 206 may drive display panel 224 using the driving voltage generated by power supply circuit 204. Display panel 224 may be, for example, a liquid crystal display panel, an organic light-emitting device (OLED) display panel, or a plasma display panel. Memory block 208, which temporarily stores commands input to controller 202 or control signals output from controller 202 or stores required data, may include a memory such as RAM, ROM, etc. For example, memory block 208 may include the vertical non-volatile memory device 100 according to the above-described example embodiment.

[0135] Figure 9 is a block diagram of an electronic device 300 according to an example embodiment. Figure 9 , the electronic device 300 may include a memory 310 and a memory controller 320. In response to a request from a host 330, the memory controller 320 may control the memory 310 to read data from the memory 310 and / or write data to the memory 310. The memory 310 may include the vertical nonvolatile memory device 100 according to the above-described example embodiment.

[0136] Figure 10 is a block diagram of an electronic device 400 according to an example embodiment. Figure 10 The electronic device 400 may constitute a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The electronic device 400 may include a controller 410, an input / output (I / O) device 420, a memory 430, and a wireless interface 440, which are interconnected via a bus 450.

[0137] The controller 410 may include at least one of a microprocessor, a digital signal processor, or a similar type of processing device. The I / O device 420 may include at least one of a keypad, a keyboard, or a display. The memory 430 may be used to store commands executed by the controller 410. For example, the memory 430 may be used to store user data. The electronic device 400 may use a wireless interface 440 to send / receive data via a wireless communication network. The wireless interface 440 may include an antenna and / or a wireless transceiver. In some example embodiments, the electronic device 400 may be used for a communication interface protocol of a third-generation communication system, such as code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), extended time division multiple access (E-TDMA), and / or wideband code division multiple access (WCDMA). The memory 430 of the electronic device 400 may include the vertical non-volatile memory device 100 according to the above-described example embodiments.

[0138] Figure 11 and Figure 12 Each is a conceptual diagram schematically illustrating a device architecture applicable to an electronic apparatus according to some example embodiments.

[0139] refer to Figure 11 , the electronic device architecture 500 may include a memory unit 510 and a control unit 530, and may further include an arithmetic logic unit (ALU) 520. The memory unit 510, the ALU 520, and the control unit 530 may be electrically connected to each other. For example, the electronic device architecture 500 may be implemented as a single chip including the memory unit 510, the ALU 520, and the control unit 530. For example, the memory unit 510, the ALU 520, and the control unit 530 may be interconnected by on-chip metal lines and communicate directly with each other. The memory unit 510, the ALU 520, and the control unit 530 may be integrated in a monolithic manner on a substrate ( Figure 1 101) and constitute a single chip. Input / output device 550 can be connected to electronic device architecture (chip) 500. Memory unit 510 can include both main memory and cache memory. Such electronic device architecture (chip) 500 can be an on-chip memory processing unit. Memory unit 510, ALU 520, and / or control unit 530 can each independently include a vertical non-volatile memory device 100 according to the above-described example embodiment.

[0140] Reference Figure 12, the cache memory 651, the ALU 652, and the control unit 653 may constitute a central processing unit (CPU) 650, and the cache memory 651 may include a static random access memory (SRAM). Separately from the CPU 650, a main memory 660 and an auxiliary storage device 670 may be provided, and an input / output device 680 may be further provided. The main memory 660 may be, for example, a dynamic random access memory (DRAM), and may include the vertical nonvolatile memory device 100 according to the above-described example embodiment.

[0141] In some cases, electronic device architecture may be implemented in a form where computing unit devices and memory unit devices are adjacent to each other on a single chip without being separated into sub-units.

[0142] The vertical non-volatile memory device according to the above-described example embodiments can be applied to various user devices, such as computers, laptops, ultra-mobile personal computers (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, web tablets, wireless phones, mobile phones, smart phones, digital cameras, digital audio recorders, digital audio players, digital photo recorders, digital photo players, digital video recorders, digital video players, devices capable of receiving and transmitting information in a wireless environment, and home networks.

[0143] The vertical non-volatile memory device according to the above-described exemplary embodiment may include a boron nitride film having a relatively low dielectric constant and a relatively high Young's modulus. By using a boron nitride film having a small thickness as an insulating layer between gate electrodes 131, parasitic capacitance between the gate electrodes can be reduced. Furthermore, since the boron nitride film of the vertical non-volatile memory device according to the above-described exemplary embodiment has excellent mechanical properties, such as Young's modulus, even when its thickness is thin, the boron nitride film can have stable physical / mechanical properties. Therefore, a vertical non-volatile memory device can be implemented while reducing or minimizing performance degradation caused by crosstalk between gate electrodes.

[0144] Any functional blocks shown in the figures and described above may be implemented in processing circuitry, such as hardware including logic circuitry, a hardware / software combination (such as a processor executing software), or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0145] It should be understood that the example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each example embodiment should generally be considered applicable to other similar features or aspects in other example embodiments. Although one or more example embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A vertical non-volatile memory device comprising a plurality of cell strings, wherein: Each of the plurality of cell strings comprises: channel layer; a charge tunneling layer on the channel layer; a charge trapping layer on the charge tunneling layer; a charge blocking layer on the charge trapping layer; a gate electrode on the charge blocking layer; a boron nitride film on the gate electrode, and wherein the gate electrodes and the boron nitride films are alternately stacked, and The boron nitride film has a dielectric constant of 4 or less at an operating frequency of 100 kHz and a Young's modulus of 60 GPa or more.

2. The vertical non-volatile memory device according to claim 1, wherein: The boron nitride film has a thickness of 16 nm or less.

3. The vertical non-volatile memory device according to claim 1, wherein: The boron nitride film has a boron to nitrogen ratio of 0.9 to 1.

1.

4. The vertical non-volatile memory device according to claim 1, wherein: The boron nitride film has a g / cm 3 Up to 3g / cm 3 mass density.

5. The vertical non-volatile memory device according to claim 1, wherein: The boron nitride film has a 4MVcm -1 or larger breakdown field.

6. The vertical non-volatile memory device according to claim 1, wherein: The boron nitride film has a roughness of 0.3 root mean square (RMS) to 0.6 RMS.

7. The vertical non-volatile memory device according to claim 1, wherein: The boron nitride film has a hydrogen content of 10% or less.

8. The vertical non-volatile memory device according to claim 1, wherein: The boron nitride film has an amorphous structure or a nanocrystalline structure.

9. The vertical non-volatile memory device according to claim 1, wherein: The charge blocking layer includes a first charge blocking layer and a second charge blocking layer, and the second charge blocking layer includes a fluorite-based material, a perovskite-based material, or a wurtzite-based material.

10. The vertical non-volatile memory device according to claim 9, wherein: The fluorite-based material includes HfO 2 or ZrO 2 .

11. The vertical non-volatile memory device according to claim 10, wherein: The fluorite-based material also includes a dopant, and the dopant includes at least one of aluminum (Al), gallium (Ga), cobalt (Co), nickel (Ni), magnesium (Mg), indium (In), lanthanum (La), yttrium (Y), neodymium (Nd), samarium (Sm), erbium (Er), strontium (Sr), barium (Ba), gadolinium (Gd), germanium (Ge), nitrogen (N) or silicon (Si).

12. The vertical non-volatile memory device according to claim 9, wherein: The perovskite-based materials include materials having an ABO3 composition, wherein A and B are metal elements.

13. The vertical non-volatile memory device according to claim 12, wherein: The perovskite-based material includes at least one of PbZrO 3 , PbTiO 3 , BaTiO 3 , SrTiO 3 , or CaTiO 3 .

14. The vertical non-volatile memory device according to claim 9, wherein: The wurtzite-based material includes at least one of AlN, GaN, InN, doped AlN, doped GaN, or doped InN.

15. The vertical non-volatile memory device according to claim 9, wherein: The second charge blocking layer has a thickness of 1 nm to 3 nm.

16. The vertical non-volatile memory device of claim 1 , further comprising: a diffusion preventing layer between the gate electrode and the charge blocking layer.

17. The vertical non-volatile memory device according to claim 16, wherein: The diffusion prevention layer comprises: At least one of titanium (Ti), zirconium (Zr), vanadium (V), aluminum (Al), lanthanum (La), niobium (Nb) or tantalum (Ta), or A nitride including at least one of titanium (Ti), zirconium (Zr), vanadium (V), aluminum (Al), lanthanum (La), niobium (Nb), or tantalum (Ta).

18. An electronic device comprising: Memory; as well as a memory controller configured to control the memory to read data from the memory and / or write data on the memory, The memory is a vertical non-volatile memory device including a plurality of cell strings, and each of the plurality of cell strings includes a channel layer, a charge tunneling layer on the channel layer; a charge trapping layer on the charge tunneling layer, a charge blocking layer on the charge trapping layer, a gate electrode on the charge blocking layer, and a boron nitride film on the gate electrode. wherein the gate electrodes and the boron nitride films are alternately stacked, and The boron nitride film has a dielectric constant of 4 or less at an operating frequency of 100 kHz and a Young's modulus of 60 GPa or more.

19. The electronic device according to claim 18, wherein: The boron nitride film has a thickness of 16 nm or less.

20. The electronic device according to claim 18, wherein The boron nitride film has a boron to nitrogen ratio of 0.9 to 1.1.

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