Apparatus and method for manufacturing AIII-BV compound semiconductor single crystal and AIII-BV compound semiconductor single crystal and

Abstract

An apparatus (1) for producing an AIII-BV compound semiconductor single crystal (4) from a melt (5) of a raw material, comprising a crucible (6) for receiving the melt, in which the crucible (7) has a central axis (M) and a crucible wall (7) having a shell-shaped outer surface facing away from the central axis (M) in a radially outward direction, and a member (10) substantially surrounding the crucible (6) and opposed at a distance from the crucible wall (7) by an inner face facing the outer face, wherein the crucible wall (7) and the member (10) surrounding the crucible (6) are arranged in a relationship to substantially exchange heat radiation. The outer face of the crucible wall (7) has a first emissivity ([epsilon] 1) and the inner face of the opposing component (10) surrounding the crucible (6) has a second emissivity ([epsilon] 2), where the first and second emissivity ([epsilon] 1, [epsilon] 2) indicate how much radiation is emitted from the crucible wall (7) and the component (10) surrounding the crucible, respectively, compared to an ideal radiant heater. The outer face of the crucible wall (7) and the inner face of the part (10) surrounding the crucible are each provided at least partially by a coating (8a, 8b) defining a first emissivity ([epsilon] 1) and a second emissivity ([epsilon] 2), respectively, such that the first emissivity and / or the second emissivity are each equal to a value of 0.1 or less, respectively. This configuration allows for the fabrication of wafers, in particular wafers from GaAs or InP, whose annular edge region is at a distance between 1-3 mm from the wafer edge, which can be used for epitaxial steps after fabrication for subsequent device production purposes.

Description

Technical Field

[0001] The present invention relates to an apparatus and a method for producing an AlIII-BV compound semiconductor single crystal, and to a corresponding AlIII-BV compound semiconductor single crystal, or a large-area substrate or wafer obtained by separation thereof. The present invention particularly relates to single crystals or wafers formed from gallium arsenide and / or indium phosphide. Technical Background

[0002] The single crystals of the type considered here are typically produced by solidifying a melt containing the semiconductor material in a crucible using a seed crystal made of the same semiconductor material as the semiconductor single crystal to be produced. The crucible is typically cylindrical, having a central axis and a diameter that corresponds approximately to the nominal diameter of the AIII-BV compound semiconductor wafer to be produced, taking into account a slight excess dimension removed by substantial material removal in the process following solidification. A narrow seed channel is located at the lower end of the crucible in the vertical direction, which channel can also be arranged off-center. During operation, a temperature field generated by appropriately arranged and controlled heating elements and aligned parallel to the central axis extends from this channel. A crystallization front or phase boundary, substantially perpendicular to the central axis, moves vertically upward from the seed crystal.

[0003] Gallium arsenide or indium phosphide substrate wafers are particularly, but not exclusively, suitable for the manufacture of light-emitting components such as micro-LEDs or vertical-cavity surface-emitting lasers (VCSELs) or high-frequency transistors (pHEMTs, HBTs, DHBTs, BiHEMTs). Their operating properties and performance can be significantly affected or compromised by the physical properties of the substrate and its surface. Therefore, it is important to distribute these properties as evenly as possible across the surface of the substrate or wafer so that all optical or electronic devices manufactured from the wafer are subject to the same, uniform, and preferably high-quality requirements.

[0004] The physical properties or variables mentioned include, in particular, mechanical residual stress or strain, flatness, roughness, grain density, resistivity or dislocation density, etc. Some of these variables, in particular dislocations, resistivity or residual mechanical stress, are subject to greater deviations, especially at the wafer edge. This is caused in particular by thermal stresses that arise during the cooling of the crystal after solidification, and which arise in particular at the crucible wall or at and near the surface of adjacent single crystals.

[0005] Therefore, in order to ensure high uniformity of performance, edge exclusion is usually defined, which represents an annular area on the surface of the wafer (or a portion in the shape of a cylindrical shell within a single crystal or ingot that has not yet been separated into wafers), which is not used by device manufacturers for the actual production of devices, while the center area of the wafer used for device production and filling the edge exclusion regularly shows excellent uniformity values.

[0006] For example, depending on the diameter and the material (GaAs or InP), the values of edge exclusion known in the patent literature can range between 2.5 mm and 5 mm (see, for example, US 2021 / 310155A1, EP 3514266A1, US 2019 / 371620A1, EP 1634981B1, EP 3591102A1, US 10,473,445B2, EP 3862134A1, EP 2458041B1). As an example, the usable area for manufacturing devices for a GaAs wafer with a diameter of 150 mm and an edge exclusion of 3 mm is equal to about 169.7 cm 2 , with a total wafer area of 176.7cm 2 Therefore, the edge exclusion results in a relative loss of about 4% of unusable area. In the case of InP wafers with diameters currently up to 100 mm, the typical edge exclusion range can also be in the range of 3 mm. In this case, the usable area for device fabrication is 73.9 cm 2 , with a total wafer area of 78.5cm 2 In this case, edge exclusion results in a relative loss of unusable area of approximately 6%. This means that the relative loss of area will decrease with technological advancements (i.e., larger diameters). However, applying a constant amount of edge exclusion, the loss of unusable area in absolute terms will still increase linearly with increasing diameter.

[0007] For economic and sustainability reasons, it is therefore necessary to reduce the loss of AlIII-BV compound semiconductor material during device manufacturing. A key starting point for this is to improve the quality and homogeneity of the aforementioned physical parameters (residual stress, resistivity), particularly in the edge region, thereby, for example, being able to reduce the corresponding specified values for edge exclusion.

[0008] Thermal stresses in the edge regions of single crystals can be caused, in particular, by the curvature of the temperature field during crystallization or by phase boundary deflections. Due to the relatively low curvature of the corresponding temperature fields involved, vertical Bridgman (VB) or vertical gradient freezing (VGF) processes, or thermally similar processes, are generally preferred growth methods (see, for example, M. Jurisch et al., "Handbook of Crystal Growth, Bulk Crystal Growth: Basic Technologies," Vol. 11, Part A, 2nd Edition, Chapter 9, "Vertical Bridgman Growth of Divisions Components," 2015).

[0009] According to experimental and theoretical studies, the amount and distribution of dislocation density are mainly determined by the lattice relaxation process caused by thermal stress induced by large thermal gradients during plastic deformation (see, for example, J. Yang, W. Lu, M. Duan, H. Xie, G. Shen, J. Liu, Z. Dong, Y. Zhao, "VGF growth of high quality InAs single crystals with low dislocation density", Journal of Crystal Growth 531 (2020) 125350; J. "Stress in the cooling crystal", in: DTJ Hurle (Ed.), Handbook of Crystal Growth, Elsevier Science B, 1994, p. 821; P. Rudolph, M. Jurisch, Crystal Growth Technology, John Wiley & Sons, Ltd, 1994, p. 800). Therefore, if the thermal stress exceeds a critical value for the shear stress with respect to lattice slip, dislocations may occur. Regarding this critical value, the deviation of the isotherm from the linear plane and the degree of thermal gradient or phase boundary deflection play an important role (see, for example, N.A. Anastaskeva, V.T. Bulik, V.V. Karatsev et al., Sov. Phys. Crystogram. 34 (1989) 912).

[0010] In order to grow a crystal from a melt, a temperature gradient in the crystal is a prerequisite. The single crystal acts as a heat transfer medium, through which heat—the heat of fusion released in each case, as well as the heat contained in the melt due to initial heating—is transferred to the surroundings via the crucible wall. In particular, heat enters the crystal at the interface between the single crystal and the melt and leaves the crystal via radiation and convection. Consequently, the interior of the single crystal is hotter than its edges, and the end of the single crystal near the seed channel is cooler than the material near the phase boundary. The resulting temperature gradient therefore leads to thermal stresses and strains in various parts of the single crystal, which may ultimately lead to plastic deformation due to the movement of already formed dislocations (see, for example, Vishwanath Prasad, Srinivas Pendurti, "Part F Modeling in Crystal Growth and Defects. 39 Models for Stress and Dislocation Generation in Melt Based Compound Crystal Growth" in "Springer Handbook of Crystal Growth", G. Dhanaraj, K. Byrappa, V. Prasad, M. Dudley (Eds.), Springer-Verlag, Berlin-Heidelberg (2010) p. 1349).

[0011] In document US2020 / 066850A1, specific measurements of residual strain content are provided at least near the edge of conventionally grown InP wafers with a diameter of 100 mm to 205 mm. The region near the edge is studied, extending from a 2 mm flat surface or notch to the interior of the wafer surface. The substrate has a thickness of 300 to 800 μm and contains impurity atoms with an abundance of 2.0 to 8.0 × 10 18 cm -3 (sulfur), 1.0 to 4.0×10 18 cm -3 (tin) or 5.0×10 15 to 1.0×10 17 cm -3 (Fe). The average value of the residual strain in the edge region defined in this way is 5×10 -6 to 5×10 -5 .

[0012] In document EP 3835465A1, the residual strain content is determined in the near-edge region of a C-doped semi-insulating GaAs wafer, which in the embodiment shown has a diameter of 152.4 mm and a thickness of 700 μm. Here, the region near the edge is characterized by an annular portion symmetrical with respect to the center of the wafer, having a width of 5 mm and a distance to the edge of the wafer also of 5 mm (i.e., a depth of 5 mm to 10 mm, viewed from the edge). The residual stresses of the various wafers were measured as a function of the temperature difference that occurs between one end of the seed channel and the opposite end of a 200 mm long single crystal (not yet separated into wafers) during cooling after the growth process (VB process), whereby the temperature difference can ultimately be controlled by a heating element. This temperature difference can also represent the radial temperature gradient of the outer edge of the single crystal. It was found that those samples with the lowest set temperature difference (i.e., 2°C) showed a 3.5×10 -6 (The separated wafer corresponds to the position near the seed channel in the crucible) to 1.2×10 -5 (The separated wafers correspond to the positions in the crucible close to the end that crystallized last.) Relatively high values of slip and thus dislocation density are recorded only for the sample with high temperature difference (ie 20°C).

[0013] Here, it should be noted that a distinction must be made between dislocations which, for example, continue from the seed channel in the direction of the advancing crystallization front during crystal growth (presenting a more or less free or "cloud-like" distribution in cross section) and dislocations in the so-called slip lines which are generated by thermal stresses at the edges during cooling of the solidifying crystal.

[0014] Therefore, it is desirable to determine the deflection of the phase boundary by the cooling rate to which the crystal is subjected. During crystal growth, the cooling rate should be adjusted from the melting point down to room temperature so that the resulting thermal stresses are below the critical shear stress for dislocation propagation and slip. The cooling rate also determines the generally concave shape of the phase boundary, which has an increasing curvature toward the crucible wall, which is indicative of the shape of the isotherms and, therefore, the nonlinearity of the temperature field. As described above, the nonlinear temperature field leads to a curved phase boundary shape, resulting in thermal stress in the growing crystal, resulting in dislocations aligned in the slip lines (if the thermal stress is too high), resulting in dislocation proliferation under high thermal stress and resulting in residual stress in the crystal at room temperature (see Manfred Jurisch, Stefan Eichler, Martin Bruder, "9-Vertical Bridgman Growth of Binary Compound Semiconductors", Ed. Peter Rudolph, In Handbook of Crystal Growth, Handbook of Crystal Growth (Second Edition), Elsevier, 2015, Pages 331-372, ISBN 9780444633033, https: / / doi.org / 10.1016 / B978-0-444-63303-3.00009-2).

[0015] Slip lines are generated by the intersection of dislocation loops, which extend in the slip plane and are emitted by the Frank-Read source and are collinear with each other, with a cross-sectional surface that can be the flat surface of a separated wafer. In single crystals, slip planes form the planes between the atomic layers with the densest packing and large interlayer spacing. In the case of the AIII-BV compound semiconductors considered here, these can regularly be {111} lattice planes, especially at critical crystal boundaries. The individual dislocation loops lead to intersection points within the respective cut cross section, and due to the collinearity within the slip planes, these intersection points lie on a line, which is called a slip line. Depending on the mechanical stress and the specific thermal load, the dislocation loops can expand or contract towards the Frank-Read source. In this case, however, the intersection points remain on the slip line or move along the slip line, respectively.

[0016] Morphologically, slip lines have almost no effect on the flatness or roughness of the original wafer surface. However, during epitaxy for subsequent device fabrication, undesirable macroscopic steps may form on the surface at these slip lines (Sawada, S; Yoshida, H.; Kiyama, M.; Mukai, H.; Nakai, R.; Takebe, T.; Tatsumi, M.; Kaji, M.; Fujita, K: "Slip defect generation on GaAs wafers during high temperature process: a thermoelastic study from a crystallographic viewpoint," in GaAsIC Symposium IEEE, 18 th Annual technical Digest (1996): 50-53).

[0017] It is therefore desirable to assign dislocations detectable in a known manner by etch pit formation in the cross section (wafer surface) to slip lines or to classify them as free dislocations in order to be able to quantify the slip lines formed in the wafer edge region with respect to undesired steps.

[0018] The standard SEMIM10 - Terminology for Identification of Structures and Features Seen on Gallium Arsenide Wafers (available via SEM org: https: / / store-us.semi.org / products / m01000-semi-m10-terminology-for-identification-of-structures-and-features-seen-on-gallium-arsenide-wafers) provides a definition in this regard: "... slip is evidenced by a pattern of one or more straight lines of 10 or more dislocations per millimeter, which are not necessarily touching each other." This means the average mutual spacing of dislocations within a slip line of about 100 μm. Unfortunately, this definition is not useful for substrates with low dislocation density (EPD; pit density) discussed in this application, as the average spacing can actually be as high as 500 μm. Moreover, the actual slip lines (or the arrangement of the associated crosses in a cross section) may deviate from exact straight lines due to interactions with point defects and other dislocations.

[0019] For substrates with a low dislocation density, slip lines are therefore identified or detected by measurement in this specification if:

[0020] - in said cross section, more than 10 etch pits representing dislocations extend along one direction;

[0021] - These dislocations form chains with a maximum distance of 500 μm between each adjacent etch pit;

[0022] - the pits are located perpendicular to said direction within a tolerance interval of 250 μm; and

[0023] The slip line extends from a point within the annular edge region of the cross section or planar cross-sectional area, respectively, the width of the edge region being defined by a distance of 5 mm measured from the outer edge of the single crystal or wafer, with an edge exclusion of 2 mm.

[0024] This definition allows the detection and quantification of slip lines close to the edge.

[0025] However, the problem that still exists is that it is impossible to produce devices on a wafer up to 3mm into the crystal (or towards its central axis) in the edge region of the wafer because the residual stress and dislocation density in the edge region are too high or unknown. The device is built in the epitaxial layer grown on the wafer. The residual stress exceeding the limit value at the edge of the wafer can cause the epitaxial layer to be stressed, so that the components or devices derived from the edge of the wafer have different properties compared with the components or devices derived from the center region of the wafer. In particular, slip under the influence of thermally induced stress can lead to a localized large increase in dislocation density, which can be several times the average dislocation density of the entire wafer. The correlation between the phase boundary deflection and crystal quality in the edge region of the wafer mentioned above clearly shows that improvements in crystal growth and cooling processes are desirable. In particular, the purpose of an embodiment of the present invention is to reduce thermal stress, limit related dislocations and improve crystal structure. In addition, the purpose is to provide an AIII-BV compound semiconductor single crystal and a wafer produced by separating the same, wherein the expensive material loss caused by the region that cannot be used for subsequent component or device production is limited. Summary of the Invention

[0026] This object is achieved by an apparatus for producing an AIII-BV compound semiconductor single crystal from a melt of raw materials, the apparatus comprising: a crucible for receiving the melt, wherein the crucible has a central axis and a crucible wall having a shell-shaped outer surface, the shell-shaped outer surface facing away from the central axis in a radially outward direction, and a component that substantially surrounds the crucible and is opposed to the crucible wall at a distance via an inner surface facing the outer surface, wherein the crucible wall is arranged in a relationship that substantially exchanges heat with the component surrounding the crucible.

[0027] The exterior of the crucible wall has a first emissivity, while the interior of the opposing component surrounding the crucible has a second emissivity. The first emissivity and the second emissivity each indicate how much radiation is emitted from the crucible wall and the elements surrounding the crucible compared to an ideal radiative heater (i.e., the ratio of thermal radiation from the surface to radiation from an ideal black surface at the same temperature given by the Stefan-Boltzmann law).

[0028] The outer face of the crucible and / or the inner face of a component surrounding the crucible is at least partially provided by a coating defining first and second emissivities, respectively, such that the first emissivity and / or the second emissivity are each equal to a value of 0.1 or less.

[0029] The present invention is based on the recognition that the uniformity of crystal properties in the wafer cutting direction or perpendicular to the central axis of the single crystal (from which the wafer is separated) is substantially influenced by the curvature of the phase boundary between the growing crystal and the melt. Increased thermal stresses (accompanied by a curvature of the temperature field) can occur here, and the dislocation density can increase locally. Furthermore, the incorporation of dopants into the crystal lattice can often occur at a constant concentration along the curved phase boundary, resulting in uneven dopant distribution and electrical properties on straight (flat) cut wafers. The curvature of the phase boundary at the edge of the crystal near the crucible wall becomes particularly pronounced due to the relatively large radial component of heat transport, the transport of latent heat generated at the crystallization front (GaAs: 668.5 J / g, InP: 429.5 J / g). The heat transport is determined, on the one hand, by the relatively high thermal conductivity of the crucible or crucible wall (0.8 W / cmK) compared to the solidifying crystal (GaAs: 0.0712 W / cmK, InP: 0.0911 W / cmK). On the other hand, heat transport due to radiation at the growth temperatures of GaAs and InP becomes very efficient and radially directed latent heat radiation through the crucible can be substantial.At least the latter situation is addressed by the above aspects of the invention.

[0030] In particular, radially directed thermal radiation is regulated by at least partially providing the surfaces defining the radiation volume outside the crucible with a coating having a relatively low emissivity ε. This can be applied to only one or two limiting surfaces. The radiation volume outside the crucible can essentially have the shape of a cylindrical shell. The inner surface of this radiation volume can usually be provided by the crucible wall or its outward-facing surface, respectively. The crucible itself also includes a cylindrical shape, however, according to aspects of the present invention, deviations from a cylindrical shape are also included. More specifically, crucibles with a geometric shape having a body shape with a quadrilateral, pentagonal, hexagonal or polygonal base area are also conceivable, or cylinders with laterally flattened partial surfaces are also possible.

[0031] The outer surface defining the radiation volume is the inner surface of the crucible's surroundings, which faces the exterior of the crucible wall. Thus, various components can be implemented, depending on the configuration of the growth or manufacturing equipment. Most commonly, the crucible's periphery providing the inner surface will be represented by components that substantially surround the crucible, including one or more parts that together form a functional component. Only outside of this component (as viewed from the central axis of the crucible) can one or more heating elements be provided, which are used to initially melt the raw material and are then controlled to adjust or set a suitable temperature gradient within the crucible.

[0032] For the emissivity ε of the surface and the Stefan-Boltzmann constant σ, the radiant power P of a gray body with temperature T and area A of the corresponding surface can be determined according to the Stefan-Boltzmann law:

[0033] P=εσAT 4 (1)

[0034] Emissivity is material-specific and can take real values between 0 and 1. The net radiation balance M in the space between two approximately parallel faces, as in the case of a device according to this aspect, can be calculated by the following formula (where the distance is significantly less than the surface expansion of the inner or outer faces):

[0035]

[0036] The radiation exchange degree E in formula (2) can be expressed as follows:

[0037]

[0038] Here, ε1 and ε2 represent the emissivity of the outer and inner surfaces, respectively. In conventional devices constructed according to the VGF or VB method for Al-BV compound semiconductor crystals, ε1 (the outer surface of the crucible wall) is approximately 0.5, while ε2 (the inner surface of the component surrounding the crucible, such as a tube made of graphite or SiC) is approximately 0.8. The resulting radiation exchange ratio can be obtained, by way of example only, with a value of E = 0.44.

[0039] According to an aspect of the invention, a coating on one side or the other, preferably on both sides of the radiation chamber is proposed which significantly increases the emissivity, ie ε1≤0.1 and / or ε2≤0.1.

[0040] Coatings and measures for adjusting the emissivity in different contexts are known in the art:

[0041] In US2020 / 181796A1, a device for producing SiC crystals by deposition from the vapor phase is disclosed. A graphite crucible contains the raw material to be vaporized at the bottom and the seed crystal for crystal deposition at the top. A material with low emissivity (emissivity) is attached to the outside of the crucible in the upper region of the raw material. This is to ensure that the raw material at the top enters the gas phase before the raw material at the bottom. As materials with low emissivity, carbides, nitrides, Ta, Mo, Nb, Hf, W, and Zr are mentioned.

[0042] JP3564740B2 discloses an apparatus for growing crystals using the Czochralski method. In the upper region, the emissivity of the steel boiler inner wall increases. As a result, heat is intended to escape the growing crystal more quickly. This inevitably leads to a stronger curvature of the phase boundary between the solid and liquid relative to the growing crystal.

[0043] JP 2014-162668A discloses an apparatus for producing a sapphire single crystal. The emissivity in the upper crucible region is increased compared to the emissivity in the lower crucible region. This increases the heat exchange between the growing crystal and the environment.

[0044] JP H09-315881A discloses an apparatus for growing GaAs using the vertical Bridgman method. The shaft carrying the crucible is cooled in the lower region by a surrounding cooling coil. Above the cooling coil, the shaft is coated with pyrolytic boron nitride, resulting in a lower emissivity and less heat absorption from the environment. On the other hand, the emissivity of the crucible's exterior is increased by a carbon coating.

[0045] In this case, however, the basic idea is not to increase or decrease the emissivity (emissivity) or the degree of radiation exchange locally, but to reduce them by a considerable amount for the crucible as a whole, with the goal of reducing the phase boundary deflection during and throughout the crystal growth process, that is, over the entire length of the crystal.

[0046] A preferred embodiment particularly provides an apparatus for growing or producing AIII-BV compound semiconductor crystals from a melt, which operates according to the vertical gradient solidification (VGF) or vertical Bridgman (VB) method. Both methods are well known in the art: in a crucible with a seed crystal at the bottom, the raw material, which is usually still polycrystalline, is heated and melted by means of one or more heating elements, such as resistance heaters, whereby the seed crystal is also slightly melted. A directional temperature field is set and / or adjusted so that a substantially vertical gradient is directed from the upper region of the crucible to the seed crystal in the seed crystal channel at the bottom of the crucible. The temperature field is then moved relative to the crucible. This can be achieved by mechanically moving the crucible or the heating element (VB method) or by changing the temperature field by targeted control of the heating element of the corresponding heater (VGF method). The temperature field moves in a direction opposite to the gradient, so that the melt first solidifies in the lower region of the crucible starting from the seed crystal, and crystal growth proceeds in a vertically upward direction. The heating zone moves slowly upward, so that the crystallization front also moves slowly upward. The crystallization rate can be determined in particular by the speed of the temperature field movement. Thus, the apparatus may comprise an actual crucible having a cylindrical portion as described above (e.g., for holding a raw material melt), a seed channel, and a tapered portion between the cylindrical crucible and the narrower seed channel. Furthermore, it may comprise a heater having one or more heating elements, and a control unit for regulating the temperature level and the temperature profile according to the selected method. According to the invention, the components surrounding the crucible are located between the crucible and the heating elements of the heater. The entire apparatus may also comprise an external housing that also houses the heater.

[0047] The reduced emissivity of the outer surface of the crucible wall and / or the inner surface of the surrounding components can significantly reduce thermal radiation. Heat conduction within the crucible wall is less affected by the measures according to the present invention, but it still exists. However, in conventional systems, thermal radiation can be extensive, so that, due to the present invention, regions of solidified crystals located radially outward from the central axis can only release their thermal energy with difficulty. This results in a significantly smaller radial component of the temperature gradient, or in other words, a more linear orientation parallel to the central axis of the crucible. As a result, phase boundary deflection is also reduced, and the phase boundary itself becomes flatter, extending to the edge or crucible wall, respectively. Furthermore, phase boundary deflection is reduced, and the phase boundary itself becomes flatter, extending to the edge. Consequently, it is acceptable that significantly more heat transfer must be achieved in the axial direction, which in turn increases cooling time or reduces the overall cooling rate. However, this disadvantage is offset by the advantages of improved quality and yield. However, if the cooling rate is not to be reduced, the heating power can be adjusted accordingly so that the cooling rate remains the same as in conventional systems.

[0048] For this purpose, according to a specific embodiment, the crucible wall near the seed channel (for example, in the tapered portion) or the peripheral (partial) component opposite this portion can remain uncoated, that is, can include a normal emissivity significantly greater than 0.1, in order to allow heat to be removed from the crucible. In addition, according to an embodiment, the end face of the crucible opposite the seed channel and the surface of the surrounding components facing this end face, if provided at this point, do not need to have a coating that reduces emissivity.

[0049] The coating here refers to a preferably thin adhesive layer. It can be applied in any manner, depending in particular on the coating material. It can also be a film fixed to the corresponding surface. The coating material is preferably temperature-stable and inert to the atmosphere to avoid contamination of the crystal.

[0050] According to one specific embodiment, the coating can be configured to have an emissivity of 0.05 or less. This can apply to the coating on the inner side of the component surrounding the crucible, or the coating on the outer side of the crucible wall, or both. Advantageously, the emissivity combination of the coatings on both sides can be ε1 ≤ 0.1 and ε2 ≤ 0.05, or conversely ε1 ≤ 0.05 and ε2 ≤ 0.1. However, as mentioned above, there are also simpler cases and past cases where a coating with ε ≤ 0.05 is applied to only one side of the radiation volume.

[0051] One embodiment of the present invention provides that, in the radiation exchange between the crucible wall and the components surrounding the crucible, the radiation exchange degree E calculated according to equation (3) is equal to 0.1 or less, preferably 0.05 or less.

[0052] As described above, a specific embodiment of the device according to the invention provides that the outer surface of the crucible wall and the inner surface of the opposing component jointly form and delimit an intermediate space or radiation space having a cylindrical shell shape, through which radiation exchange occurs during operation of the device.

[0053] According to another embodiment, the coating forming at least a portion of the outer and / or inner face is designed as a periodic pattern, in particular a mosaic or stripe pattern. More specifically, the emissivity can also be set via the area occupancy of the pattern.

[0054] According to another embodiment, the coating which at least partially forms the outer and / or inner surface can be made shiny metallic. Due to this measure, very low emissivity can be achieved.

[0055] According to another embodiment, the part surrounding the crucible is formed of hard graphite and has a rough metallic layer. Thus, the desired and moderately low emissivity according to the invention can still be achieved. The rough metallic layer can be made of platinum, for example.

[0056] According to another embodiment, the component surrounding the crucible is formed of hard graphite and has a shiny metallic layer. This allows for very low emissivity. The shiny metallic layer can be made, for example, of platinum. Alternatively, the hard graphite can be coated with boron nitride.

[0057] According to another embodiment, the component surrounding the crucible is a quartz tube coated with graphite.In this case, the component can be a so-called liner.

[0058] According to another embodiment, the crucible can be made of boron nitride or pyrolytic boron nitride (pBN), wherein the outer surface of the crucible wall is formed at least partially by a rough platinum or graphite coating. In this way, the desired and moderately low emissivity according to the invention can still be achieved.

[0059] According to another embodiment, the crucible can be made of boron nitride or pyrolytic boron nitride (pBN), wherein the outer surface of the crucible wall is formed at least partially by a shiny platinum coating. In this way, very low emissivity can also be achieved.

[0060] According to an embodiment, the apparatus can be configured to produce an AIII-BV-compound semiconductor single crystal comprising GaAs or InP, preferably having a nominal diameter of 100 mm, 150 mm or 200 mm. GaAs (gallium arsenide) or InP (indium phosphide) exhibits a defined melting temperature, and the control and heating elements are coordinated with each other and configured to set the temperature level and adjust the directional temperature field. With respect to the quoted nominal diameter, the crucible comprises an inner diameter that is typically 1 to 10 mm larger than the nominal diameter. This oversizing can be explained by the removal of material around the circumference of the cylinder in post-processing, which achieves the removal of particles originating from the crucible at the outer edge of the crystal, smoothing of the surface and, optionally, removal of edge material with a large dislocation density (in the case of oversizing).

[0061] Of course, the crucible wall can be made of a material with an internal structure so that the heat conduction is isotropic. This is by no means a problem. In the case of equipment for growing GaAs or InP single crystals, the crucible wall is typically made of stacked pBN. The layering direction is perpendicular to the wall, that is, the layers extend parallel to the central axis of the crucible. Heat transfer (heat conduction) is easier within the individual layers of the stack than heat conduction from layer to layer. This structure is often used to minimize the loss of material in the crucible after each use of the crucible due to the strong bonding of the components to the crystal. The layered structure allows a quantifiable amount of material to be lost in advance and layer by layer, and thus extends the service life of the crucible. However, the anisotropic heat conduction relative to the direction of the central axis of the crucible means that heat is dissipated very efficiently radially outward from the edge of the growing crystal. The proposed embodiment helps to limit this heat dissipation by heat conduction by using a material that is isotropic in this respect.

[0062] One embodiment provides that the crucible wall is made of a material having an internal structure such that the thermal conductivity is 3 W / mK or less. For example, the crucible can be made of glassy carbon.

[0063] Another aspect of the present invention relates to a corresponding method for producing an AIII-BV compound semiconductor single crystal from a melt of raw materials. To this end, a device according to one of the above aspects or one of the above embodiments is first provided. The method further comprises the following steps:

[0064] providing a seed crystal in a seed crystal channel of the apparatus;

[0065] A directional temperature field is set parallel to the central axis of the crucible by one or more heating elements;

[0066] The growth rate is set by controlling one or more heating elements so that the inclination angle between the phase boundary and the horizontal direction perpendicular to the inner surface of the crucible wall is continuously maintained at 40 degrees or less, preferably 30 degrees or less;

[0067] Solidification and further cooling of the single crystal.

[0068] In the step of setting the growth rate, the angle between the phase boundary and the horizontal direction perpendicular to the inner surface of the adjacent lateral crucible wall is preferably continuously maintained at 37 degrees or less in the case of GaAs as the AIII-BV compound semiconductor, or continuously maintained at 34 degrees or less in the case of InP as the AIII-BV compound semiconductor, and more preferably continuously maintained at 32 degrees or less in the case of GaAs as the AIII-BV compound semiconductor, or continuously maintained at 31 degrees or less in the case of InP as the AIII-BV compound semiconductor.

[0069] The same advantages as described above can be achieved. The ideal goal would be a tilt angle of 0°, however, this can be difficult to achieve in practice. At least for the crystal diameter range considered here, the tilt angle or phase boundary deflection generally does not involve a strong dependence on diameter. The deflection occurs particularly towards and near the edge of the crystal or near the crucible wall. A tilt angle of 40 degrees or less corresponds to a phase boundary deflection of approximately 11-12 mm. A tilt angle of 30 degrees or less corresponds to a phase boundary deflection of approximately 4.5-5.0 mm. Since there is almost no suitable sensor technology available for the corresponding temperatures, it is practically impossible to determine or measure both the tilt angle and the phase boundary deflection during the growth process. Therefore, these parameters are predetermined based on the specific configuration from simulations used to control the heater or heating element. To this end, a fairly suitable simulation program can be used that can indicate the phase boundary deflection or the tilt angle depending on the growth process. Based on the calculated results, the emissivity can be determined and implemented, and the heating power can be configured and controlled during operation so that the tilt angle can be achieved.

[0070] Other aspects of the present invention relate to AIII-BV compound semiconductor single crystals or in particular to wafers obtained therefrom by separation, the crystals or wafers being produced by the apparatus and / or method as described above.

[0071] Yet another aspect of the present invention relates to an AIII-BV compound semiconductor single crystal or, in particular, to a wafer obtained therefrom by separation, wherein, in an annular edge region of the cross-sectional area of the single crystal or wafer (in the case of a wafer, the cross-sectional area is one of the two planar main surfaces) perpendicular to the central axis, the share of dislocation pits associated with slip lines (slip dislocation lines) is equal to 30% or less of the total number of dislocation pits formed in the entire cross-sectional area (excluding an edge equal to 2 mm measured from the outer edge of the single crystal or wafer), wherein the slip lines extend from the edge region of the single crystal or wafer within the cross-sectional area.

[0072] The width of the edge region is given or measured at a distance of 5 mm from the outer edge of the single crystal or wafer. However, an edge exclusion of 2 mm is also defined or deducted, resulting in a radial width of the annular edge region of 3 mm. The annular region is symmetrical with respect to the central axis of the single crystal or wafer. The edge exclusion extends directly from the outer edge and takes into account the region for reliable detection of the physical quantity, as well as the adjacent region, which is no longer accessible in metrological terms due to the typical edge rounding of the wafer in question.

[0073] As mentioned above, a problem that arises at the edges of produced single crystals or wafers is the generation of thermal stresses during the cooling process, which can have the effect, for example, of generating slip lines originating from Frank-Read sources, particularly in the edge region. The sheer number of dislocation pits associated with these slip lines is related to the quality of the single crystal or wafer production process, particularly the cooling process. Such dislocation pits must be distinguished from those associated with dislocations that, for example, have advanced from the seed channel during growth and can be more or less freely distributed.

[0074] Thus, as described in the previous aspects, the specified parameters, for example, describe the quality of the measurement affecting the peripheral region. In the case of a single crystal or wafer, which includes a relatively low proportion of dislocation pits arranged on slip lines (slip dislocation lines), which originate geometrically in the edge region as described above, the quality (EPD) of this edge region is closer to the corresponding quality of the inner region of the cross-sectional area (i.e., the area within the circle defined by the inner boundary line of the edge region facing the central axis). In other words, if the inner region of such a wafer (after separation) meets the requirements for subsequent device manufacturing, this also extends to the surface area within the etched region, and if the value of the specified parameter is sufficiently low, the proportion of the area available for device manufacturing can be increased.

[0075] However, in particular, the proportion of dislocation pits obtained here, which belong to slip lines (herein indicated as slip dislocation lines) extending in a cross-sectional area starting or originating from an edge region of a single crystal or wafer, can advantageously avoid or at least significantly reduce the formation of morphologically macroscopic steps in the wafer surface during the epitaxy step after production. It should be noted that the present low value of the parameter can be achieved in particular by the above-described apparatus.

[0076] According to a preferred embodiment, the proportion of dislocation pits belonging to slip lines extending from the edge region of the single crystal or wafer relative to the total number of dislocation pits may be less than 10%, more preferably less than 5%. The proportion determined in this manner may also be referred to herein as "slip degree."

[0077] To determine this fraction, etch pits are first created in the surface (cross section) of a separated wafer at the locations where dislocations intersect the surface. This can be done in a conventional manner, for example by immersing the surface in molten KOH. The resulting etch pits allow the dislocations to be detected. Then, using a scanning optical microscope with a camera and image processing, for example, with a lateral resolution of 3.7 μm, all etch pits on the surface can be recorded and stored, along with their positional information (XY coordinates, etc.), in a table, for example.

[0078] There may be tens of thousands of etch pits on an 8" wafer. All etch pits on this database are then checked for the assignment of slide lines, whereby the following requirements must be met for the presence and assignment of slide lines as described above:

[0079] - pits representing more than 10 dislocations extending in one direction in the cross-sectional surface;

[0080] - These dislocations form chains with a maximum distance of 500 μm between each adjacent etch pit;

[0081] - the pits are located within a 250 μm wide tolerance interval perpendicular to the direction; and

[0082] - the slip line extends from a point within an annular edge region of the cross-sectional surface, wherein the edge region is defined as being near an outer edge of the surface, the boundary of the outer edge pointing towards the center of the surface being defined by a distance of 5 mm measured from the outer edge of the single crystal or wafer, with an edge exclusion of 2 mm.

[0083] A corresponding algorithm may be provided for searching for the nearest neighbors of the considered pit position and successively checking the above conditions.Finally, the dislocation pits assigned to the slip line are divided by the total number of all dislocation pits.

[0084] According to another embodiment of the above-mentioned AIII-BV compound semiconductor single crystal or a wafer produced therefrom by separation, the relative frequency of the slip lines extending within the cross-sectional area starting or originating from the edge area of the single crystal or wafer is equal to 0.25 cm -1 or smaller, in particular equal to 0.20 cm -1 or smaller.

[0085] In this embodiment, the number of slip lines associated with the periphery of the single crystal or wafer is taken into account (as determined above). This parameter also relates to the quality of the edge region and the amount of reduction in pit density due to improved cooling. This quantity can also be referred to as the "slip dislocation line density". Preferred embodiments provide that this relative frequency can even be less than only 0.1 cm -1 or smaller, more preferably 0.05 cm -1 or smaller.

[0086] Another embodiment provides for calculating the sum of the lengths of the slip lines (determined as described above) and relating this to the diameter of the single crystal or wafer (i.e., the sum of the lengths divided by the diameter). It has been found that, in order to avoid the formation of macroscopic steps during the epitaxial process following fabrication as described above, a value of 6 or less, preferably 1.5 or less, and more preferably 0.8 or less, is particularly suitable for this parameter. This parameter may also be referred to as "slip density" and is a dimensionless parameter.

[0087] Another optional aspect of the present invention relates to a wafer obtained from an AIII-BV compound semiconductor single crystal, or in particular to a wafer obtained therefrom by separation, wherein the wafer has a resistivity distribution within a cross-sectional area perpendicular to its central axis, and wherein the overall standard deviation (σ overall) of the distribution can be equal to 16.0% or less of the resistivity average value within the cross-sectional area of the wafer, wherein the overall standard deviation is based on a characteristic length of 10 mm and takes into account an edge exclusion of 1 mm.

[0088] According to a specific embodiment, the AIII-BV-compound semiconductor is GaAs, and the diameter of the wafer is equal to 150 mm or 6 inches or less, and the overall standard deviation of the distribution (σ overall) is equal to 4.0% or less of the average value of the resistivity within the cross-sectional area of the wafer.

[0089] According to other specific embodiments, the AIII-BV-compound semiconductor is GaAs, and the diameter of the wafer is equal to 200 mm or more than 8 inches, and the overall standard deviation of the distribution (σ overall) is equal to 16.0% or less of the average value of the resistivity within the cross-sectional area of the wafer.

[0090] According to other specific embodiments, the AIII-BV-compound semiconductor is InP, and the diameter of the wafer is preferably equal to 100 mm or 4 inches, and the overall standard deviation of the distribution (σ overall) is equal to 17.0% or less of the average value of the resistivity within the cross-sectional area of the wafer.

[0091] These parameters describing the electrical properties of single crystals and / or wafers include in particular the electrical resistance p. Spatially resolved measurements of the well-known electrical resistance p can be performed using the so-called COREMA (contactless resistivity mapping) (Jantz, W. and Stibal, R. in "Contactless resistivity mapping of semi-insulating substrates". III-Vs Review 6[4], 38-39. 1993; and Stibal, R., Wickert, M., Hiesinger, P., and Jantz, W. in "Contactless mapping of mesoscopic resistivity variations in semi-insulating substrates", Materials Science and Engineering B 66[1-3], 21-25, 1999). The typical spatial resolution of this method is around 1 mm. 2 and the mapping can be performed over the entire surface, as reflected in the term cross-sectional area used herein, with the exception of the edges.

[0092] The determination of global, local and "overall" standard deviations from corresponding measurement data is described in DE 10 2007 026 298 A1 and WO 2008 / 148542 A1 (or US Pat. No. 8,652,253 B1). The contents of WO 2008 / 148542 A1, pages 20-23, are incorporated herein by reference, but will be summarized again as follows:

[0093] Therefore, the COREMA measurement data of these points are divided: for each point (x, y) in the cross section or wafer plane perpendicular to the central axis, a regression plane is calculated from the measurement data of those neighboring points lying inside a circle of radius ζ, i.e. the characteristic length mentioned above:

[0094] ρ measurement = ρ regression plane + ρ change (4)

[0095] The measured resistance ρ is expressed as the sum of two summands. 回归平面 is the value of the regression plane at point (x, y), and ρ 变化 is the distance between the function value and the measured value in the regression plane.

[0096] The least squares fit of the plane ρ(x, y) = a + bx + cy for N data points can be uniquely calculated by solving the linear equation system

[0097]

[0098] The degree of uniformity of the resistance on different length scales across the wafer surface can now be expressed as follows:

[0099] 1. Total standard deviation:

[0100] in

[0101] 2. Local standard deviation:

[0102]

[0103] is the regression plane at point (x i ,y i ) at the function value; and

[0104] 3. Population standard deviation:

[0105] in

[0106] Examining the measured variables (parameters) at different length scales allows for more precise analysis. A range on the order of a few dislocation units or grains (radius ζ equal to 5-10 mm) is considered local. Using the minimum resolution of radius ζ, fluctuations across the entire wafer are considered global. Fluctuations at different length scales may have different physical causes.

[0107] In order to individually consider local and global fluctuations in the measured resistivity, measurement mapping with high lateral resolution is required. Distances to the wafer edge that are smaller than the edge-excluded measurement field are not taken into account in the evaluation.

[0108] Thus, two variables can be defined: boundary exclusion and characteristic length ζ, after which the numerical calculation of the variables is well defined and can be reproduced by anyone.

[0109] In the COREMA map of resistance ρ, the global fluctuations are determined by the slow changes in the defect budget. Global fluctuations are larger than local fluctuations, so the standard deviation of all measured values of the resistance is more of a measure of the global variation.

[0110] Considering for example a wafer with a diameter of 150 mm, all measurements can be performed with a scan width of 160×160 mm and 320×320 data points in the x and y directions, averaged over ζ=10 mm and in this case with an edge exclusion of 1 mm.

[0111] In this context, a particular embodiment of the wafer according to this aspect provides that the corresponding value of the relative overall standard deviation (σ overall divided by the average value over the entire wafer) of the resistance measured only in an edge region taking into account an edge exclusion of 1 mm is equal to 35.0% or less, wherein the width of the edge region is defined by a distance of 3 mm or less measured from the outer edge of the wafer, the edge exclusion being 1 mm.

[0112] With such values, acceptable conditions can already be created in the edge region with regard to the homogeneity of the electrical parameters, so that this edge region, i.e. the portion of the wafer surface below a distance of 3 mm from the wafer edge, can now also be considered for subsequent production of the component.

[0113] Another embodiment of the proposed wafer provides that in the annular edge region of the cross-sectional area of the single crystal or wafer, the mean value or the median value of the residual strain content distribution perpendicular to its central axis (M) can be equal to 2.5×10 -6 or smaller, preferably 1.6×10 -6 or less, wherein the residual strain in a cross-sectional area in the edge region of the single crystal or wafer is derived in a spatially resolved manner from measurements according to the SIRIS method, wherein the lateral resolution of the spatially resolved measurement is 100 μm, wherein the width of the edge region is defined by a distance of 3 mm or less measured from the outer edge of the single crystal or wafer, wherein the edge is excluded by 1 mm.

[0114] This further embodiment provides for the simultaneous specification of electrical parameters (homogeneity of resistivity) and mechanical parameters (e.g. residual strain or residual stress) of the edge region. The mechanical parameters are closely related to the structural perfection (e.g. represented by the EPD). Structural perfection and electrical homogeneity can be contradictory properties in a particular crystal with respect to its quality: if one parameter has an excellent value, the other parameter can still leave a lot of potential open space, and vice versa. This is probably due to the interaction between the generally known extrinsic and intrinsic point defects and structural defects such as dislocations or grain boundaries, which are responsible for the electrical properties of the material. Microsegregation can thus be observed. If the structural defects are very dense, the concentration inhomogeneities are small, resulting in a satisfactory uniformity of the electrical properties. In the opposite case, the average distance between the structural defects is large, so that relatively large concentration differences can occur for the point defects due to microsegregation.

[0115] The residual strain can be calculated directly from the residual shear stress determined by measurement according to Kelly, PA Mechanics Lecture Notes: An introduction to Solid Mechanics, which is available from http: / / homepages.engineering.auckland.ac.nz /

[0116] ~pkel015 / SolidMechanicsBooks / index.html,http: / / homepages.engineering.auckland.ac.nz / ~pkel015 / SolidMechanicsBooks / Part_II / 04_ElasticityPolar / ElasticityPolars_Complete.pdf, as follows: The relationship between two-dimensional stress and strain is

[0117]

[0118] The following apply to states of plane stress and strain, respectively:

[0119]

[0120] Hooke's law (plane strain) (4.2.5b)

[0121] Therefore, the residual strain can be calculated as follows:

[0122]

[0123]

[0124]

[0125] in

[0126] The material constants are expressed as the elastic constant E and the lateral contraction number ν (or Poisson's ratio), with E = 85.9 GPa, ν = 0.31 for GaAs and E = 61.1 GPa, ν = 0.36 for InP.

[0127] The lateral residual shear stress distribution can be measured by measuring the photoelastic infrared depolarization using a transmission dark-field polarimeter (e.g., Transmission Vertical Integrated Photoelastic Measurement with Lateral Resolution, Scanning Infrared Stress Inspection System (SIRIS): saHerms, M., Irmer, G., Kupka, G., et al.: "Comparative Study of the Photoelastic Anisotropy of Si and GaAs". J. Electron. Mater. 49, 5205-5212 (2020), https: / / doi.org / 10.1007 / s11664-020-08141-7, also see: Geiler, Hans D., et al.: "Photoelastic characterization of residual stress in GaAs-wafers." Materials Science in Semiconductor Processing 9 (2006): 345-350). Using multipolarization analysis of multiple measurements of wafers with different rotation axes, the residual stress can be quantitatively determined over the entire wafer surface, independent of the crystallographic direction, as in the case of the SIRD method. However, the values given here can also be applied objectively and independently of the measurement method.Further information on the methods and evaluations can be found in the following publications: Higginbotham, CW, Cardona, M. and Pollak, FH, "Intrinsic Piezobirefringence of Ge, Si and GaAs", Phys. Rev. 184, 821 (1969); Timoshenko, S. and Goodier, JN, Theory of Elasticity, McGraw-Hill Book Company, Inc. 1951; Suzuki, T., Yasutomi, T., Tokuoka, T., Yonenaga, I., "Plastic deformation of GaAs at low temperatures", Phil. Mag. A, 1999, Vol. 79, No. 11, 2637-2654; Herms, M., Wagner, M., Kayser, S., Kiessling, F. M., Poklad, A., Zhao, M., Kretzer, U., "Defect-induced Stress Imaging in Single and Multi-crystalline SemiconductorMaterials",Materials Today:Proceedings,Volume 5,Issue 6,Part 3,2018,Pages14748-14756.

[0128] In each case, the quantity measured is the phase shift between the different polarization directions of the light beam, which depends on the voltage-induced birefringence (photoelastic effect). The phase shift Δ is related to the difference Δσ in the principal stress values by Wertheim's law from stress optics and is therefore related to the maximum shear stress by the stress optics material constant. For small changes, the stress-induced change in the inverse dielectric tensor ΔB is linearly related to the stress or strain. In particular, there is a high degree of linearity in the stress range up to 1 MPa considered here, especially because these stresses are several orders of magnitude lower than the critical shear stress at room temperature (which is 600 MPa or more). The minimum resolvable shear stress with the SIRIS method is about 0.1 kPa, which represents the lower limit for the specified residual stress.

[0129] According to this embodiment, the wafer is therefore provided with an edge region, such that the edge region is now also at least partially available (ie still without edge exclusion) for subsequent device production.

[0130] An embodiment of the wafer according to this aspect provides that the mean or median value of the distribution of the residual stress content in the edge region is equal to 1.1×10 -6 or smaller.

[0131] Another aspect of the present invention relates to a wafer produced by separation from an AIII-BV compound semiconductor single crystal, wherein the mean value of the residual stress content distribution within an annular edge region of a cross-sectional area of the wafer perpendicular to its central axis (M) is equal to 60 kPa or less, wherein spatially resolved measurements of the residual stress within a cross-sectional area within the edge region of the single crystal or wafer are performed according to the SIRIS method, wherein the lateral resolution of the spatially resolved measurements is equal to 100 μm, wherein the width of the edge region is defined by a distance of 3 mm measured from the outer edge of the single crystal or wafer, wherein the edge exclusion is 1 mm.

[0132] According to this aspect, wafers are also provided such that their edge regions are at least partially (ie except for the edge exclusion) available for the subsequent production of devices.

[0133] An embodiment of the wafer according to this aspect provides that the mean value of the distribution of the residual stress content in the edge region is equal to 30 kPa or less, preferably 25 kPa or less.

[0134] According to a specific embodiment, the average value of the residual stress content distribution in the annular edge area of the cross-sectional area of the single crystal or wafer perpendicular to its central axis (M) is equal to 60 kPa or less, wherein the AIII-BV-compound semiconductor is GaAs and the diameter of the wafer is equal to 200 mm or 8 inches or more, respectively.

[0135] According to another specific embodiment, the average value of the residual stress content distribution in the annular edge area of the cross-sectional area of the single crystal or wafer perpendicular to its central axis (M) is equal to 30 kPa or less, wherein the AIII-BV-compound semiconductor is GaAs and the wafer diameter is 150 mm or 6 inches, respectively.

[0136] According to other embodiments, the AIII-BV-compound semiconductor is InP, the diameter of the wafer is equal to 100 mm or 4 inches or more, respectively, and the average value of the residual stress content distribution in the annular edge area of the cross-sectional area of the single crystal or wafer perpendicular to its central axis (M) is equal to 60 KPa or less, preferably 30 KPa or less.

[0137] It should be noted that the present invention also provides single crystals or wafers that provide the properties according to the above-mentioned independent aspects in a combined manner, such as a wafer having parameter values specified with respect to slip lines emanating from the edge region (share of dislocation pits to be allocated to the slip lines, total length of the slip lines relative to the wafer diameter, number / frequency of slip lines relative to the wafer circumference), which conforms to the resistance value range in the edge region as described above, for example as determined in a COREMA measurement, and which has residual mechanical shear stress and / or strain in the edge region.

[0138] These and all wafers or single crystals listed above can have a diameter perpendicular to the central axis of between 100 mm and 220 mm, including the boundary values at the specified intervals. In particular, the nominal diameter can be 100 mm (corresponding to 4"), 150 mm (corresponding to 6") or 200 mm (corresponding to 8").

[0139] Furthermore, the above-mentioned AIII-BV compound semiconductor single crystal or a wafer produced therefrom by separation may specifically include gallium arsenide (GaAs) or indium phosphide (InP).

[0140] It should be noted that the arrangement proposed here can also be specifically configured to perform crystallization according to a VGF process or alternatively according to a VB process or alternatively a combined VGF and VB process, i.e. varying the temperature field and the movement of the crucible relative to the heater or heating element.

[0141] Further advantageous embodiments of the invention can be found in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0142] The present invention will now be explained in more detail with reference to the accompanying drawings.

[0143] Figure 1 : shows a schematic cross section of an apparatus for producing an AIII-BV compound semiconductor single crystal from a melt of raw materials according to an embodiment;

[0144] Figure 2 : Shows that compared with the traditional case, when using Figure 1 An enlarged view of the phase boundary formed between the melt of the raw material and the growing single crystal in the region of the crucible wall when the device is used;

[0145] Figure 3 : purely schematically shows only those edge regions at the wafer edge which are reasonably accessible for measuring various parameters, such as etch pit density (EPD), resistivity, residual mechanical shear stress or strain;

[0146] Figure 4 : shows a cross section of a wafer surface in which dislocation etch pits are formed to capture slip lines;

[0147] Figure 5 : shows a cross section of a wafer surface in which dislocation etch pits are formed to detect slip lines;

[0148] Figure 6 :like Figure 6 , but showing the corresponding top view of a flat wafer surface;

[0149] Figure 7 : shows the distribution of etch pits across the wafer surface of an 8" GaAs wafer (diameter: 200 mm) according to one embodiment;

[0150] Figure 8 : Shows Figure 7 distribution of those dislocation etch pits determined in

[0045] , which can be assigned to slip lines generated in a defined edge region at a distance of 2 to 5 mm from the outer wafer edge (or contacting this edge region with dislocation etch pits);

[0151] Figure 9 : shows the distribution of residual stress measured by SIRIS at a distance of ≤3 mm from the wafer edge (excluding 1 mm from the edge) on six 6" GaAs wafers made of two different single crystals according to the embodiment;

[0152] Figure 10 :shows the Figure 9 Residual strain distribution calculated from residual stress measured by SIRIS at a distance ≤3 mm from the wafer edge on six 6" wafers made from two single crystals of the embodiment, thereby converting the plane stress state into a plane strain state, where the material constants E = 85.9 GPa, ν = 0.31 (for GaAs);

[0153] Figure 11 : shows the profile of the values of the resistivity across the wafer surface determined in a COREMA measurement, whereby a wafer with 1 mm oversize and with missing edge rounding (solid line) and a wafer with edge rounding and no oversize for comparison (dashed line) are measured, according to an embodiment;

[0154] Figure 12 : shows the distribution of etch pits across the wafer surface (cross-sectional area) of a 4" InP wafer (diameter: 100 mm) according to one embodiment;

[0155] Figure 13 : shows the distribution of etch pits across the wafer surface (cross-sectional area) of another 4" InP wafer (diameter: 100 mm) according to one embodiment;

[0156] Figure 14: shows the distribution of etch pits across the wafer surface (cross-sectional area) of a 6" GaAs wafer (diameter: 150 mm) according to one embodiment;

[0157] Figure 15 : shows the distribution of etch pits across the wafer surface (cross-sectional area) of another 6" GaAs wafer (diameter: 150 mm) according to one embodiment;

[0158] Figure 16 : shows the resistivity distribution across the wafer surface (cross-sectional area) of a 4" InP wafer (diameter: 100 mm) according to one embodiment;

[0159] Figure 17 : shows the resistivity distribution across the wafer surface (cross-sectional area) of another 4" InP wafer (diameter: 100 mm) according to one embodiment;

[0160] Figure 18 : shows the resistivity distribution across the wafer surface (cross-sectional area) of an 8" GaAs wafer (diameter: 200 mm) according to one embodiment;

[0161] Figure 19 : shows the resistivity distribution across the wafer surface (cross-sectional area) of another 8" GaAs wafer (diameter: 200 mm) according to one embodiment;

[0162] Figure 20 : shows the resistivity distribution across the wafer surface (cross-sectional area) of another 8" GaAs wafer (diameter: 200 mm) according to one embodiment;

[0163] Figure 21 : shows the resistivity distribution across the wafer surface (cross-sectional area) of another 8" GaAs wafer (diameter: 200 mm) according to one embodiment.

[0164] Detailed description of the preferred embodiment:

[0165] In the following description of preferred embodiments, it should be taken into account that the various aspects of the present disclosure are not limited to the details of the construction and arrangement of the components as shown in the following description and drawings. The embodiments may be implemented or realized in various ways. It should also be noted that the expressions and terms used herein are only for the purpose of specific description and should not be interpreted in a restrictive manner by the skilled person. In addition, in the following description, the same reference numerals in the various embodiments or drawings represent the same or similar features or objects, so that in some cases, repeated detailed descriptions of the same features or objects are omitted in order to maintain the compactness and clarity of the description.

[0166] Figure 1A schematic cross-sectional view of an apparatus 1 for producing an AIII-BV compound semiconductor single crystal from a raw material melt according to an embodiment is shown. The apparatus 1 includes a crucible 6 for containing a raw material melt or for containing raw materials before melting; and a component 10 surrounding the crucible 6. The apparatus also includes a heater and a controller, the heater including one or more heating elements, the controller controlling the heater to melt the raw materials and generate and maintain a directional temperature field during controlled cooling. Figure 1 , the heater is not shown as being separate from the surrounding components 10, but is still present. The crucible has a central axis M, and the heater is located behind / outside the components 10 surrounding the crucible when viewed from the central axis M of the crucible 6.

[0167] The crucible 6 has a seed channel 3 into which the seed crystal is inserted. Starting from the seed channel 3 having a diameter of, for example, 5-100 mm, a tapered (conical) crucible portion extends with increasing diameters, and a cylindrical crucible portion extends therefrom with a diameter d of, for example, 100-120 mm, 150-170 mm or 200-220 mm. The prescribed intervals of diameter correspond to the nominal diameter of the wafer obtained from the single crystal by separation (cutting) plus an oversize of, for example, 0-20 mm, which takes into account the removal of uneven or uneven surface material from its side surfaces. The AIII-BV compound semiconductor single crystal can be made of GaAs or InP. Without limiting generality, the nominal diameter of an InP single crystal can be 100 mm (4") or 150 mm (6"), and the nominal diameter of a GaAs single crystal can be 150 mm (6") or 200 mm (8"). In principle, other diameters (eg 200 mm or 8 inches for InP or 12 inches or 300 mm for GaAs) and materials (eg GaP) are also possible.

[0168] exist Figure 1 The lower part of the crucible 6 is shown, showing a single crystal 4 growing upward from a seed crystal. Crystal growth or phase boundaries 2, 2* represent the transition to the above-located raw material melt 5. The raw material melt 5 is covered by a protective layer (not shown) of boron oxide (B2O3), which may also extend between the melt or single crystal and the crucible wall 7. Figure 1 The heater (not shown) generates a temperature field in the crucible 6 that is substantially parallel to the central axis M. The gradient is directed downward in the vertical direction. Figure 1 As shown, especially in Figure 2In the enlarged view of FIG, phase boundary 2 or 2* does not form a straight, flat surface, but rather curves in a direction parallel to the central axis M toward the edge of crucible 6, i.e., outer crucible wall 7. As described above, this is because, on the one hand, heat can be transferred along outer crucible wall 7 more efficiently than through the melt and / or the crystalline material itself, while, on the other hand, heat losses due to thermal radiation are clearly relevant here. As a result, the edge regions of the single crystal and the overlying melt are subject to a thermal gradient component, which in this case is also radial, so that during the immediate cooling period after crystallization, thermal stresses can occur in the edge regions of the single crystal, leading to increased dislocation formation compared to the interior of the crystal (closer to the central axis M).

[0169] However, Figure 1 Also shown are measures according to the present invention, which are intended to offset this deviation from the linear phase boundary. In particular, in this embodiment, the crucible outer wall 7, which is itself formed by pyrolytic boron nitride (pBN), has an outside 11a formed by a shiny metallic coating 8a made of platinum. The melting point of platinum is 2041.4K, which is significantly higher than GaAs (1511K), InP (1343K) or GaP (1621K), and can be technically deposited in a suitable manner on a crucible formed by pBN (melting point BN: 3240K) without further processing. Without limiting generality, for example, sputtering (including bombarding platinum with an electron beam to evaporate platinum and depositing it on or against the crucible wall) can be considered. A platinum layer thickness between 1 μm and 10 μm can be sufficient, but smaller or larger thicknesses are also possible. In this exemplary embodiment, the outside 11a of the crucible wall is formed by coating 8a substantially over its entire surface - at least in the cylindrical crucible partial region.

[0170] Furthermore, the crucible-surrounding component 10, which can be, for example, a hard graphite shell or a graphite-coated quartz tube (so-called liner), has an inner surface 11b, which is arranged opposite the outer surface 11a of the crucible wall 7 and is formed by a platinum coating 8a which is sandwiched by the intermediate space 8 and is separated from the outer surface 11a by a distance e. Thus, the inner surface 11b is also formed by a shiny metallic (or optionally also metallically rough) coating 8b, which is formed of metal in this case. The intermediate space 8 is delimited by the inner surface 11b of the crucible-surrounding component 10 and the outer surface 11a of the crucible wall 6 (but can also be, for example, Figure 1 The distance e can be, for example, between 1 mm and 15 mm (inclusive), preferably between 1 and 3 mm.

[0171] Between the crucible 6 and the peripheral device (e.g., component 10), a heat radiation exchange occurs across the intermediate space 8. Due to the shiny metallic coating 8a formed of platinum, in a particular embodiment, the emissivity ε1 of the outside of the crucible wall 7 is equal to a value of 0.01, where the emissivity indicates how much radiation the crucible wall emits compared to an ideal radiant heater. In addition, the shiny metallic coating 8b of the inner face of the component surrounding the crucible has an emissivity ε2, for example, equal to 0.01. Using equation (3), the radiation exchange degree E in this design example is therefore a value of about 0.005. Therefore, the exchange of heat radiation is significantly reduced.

[0172] exist Figure 1 In the figure, for simplicity of illustration and comparison with the prior art, only the coatings 8a and 8b are shown on the left. However, in this embodiment, the actual coatings 8a and 8b extend around the circumference of the inner face 11a and the outer face 11b, respectively. The corresponding phase boundaries are indicated by dashed lines and are marked with the reference numeral 2*. Figure 1 On the right-hand side, the coating is omitted for comparison, which corresponds to a conventional structure. In this (conventional example), the emissivity ε1 on the outer side of the crucible wall 6 and the emissivity ε2 on the inner side of the component 10 are, for example, equal to 0.5 and 0.8, respectively, so that the radiation exchange coefficient E has a value of 0.44. Figure 1 In the embodiment, the corresponding phase boundary is denoted by reference numeral 2 and has a significantly greater phase boundary deflection than the phase boundary 2*, as in particular in Figure 2 It can be seen in.

[0173] For the two phase boundaries 2, 2*, the inclination angle of the phase boundary at the crucible wall 7 is also given by Figure 2 As mentioned above, the shape of the phase boundary is unfortunately beyond the capabilities of direct observation, however, thermal simulations (latent heat, heat conduction, thermal radiation and laminar convection) using the CGSIM software package (https: / / www.str-soft.com / ) have been able to confirm the influence of the lower phase boundary deflection on the lower radiation exchange degree due to measurements taken at the crucible edge (value calculated for growing a 6″ GaAs single crystal at a growth rate of 2 mm / h):

[0174] Table 1:

[0175]

[0176] In Table 1, at or near the crucible wall 7, the inclination angle between the phase boundary and the horizontal is given, which corresponds to Figure 2 The crucible contact angles shown in FIG are different. The tilt angle is calculated as 90° minus the crucible contact angle. A tilt angle of 0° corresponds to a flat phase boundary at the crucible wall 7.

[0177] For a growth rate of 0.4 mm / h at emissivities of 0.5 and 0.8, a phase boundary deflection of 11.0 mm was obtained at a crucible contact angle of 38°.

[0178] Table 2 lists the values obtained from the corresponding thermal simulation of indium phosphide (6"InP single crystal). The growth rate used here is also equal to 2 mm / h.

[0179] Table 2:

[0180]

[0181] In addition, the effect of growth rate on phase boundary deflection was investigated in thermal simulations. The results are summarized in Table 3, using the example of a 6" GaAs single crystal:

[0182] Table 3:

[0183]

[0184] Table 4 shows the corresponding results of thermal simulation of a 6" InP single crystal:

[0185] Table 4:

[0186]

[0187] The effect of the thermal conductivity of the crucible wall material (or its composition) on the resulting phase boundary deflection for different emissivities can also be determined from thermal simulations. The results for a 6" GaAs single crystal are shown in Table 5:

[0188] Table 5:

[0189]

[0190] Table 6 shows the corresponding results of thermal simulation of a 6" InP single crystal:

[0191] Table 6:

[0192]

[0193] To achieve the desired emissivity for a given device, the values listed in Table 7 below can be considered:

[0194] Table 7:

[0195]

[0196]

[0197] In order to obtain a radiation exchange degree of 0.1 or less, according to the invention, it is sufficient to realize an emissivity of 0.1 on only one side, taking into account equation (3), while realizing any type of surface on the opposite side, using, for example, the data from Table 2. The suitability of materials for realizing temperature-dependent emissivity is known, for example, from: https: / / www.sciencedirect.com / science / article / abs / pii / S0017931019321623.

[0198] Furthermore, simulations have shown that the implementation of the measures according to the invention (coating with reduced emissivity) can result in a reduced growth rate, which, however, may no longer be economical in production due to increased production costs. For example, by correspondingly controlling the heater or heating element in a conventional setup, the crystal growth rate can be reduced from 2.0 mm / h to 0.4 mm / h (five times the cooling time) in order to obtain a similar phase boundary deflection and a similar tilt angle near the crucible edge as shown in Table 1 for the device 1 according to the invention with ε1=0.01 and ε2=0.01. Unfortunately, at least from an economic point of view, emissivity values below 0.04 or even lower are currently technically almost impossible to achieve.

[0199] According to an embodiment of the method of the present invention, there is also provided Figure 1 and 2 The apparatus 1 shown in FIG. 1 is configured to perform the following steps: inserting a seed crystal into a seed crystal channel, filling a crucible with raw materials (comprising Ga and As, or In and P, etc.), melting the raw materials to obtain a raw material melt until the seed crystal is slightly melted, applying a directional temperature field, reducing the temperature level of the temperature field for long-term crystal growth in the vertical direction, and controlled cooling of the grown single crystal. Thus, the reduced phase boundary deflection can be improved by further slowing the growth rate, for example, to 1 mm / h or less, 0.5 mm / h or less, or even 0.4 mm / h or less. Here, an economical compromise can be made between the resulting higher yield (a larger proportion of the usable area at the edge of each wafer) and the extended production time.

[0200] The apparatus and method enable the production of AIII-BV compound semiconductor single crystals and wafers obtained therefrom by separation, which have particularly excellent properties with respect to the wafer edge. Wafers having corresponding properties (described below) can be produced by the apparatus or by equivalent methods described above with reduced growth rates:

[0201] Figure 3First, a purely schematic representation of the edge region at the wafer edge is shown. This edge region can only be used to measure various parameters such as etch pit density (EPD). For example, according to the definition given above, an edge exclusion of 2 mm (measured from the wafer edge) is required for recording slip lines (slip dislocation lines) for etch pit density. A width of 3 mm results in an edge region between 2 and 5 mm from the wafer edge.

[0202] In the resistivity measurement according to the COREMA method, the edge exclusion is 1 mm, and the width of the edge region is 2 mm (range: 1 mm to 3 mm from the wafer edge). However, this measurement is performed before the usual edge rounding (KV) of the wafer and has an additional 1 mm (radius, 2 mm diameter) oversize (exceeding the nominal diameter) because otherwise the measurement would be too prone to errors. The oversize is subsequently removed from the non-edge-rounded wafers.

[0203] Figure 4 An example of a cross section through a wafer surface with dislocation pits formed therein is shown. The slight modification of the required slip line definition compared to the SEMI M10 standard is immediately apparent from this figure: at low EPDs, the mutual distances between pits are so large that the existing definition breaks down. Furthermore, slight lateral deviations of the pits involved in the slip line can be identified, which may be due to interactions with other dislocations. Therefore, the definition given above, which logically derives from SEMI M10, is used for the determination of slip lines (and here also denoted as slip dislocation lines).

[0204] Figure 5 A schematic diagram illustrating the formation of slip lines is shown. Slip planes 111 are closely packed planes in the crystal lattice that have a relatively large lattice spacing relative to the next plane. Prior to separation, they are oriented at an angle to the wafer surface 100 or the cross-sectional area of the single crystal. Dislocation loops 120 are emitted from the Frank-Read source (visible on the left) in the slip planes. These are arranged in slip lines 130 on the wafer surface 100 to form dislocation pits 140 (if the surface is treated with a KOH solution). Figure 6 A corresponding top view of the wafer surface 100 is shown.

[0205] Figure 7 Shown is the distribution of etch pits across the surface for an 8" GaAs wafer (diameter: 200 mm) similarly manufactured according to the embodiment of the present invention as described above. Figure 8 The distribution of dislocation pits determined according to this embodiment is shown, which can be associated with slip lines originating from and extending from the edge region as defined above. Measurements were performed on semiconductor silicon doped materials to determine the slip lines (where the corresponding resistivity is in the range of 0.05-10·10 18 cm -3, especially 0.3-3·10 18 cm -3 The average density of the etch pits over the entire wafer surface (i.e., the cross-sectional surface, but without the edge exclusion area: 2 mm) was 112 cm -2 .exist Figure 7 and 8 In the embodiment shown, the relative frequency of the slip lines extending from the planar wafer surface or the single crystal or wafer edge region within the cross-sectional area, respectively, is related to the perimeter of the cross-sectional area of the wafer or single crystal, and is equal to 0.27 cm -1 .

[0206] In Table 8 below, values measured for three 8" GaAs wafers (diameter: 200 mm) produced by separation from a single crystal according to an embodiment of the present invention or values determined from the measurement results are shown:

[0207] -Etch pit density ((a) average; (b) EPD = 0 cm -2 The share of the measurement field; (c) EPD < 500 cm -2 (d)EPD<1000cm -2 ),

[0208] - the proportion of dislocation pits (which may be associated with slip lines extending from the edge region of the wafer) (simply expressed as the parameter "slip degree"),

[0209] - the total length of these slip lines related to (divided by) the wafer diameter (simply expressed as the parameter "slip density"), and

[0210] - The frequency (number) of such relevant slip lines (divided by the wafer circumference (simply expressed as the parameter "slip dislocation line density"):

[0211] Table 8A:

[0212]

[0213] Wafers having these low values of slip degree, slip density and slip line density as defined above are particularly suitable for the subsequent use of previously unused edge areas at the edge of the wafer in epitaxial steps for manufacturing electronic or optical components without intolerable morphologically macroscopic step formation on the surface which exceeds the specified tolerance values regarding the number and / or length of steps.

[0214] Research has also been extended to GaAs wafers with reduced diameter (6" or 150 mm), as well as InP wafers.

[0215] The corresponding measurement results on three 6″-GaAs wafers (diameter: 150 mm) are described in Table 8B below:

[0216] Table 8B:

[0217]

[0218] The corresponding measurement results for three 4″-InP wafers (diameter: 100 mm) are described in Table 8C below:

[0219] Table 8C:

[0220]

[0221]

[0222] The same conclusions regarding the embodiments of the 6" GaAs wafer and the 4" InP wafer can be drawn for the 8" GaAs wafer fabricated according to an embodiment of the present invention. Figure 12-15 Describes a 6″GaAs wafer ( Figure 14 and 15 Wafer samples #9 and #10) and 4″InP wafer ( Figure 12 and 13 The cross-surface etch pit distribution of wafer samples #7 and #7 in FIG is similar to that of FIG. Figure 7 The same is true for wafer sample #4 of the 8″ GaAs wafer.

[0223] Figure 9 and 10 The cumulative distribution of residual mechanical shear stress or residual strain measured using the SIRIS method (as described above) within an edge region defined by a distance of 1-3 mm from the edge of the wafer is disclosed for six 6" GaAs wafers (diameter: 150 mm) according to an embodiment of the present invention.

[0224] Here, too, particularly low values were found, such as the median value: 100% of all measured values for residual stress (for each edge region of the respective wafer) were below 80 kPa, 80% of all measured values for residual stress (for each edge region of the respective wafer) were below 50 kPa, and 50% of all measured values for residual stress (for each edge region of the respective wafer) were significantly below 30 kPa, or more precisely, below 25 kPa. In three of the six samples, the median value (50% of the measurement range) was even less than 15 kPa.

[0225] The same applies to the residual strains calculated directly from the residual shear stress determined for the material: 100% of all measured values of the residual strain (for each edge region of the corresponding wafer) are below 2.50 × 10 -6 , 80% of all measured values of residual strain (for each edge region of the corresponding wafer) are below 1.53×10 -6, and 50% (median value) of all measured values of residual strain (for each edge region of the corresponding wafer) are below 0.92×10 -6 , or more precisely less than 0.75×10 -6 .

[0226] Table 9A below shows the average (or mean) values of the mechanical parameters of residual stress and residual strain determined for samples according to the embodiment:

[0227] Table 9A:

[0228]

[0229]

[0230] In particular, the average (mean) value of the residual strain is significantly lower than the 2.5×10 -6 These values also emphasize that the wafer according to the embodiment is suitable for achieving a step-free epitaxial rear surface on the wafer, even in its edge region, with an edge exclusion of up to 1 mm.

[0231] According to the embodiment, residual stress measurements were also performed on 8" GaAs wafers (diameter: 200 mm, formed of semiconductor materials). Table 9B below shows the average values of mechanical residual stress and residual strain measured for the samples according to the embodiment:

[0232] Table 9B:

[0233]

[0234] The results can still be considered favorable and reasonable.

[0235] Figure 11 The resistivity across the wafer surface determined in a COREMA measurement of a wafer sample (6"-GaAs wafer diameter: 150 mm, made of semi-insulating material (range of resistivity values, e.g., 10 7 -10 9 Ωcm, especially 1·10 8 Ωcm-8·10 8 The graph shows the values of the resistivity in Ωcm). As described, measurements were made on wafers with an oversize of 1 mm and without edge rounding. The dashed line shows the corresponding measurement with edge rounding and without oversizing for comparison. The measured values at the very edges show strong, unrepresentative deviations that do not allow any statements to be made about the actual resistivity conditions in the edge region of the sample, which is why the measurements were made with wafer oversizing, which is more representative.

[0236] Evaluation of the curves for determining the uniformity of the resistance distribution shows (see equations (4) to (8) above), for example Figure 11 The overall standard deviation of the samples is less than 4% with respect to the entire wafer surface excluding only 1 mm from the edge, that is:

[0237] σ ρ Total = 5.23%

[0238] σ ρ Overall = 3.51%

[0239] σ ρ Local = 3.61%

[0240] The values for the same wafer sample or embodiment with an edge exclusion of 3 mm are as follows:

[0241] σ ρ Total = 5.07%

[0242] σ ρ Overall = 3.39%

[0243] σ ρ Local = 3.55%.

[0244] The annular edge region defined solely by the distance from the wafer edge of 1 to 3 mm (ie, excluding the edge by 1 mm) provides an overall standard deviation of 31.65%.

[0245] The corresponding values for conventionally manufactured 6" GaAs VGF wafers are described in the aforementioned publications DE 102007026298 A1 or WO 2008 / 148542 A1 (or US 8,652,253 B1), where only the 3 mm edge exclusion of interest is taken into account:

[0246] Example 1:

[0247] σ ρ Total = 6.5%

[0248] σ ρ Overall = 5.3%

[0249] σ ρ Local = 2.5%

[0250] Example #2:

[0251] σ ρ Total = 4.5%

[0252] σ ρ Overall = 2.8%

[0253] σ ρ Local = 1.25%

[0254] Since the overall standard deviation of the resistivity related to the edge region covering the distance range of 1-3 mm towards the edge of the wafer allows to expect even relatively higher values, as in the above-described embodiment, the values of 5.3% and 4.5% according to the comparative example will increase significantly if only an edge exclusion of 1 mm is taken into account.

[0255] The values achieved with this embodiment are therefore also very low, especially when taking into account the now narrower edge exclusion compared to the prior art.

[0256] In view of the positive results of 6-inch GaAs wafers, according to an embodiment of the present invention, 8-inch GaAs wafers (diameter: 200 mm, made of semi-insulating material, with a resistivity value ranging from, for example, 10 7 -10 9 Ωcm, specifically 1·10 8 Ωcm-8·10 8 The COREMA measurement was performed in Ωcm. Since the wafer diameter was too large to fit in the measuring device before edge rounding, the wafer was divided into exactly four sections and each section was measured separately. Evaluation of the measurement data for the complete (entire) wafer surface, with an edge exclusion of only 1 mm, yielded the following values:

[0257] Table 10

[0258]

[0259] With reference to the edge region only, evaluation of the measurement data for the same embodiment provides the following values for a distance from the wafer edge ranging from 1 to 3 mm (i.e. excluding 1 mm from the edge):

[0260] Table 11

[0261]

[0262] The topography of the wafer P0790_24 is Figure 18 As shown in FIG, the topography of the wafer Q2250_02 is Figure 19 As shown in FIG, the topography of the wafer Q2250_46 is Figure 20 As shown in FIG, the topography of the wafer Q2250_93 is Figure 21 Shown in.

[0263] According to the embodiment, four 4″-InP wafers (diameter: 100 mm, made of semi-insulating material with a resistivity of 0.8·10 8 Ωcm-4·10 8 The COREMA measurement was performed with an edge exclusion of only 1 mm and the evaluation of the measurement data relative to the complete (entire) wafer surface yielded the following values:

[0264] Table 12:

[0265]

[0266] With reference to the edge region only, evaluation of the measurement data for the same embodiment provides the following values for a distance from the wafer edge ranging from 1 to 3 mm (i.e. excluding 1 mm from the edge):

[0267] Table 13:

[0268]

[0269] The morphology of chip P7763_33 is as follows Figure 16 As shown, the topography of the wafer 7763_67 is as follows Figure 17 shown.

Claims

1. An apparatus (1) for producing an AIII-BV compound semiconductor single crystal (4) from a melt (5) of a raw material, comprising: A crucible (6) for accommodating a melt, wherein the crucible (7) has a central axis (M) and a crucible wall (7) having a shell-shaped outer surface facing away from the central axis (M) in a radially outward direction; a member (10) substantially surrounding the crucible (6) and opposed to the crucible wall (7) at a distance by an inner face facing outwards, wherein the crucible wall (7) is arranged in a relationship substantially in heat exchange with the member (10) surrounding the crucible (6); The outer surface of the crucible wall (7) has a first emissivity (ε 1 ), and the inner surface of the opposing component (10) surrounding the crucible (6) has a second emissivity (ε 2 ), wherein the first emissivity and the second emissivity (ε 1 , ε 2 ) represent how much radiation is emitted from the crucible wall (7) and the components (10) surrounding the crucible, respectively, compared to an ideal radiant heater, wherein the outer face of the crucible wall (7) and the inner face of the part (10) surrounding the crucible are each at least partially formed by a plurality of surfaces defining the first emissivity (ε 1 ) and the second emissivity (ε 2 ) is provided so that the first emissivity and / or the second emissivity are each equal to a value of 0.1 or less.

2. The device (1) according to claim 1, wherein the first emissivity (ε 1 ) and the second emissivity (ε 2 ) is equal to 0.1 or less.

3. The device (1) according to claim 1 or 2, wherein the first emissivity (ε 1 ) and the second emissivity (ε 2 ) is equal to 0.05 or less.

4. The device (1) according to any one of claims 1 to 3, wherein the degree of radiation exchange in the radiation exchange between the crucible wall (7) and the component (10) surrounding the crucible is equal to 0.1 or less.

5. The device (1) according to any one of claims 1 to 4, wherein The outer face of the crucible wall (7) and the inner face of the opposing part (10) together form and delimit an intermediate space (8) in the form of a cylindrical shell, through which radiation exchange takes place during operation of the device.

6. The device (1) according to any one of claims 1 to 5, wherein The coating (8a, 8b) at least partially forming the outer and / or inner face is provided in a periodic pattern, in particular a mosaic or stripe pattern.

7. The device (1) according to any one of claims 1 to 6, wherein The coating (8a, 8b) which at least partially forms the outer and / or inner surface is made glossy and metallic.

8. The device (1) according to any one of claims 1 to 6, wherein The part (10) surrounding the crucible is made of hard graphite and includes a rough metallic layer.

9. The device (1) according to any one of claims 1 to 6, wherein The part (10) surrounding the crucible is made of hard graphite and includes a shiny metallic layer.

10. The device (1) according to any one of claims 1 to 6, wherein The part (10) surrounding the crucible is a quartz tube coated with graphite.

11. The device (1) according to claim 11, wherein The part (10) surrounding the crucible is the lining.

12. The device (1) according to any one of claims 1 to 11, wherein The crucible (6) is made of boron nitride or pyrolytic boron nitride, wherein the outer surface of the crucible wall (7) is formed at least partially by a rough platinum or graphite coating.

13. The apparatus according to any one of claims 1 to 11, wherein the crucible (6) is made of boron nitride or pyrolytic boron nitride, wherein the outer surface of the crucible wall (7) is at least partially formed by a shiny platinum or graphite coating.

14. The device (1) according to any one of claims 1 to 13, further comprising: One or more heating elements are arranged outside the component (10) and opposite to the crucible (6) when viewed from the central axis (M) of the crucible (6).

15. The device (1) according to any one of claims 1 to 14, wherein The apparatus (1) is configured to produce AlIII-BV-compound semiconductor single crystals containing GaAs or InP, preferably for separation into wafers having a nominal diameter of 100 mm, 150 mm or 200 mm.

16. The device (1) according to any one of claims 1 to 15, wherein The crucible wall (7) is formed of a material having an internal structure such that heat conduction is isotropic.

17. The device (1) according to any one of claims 1 to 16, wherein The crucible wall (7) is formed of a material having an internal structure such that the heat conduction is equal to 3 W / mK or less.

18. Apparatus according to any one of claims 1 to 17, wherein the crucible (6) is formed from glassy carbon.

19. A method for producing an AIII-BV compound semiconductor single crystal from a melt of raw materials, comprising: Providing an apparatus according to any one of the preceding claims 1 to 18; inserting a seed crystal into the seed crystal channel; Setting a directional temperature field parallel to the central axis of the crucible by one or more heating elements; The crystal growth rate is adjusted by controlling the one or more heating elements so that the tilt angle between the phase boundary and the horizontal direction perpendicular to the inner face of the adjacent lateral crucible wall is continuously maintained at 40 degrees or less, preferably 37 degrees or less in the case of GaAs as the AlIII-BV compound semiconductor, or at 34 degrees or less in the case of InP as the AlIII-BV compound semiconductor, more preferably at 32 degrees or less in the case of GaAs as the AlIII-BV compound semiconductor, or at 31 degrees or less in the case of InP as the AlIII-BV compound semiconductor; A single crystal is crystallized and further cooled.

20. The method according to claim 19, wherein The growth rate is equal to 2 mm / h or less. 21 . An AIII-BV compound semiconductor single crystal or a wafer obtained by separation thereof, produced by a method according to claim 19 or 20 using an apparatus according to claim 1 .

22. An AIII-BV compound semiconductor single crystal or a wafer obtained by separation thereof, wherein in an annular edge region of a cross-sectional area of the single crystal or wafer perpendicular to the central axis, the share of dislocation pits associated with slip lines is equal to 30% or less, preferably 10% or less, more preferably 5% or less of the total number of dislocation pits, said slip lines extending from the edge region of the single crystal or wafer in the cross-sectional area, wherein the width of the edge region measured from the outer edge of the single crystal or wafer is equal to 5 mm or less when the edge exclusion measured from the outer edge of the single crystal or wafer is 2 mm.

23. The AIII-BV compound semiconductor single crystal or a wafer separated therefrom according to claim 22, wherein the relative frequency of slip lines extending within the cross-sectional area originating from the edge area of the single crystal or wafer relative to the perimeter of the cross-sectional area of the single crystal or wafer is equal to 0.25 cm -1 or smaller, preferably 0.1 cm -1 or smaller, more preferably 0.05 cm -1 or smaller.

24. A wafer obtained by separation from an AIII-BV-compound semiconductor single crystal, wherein the wafer has a resistivity distribution within a cross-sectional area perpendicular to its central axis, and wherein the overall standard deviation (σ overall ) of the distribution is equal to 17.0% or less, preferably 16.0% or less, of the resistivity average value within the cross-sectional area of the wafer, wherein the overall standard deviation is determined based on a characteristic length of 10 mm and an edge exclusion of 1 mm measured from the outer edge of the wafer.

25. The wafer according to claim 24, wherein the AIII-BV-compound semiconductor is GaAs and the overall standard deviation of the distribution (σ overall) is equal to 4.0% or less of the average value of the resistivity within the cross-sectional area of the wafer, and / or wherein the diameter of the wafer is equal to 150 mm or 6 inches or less.

26. The wafer according to claim 24, wherein the AIII-BV-compound semiconductor is GaAs and the overall standard deviation of the distribution (σ overall) is equal to 16.0% or less of the average value of the resistivity within the cross-sectional area of the wafer, and / or wherein the diameter of the wafer is equal to 200 mm or 8 inches or greater.

27. A wafer according to claim 24, wherein the AIII-BV-compound semiconductor is InP and the overall standard deviation of the distribution (σ overall) is equal to 17.0% or less of the average value of the resistivity within the cross-sectional area of the wafer, and / or the diameter of the wafer is equal to 100 mm or 4 inches or more.

28. A wafer according to any one of claims 24 to 27, wherein the value of the overall standard deviation (σ overall ) measured only in the edge region taking into account an edge exclusion of 1 mm is equal to 35.0% or less, preferably 30.0% or less, of the average value of the resistivity, wherein the width of the edge region is defined by a distance of 3 mm or less measured from the outer edge of the wafer when the edge exclusion measured from the outer edge of the wafer is 1 mm.

29. The wafer according to any one of claims 22 to 28, wherein The average or median value of the residual strain content distribution of the single crystal or wafer in the annular edge region of the cross-sectional area perpendicular to the central axis (M) thereof is equal to 2.5×10 -6 or smaller, preferably 1.6×10 -6 or less, wherein the residual strain in a cross-sectional area within an edge region of the single crystal or wafer is derived in a spatially resolved manner from measurements according to the SIRIS method, wherein the lateral resolution of the spatially resolved measurement is 100 μm, wherein the width of the edge region is defined by a distance of 3 mm or less measured from an outer edge of the single crystal or wafer, wherein the edge exclusion measured from the outer edge is 1 mm.

30. The wafer according to claim 29, wherein the mean or median value of the residual strain content distribution in the edge region is 1.1×10 -6 or smaller.

31. A wafer obtained by separation from an AIII-BV-compound semiconductor single crystal, wherein the average value of the distribution of residual stress content in an annular edge region of a cross-sectional area perpendicular to its central axis (M) is equal to 60 kPa or less, wherein the residual stress in the edge region of the cross-sectional area of the single crystal or the wafer is spatially resolved according to the SIRIS method, wherein the lateral resolution of the spatially resolved measurement is equal to 100 μm, wherein the width of the edge region is defined by a distance of 3 mm measured from the outer edge of the single crystal or the wafer, wherein the edge measured from the outer edge is excluded as 1 mm.

32. A wafer according to claim 31, wherein the average value of the residual stress content distribution in the annular edge area of the cross-sectional area of the single crystal or wafer is equal to 60 kPa or less, and the AIII-BV-compound semiconductor is GaAs, and the diameter of the wafer is equal to 200 mm or 8 inches or more, respectively.

33. A wafer according to claim 31, wherein the average value of the residual stress content distribution in the annular edge area of the cross-sectional area of the single crystal or wafer is equal to 30 kPa or less, and the AIII-BV compound semiconductor is GaAs, and the diameter of the wafer is equal to 150 mm or 6 inches, respectively.

34. The wafer according to any one of claims 31 to 33, wherein the average value of the distribution of the residual stress content in the edge region is equal to 25 kPa or less.

35. The AIII-BV compound semiconductor single crystal or a wafer obtained by separation thereof according to any one of claims 22 to 34, wherein the diameter of the single crystal or wafer perpendicular to its central axis is between 100 mm and 220 mm, inclusive. 36 . The AIII-BV compound semiconductor single crystal according to claim 22 , or a wafer obtained by separation thereof, wherein the AIII-BV compound semiconductor comprises gallium arsenide (GaAs) or indium phosphide (InP).

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