Preparation method for semiconductor structure and semiconductor structure

Abstract

The invention provides a preparation method for a semiconductor structure and the semiconductor structure. The preparation method comprises the following steps: forming a plurality of stacked deposition layers with different resistivity; and separating the plurality of deposition layers to obtain a plurality of corresponding semiconductor structures.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a preparation method for a semiconductor structure and a semiconductor structure. Background Art

[0002] Semiconductor structures, such as those made of silicon carbide (SiC), are widely used in power electronics, radio frequency communications, and high-temperature sensors due to their excellent physical and chemical properties.

[0003] However, when preparing semiconductor structures, there are still some technical challenges. Specifically, in the relevant preparation method, only semiconductor structures with the same resistivity can be prepared in the same heat, and this is mainly because semiconductor structures with different resistivities need to be carried out under different preparation conditions. At present, when preparing semiconductor structures with different resistivities, a method of depositing in separate heats is usually adopted, that is, after the preparation of a semiconductor structure with one resistivity is completed, the key auxiliary materials in the equipment are replaced or cleaned, and then the preparation of the semiconductor structure with the next resistivity is carried out. This operation not only increases the downtime in the production process, reduces overall production efficiency, but also significantly increases production costs. In addition, deposition in separate heats may also result in waste of raw materials.

[0004] Based on this, how to efficiently prepare semiconductor structures with different resistivities in the same furnace is a problem that needs to be solved urgently. Summary of the Invention

[0005] The present disclosure provides a method for preparing a semiconductor structure and a semiconductor structure; semiconductor structures with different resistivities can be prepared in the same furnace, thereby improving production efficiency.

[0006] The technical solution of the present disclosure is achieved as follows: In a first aspect, the present disclosure provides a method for preparing a semiconductor structure, the method comprising: forming a plurality of deposited layers stacked together having resistivities different from each other; The plurality of deposited layers are separated to obtain corresponding plurality of semiconductor structures.

[0007] Optionally, in some possible implementations, the resistivity of a deposited layer formed earlier among the multiple deposited layers is greater than the resistivity of a deposited layer formed later.

[0008] Optionally, in some possible implementations, the multiple deposition layers are formed by chemical vapor deposition.

[0009] Optionally, in some possible implementations, a dopant gas is supplied during the chemical vapor deposition process, and the resistivity is controlled by adjusting the flow rate of the dopant gas.

[0010] Optionally, in some possible implementations, the preparation method further comprises: By stopping the supply of the dopant gas during the chemical vapor deposition, an isolation layer is formed between every two adjacent deposition layers among the plurality of deposition layers.

[0011] Optionally, in some possible implementations, the thickness of the isolation layer is determined based on expected resistivities of two adjacent deposition layers among the plurality of deposition layers.

[0012] Optionally, in some possible implementations, when the deposited layer is a SiC layer, When the desired resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 15 μm and less than or equal to 20 μm; or When the desired resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 10 μm and less than or equal to 12 μm; or When the desired resistivity of two adjacent SiC layers is greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 5 μm and less than or equal to 8 μm.

[0013] Optionally, in some possible implementations, the strength or density of the isolation layer is less than the mechanical strength or material density of the corresponding two adjacent deposition layers.

[0014] Optionally, in some possible implementations, the preparation method further comprises: After the deposition layer is formed, the supply of the raw material gas and the dopant gas in the chemical vapor deposition is stopped for a set time period.

[0015] Optionally, in some possible implementations, the preparation method further comprises: After the deposition layer or the isolation layer is formed, the supply of the raw material gas and the dopant gas in the chemical vapor deposition is stopped for a set time period.

[0016] Optionally, in some possible implementations, the duration is greater than or equal to 30 seconds and less than or equal to 60 seconds.

[0017] Optionally, in some possible implementations, the preparation method further comprises: Each separated semiconductor structure is planarized according to a set processing removal amount.

[0018] In a second aspect, the present disclosure provides a semiconductor structure, which is prepared according to the preparation method for a semiconductor structure described in the first aspect.

[0019] In a third aspect, the present disclosure provides a semiconductor structure comprising a plurality of stacked deposition layers having different resistivities.

[0020] Optionally, in some possible implementations, the resistivity of each of the multiple deposition layers gradually increases or decreases along the thickness direction of the semiconductor structure.

[0021] Optionally, in some possible implementations, the semiconductor structure further includes an isolation layer, where the isolation layer is located between every two adjacent deposition layers in the plurality of deposition layers, so as to prevent mutual interference in the resistivity of the two deposition layers.

[0022] Optionally, in some possible implementations, when the deposited layer is a SiC layer, When the resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 15 μm and less than or equal to 20 μm; or When the resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 10 μm and less than or equal to 12 μm; or When the resistivity of two adjacent SiC layers is greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 5 μm and less than or equal to 8 μm.

[0023] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure. Multiple stacked deposited layers with varying resistivities are formed in a single heat, and the layers are separated using interface engineering to obtain multiple corresponding semiconductor structures. The technical solution provided by this disclosure enables the fabrication of multiple semiconductor structures with varying resistivities in a single heat, significantly improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided by the present disclosure.

[0025] Figure 2A schematic diagram of multiple deposition layers formed by deposition on a substrate according to an embodiment of the present disclosure.

[0026] Figure 3 A schematic diagram of multiple deposition layers formed by deposition on a substrate according to another embodiment of the present disclosure is provided.

[0027] Figure 4 A schematic diagram of depositing an isolation layer between two adjacent deposition layers provided in the present disclosure.

[0028] Figure 5 A schematic diagram of multiple SiC layers deposited on a graphite substrate according to an embodiment of the present disclosure.

[0029] Figure 6 A schematic diagram of multiple SiC layers deposited on a graphite substrate according to another embodiment of the present disclosure.

[0030] Figure 7 A schematic flow chart of another method for preparing a semiconductor structure provided by the present disclosure. DETAILED DESCRIPTION

[0031] The technical solutions in the present disclosure will be described clearly and completely below with reference to the accompanying drawings in the present disclosure.

[0032] As mentioned earlier, when preparing semiconductor structures with different resistivities, a method of deposition in batches is usually required. However, there are many problems with batch preparation. For example, when changing batches, the formed semiconductor structure may cause lattice distortion due to temperature changes, which in turn affects the performance and reliability of the semiconductor structure finally prepared. In addition, batch deposition requires recalibration of key parameters such as gas flow rate and reaction temperature gradient. This process is not only cumbersome, but also prone to errors, resulting in deviations in the resistivity of semiconductor structures prepared in different batches.

[0033] In summary, although different heats can be used to prepare semiconductor structures with different resistivities, the temperature changes and parameter calibration complexity it brings about affect the stability and production efficiency of the semiconductor structure. In order to solve the above problems, the present disclosure provides a method for preparing a semiconductor structure, specifically as follows: Figure 1 As shown, the preparation method includes the following steps.

[0034] In step S101 , a plurality of stacked deposition layers having different resistivities are formed.

[0035] like Figure 2 As shown, when forming a plurality of stacked deposition layers 20, these plurality of deposition layers 20 are usually formed on the substrate 10. Of course, in the specific implementation process, as shown in FIG. Figure 3As shown, the deposition layer 20 may also be formed only on one surface of the substrate 10 , which is not specifically limited in the present disclosure.

[0036] It should be noted that the preparation method of the deposition layer 20 in the present disclosure is not limited to the chemical vapor deposition (CVD) method, and may also be a physical vapor deposition (PVD) method.

[0037] In step S102 , the plurality of deposition layers 20 are separated to obtain corresponding plurality of semiconductor structures.

[0038] After forming a plurality of deposition layers 20 , the plurality of deposition layers 20 may be separated along the interfaces between the layers, thereby obtaining a plurality of semiconductor structures with corresponding different resistivities.

[0039] It should be noted that when multiple deposition layers 20 are separated along the interfaces between the layers, the corresponding processing removal amount of each deposition layer 20 can be determined according to actual conditions to ensure that the resistivity of each semiconductor structure obtained remains consistent.

[0040] The technical solution provided by this disclosure forms multiple stacked deposited layers 20 with different resistivities using the same heat, and separates the multiple deposited layers 20 based on interface engineering to obtain multiple corresponding semiconductor structures. The technical solution provided by this disclosure enables the production of multiple semiconductor structures with different resistivities in the same heat, significantly improving production efficiency.

[0041] for Figure 1 In the technical solution shown, in some possible implementations, the resistivity of the deposited layer 20 formed earlier among the multiple deposited layers 20 is greater than the resistivity of the deposited layer 20 formed later.

[0042] When multiple deposited layers 20 with different resistivities are formed on a substrate 10, the dopant concentrations corresponding to each deposited layer 20 vary. It is understood that if the preparation conditions, etc., are not precisely controlled during the preparation of the deposited layers 20, dopant diffusion may occur between the different deposited layers 20. This diffusion phenomenon can disrupt the original resistivity distribution of the deposited layers 20, thereby affecting the electrical performance and stability of subsequently manufactured semiconductor devices.

[0043] Generally speaking, the above-mentioned diffusion phenomenon is manifested as dopants diffusing from a high-concentration region to a low-concentration region.

[0044] In the present disclosure, the resistivity of the deposited layer 20 formed earlier is higher than that of the deposited layer 20 formed later. This means that the concentration of the dopant in the deposited layer 20 formed earlier is relatively low, while the concentration of the dopant in the deposited layer 20 formed later is relatively high. In this case, the possibility of the dopant diffusing from the deposited layer 20 formed earlier to the deposited layer 20 formed later is relatively low, and therefore the resistivity distribution of both is relatively small. Conversely, if the deposited layer 20 with low resistivity is formed earlier, due to its high dopant concentration, when the deposited layer 20 with high resistivity is subsequently formed, the dopant may diffuse from the deposited layer 20 with low resistivity to the deposited layer 20 with high resistivity, thereby affecting the resistivity distribution of the deposited layer 20 with high resistivity.

[0045] for Figure 1 In some possible implementations of the technical solution shown, multiple deposition layers 20 are formed by chemical vapor deposition.

[0046] In the preparation of the deposition layer 20, the CVD method has become one of the main methods for industrial preparation due to its high purity characteristics and excellent large-area uniform deposition ability. Based on this, optionally, in the present disclosure, the deposition layer 20 is prepared by the CVD method.

[0047] for Figure 1 In the technical solution shown, in some possible implementations, a dopant gas is supplied during chemical vapor deposition, and the resistivity is controlled by adjusting the flow rate of the dopant gas.

[0048] The dopant gas used can be determined based on the conductivity type of the semiconductor structure. For n-type semiconductor structures, the corresponding dopant gas can be nitrogen (N2), ammonia (NH3), etc. For p-type semiconductor structures, the corresponding dopant gas can be diborane (B2H6), boron trifluoride (BF3), etc.

[0049] The resistivity of the deposited layer 20 is significantly related to the concentration of the dopant therein. In practice, the resistivity of the deposited layer 20 can be adjusted by adjusting process parameters such as the dopant gas flow rate, chemical vapor deposition temperature, and chemical vapor deposition time to control the dopant concentration.

[0050] In the present disclosure, considering that the deposition layers 20 with different resistivities are deposited in the same furnace, it is chosen to control the resistivity of each deposition layer by controlling the flow rate of the dopant gas. This is mainly because by adjusting the flow rate of the dopant gas, the continuous deposition of deposition layers 20 with different resistivities can be achieved in the same furnace without frequently changing the chemical vapor deposition conditions or interrupting the process. Moreover, the flow rate of the dopant gas is a relative and easy-to-monitor method that can achieve precise control of the concentration of the dopant, thereby ensuring the consistency and uniformity of the resistivity of each deposition layer 20. In general, adjusting the resistivity of the deposition layer 20 by controlling the flow rate of the dopant gas is convenient to operate and easy to control.

[0051] For the above-mentioned implementation, in some examples, such as Figure 4 As shown, the preparation method also includes: By stopping the supply of the dopant gas during the chemical vapor deposition, the isolation layer 30 is formed between every adjacent two deposition layers 20 among the plurality of deposition layers 20 .

[0052] In the present disclosure, the resistivity of each deposition layer 20 is different, which means that the concentration of dopants in each deposition layer 20 is also different. Even if the concentration of dopants in the first deposition layer 20 is lower than that in the second deposition layer 20, dopants may still diffuse from the first deposition layer 20 to the second deposition layer 20 under high temperature conditions. To prevent this dopant diffusion, the present disclosure forms an isolation layer 30 between each two adjacent deposition layers 20. The isolation layer 30 can effectively prevent dopants from diffusing from high-concentration areas to low-concentration areas, thereby ensuring that the resistivity distribution between the corresponding two adjacent deposition layers 20 remains stable.

[0053] Furthermore, when forming the isolation layer 30, the dopant gas supply is stopped to ensure that the isolation layer 30 formed does not contain dopants. The main function of the isolation layer 30 is to block the diffusion of dopants from the high-concentration deposition layer 20 to the low-concentration deposition layer 20. Since the isolation layer 30 itself does not contain dopants, it does not affect the dopant concentration of the deposition layer 20 formed thereafter.

[0054] Furthermore, even if the isolation layer 30 contains dopants due to residual dopant gas and dopant diffusion within the deposition layer 20, the dopant concentration is very low and thus does not significantly affect the dopant concentration of the deposition layer 30 formed after the isolation layer 30. Based on the above, electrical interference between two adjacent deposition layers 20 can be minimized, thereby helping to improve the overall performance and reliability of the subsequently manufactured semiconductor device.

[0055] In addition, the presence of the isolation layer 30 also helps to isolate the corresponding two adjacent deposition layers 20, so that each deposition layer 20 can be manufactured to form a semiconductor structure with a corresponding resistivity.

[0056] For the above-described embodiments, in some examples, the thickness of the isolation layer 30 is determined based on the desired resistivity of two adjacent deposition layers 20 among the plurality of deposition layers 20 .

[0057] There is a significant difference in dopant concentration between the deposited layers 20 of different resistivities, and this difference directly affects the diffusion depth of the dopant. Specifically, during the deposition process, the dopant diffuses from the high-concentration area to the low-concentration area, which may cause the resistivity between the two adjacent deposited layers 20 to change. In order to effectively block this diffusion behavior, the thickness of the isolation layer 30 needs to be optimized according to the resistivity difference between the two adjacent deposited layers 20. When the resistivity difference between the two adjacent deposited layers 20 is large, the diffusion depth of the dopant may be deep, so a thicker isolation layer 30 is required to ensure that the dopant does not penetrate the isolation layer 30, thereby avoiding affecting the resistivity of the subsequently formed deposited layer 20. On the contrary, when the resistivity difference between the two adjacent deposited layers 20 is small, the diffusion depth of the dopant is shallow, and the thickness of the isolation layer 30 can be reduced accordingly while still effectively blocking the diffusion of the dopant. In this way, not only can the isolation layer 30 effectively block the diffusion of dopants from the high-concentration area to the low-concentration area, but it can also avoid wasting raw materials.

[0058] Optionally, when the deposited layer 20 is a SiC layer, When the desired resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 15 μm and less than or equal to 20 μm; or When the desired resistivities of two adjacent SiC layers are less than or equal to 0.5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 10 μm and less than or equal to 12 μm; or When the desired resistivity of two adjacent SiC layers is greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 5 μm and less than or equal to 8 μm.

[0059] In some examples, the dopant used in forming the SiC layer is nitrogen (N).

[0060] like Figure 5, which shows a schematic diagram of forming multiple SiC layers on a graphite substrate. The resistivity of SiC layer 20A is above 60 ohm-cm, the resistivity of SiC layer 20B is in the range of 1 ohm-cm to 5 ohm-cm, and the resistivity of SiC layer 20C is below 0.5 ohm-cm.

[0061] In a specific implementation, when SiC layer 20A and SiC layer 20B are formed sequentially, a relatively thin isolation layer 30A can be formed between SiC layer 20A and SiC layer 20B due to the higher resistivity and lower dopant concentration of SiC layer 20A. In some examples, the thickness of isolation layer 30A ranges from 5 μm to 8 μm.

[0062] When SiC layer 20B and SiC layer 20C are formed sequentially, SiC layer 20B has a higher dopant concentration due to its lower resistivity, while SiC layer 20C has a relatively lower resistivity and a relatively higher dopant concentration. To prevent dopants from diffusing from high-concentration areas to low-concentration areas in high-temperature environments, a relatively thick isolation layer 30B is formed between SiC layers 20B and 20C. In some examples, the thickness of isolation layer 30B ranges from 15 μm to 20 μm.

[0063] like Figure 6 As shown, when SiC layer 20A and SiC layer 20C are formed sequentially, SiC layer 20A has a higher resistivity and a lower dopant concentration, while SiC layer 20C has a lower resistivity and a higher dopant concentration. To prevent dopant diffusion between the two layers in a high-temperature environment, a relatively thick isolation layer 30C is required between the two layers. In some examples, the thickness of isolation layer 30C ranges from 10 μm to 12 μm.

[0064] For the above-mentioned embodiments, in some examples, the mechanical strength or material density of the isolation layer 30 is less than the mechanical strength or material density of the corresponding two adjacent deposition layers 20 .

[0065] In this case, because the mechanical strength or material density of the isolation layer 30 is lower than that of the two adjacent deposited layers 20, machining during separation is relatively easy. This lower mechanical strength or density makes the isolation layer 30 easier to remove during the separation process without damaging the deposited layers 20. This not only improves separation efficiency but also reduces potential defects or damage caused by the separation process, thereby ensuring the integrity and performance of the deposited layers 20.

[0066] In some examples, by precisely controlling parameters such as the deposition temperature and the ratio of raw material gases when forming the isolation layer 30, the mechanical strength or material density of the isolation layer 30 can be adjusted to be lower than the mechanical strength or material density of the corresponding two adjacent deposition layers 20.

[0067] In this disclosure, the raw materials used in chemical vapor deposition (CVD) typically include reactant gases, carrier gases, and diluent gases. Taking the formation of a SiC layer as an example, the reactant gases primarily include a carbon source gas and a silicon source gas. Common carrier gases include hydrogen (H2), and diluent gases include argon. In some specific CVD processes, the carbon source gas may include methane (CH4), and the silicon source gas may include methyltrichlorosilane (MTS).

[0068] for Figure 1 In some possible implementations of the technical solution shown, the preparation method further includes: After the deposition layer 20 is formed, the supply of the raw material gas and the dopant gas in the chemical vapor deposition is stopped for a set period of time.

[0069] by Figure 2 For example, when multiple deposition layers 20 are formed on the substrate 10, after each deposition layer 20 is formed, the supply of raw material gas and dopant gas is stopped for a set period of time, so that the previously formed deposition layer 20 can be provided with sufficient cooling time and stabilization time, so that the interlayer interface between the later formed deposition layer 20 and the previously formed deposition layer 20 is clearer, which is helpful for subsequent separation.

[0070] For the above embodiments, in some examples, the preparation method further includes: After the deposition layer 20 or the isolation layer 30 is formed, the supply of the raw material gas and the dopant gas in the chemical vapor deposition is stopped for a set period of time.

[0071] by Figure 4 For example, by stopping the supply of raw material gases and dopant gases after the deposition layer 20 or isolation layer 30 is formed, sufficient cooling and stabilization time can be provided for the previously formed deposition layer 20 or isolation layer 30, thereby making the interface between the later-formed deposition layer 20 or isolation layer 30 and the previously formed deposition layer 20 or isolation layer 30 clearer and avoiding the blurring of the interface caused by continuous deposition. This not only helps improve the electrical performance and reliability of each deposition layer 20, but also facilitates the subsequent separation of each deposition layer 20.

[0072] Furthermore, in this disclosure, the chemical vapor deposition reaction is interrupted by stopping the supply of feedstock and dopant gases. This is primarily because feedstock and dopant gases are the core driving forces of the chemical vapor deposition reaction. By directly stopping the supply of these gases, the chemical vapor deposition reaction can be quickly interrupted, preventing unnecessary deposition from continuing. This method is simple and direct, enabling precise control of the deposition process in a short period of time.

[0073] Optionally, the above duration is in the range of 30s to 60s.

[0074] By briefly interrupting the chemical vapor deposition reaction, a clear interlayer interface can be formed between the later-formed deposition layer 20 or isolation layer 30 and the earlier-formed deposition layer 20 or isolation layer 30. This interlayer interface is not only easy to distinguish, but also serves as an important reference in the subsequent separation process, thereby improving the accuracy and efficiency of the separation process.

[0075] Moreover, a short interruption of the chemical vapor deposition reaction will not negatively impact subsequent chemical vapor deposition reactions. When deposition is resumed after the chemical vapor deposition reaction is interrupted, the concentrations of the feed gas and dopant gas, as well as the chemical vapor deposition reaction conditions, can be quickly restored to their pre-interruption states, thereby ensuring a consistent deposition rate. Furthermore, a short interruption will not significantly affect the stability of process parameters such as gas flow, reaction temperature, and pressure. Therefore, by briefly interrupting the chemical vapor deposition reaction, not only can a clear interlayer interface be formed between different layers, but the high quality and performance of each layer can also be guaranteed.

[0076] like Figure 7 As shown, the preparation method provided by the present disclosure further includes: step S103, performing a planarization process on each separated semiconductor structure according to a set processing removal amount.

[0077] In the present disclosure, each separated semiconductor structure is subjected to a planarization process, which can effectively remove surface defects and damage layers, thereby reducing the impact of these defects on the applicability of the semiconductor structure.

[0078] It should be noted that the aforementioned machining removal amount is determined based on actual conditions. On the one hand, by setting an appropriate machining removal amount, the resistivity of the corresponding semiconductor structure can be ensured to remain consistent, thereby meeting the uniformity requirements of the performance of subsequently manufactured semiconductor devices. On the other hand, the machining removal amount can be adjusted based on the actual application scenario of the semiconductor structure to ensure that the semiconductor structure after planarization can meet the needs of specific applications.

[0079] In addition, the present disclosure also provides a semiconductor structure, which is prepared according to the preparation method for a semiconductor structure described in the aforementioned technical solution.

[0080] Finally, the present disclosure also provides a semiconductor structure including a plurality of stacked deposition layers having different resistivities.

[0081] For the above-mentioned semiconductor structure, in some possible implementations, the resistivity of each of the multiple deposition layers gradually increases or gradually decreases along the thickness direction of the semiconductor structure.

[0082] For the above embodiments, in some examples, the semiconductor structure further includes an isolation layer, where the isolation layer is located between every two adjacent deposition layers in the plurality of deposition layers to prevent mutual interference in resistivity of the two deposition layers.

[0083] Optionally, in the case where the deposited layer is a SiC layer, When the resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 15 μm and less than or equal to 20 μm; or When the resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 10 μm and less than or equal to 12 μm; or When the resistivity of two adjacent SiC layers is greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 5 μm and less than or equal to 8 μm.

[0084] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily without conflict.

[0085] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: forming a plurality of deposited layers stacked together having resistivities different from each other; The plurality of deposited layers are separated to obtain corresponding plurality of semiconductor structures.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The resistivity of a deposition layer formed earlier among the plurality of deposition layers is greater than the resistivity of a deposition layer formed later.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The plurality of deposition layers are formed by chemical vapor deposition.

4. The method for preparing a semiconductor structure according to claim 3, wherein: Dopant gas is supplied during the chemical vapor deposition, and the resistivity is controlled by adjusting the flow rate of the dopant gas.

5. The method for preparing a semiconductor structure according to claim 4, wherein: The preparation method further comprises: By stopping the supply of the dopant gas during the chemical vapor deposition, an isolation layer is formed between every two adjacent deposition layers among the plurality of deposition layers.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The thickness of the isolation layer is determined based on the desired resistivity of corresponding two adjacent deposition layers among the plurality of deposition layers.

7. The method for preparing a semiconductor structure according to claim 6, wherein: In the case where the deposited layer is a SiC layer, When the desired resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 15 μm and less than or equal to 20 μm; or When the desired resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 10 μm and less than or equal to 12 μm; or When the desired resistivity of two adjacent SiC layers is greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 5 μm and less than or equal to 8 μm.

8. The method for preparing a semiconductor structure according to claim 5, wherein: The mechanical strength or material density of the isolation layer is smaller than the mechanical strength or material density of the corresponding two adjacent deposition layers.

9. The method for preparing a semiconductor structure according to claim 3, wherein: The preparation method further comprises: After the deposition layer is formed, the supply of the raw material gas and the dopant gas in the chemical vapor deposition is stopped for a set time period.

10. The method for preparing a semiconductor structure according to claim 5, wherein: The preparation method further comprises: After the deposition layer or the isolation layer is formed, the supply of the raw material gas and the dopant gas is stopped for a set period of time.

11. The method for preparing a semiconductor structure according to claim 9 or 10, characterized in that: The duration is greater than or equal to 30 seconds and less than or equal to 60 seconds.

12. The method for preparing a semiconductor structure according to claim 1, wherein: The preparation method further comprises: Each separated semiconductor structure is planarized according to a set processing removal amount.

13. A semiconductor structure, characterized in that The semiconductor structure is manufactured according to the method for manufacturing a semiconductor structure according to any one of claims 1 to 12.

14. A semiconductor structure, characterized in that The semiconductor structure includes a plurality of stacked deposited layers having different resistivities from each other.

15. The semiconductor structure according to claim 14, wherein: The resistivity of each of the plurality of deposition layers gradually increases or decreases along the thickness direction of the semiconductor structure.

16. The semiconductor structure according to claim 14 or 15, characterized in that: The semiconductor structure further includes an isolation layer located between every two adjacent deposition layers in the plurality of deposition layers, so as to prevent mutual interference in resistivity of the two deposition layers.

17. The semiconductor structure according to claim 16, wherein: In the case where the deposited layer is a SiC layer, When the resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 15 μm and less than or equal to 20 μm; or When the resistivity of two adjacent SiC layers is less than or equal to 0.5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 10 μm and less than or equal to 12 μm; or When the resistivity of two adjacent SiC layers is greater than or equal to 1 ohm-cm and less than or equal to 5 ohm-cm and greater than or equal to 60 ohm-cm, respectively, the thickness of the corresponding isolation layer is greater than or equal to 5 μm and less than or equal to 8 μm.

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