Semiconductor device and semiconductor system

Abstract

The invention relates to a semiconductor device and a semiconductor system. A semiconductor device includes an error correction buffer circuit that generates an error correction signal when one of a first write operation and a second write operation is performed based on a command address, a first chip selection signal, a second chip selection signal, first data, and second data; a first data storage block that stores first data when a first write operation is performed based on the command address, the first chip selection signal, and the second chip selection signal; a second data storage block that stores second data when a second write operation is performed based on the command address, the first chip selection signal, and the second chip selection signal; and an error correction signal storage circuit that stores an error correction signal when one of the first write operation and the second write operation is performed based on the command address.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from Korean Patent Application No. 10-2024-0019123 filed on February 7, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0138036 filed on October 10, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to semiconductor devices and semiconductor systems including but not limited to data error correction. Background Art

[0003] To correct one or more errors in received data, various block codes are used, such as Hamming codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and Reed-Solomon (RS) codes. Hamming codes are often used during data transmission over channels in computer storage systems because they effectively detect and correct single-bit errors. BCH codes are widely used in various fields, such as communication systems, storage devices, and computer networks, because they can correct multiple errors and burst errors. RS codes are widely used in applications requiring high levels of error correction, such as satellite communications and wireless communication systems, because they can achieve high levels of error correction with a relatively small number of redundant or overhead bits. Summary of the Invention

[0004] In an embodiment, a semiconductor device may include: an error correction buffer circuit configured to generate an error correction signal based on a command address, a first chip selection signal, a second chip selection signal, first data, and second data when one of a first write operation and a second write operation is performed; a first data storage block configured to store the first data based on the command address, the first chip selection signal, and the second chip selection signal when the first write operation is performed; a second data storage block configured to store the second data based on the command address, the first chip selection signal, and the second chip selection signal when the second write operation is performed; and an error correction signal storage circuit configured to store the error correction signal based on the command address when one of the first write operation and the second write operation is performed.

[0005] In an embodiment, a semiconductor device may include: a first data storage block configured to store first data based on a command address, a first chip selection signal, and a second chip selection signal when a first write operation is performed; a second data storage block configured to store second data based on the command address, the first chip selection signal, and the second chip selection signal when a second write operation is performed; and an error correction signal storage circuit configured to store an error correction signal from a controller based on the command address when one of the first write operation and the second write operation is performed.

[0006] In an embodiment, a semiconductor device may include: an error correction buffer circuit configured to generate a first error correction signal and a second error correction signal based on a command address, a first chip select signal, a second chip select signal, first channel data, and second channel data when at least one of a first write operation of the first channel data and a second write operation of the second channel data is performed; a first data storage block configured to store the first channel data based on the command address, the first chip select signal, and the second chip select signal when the first write operation is performed; a second data storage block configured to store the second channel data based on the command address, the first chip select signal, and the second chip select signal when the second write operation is performed; a first error correction signal storage block configured to store the first error correction signal based on the command address, the first chip select signal, and the second chip select signal when the first write operation is performed; and a second error correction signal storage block configured to store the second error correction signal based on the command address, the first chip select signal, and the second chip select signal when the second write operation is performed.

[0007] In an embodiment, a semiconductor device may include: a first data storage block configured to store first data when a first write operation is performed; a second data storage block configured to store second data when a second write operation is performed; and an error correction signal storage circuit configured to store an error correction signal that corrects the first data stored in the first data storage block and the second data stored in the second data storage block. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a semiconductor system according to an embodiment of the present disclosure.

[0009] Figure 2 is a block diagram illustrating an embodiment of a semiconductor device according to the present disclosure.

[0010] Figure 3 is a block diagram illustrating an embodiment of a semiconductor device according to the present disclosure.

[0011] Figure 4 is a block diagram illustrating a semiconductor system according to an embodiment of the present disclosure.

[0012] Figure 5 is a block diagram illustrating an embodiment of a semiconductor device according to the present disclosure.

[0013] Figure 6 is a block diagram illustrating a semiconductor system according to an embodiment of the present disclosure.

[0014] Figure 7 is a block diagram illustrating an embodiment of a semiconductor device according to the present disclosure.

[0015] Figure 8 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure.

[0016] Figure 9 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] When one element is referred to as being “connected” to another element, the elements may be directly connected or connected through an intervening element between the elements. When two elements are referred to as being “directly connected,” one element is directly connected to the other element with no intervening elements between the two elements.

[0018] Terms such as "first" and "second" are used to distinguish between various elements and do not imply the size, order, priority, quantity or importance of the elements. For example, in one example, a first element can be called a second element, while in another example, a second element can be called a first element.

[0019] Embodiments of the present disclosure are described in detail with reference to the accompanying drawings. For illustrative purposes only, specific structural or functional descriptions of the embodiments are provided as examples of the concepts disclosed herein. Examples or embodiments based on the concepts may be implemented in various forms, and the scope of the present disclosure is not limited to the examples or embodiments described in this specification.

[0020] Figure 1 FIG. 1 is a block diagram showing a semiconductor system 1 according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor system 1 includes a controller 11 and a semiconductor device 13 .

[0021] The controller 11 includes a first control pin 11-1 and a second control pin 11-3. The semiconductor device 13 includes a first device pin 13-1 and a second device pin 13-3. The controller 11 transmits a command address CA, a first chip select signal CS0, and a second chip select signal CS1 to the semiconductor device 13 via a first transmission line 12-1 connected between the first control pin 11-1 and the first device pin 13-1. In an embodiment, the command address CA includes a plurality of bits corresponding to a command and an address. Depending on the number of bits included in each of the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the controller 11 may include multiple first control pins 11-1, multiple first transmission lines 12-1, and multiple first device pins 13-1. The controller 11 transmits first data D1 and second data D2 to the semiconductor device 13 via a second transmission line 12-3 connected between the second control pin 11-3 and the second device pin 13-3. According to the number of bits included in the first data D1 and the second data D2, a plurality of second control pins 11-3, a plurality of second device pins 13-3, and a plurality of second transmission lines 12-3 may be included.

[0022] The semiconductor device 13 receives a command address CA, a first chip select signal CS0, a second chip select signal CS1, and first and second data D1 and D2 from a controller 11 electrically connected to the semiconductor device 13. The semiconductor device 13 generates an error correction signal (e.g., Figure 2 The semiconductor device 13 may further include an ECC-S in the first data D1 and the second data D2, and internally stores an error correction signal that corrects one or more errors received in the first data D1 and the second data D2. When the semiconductor device 13 corrects one or more errors received in the first data D1 and the second data D2 based on the error correction signal, the semiconductor device 13 may improve the reliability of the first data D1 and the second data D2.

[0023] Figure 2 is shown as Figure 1 A block diagram of an embodiment of a semiconductor device 13 is shown.

[0024] like Figure 2 As shown, the semiconductor device 13 includes an error correction buffer circuit (ECC BF) 111 , a first data storage block 113 , a second data storage block 115 , and an error correction signal storage circuit (ECC-S STG) 117 .

[0025] The error correction buffer circuit 111 receives a command address CA, a first chip select signal CS0, a second chip select signal CS1, and first and second data D1 and D2 from a controller 11 electrically connected thereto. Based on the command address CA, the first and second chip select signals CS0 and CS1, the error correction buffer circuit 111 generates an error correction signal ECC-S from the first and second data D1 and D2 when at least one of a first write operation to the first data storage block 113 and a second write operation to the second data storage block 115 is performed. The error correction buffer circuit 111 generates the error correction signal ECC-S based on an error correction code implemented, for example, by an H matrix or RS code. The error correction signal ECC-S includes information identifying one or more errors received in the first and second data D1 and D2. The error correction signal ECC-S may include one or more symbols or syndromes including information identifying the locations of one or more errors in the data. The error correction buffer circuit 111 outputs the command address CA, the first and second chip select signals CS0 and CS1, the first and second data D1 and D2, and the error correction signal ECC-S.

[0026] First data storage block 113 receives first data D1, a command address CA, and first and second chip select signals CS0 and CS1 from error correction buffer circuit 111 electrically connected to first data storage block 113. Based on command address CA, first and second chip select signals CS0 and CS1, first data storage block 113 stores first data D1 when a first write operation is performed. First data storage block 113 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG of first data storage block 113 stores first data D1 when selectively activated by first and second chip select signals CS0 and CS1.

[0027] Second data storage block 115 receives second data D2, a command address CA, and first and second chip select signals CS0 and CS1 from error correction buffer circuit 111 electrically connected to second data storage block 115. Based on command address CA, first and second chip select signals CS0 and CS1, second data storage block 115 stores second data D2 when a second write operation is performed. Second data storage block 115 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG of second data storage block 115 stores second data D2 when selectively activated by first and second chip select signals CS0 and CS1.

[0028] The error correction signal storage circuit 117 receives a command address CA and an error correction signal ECC-S from the error correction buffer circuit 111, which is electrically connected to the error correction signal storage circuit 117. The error correction signal storage circuit 117 stores the error correction signal ECC-S based on the command address CA. Based on the command address CA, the error correction signal storage circuit 117 stores the error correction signal ECC-S when at least one of a first write operation and a second write operation is performed. When a read operation is performed on the first data storage block 113, the error correction signal storage circuit 117 outputs the error correction signal ECC-S to correct one or more errors received in the first data D1 output by the first data storage block 113. When a read operation is performed on the second data storage block 115, the error correction signal storage circuit 117 outputs the error correction signal ECC-S to correct one or more errors received in the second data D2 output by the second data storage block 115.

[0029] When the semiconductor device 13 includes the error correction signal storage circuit 117, the error correction signal storage circuit 117 stores the error correction signal ECC-S for correcting one or more errors received in the first data D1 and the second data D2 stored in the first data storage block 113 and the second data storage block 115, respectively. The semiconductor device 13 can improve the reliability of the first data D1 and the second data D2. Since the error correction signal storage circuit 117 storing the error correction signal ECC-S is shared by the first data storage block 113 and the second data storage block 115, the semiconductor device 13 can have a reduced layout area.

[0030] Figure 3 is shown as Figure 1 A block diagram of an embodiment of a semiconductor device 13 is shown.

[0031] like Figure 3 As shown, the semiconductor device 13 includes an error correction buffer circuit (ECC BF) 121 , a first data storage block 122 , a second data storage block 123 , a third data storage block 124 , a fourth data storage block 125 , and an error correction signal storage block (ECC-SSTG) 126 .

[0032] The error correction buffer circuit 121 receives a command address CA, a first chip select signal CS0, a second chip select signal CS1, and first and second data D1 and D2 from the controller 11 electrically connected thereto. Based on the command address CA, the first and second chip select signals CS0 and CS1, the error correction buffer circuit 121 generates an error correction signal ECC-S from the first and second data D1 and D2 when at least one of a first write operation to the first data storage block 122, a second write operation to the second data storage block 123, a third write operation to the third data storage block 124, and a fourth write operation to the fourth data storage block 125 is performed. The error correction buffer circuit 121 generates the error correction signal ECC-S based on an error correction code implemented, for example, using an H matrix or a RS code. The error correction signal ECC-S includes information identifying one or more errors received in the first and second data D1 and D2. The error correction signal ECC-S may include one or more symbols or syndromes including information identifying the locations of one or more errors in the data. The error correction buffer circuit 121 outputs a command address CA, a first chip select signal CS0 , a second chip select signal CS1 , first and second data D1 and D2 , and an error correction signal ECC-S.

[0033] First data storage block 122 receives first data D1, a command address CA, and first and second chip select signals CS0 and CS1 from error correction buffer circuit 121 electrically connected to first data storage block 122. First data storage block 122 stores first data D1 based on command address CA, first and second chip select signals CS0 and CS1 when a first write operation is performed. First data storage block 122 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG stores first data D1 when selectively activated by first and second chip select signals CS0 and CS1.

[0034] Second data storage block 123 receives first data D1, a command address CA, and first and second chip select signals CS0 and CS1 from error correction buffer circuit 121 electrically connected to second data storage block 123. Second data storage block 123 stores first data D1 based on command address CA, first and second chip select signals CS0 and CS1 when a second write operation is performed. Second data storage block 123 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG stores first data D1 when selectively activated by first and second chip select signals CS0 and CS1.

[0035] The third data storage block 124 receives the second data D2, the command address CA, the first chip select signal CS0, and the second chip select signal CS1 from the error correction buffer circuit 121 electrically connected to the third data storage block 124. When a third write operation is performed, the third data storage block 124 stores the second data D2 based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1. The third data storage block 124 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG stores the second data D2 when selectively activated by the first chip select signal CS0 and the second chip select signal CS1.

[0036] The fourth data storage block 125 receives the second data D2, the command address CA, the first chip select signal CS0, and the second chip select signal CS1 from the error correction buffer circuit 121 electrically connected to the fourth data storage block 125. Based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the fourth data storage block 125 stores the second data D2 when a fourth write operation is performed. The fourth data storage block 125 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG stores the second data D2 when selectively activated by the first chip select signal CS0 and the second chip select signal CS1.

[0037] Error correction signal storage block 126 receives a command address CA, a first chip select signal CS0, a second chip select signal CS1, and an error correction signal ECC-S from an error correction buffer circuit 121 electrically connected to the error correction signal storage block 126. Error correction signal storage block 126 stores the error correction signal ECC-S based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1. Error correction signal storage block 126 stores the error correction signal ECC-S based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1 when at least one of the first, second, third, and fourth write operations is performed. Error correction signal storage block 126 includes a plurality of error correction signal storage circuits ECC-S STG. Each of the plurality of error correction signal storage circuits ECC-S STG stores the error correction signal ECC-S when selectively activated by the first chip select signal CS0 or the second chip select signal CS1. When a read operation is performed on the first data storage block 122, the error correction signal storage block 126 outputs an error correction signal ECC-S to correct one or more errors received in the first data D1 output by the first data storage block 113. When a read operation is performed on the second data storage block 123, the error correction signal storage block 126 outputs an error correction signal ECC-S to correct one or more errors received in the first data D1 output by the second data storage block 123. When a read operation is performed on the third data storage block 124, the error correction signal storage block 126 outputs an error correction signal ECC-S to correct one or more errors received in the second data D2 output by the third data storage block 124. When a read operation is performed on the fourth data storage block 125, the error correction signal storage block 126 outputs an error correction signal ECC-S to correct one or more errors received in the second data D2 output by the fourth data storage block 125.

[0038] When the semiconductor device 13 includes the error correction signal storage block 126, which stores the error correction signal ECC-S for correcting one or more errors received in the first data D1 and the second data D2 in the first data storage block 122, the second data storage block 123, the third data storage block 124, and the fourth data storage block 125, the semiconductor device 13 can improve the reliability of the first data D1 and the second data D2. Since the error correction signal storage block 126 storing the error correction signal ECC-S is shared by the first data storage block 122, the second data storage block 123, the third data storage block 124, and the fourth data storage block 125, the semiconductor device 13 can have a reduced layout area.

[0039] Figure 4 FIG. 2 is a block diagram showing a semiconductor system 2 according to an embodiment of the present disclosure. Figure 4 As shown, the semiconductor system 2 includes a controller 21 and a semiconductor device 23 .

[0040] The controller 21 includes a first control pin 21-1, a second control pin 21-3, and a third control pin 21-5. The semiconductor device 23 includes a first device pin 23-1, a second device pin 23-3, and a third device pin 23-5. The controller 21 transmits a command address CA, a first chip select signal CS0, and a second chip select signal CS1 to the semiconductor device 23 via a first transmission line 22-1 connected between the first control pin 21-1 and the first device pin 23-1. In an embodiment, the command address CA includes multiple bits corresponding to a command and an address. Depending on the number of bits included in each of the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the controller 21 may include multiple first control pins 21-1, multiple first transmission lines 22-1, and multiple first device pins 23-1. The controller 21 transmits first data D1 and second data D2 to the semiconductor device 23 via a second transmission line 22-3 connected between the second control pin 21-3 and the second device pin 23-3. Depending on the number of bits included in each of the first data D1 and the second data D2, a plurality of second control pins 21-3, a plurality of second device pins 23-3, and a plurality of second transmission lines 22-3 may be included. The controller 21 transmits an error correction signal ECC-S to the semiconductor device 23 via a third transmission line 22-5 connected between a third control pin 21-5 and a third device pin 23-5. The controller 21 generates the error correction signal ECC-S based on an error correction code implemented, for example, using an H matrix or RS code. The error correction signal includes information identifying one or more errors received in the first data D1 and the second data D2. The error correction signal ECC-S may include one or more symbols or syndromes including information identifying the locations of one or more errors in the data.

[0041] The semiconductor device 23 receives a command address CA, a first chip select signal CS0, a second chip select signal CS1, first and second data D1 and D2, and an error correction signal ECC-S from a controller 21 electrically connected to the semiconductor device 23. The semiconductor device 23 internally stores the error correction signal ECC-S based on the command address CA, the first and second chip select signals CS0 and CS1. When one or more errors received in the first and second data D1 and D2 are corrected based on the error correction signal ECC-S, the semiconductor device 23 can improve the reliability of the first and second data D1 and D2.

[0042] Figure 5 is shown as Figure 4 A block diagram of an embodiment of a semiconductor device 23 is shown.

[0043] like Figure 5As shown, the semiconductor device 23 includes a first data storage block 213 , a second data storage block 215 , and an error correction signal storage circuit ECC-S STG 217 .

[0044] When a first write operation is performed on the first data storage block 213 based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the first data storage block 213 stores the first data D1. The first data storage block 213 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG of the first data storage block 213 stores the first data D1 when selectively activated by the first chip select signal CS0 and the second chip select signal CS1.

[0045] When a second write operation is performed on the second data storage block 215 based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the second data storage block 215 stores the second data D2. The second data storage block 215 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG of the second data storage block 215 stores the second data D2 when selectively activated by the first chip select signal CS0 and the second chip select signal CS1.

[0046] The error correction signal storage circuit 217 stores an error correction signal ECC-S based on the command address CA. The error correction signal storage circuit 217 stores the error correction signal ECC-S when at least one of a first write operation and a second write operation is performed based on the command address CA. When a read operation is performed on the first data storage block 213, the error correction signal storage circuit 217 outputs the error correction signal ECC-S to correct one or more errors received in the first data D1 output by the first data storage block 213. When a read operation is performed on the second data storage block 215, the error correction signal storage circuit 217 outputs the error correction signal ECC-S to correct one or more errors received in the second data D2 output by the second data storage block 215.

[0047] When the semiconductor device 23 includes the error correction signal storage circuit 217, the error correction signal storage circuit 217 stores the error correction signal ECC-S for correcting one or more errors received in the first data D1 and the second data D2 stored in the first data storage block 213 and the second data storage block 215, respectively, the semiconductor device 23 can improve the reliability of the first data D1 and the second data D2. Since the error correction signal storage circuit 217 storing the error correction signal ECC-S is shared by the first data storage block 213 and the second data storage block 215, the semiconductor device 23 can have a reduced layout area.

[0048] Figure 6FIG. 3 is a block diagram showing a semiconductor system 3 according to an embodiment of the present disclosure. Figure 6 As shown, the semiconductor system 3 includes a controller 31 and a semiconductor device 33 .

[0049] The controller 31 includes a first control pin 31-1, a second control pin 31-3, and a third control pin 31-5. The semiconductor device 33 includes a first device pin 33-1, a second device pin 33-3, and a third device pin 33-5. The controller 31 transmits a command address CA, a first chip select signal CS0, and a second chip select signal CS1 to the semiconductor device 33 via a first transmission line 32-1 connected between the first control pin 31-1 and the first device pin 33-1. In an embodiment, the command address CA includes multiple bits corresponding to the command and address. Depending on the number of bits included in each of the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the controller 31 may include multiple first control pins 31-1, multiple first transmission lines 32-1, and multiple first device pins 33-1. The controller 31 transmits first channel data D-CH1 to the semiconductor device 33 via a second transmission line 32-3 connected between the second control pin 31-3 and the second device pin 33-3. Depending on the number of bits in the first channel data D-CH1, a plurality of second control pins 31-3, a plurality of second device pins 33-3, and a plurality of second transmission lines 32-3 may be included. The controller 31 transmits the second channel data D-CH2 to the semiconductor device 33 via a third transmission line 32-5 connected between the third control pin 31-5 and the third device pin 33-5. Depending on the number of bits included in the second channel data D-CH2, a plurality of third control pins 31-5, a plurality of third device pins 33-5, and a plurality of third transmission lines 32-5 may be included.

[0050] The semiconductor device 33 receives a command address CA, a first chip select signal CS0, a second chip select signal CS1, first channel data D-CH1, and second channel data D-CH2 from a controller 31 electrically connected to the semiconductor device 33. The semiconductor device 33 generates an error correction signal (e.g., Figure 7 The semiconductor device 33 stores an error correction signal internally, which corrects one or more errors received in the first channel data D-CH1 and the second channel data D-CH2. When the semiconductor device 33 corrects one or more errors received in the first channel data D-CH1 and the second channel data D-CH2 based on the error correction signal, the semiconductor device 33 can improve the reliability of the first channel data D-CH1 and the second channel data D-CH2.

[0051] Figure 7is shown as Figure 6 A block diagram of an embodiment of a semiconductor device 33 is shown.

[0052] like Figure 7 As shown, the semiconductor device 33 includes an error correction buffer circuit 321, a first data storage block 322, a second data storage block 323, a third data storage block 324, a fourth data storage block 325, a first error correction signal storage block 326 and a second error correction signal storage block 327.

[0053] The error correction buffer circuit 321 receives a command address CA, a first chip select signal CS0, a second chip select signal CS1, first channel data D-CH1, and second channel data D-CH2 from the controller 31. Based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, when at least one of a first write operation to the first data storage block 322, a second write operation to the second data storage block 323, a third write operation to the third data storage block 324, and a fourth write operation to the fourth data storage block 325 is performed, the error correction buffer circuit 321 generates a first error correction signal ECC-S1 and a second error correction signal ECC-S2 from the first channel data D-CH1 and the second channel data D-CH2, respectively. The error correction buffer circuit 321 generates the first error correction signal ECC-S1, which includes information identifying one or more errors received in the first channel data D-CH1, and the second error correction signal ECC-S2, which includes information identifying one or more errors received in the second channel data D-CH2, based on an error correction code implemented, for example, by an H matrix or a RS code. Each of the first error correction signal ECC-S1 and the second error correction signal ECC-S2 may include one or more symbols or syndromes including information identifying the location of one or more errors in the data. The error correction buffer circuit 321 outputs a command address CA, a first chip select signal CS0, a second chip select signal CS1, first channel data D-CH1, second channel data D-CH2, and the error correction signal ECC-S.

[0054] The first data storage block 322 receives first channel data D-CH1, a command address CA, and a first chip select signal CS0 and a second chip select signal CS1 from an error correction buffer circuit 321 electrically connected to the first data storage block 322. Based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the first data storage block 322 stores the first channel data D-CH1 when a first write operation is performed. The first data storage block 322 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG in the first data storage block 322 stores the first channel data D-CH1 when selectively activated by the first chip select signal CS0 and the second chip select signal CS1.

[0055] The second data storage block 323 receives the first channel data D-CH1, the command address CA, the first chip select signal CS0, and the second chip select signal CS1 from the error correction buffer circuit 321 electrically connected to the second data storage block 323. Based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the second data storage block 323 stores the first channel data D-CH1 when the second write operation is performed. The second data storage block 323 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG in the second data storage block 323 stores the first channel data D-CH1 when selectively activated by the first chip select signal CS0 and the second chip select signal CS1.

[0056] The third data storage block 324 receives the second channel data D-CH2, the command address CA, the first chip select signal CS0, and the second chip select signal CS1 from the error correction buffer circuit 321 electrically connected to the third data storage block 324. Based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the third data storage block 324 stores the second channel data D-CH2 when the third write operation is performed. The third data storage block 324 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG in the third data storage block 324 stores the second channel data D-CH2 when selectively activated by the first chip select signal CS0 and the second chip select signal CS1.

[0057] The fourth data storage block 325 receives the second channel data D-CH2, the command address CA, the first chip select signal CS0, and the second chip select signal CS1 from the error correction buffer circuit 321 electrically connected to the fourth data storage block 325. Based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the fourth data storage block 325 stores the second channel data D-CH2 when the fourth write operation is performed. The fourth data storage block 325 includes a plurality of data storage circuits DATA STG. Each of the plurality of data storage circuits DATA STG in the fourth data storage block 325 stores the second channel data D-CH2 when selectively activated by the first chip select signal CS0 and the second chip select signal CS1.

[0058] The first error correction signal storage block 326 receives a command address CA, a first chip select signal CS0, a second chip select signal CS1, and a first error correction signal ECC-S1 from an error correction buffer circuit 321 electrically connected to the first error correction signal storage block 326. The first error correction signal storage block 326 stores the first error correction signal ECC-S1 based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1. Based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the first error correction signal storage block 326 stores the first error correction signal ECC-S1 when at least one of the first write operation, the second write operation, the third write operation, and the fourth write operation is performed. The first error correction signal storage block 326 includes a plurality of error correction signal storage circuits ECC-S STG. Each of the plurality of error correction signal storage circuits ECC-S STG in the first error correction signal storage block 326 stores the first error correction signal ECC-S1 when selectively activated by the first chip select signal CS0 or the second chip select signal CS1. When a read operation is performed on the first data storage block 322, the first error correction signal storage block 326 outputs the first error correction signal ECC-S1 to correct one or more errors received in the first channel data D-CH1 output through the first data storage block 322. When a read operation is performed on the second data storage block 323, the error correction signal storage block 326 outputs the first error correction signal ECC-S1 to correct one or more errors received in the first channel data D-CH1 output through the second data storage block 323.

[0059] The second error correction signal storage block 327 receives a command address CA, a first chip select signal CS0, a second chip select signal CS1, and a second error correction signal ECC-S2 from an error correction buffer circuit 321 electrically connected to the second error correction signal storage block 327. The second error correction signal storage block 327 stores the second error correction signal ECC-S2 based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1. Based on the command address CA, the first chip select signal CS0, and the second chip select signal CS1, the second error correction signal storage block 327 stores the second error correction signal ECC-S2 when at least one of the first write operation, the second write operation, the third write operation, and the fourth write operation is performed. The second error correction signal storage block 327 includes a plurality of error correction signal storage circuits ECC-S STG. Each of the plurality of error correction signal storage circuits ECC-S STG of the second error correction signal storage block 327 stores the second error correction signal ECC-S2 when selectively activated by the first chip select signal CS0 or the second chip select signal CS1. When a read operation is performed on the third data storage block 324, the error correction signal storage block 326 outputs the second error correction signal ECC-S2 to correct one or more errors received in the second channel data D-CH2 output through the third data storage block 324. When a read operation is performed on the fourth data storage block 325, the error correction signal storage block 326 outputs the second error correction signal ECC-S2 to correct one or more errors received in the second channel data D-CH2 output through the fourth data storage block 325.

[0060] When the semiconductor device 33 includes the first error correction signal storage block 326 and the second error correction signal storage block 327, the first error correction signal storage block 326 stores the first error correction signal ECC-S1 for correcting one or more errors received in the first channel data D-CH1 stored in the first data storage block 322 and the second data storage block 323, and the second error correction signal storage block 327 stores the second error correction signal ECC-S2 for correcting one or more errors received in the second channel data D-CH2 stored in the third data storage block 324 and the fourth data storage block 325. The semiconductor device 33 can improve the reliability of the first channel data D-CH1 and the second channel data D-CH2. Because the first error correction signal storage block 326 storing the first error correction signal ECC-S1 is shared by the first data storage block 322 and the second data storage block 323, and the second error correction signal storage block 327 storing the second error correction signal ECC-S2 is shared by the third data storage block 324 and the fourth data storage block 325, the semiconductor device 33 can have a reduced layout area.

[0061] refer to Figure 1 Semiconductor system described 1, reference Figure 4 The semiconductor system 2 described and reference Figure 6 The semiconductor system 3 described can be incorporated into electronic systems including storage systems, graphics systems, computing systems, and mobile systems. Figure 8 , an electronic system 1000 according to an embodiment of the present disclosure includes a data storage unit 1001 , a memory controller 1002 , a buffer memory 1003 , and an input and output I / O interface 1004 .

[0062] Based on a control signal from the memory controller 1002, the data storage unit 1001 stores data (not shown) output from the memory controller 1002, reads the stored data, and outputs the read data to the memory controller 1002. The data storage unit 1001 may include a non-volatile memory that can continuously store data without losing the data even if power is interrupted. The non-volatile memory may be implemented using a flash memory such as NOR flash memory or NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), or a magnetic random access memory (MRAM).

[0063] The storage controller 1002 receives instructions or commands from an external device (such as a host device) through the I / O interface 1004 and decodes them, and controls the input and output of data to and from the data storage unit 1001 and the buffer memory 1003 based on the decoded commands. Figure 8 , the memory controller 1002 is shown as one block, but the memory controller 1002 may include a separate controller for controlling the data storage unit 1001 and a controller for controlling the buffer memory 1003 (eg, a volatile memory). The memory controller 1002 may be referred to as Figure 1 Controller 11 described, reference Figure 4 The controller 21 described or referenced Figure 6 The controller 31 described above is implemented.

[0064] The buffer memory 1003 temporarily stores data processed by the memory controller 1002 (eg, data input to and output from the data storage unit 1001). The buffer memory 1003 stores data output from the memory controller 1002 based on a control signal. The buffer memory 1003 can be used with a reference signal. Figure 1 The semiconductor device 13 described in reference Figure 4 The semiconductor device 23 described or referenced Figure 6The semiconductor device 33 described above is implemented as shown. Buffer memory 1003 reads data stored in buffer memory 1003 and outputs the read data to memory controller 1002. Buffer memory 1003 may include volatile memory, such as dynamic random access memory (DRAM), mobile DRAM, or static random access memory (SRAM). Buffer memory 1003 may improve data reliability by including one or more error correction signal storage blocks (storing one or more error correction signals for correcting one or more errors in the received data, as described above).

[0065] I / O interface 1004 provides a physical connection between storage controller 1002 and an external device or host, allowing storage controller 1002 to receive control signals for controlling data input and output from the external device and exchange data with the external device. I / O interface 1004 can utilize one or more of a variety of interface protocols, such as Universal Serial Bus (USB), MultiMediaCard (MMC), Peripheral Component Interconnect-Express (PCI-E), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0066] The electronic system 1000 can be used as an auxiliary storage device or an external storage device of a host device. The electronic system 1000 can include a solid-state drive (SSD), a USB memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro SD card, a secure digital high-capacity (SDHC) card, a memory stick card, a smart media (SM) card, an MMC, an embedded MMC (eMMC), and a compact flash (CF) card.

[0067] Figure 9 2 is a block diagram showing an electronic system 2000 according to an embodiment of the present disclosure. Figure 9 As shown, the electronic system 2000 includes a host 2100 and a semiconductor system 2200 .

[0068] The host 2100 and the semiconductor system 2200 can transmit signals to each other using an interface protocol. Examples of the interface protocols used between the host 2100 and the semiconductor system 2200 include MMC, ESDI, IDE, PCI-E, Advanced Technology Attachment (ATA), SATA, PATA, SAS, and USB.

[0069] The semiconductor system 2200 includes a controller 2300 and a semiconductor device 2400 (1:K).

[0070] The controller 2300 can use the reference Figure 1 Controller 11 described, reference Figure 4 The controller 21 described or referenced Figure 6 Each semiconductor device 2400 (1:K) can be implemented by the controller 31 described above. Figure 1 The semiconductor device 13 described in reference Figure 4 The semiconductor device 23 described or referenced Figure 6 The semiconductor device 33 described above is implemented as shown. The semiconductor device 2400 (1:K) can be implemented using one or more of dynamic random access memory (DRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM). The semiconductor device 2400 (1:K) can improve data reliability by including one or more error correction signal storage blocks that store one or more error correction signals for correcting one or more errors received in the data.

[0071] The concepts are disclosed in conjunction with the examples and embodiments. Those skilled in the art will appreciate that various modifications, additions, and substitutions may be made without departing from the scope and technical concepts of the present disclosure. The embodiments disclosed in this specification should be considered from an illustrative rather than a restrictive perspective. Therefore, the scope of the present disclosure is not limited to the foregoing description. All variations within the meaning and scope of the equivalents of the claims are intended to be included within their scope.

Claims

1. A semiconductor device comprising: an error correction buffer circuit that: generates an error correction signal based on a command address, a first chip selection signal, a second chip selection signal, first data, and second data when one of a first write operation and a second write operation is performed; a first data storage block, which: stores the first data based on the command address, the first chip selection signal, and the second chip selection signal when the first write operation is performed; a second data storage block which: stores the second data when the second write operation is performed based on the command address, the first chip select signal, and the second chip select signal; and An error correction signal storage circuit stores the error correction signal when one of the first write operation and the second write operation is performed based on the command address.

2. The semiconductor device according to claim 1, wherein The error correction buffer circuit generates the error correction signal based on an error correction code, the error correction signal including information identifying received errors in the first data and the second data.

3. The semiconductor device according to claim 1, wherein: The first data storage block includes a plurality of data storage circuits; and Each of the plurality of data storage circuits stores the first data when selectively activated by the first chip select signal and the second chip select signal.

4. The semiconductor device according to claim 1, wherein: The second data storage block includes a plurality of data storage circuits, and Each of the plurality of data storage circuits stores the second data when selectively activated by the first chip select signal and the second chip select signal.

5. The semiconductor device according to claim 1, wherein When a read operation is performed on the first data storage block, the error correction signal storage circuit outputs the error correction signal to correct an error received in the first data output through the first data storage block. The semiconductor device according to claim 1 , wherein: When a read operation is performed on the second data storage block, the error correction signal storage circuit outputs the error correction signal to correct an error received in the second data output through the second data storage block.

7. A semiconductor device comprising: a first data storage block that: stores first data when a first write operation is performed based on a command address, a first chip selection signal, and a second chip selection signal; a second data storage block which: stores second data when a second write operation is performed based on the command address, the first chip select signal, and the second chip select signal; and An error correction signal storage circuit stores an error correction signal from a controller when one of the first write operation and the second write operation is performed based on the command address.

8. The semiconductor device according to claim 7, wherein: The first data storage block includes a plurality of data storage circuits; and Each of the plurality of data storage circuits stores the first data when selectively activated by the first chip select signal and the second chip select signal.

9. The semiconductor device according to claim 7, wherein: The second data storage block includes a plurality of data storage circuits; and Each of the plurality of data storage circuits stores the second data when selectively activated by the first chip select signal and the second chip select signal.

10. The semiconductor device according to claim 7, wherein When a read operation is performed on the first data storage block, the error correction signal storage circuit outputs the error correction signal to correct an error received in the first data output through the first data storage block.

11. The semiconductor device according to claim 7, wherein When a read operation is performed on the second data storage block, the error correction signal storage circuit outputs the error correction signal to correct an error received in the second data output through the second data storage block.

12. A semiconductor device comprising: an error correction buffer circuit that: generates a first error correction signal and a second error correction signal based on a command address, a first chip select signal, a second chip select signal, first channel data, and second channel data, when one of a first write operation of the first channel data and a second write operation of the second channel data is performed; a first data storage block, which: stores the first channel data based on the command address, the first chip selection signal, and the second chip selection signal when the first write operation is performed; a second data storage block, which: stores the second channel data based on the command address, the first chip selection signal, and the second chip selection signal when the second write operation is performed; a first error correction signal storage block that: stores the first error correction signal based on the command address, the first chip selection signal, and the second chip selection signal when the first write operation is performed; and A second error correction signal storage block stores the second error correction signal when the second write operation is performed based on the command address, the first chip selection signal, and the second chip selection signal.

13. The semiconductor device according to claim 12, wherein The error correction buffer circuit receives the first channel data transmitted from a controller through a first transmission line and the second channel data transmitted from the controller through a second transmission line.

14. The semiconductor device according to claim 12, wherein The error correction buffer circuit: generating the first error correction signal based on a first error correction code, the first error correction code including information identifying locations of errors received in the first channel data; as well as The second error correction signal is generated based on a second error correction code, the second error correction code including information identifying locations of errors received in the second channel data.

15. The semiconductor device according to claim 12, wherein: The first data storage block includes a plurality of data storage circuits; and Each of the plurality of data storage circuits stores the first channel data when selectively activated by the first chip select signal and the second chip select signal.

16. The semiconductor device according to claim 12, wherein: The second data storage block includes a plurality of data storage circuits; and Each of the plurality of data storage circuits stores the second channel data when selectively activated by the first chip select signal and the second chip select signal.

17. The semiconductor device according to claim 12, wherein When a read operation is performed on the first data storage block, the first error correction signal storage block outputs the first error correction signal to correct errors received in the first channel data output through the first data storage block.

18. The semiconductor device according to claim 12, wherein When a read operation is performed on the second data storage block, the second error correction signal storage block outputs the second error correction signal to correct errors received in the second channel data output through the second data storage block.

19. A semiconductor device comprising: a first data storage block that: stores first data when a first write operation is performed; a second data storage block which: stores second data when a second write operation is performed; and An error correction signal storage circuit stores an error correction signal, wherein the error correction signal corrects the first data stored in the first data storage block and the second data stored in the second data storage block.

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