Consistency system and method for keeping cache consistency by using same

Abstract

The invention relates to a consistency system characterized by: a plurality of processing units; an interconnect comprising a snoop filter (10), a collision buffer (20) for tracking ongoing or uncompleted snoops, and a snoop state machine (30) for managing snoop requests and snoop responses between the snoop filter (10), the collision buffer (20) and the processing unit; wherein the snoop filter (10) is configured to copy cache line data of a cache line read by the processing unit, match a cache line address with a tag of the snoop filter (10), and receive a snoop response; wherein the conflict buffer (20) is configured to indicate a hit or miss state based on a match condition of the snoop filter (10), and to send peer-to-peer cached snoop requests to a different processing unit. In addition, a method (100) for maintaining cache coherency using the coherency system is also disclosed.

Description

Technical Field

[0001] The present invention generally relates to a cache-coherent network-on-chip (NoC) architecture. More particularly, the present invention relates to a coherence system implemented with a snoop filter and a method for maintaining cache coherence using the coherence system. Background Art

[0002] A snoop filter is essentially a directory that keeps track of which CPUs in a coherent system have copies of a cache line. A snoop filter is an array of multiple entries. It is essentially organized like a cache. The array can be arranged in a direct-mapped or set-associative fashion, similar to a data cache. In a regular cache, the entire cache line is stored as data. Traditionally, static random access memory (SRAM) is used to achieve a 1:1 mapping of valid and in-progress status bits to each snoop filter entry, which requires a large storage area to implement and limits network bandwidth capacity.

[0003] Several solutions have been proposed to improve coherence systems and the methods used to maintain cache coherence using coherence systems, one of which is discussed below:

[0004] US20160062890 A1 relates to an interconnect having a consistency control circuit for performing consistency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and no spare snoop filter entries are available, the snoop filter selects a victim entry corresponding to a victim address and issues an invalidation transaction to invalidate a local cached copy of the data identified by the victim. The consistency control circuit used to perform consistency check operations on data access transactions is reused to perform consistency control operations on invalidation transactions issued by the snoop filter.

[0005] The aforementioned reference provides an interconnect having a coherence control circuit for performing coherence control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. However, the interconnect still has many limitations and disadvantages, such as being non-scalable, requiring a large storage area for implementation, and being inflexible. Therefore, there remains a need for a scalable coherence system and a method for maintaining cache coherence using the coherence system to conserve storage area and achieve better performance. Summary of the Invention

[0006] To provide a basic understanding of certain aspects of the present invention, a simplified summary of the present invention is provided below. This summary is not an extensive overview of the present invention. Its sole purpose is to present some concepts of the present invention in a simplified form as a prelude to the more detailed description that will be presented later.

[0007] The object of the present invention is to provide a dual-mode snoop filter with a conflict buffer to achieve high area utilization, flexible implementation, and can be easily expanded according to system requirements.

[0008] Therefore, these objects can be achieved by following the teachings of the present invention. The present invention relates to a coherence system characterized by: a plurality of processing units; an interconnect including a snoop filter, a conflict buffer for tracking in-progress or incomplete snoops, and a snoop state machine for managing snoop requests and snoop responses between the snoop filter, the conflict buffer, and the processing units; wherein the snoop filter is configured to copy cache line data of a cache line read by a processing unit, match the cache line address with a tag of the snoop filter, and receive a snoop response; wherein the conflict buffer is configured to indicate a hit or miss status based on a match of the snoop filter and send a snoop request of a peer cache to a different processing unit.

[0009] The present invention also relates to a method for maintaining cache coherence using a coherence system, the method comprising the steps of: sending a query to a snoop filter by a snoop state machine when a processing unit reads a cache line; matching a query address of the snoop filter with an address of the cache line; comparing the address of the cache line with all tags of the snoop filter; if there is no match with the tags, indicating a miss result in the snoop filter; selecting a set of snoop filters to pass the miss result to the snoop state machine; searching a snoop ID in a conflict buffer having fewer entries than the snoop filter, and if no entry matches, selecting a free entry in the conflict buffer, marking the snoop ID of the selected free entry of the conflict buffer with the value of the query address, and setting the in-progress bits of the entry of the conflict buffer to 1, indicating that the snoop filter is now snooping on the query address; sending a query to a subsequent cache line by a subsequent processing unit; and repeating the step of comparing the address of the subsequent cache line with all tags of the snoop filter to find a match.

[0010] The foregoing and other objects, features, aspects and advantages of the present invention will be better understood through careful reading of the following detailed description provided in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to enable a detailed understanding of the above-enumerated features of the present invention, a more particular description of the invention briefly summarized above may be made by reference to exemplary embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the invention and are therefore not to be considered as limiting the scope of the invention, as the invention may be adapted to other equally effective embodiments.

[0012] These and other features, benefits and advantages of the present invention will become apparent by reference to the following text and drawings, in which like reference numerals represent like structure throughout the several views, and in which:

[0013] Figure 1 is a flow chart illustrating a method for maintaining cache coherence using a coherence system according to an embodiment of the present invention;

[0014] Figure 2 is an example showing a 4-way set associative snoop filter with 256 entries, where 8 address bits are extracted from the query address to map to the 256 entries;

[0015] Figure 3 An example of a coherence system architecture including a snoop filter, a conflict buffer, and a snoop state machine according to an embodiment of the present invention is shown;

[0016] Figure 4 An example of a collision buffer for tracking outstanding snoops according to an embodiment of the present invention is shown;

[0017] Figure 5 An example is shown in which entry-0 of the collision buffer marked as "snoop ID" is set to 5 (A[13:6]==5), and bits[0] of the 4-bit "ip" bit is set to 1;

[0018] Figure 6 An example showing a second request to address B, but with address bits A[13:6] == 5;

[0019] Figure 7 An example is shown where all four sets of entry-5 of the snoop filter are currently being snooped;

[0020] Figure 8 shows an example where a miss in the snoop filter causes a "violation" in the snoop state machine, causing the query to have to be retried;

[0021] Figure 9 An example is shown of how a snoop filter receives an update to set-0 of the snoop filter, which causes the "ip" bit[0] to be cleared and set-0 is no longer a snoop in progress;

[0022] Figure 10 An example showing the snoop status bits of each set in entry-5 of the snoop filter, where each set is now updated based on information about which CPU has the cache line;

[0023] Figure 11 An example is shown where a request to address E will result in a miss, where address bits [13:6] == 5;

[0024] Figure 12 shows an example where a request on cache line D must be postponed and retried due to a conflict on entry-0 of the conflict buffer;

[0025] Figure 13 An example is shown where the conflict buffer entry-11 is cleared;

[0026] Figure 14 An example is shown where way-0 of snoop filter entry-5 is now snooping, i.e., "ip" bit[0] is set to 1;

[0027] Figure 15 An example is shown where all 4 sets are snooping;

[0028] Figure 16 An example is shown where no other sets are snooping;

[0029] Figure 17 shows an example where a request to address E with address bits [13:6] == 5 will result in a miss; and

[0030] Figure 18 An example is shown in which the ongoing "ip" of the conflict buffer entry-11 is cleared to 0000. DETAILED DESCRIPTION

[0031] As required, detailed embodiments of the present invention are disclosed herein; however, it should be understood that the disclosed embodiments are merely exemplary embodiments of the present invention that can be implemented in various forms. Therefore, the specific structural and functional details disclosed herein should not be interpreted as restrictive, but only as the basis of the claims. It should be understood that the drawings and their detailed description are not intended to limit the present invention to the specific forms disclosed. On the contrary, the present invention will cover all modifications, equivalents and substitutes within the scope of the present invention defined by the appended claims. As used in this application, the word "may" is used in a permissive sense (i.e., meaning possible), rather than a mandatory sense (i.e., meaning must). Similarly, the words "include", "includes" and "includes" mean including but not limited to. In addition, unless otherwise indicated, the words "a" or "an" mean "at least one", and the word "some" means one or more. When abbreviations or technical terms are used, they represent the generally accepted meanings known in the technical field.

[0032] The present invention is described below by various embodiments with reference to the accompanying drawings, wherein the reference numerals used in the drawings correspond to similar elements throughout the description. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Specifically, the embodiments are provided to enable the present invention to be thoroughly and completely disclosed and to fully convey the scope of the invention to those skilled in the art. In the detailed description below, values and ranges are provided for various aspects of the described embodiments. These values and ranges are considered to be examples only and are not intended to limit the scope of the claims. In addition, many materials are considered to be applicable to various aspects of the embodiments. These materials will be considered to be exemplary and are not intended to limit the scope of the invention.

[0033] The present invention will now be described in more detail with reference to the accompanying drawings.

[0034] The present invention relates to a consistency system, characterized by: a plurality of processing units; an interconnection including a snoop filter (10), a conflict buffer (20) for tracking ongoing or incomplete snoops, and a snoop state machine (30) for managing snoop requests and snoop responses between the snoop filter (10), the conflict buffer (20) and the processing units; wherein the snoop filter (10) is configured to copy cache line data of a cache line read by a processing unit, match the cache line address with a tag of the snoop filter (10), and receive a snoop response; wherein the conflict buffer (20) is configured to indicate a hit or miss status based on a match condition of the snoop filter (10) and send a peer cache snoop request to a different processing unit.

[0035] According to an embodiment of the present invention, the coherency system may be extended to include data on top of cache ownership information to implement system-level cache support.

[0036] According to an embodiment of the present invention, a snoop filter (10) includes a plurality of sets (12), a plurality of entries, a plurality of address bits, each set including a tag and a snoop state.

[0037] According to an embodiment of the present invention, the snoop filter (10) is a direct-mapped array or a set-associative array.

[0038] According to an embodiment of the present invention, the collision buffer (20) includes a configurable number of entries, each of which includes a snoop ID and a plurality of bits indicating the status of the snoop. In addition, the snoop ID is an address field that is compared with the query address. If the two match, this is a collision buffer (20) hit. Its data field is then sent to the snoop filter (10).

[0039] According to an embodiment of the present invention, a conflict buffer (20) is used in conjunction with a snoop filter whereby when a cache line address is presented to the snoop filter (10), a portion of the address is used to select an entry from the snoop filter (10). The same portion of the address is used to look up the conflict buffer (20), e.g. Figure 3 shown.

[0040] According to an embodiment of the present invention, the number of in-progress bits of the collision buffer (20) corresponds to the number of sets (12) of snoop filters (10).

[0041] According to an embodiment of the present invention, the number of entries of the snoop filter (10) is higher than the number of entries of the collision buffer.

[0042] According to an embodiment of the present invention, a conflict buffer (20) is used to track unfinished snoops, starting from a query of the snoop state machine (30) to the snoop filter (10), and finally until the snoop state machine (30) updates the entry of the snoop filter (10) with the latest processing unit consistency information, in particular, the processing unit refers to the central processing unit (CPU). The "ip" bit indicates that the snoop is in progress, such as Figure 4 shown.

[0043] According to an embodiment of the present invention, the coherence system is capable of executing two different modes including an area saving mode and a high performance mode.

[0044] The present invention also relates to a method (100) for maintaining cache consistency using the above consistency system. The method comprises the following steps: when a processing unit reads a cache line, a query is sent by a snoop state machine to a snoop filter (101); a query address of the snoop filter is matched with an address of the cache line (102); the address of the cache line is compared with all tags of the snoop filter (103); if there is no match with the tag, a miss result is indicated in the snoop filter (104); a set of snoop filters is selected to pass the miss result to the snoop state machine (105); a snoop ID is searched in a conflict buffer having fewer entries than the snoop filter, and if there is no matching entry, a free entry is selected in the conflict buffer, the snoop ID of the selected free entry of the conflict buffer is marked with the value of the query address, and the in-progress bit of the entry of the conflict buffer is set to 1 to indicate that the snoop filter is now snooping on the query address (106); a query is sent by a subsequent processing unit to a subsequent cache line (107); and the step of comparing the address of the subsequent cache line with all tags of the snoop filter to find a match is repeated (108), such as Figure 1 shown.

[0045] According to an embodiment of the present invention, for the area saving mode, while searching the snoop ID miss result in the conflict buffer (20), the snoop state machine (30) sends a snoop request to other processing units to snoop any processing unit containing the same cache line.

[0046] According to an embodiment of the present invention, when a processing unit requests a duplicate cache line, a snoop filter (10) having a tag matching the cache line address is hit, enabling the corresponding processing unit to send a snoop request.

[0047] According to an embodiment of the present invention, the method further comprises the following steps: when all the in-progress bits of an entry in a conflict buffer (20) are 1, delaying a snoop request to other processing units, wherein the snoop query address is equal to the snoop ID of the entry in the conflict buffer; updating an entry in a snoop filter (10) with information of the processing unit and ownership of the cache line; clearing the corresponding in-progress bit to 0; retrying the snoop request to a new cache line; updating the same entry in the snoop filter (10) with information of subsequent processing units and subsequent cache lines; and clearing all the in-progress bits to 0.

[0048] According to an embodiment of the present invention, when the in-progress bits of the collision buffer (20) are all zeros, entries of the collision buffer (20) are free to track other entries of the snoop filter (10).

[0049] According to an embodiment of the present invention, for the high performance mode, the processing unit having the exclusive ownership of the corresponding cache line is updated.

[0050] According to an embodiment of the present invention, when a snoop filter (10) of a used entry receives a miss result of a new cache line, a snoop invalidation request is executed to a processing unit to release the exclusive ownership of the corresponding cache line and update the exclusive ownership of the new cache line.

[0051] Hereinafter, examples of the present invention will be provided to explain in more detail. Advantages of the present invention can be more easily understood and put into practice from these embodiments. However, it should be understood that the following examples are not intended to limit the scope of the present invention in any way.

[0052] example

[0053] Figure 2 FIG2 is an example of a 4-way set-associative snoop filter (10) with 256 entries. Eight address bits are extracted from the query address to map to the 256 entries. For example, if a cache line has 512 bits (64 bytes), address bits [5:0] are ignored. Address bits [13:6] (8 address bits) can be used to address the 256-entry snoop filter (10).

[0054] An 8-bit address reads entry-M from each set. The tag is used to compare with the upper bits of the query cache line address. In this example, a 4-way set associative snoop filter (10) will have 4 tags. Address bits [31:14] are compared with all 4 tags stored in entry-M (selected by address bits [13:6] of the query cache line address). Either all tags do not match or at most one tag matches, and a hit or miss indication is generated. If it is a hit, the central processing unit (CPU) status field of entry-M of the set that hit is passed to the snoop state machine (30). If all tags do not match, then a miss indication is passed to the snoop state machine (30) along with the index of the way to be overwritten with the new cache line information. How this index is selected (1 of the 4 sets) is not within the scope or interest of this disclosure. A literature review of cache replacement strategies will reveal many approaches, with least recently used (LRU) being one of them. In this example, an LRU approach is assumed to determine 1 of the N indexes (in the N-way set associative snoop filter (10)). (Note: other embodiments may also implement different approaches to determine which of the N sets to use for replacement in the N-way set associative snoop filter (10).

[0055] The snoop filter (10) can reduce the number of snoops sent to the CPUs compared to a coherent system without the snoop filter (10). For example, if there are four CPUs in the coherent system, then without the snoop filter (10), at least three snoops must be sent from the requesting CPU or the home agent to the three CPUs. With the snoop filter (10), the snoop filter (10) will know whether any CPU has the cache line or no CPU has the cache line. If not, then no snoop request is required, thereby saving bandwidth on the system bus or on-chip network.

[0056] The combination of the snoop filter (10) and the collision buffer provides two modes of operation.

[0057] (1) Regional saving mode.

[0058] In this mode, the present snoop filter (10) utilizes minimal storage to save area compared to not using any snoop filter (10), while still providing the benefit of reducing the number of snoops required.

[0059] Table 1 shows each data field (of a tag-data pair), which contains the following Boolean information (assuming 6 CPUs, ie, R=6).

[0060] Table 1:

[0061]

[0062] Thus, the data field of each "way" of an entry in the snoop filter (10) tracks the "shared" state of the cache line across all CPUs.

[0063] Figures 5 to 13 An example of the dynamics between the snoop state machine (30) and the snoop filter (10) (256 entry, 4-way set associative, with a 32 entry collision buffer) is shown:

[0064] 1) CPU-0 performs a read of address A (cache line A). The snoop state machine (30) sends a query to the snoop filter (10).

[0065] 2) Look up address A[13:6]=5 and query entry-5 of the snoop filter (10). Compare [31:14] to all 4 tags. If none of them match, a miss result is generated. The LRU selects set-0. This information is passed to the snoop state machine (30).

[0066] 3) At the same time, the conflict buffer (20) is searched with snoop ID = 5. No entries in the conflict buffer (20) match, so a free entry in the conflict buffer (20) is allocated. Assume that entry-0 of the conflict buffer (20) is selected.

[0067] 4) Entry-0 of the collision buffer (20) is marked as having "snoop ID" set to 5 (A[13:6] == 5), and bits [0] of the 4-bit "ip" bit is set to 1. This indicates that set-0 of entry-5 of the snoop filter (10) is now being snooped.

[0068] 5) The snoop state machine (30) receives the miss information from the snoop filter (10). In the area saving mode, the snoop state machine (30) will send snoop requests to the other five CPUs because it does not know whether any CPU has cache line A. This is called peer cache snooping, that is, snooping the peer CPU at the same address A.

[0069] 6) While waiting for the snoop response of cache line A, CPU-1 sends a request for cache line B. B address [13:6] will be used for reference in the snoop filter (10).

[0070] 7) For this example, assume that B[13:6] == 5, so it points to the same entry as the previous A[13:6] (i.e., B[13:6] == A[13:6] == 5). It is also assumed that B[31:14] != A[31:14], so there is no hit between the tags of the snoop filter (10) entry A[13:6].

[0071] 8) Since it is a miss, the LRU will select a way for the query. The snoop state machine (30) will be notified of the miss result, so it will send snoop requests for cache line B to all other CPUs.

[0072] 9) At the same time, B[13:6] is compared with all 32 entries in the collision buffer. Since the value of B[13:6] == A[13:6] == 5, entry-0 of the collision buffer (20) will be indicated as a collision hit. The current "in progress" bit (in progress bit) of the collision buffer (20) is 0001, indicating that set-0 is being snooped.

[0073] 10) Therefore, the LRU will not select set-0. It should select set-1 / 2 / 3. Assuming that the LRU selects set-1, the conflict buffer (20) entry-0 will set its "in progress" bit to 1100 (indicating that set-0 and set-1 are being snooped). The snoop state machine (30) will send peer cache snoop requests to the other 5 CPUs (CPUs 0, 2, 3, 4, and 5) because it does not know whether any CPU contains cache line B.

[0074] 11) CPU-2 and CPU-3 then send requests for cache line C and cache line D, respectively. Assume that C[13:6] == D[13:16] == B[13:16] == A[13:16] == 5. Both C and D are mapped to entry-5 of the snoop filter (10).

[0075] 12) Assuming C[31:14]!=D[31:14], both requests will result in a miss between the tags of entry-5 of snoop filter (10). The LRU will select set-2 for request C and set-3 for request D. Since entry-5 of snoop filter (10) is tracked by entry-0 of conflict buffer (20), the "ip" bit of entry-0 of conflict buffer (20) is set to all 1s, i.e., 1111, indicating that all sets of entry-5 of snoop filter (10) are currently being snooped.

[0076] 13) The snoop state machine (30) will be notified of the miss result, so it will send peer snoop requests to all other CPUs for cache lines C and D.

[0077] 14) Assume that in the worst case, CPU 4 coincidentally sends a request for cache line E, and E[13:6] == 5, so it again corresponds to entry-5 of snoop filter (10). E[31:14] still causes a miss in snoop filter (10). Entry-0 of conflict buffer (20) also indicates that the "in progress" bits are all 1, so the LRU will not be able to allocate any entry to cache line E. It indicates a "conflict" to the snoop state machine (30).

[0078] 15) Upon receiving a "conflict" indication, the snoop state machine (30) will temporarily postpone the snoop query of cache line E (to be retried later).

[0079] 16) The snoop response to cache line A will eventually reach the snoop state machine (30), and it will update set-0 of entry-5 of snoop filter (10) with the information of the cache line (cpu state or cs=100000) and tag address (A[31:14]) held by CPU0. Bits[0] of entry-0 of conflict buffer (20) is cleared, indicating that set-0 of entry-5 of snoop filter (10) is no longer snooped.

[0080] 17) At this point, the query request for cache line address E can be retried.

[0081] 18) The snoop responses for cache lines B, C, and D will also eventually return to the snoop state machine (30), and the snoop state machine (30) will update entry-5 of the snoop filter (10), set-1 (for the snoop response corresponding to cache line B), set-2 (for the snoop response corresponding to cache line C), and set-3 (for the snoop response corresponding to cache line D). The "in progress" bits of entry-0 of the conflict buffer will eventually be cleared to all 0s. When this happens, entry-0 of the conflict buffer (20) is freed because it no longer needs to track entry-5 of the snoop filter (10), i.e., it can be freely reallocated / reclaimed to track other entries of the snoop filter (10). The snoop state bits of each set in entry-5 of the snoop filter (10) are now updated with the information of which CPU has the cache line.

[0082] 19) Now, if there is a new request from CPU x for cache line A (or B, C, D), it will result in a hit in entry-5 of the snoop filter (10). The data from entry-5 and the way with a tag matching address [31:14] will be used by the snoop filter (10) to determine the CPU to send the snoop request. In this example, the CPU state is 100000, which means that CPU-0 has the cache line, so the snoop state machine (30) will only snoop CPU-0 for cache line A.

[0083] 20) The previous request for cache line E was deferred and can now be retried. E[13:6] will map to entry-5 of the snoop filter (10). Snoop ID 5 is used to look up the conflict buffer (20), but there is no match. So assume entry-11 of the conflict buffer (20) is allocated. Assuming the LRU selects set-3, the "in progress" bits[3] of entry-11 of the conflict buffer (20) are set to 0001. The snoop state machine (30) will send peer cache snoops to CPUs 0, 1, 2, 3, and 5 for cache line address E.

[0084] 21) This also means that previously set-3 tracked cache line D, but now it has been reallocated to track cache line E.

[0085] 22) If the CPU subsequently issues a request for cache line D, this will again result in a mapping to entry-5 in the snoop filter (10). But this time it will result in a hit on set-3. However, entry-0 of the conflict buffer (20) has the "in progress" bit [3] set to 1, which means that another earlier request is occupying set-3, so this request for cache line D must be postponed and retried later.

[0086] 23) Once the snoop state machine (30) receives the earlier snoop response corresponding to cache line E, the snoop filter (10) is updated with entry-5, the flag of set 3 is set to E, and the conflict buffer (20) entry-11 is cleared.

[0087] The advantage of area saving mode is that it will have far fewer collision buffer (20) entries than the snoop filter (10). The snoop filter (10) can have 1 million entries, but only 32 entries in the collision buffer. The collision buffer (20) needs to be large enough to keep track of pending or incomplete snoops. Snoop delays are not indefinite, so they do not require a very large collision buffer. This is a big improvement over existing implementations, which may have a 1:1 mapping of the snoop filter (10) to the in-progress, in-use, or valid bits.

[0088] In addition, note that for this "area saving" mode, it is possible to have a very small snoop filter (10). Any miss in the snoop filter (10) will cause the snoop state machine (30) to perform a peer snoop request to all CPUs and still be functionally correct. The worst case 0-entry snoop filter (10) is similar to the case where the snoop filter (10) is not enabled, where the snoop state machine (30) always sends a peer snoop request to all CPUs on every cache line request.

[0089] Furthermore, using a small snoop filter (10) in "area saving" mode comes at the expense of increased snoop request and snoop response traffic. It does not limit the effective size of the CPU cache. That is, the CPU cache can still be made much larger than the snoop filter (10).

[0090] The number of peer snoop requests sent by the snoop state machine (30) decreases in proportion to the size of the snoop filter (10). Therefore, if storage area permits, the size of the snoop filter (10) can be significantly increased to reduce the snoop traffic (snoop requests and snoop responses).

[0091] (2) High performance mode.

[0092] The same structure is used (snoop filter (10) and collision buffer), but with some differences.

[0093] Table 2 shows that the difference is that each set of snoop filters (10) now keeps track of additional information.

[0094] Table 2:

[0095]

[0096] In addition to storing information about which CPUs can share the same cache line (with read-only permissions), each entry in the snoop filter also stores the ID of the CPU that has exclusive access to the cache line. The snoop state machine (30) uses this information to perform different types of snoops depending on the request type and the CPU snoop state.

[0097] The second difference is that a miss on the snoop filter (10) means that no CPU contains the cache line, so the snoop state machine (30) does not need to send any snoop requests. This is compared to the region saving mode, where a miss on the snoop filter (10) means that the snoop state machine (30) needs to send snoop requests to all CPUs. Another way to understand this is that the region saving mode does not save precise information about the cache state, so it can have far fewer entries, but the disadvantage is that it causes the snoop state machine (30) to send more snoops. The high performance mode needs to save precise information about the cache state of all CPUs, no more and no less, in order to send the minimum number of snoops required, but doing so requires more storage area to save this information.

[0098] The third difference is that now with the additional information (the exclusive CPU ID), the snoop state machine (30) can optimize the final snoop request required depending on the type of cache line request.

[0099] An example illustrating how the high performance snoop filter (10) works is shown below.

[0100] 1) CPU-0 performs a read of address A (cache line A). The snoop state machine (30) sends a query to the snoop filter (10).

[0101] 2) Request address A[13:6] is mapped to entry-5 in the snoop filter (10) (i.e., the value of a[13:6] is 5). a[31:14] is compared with all four tags. There is no match, resulting in a miss, and the LRU selects way-0. This information is passed to the snoop state machine (30). Snoop ID 5 is sent to the conflict buffer (20) for a lookup. Again, there is no match, and entry-0 in the conflict buffer (20) is allocated.

[0102] 3) The collision buffer (20) entry-0 is marked as having the "snoop entry ID" set to 5 (a[13:6] == 5), and the 4-bit "in progress" bit, "ip" bits[0], is set to 1. This indicates that way-0 of entry-5 of the snoop filter (10) is now being snooped.

[0103] 4) The snoop state machine (30) gets a miss from the snoop filter (10). In high performance mode, the snoop state machine (30) does not need to send any snoop requests to other CPUs.

[0104] a. Compared to area saving mode, this results in fewer snoop requests (and snoop responses), thus saving bandwidth for the on-chip network.

[0105] 5) While the cache line A operation is in progress, CPU-1, CPU-2, and CPU-3 send requests for cache line B, cache line C, and cache line D, respectively.

[0106] 6) As in the previous example, all three cache lines have addresses [13:6] == 5, so they all map to entry-5 of the snoop filter (10). All three results are misses. Entry-0 of the conflict buffer (20) is also updated, setting the "ip" in-progress bit to all 1s. In other words, all four sets are snooping.

[0107] 7) The snoop state machine (30) will be notified of the miss results on cache lines B, C, D. However, it does not need to send any snoop requests.

[0108] 8) Since no snoop request is sent, the snoop state machine (30) can easily update way-0 / 1 / 2 / 3 of entry-5 with this information:

[0109] a.set-0: tag = a[31:14], CS = 100000 (no other CPU shares this cache line). CPU ID = 0, meaning CPU-0 has exclusive ownership of cache line A.

[0110] b.set-1: Tag = B[31:14], CS = 010000 (no other CPUs share this cache line). CPU ID = 1, meaning CPU-1 has exclusive ownership of cache line B.

[0111] c.set-2: tag = C[31:14], CS = 001000 (no other CPU shares this cache line). CPU ID = 2, meaning CPU-2 has exclusive ownership of cache line C.

[0112] d.set-3: tag = D[31:14], CS = 000100 (no other CPU shares this cache line). CPU ID = 3, meaning CPU-3 has exclusive ownership of cache line D.

[0113] 9) Entry-0 of the collision buffer that tracks entry-5 of the snoop filter (10) resets its "in progress" bits to all 0s, since entry-5 of the snoop filter (10) has been updated and no other set is snooping.

[0114] 10) CPU-4 then sends a request for cache line E. E[13:6] == 5 and it also maps to entry-5 of the snoop filter (10). Snoop ID 5 is sent to the conflict buffer (20) for a lookup, but no entry matches. Entry-11 is assigned to this request. Entry-11 of the conflict buffer, which now tracks entry-5 of the snoop filter (10), has all 0s in its "in progress" bits, so there is nothing blocking the request for cache line E.

[0115] 11) Since cache line E is not in any of the sets in entry-5, this will result in a miss. Assume that the LRU selects set-0 for this. The "in progress" bit of the conflict buffer (20) entry-11 is set to 1000 (set-0 is being snooped).

[0116] 12) The snoop state machine (30) receives a miss indication on entry-5, way-0 of the snoop filter (10). The snoop state machine (30) executes a snoop invalidate request to CPU-0. This forces CPU-0 to release its cache line A.

[0117] a. This is called a victim cache snoop because there is no request for cache line A, but it is invalidated anyway to allow the set in the snoop filter (10) to hold the information for cache line E. Therefore, it is the victim due to the resource conflict in the snoop filter (10).

[0118] b. Note that this is one of the differences compared to Region Save Mode. In Region Save Mode, the snoop state machine (30) will send peer snoops on cache line E to all other CPUs, while CPU-0's cache containing cache line A is not affected.

[0119] 13) After receiving the snoop response from CPU-0, the snoop state machine (30) will update set-0 of entry-5:

[0120] a. Set-0: Tag = E[31:14], Data = 000010 (no other CPU shares this cache line), CPU ID = 4, i.e., CPU-4 has exclusive ownership of cache line E.

[0121] b. The in-progress bit "ip" of entry-11 of the collision buffer (20) is cleared to 0000.

[0122] 14) Next, CPU-5 sends a request for cache line A. A[13:6] == 5 and it also maps to entry-5 of the snoop filter (10). The "in progress" bits of entry-0 of the conflict buffer that tracks entry-5 of the snoop filter (10) are all 0, so there is nothing blocking the request for cache line A. Since cache line A is not in any of the sets of entry-5, this results in a miss. The LRU selects one of the sets, which in this example is set-0. The "in progress" bits of entry-11 of the conflict buffer (20) are set to 1000 (set-0 is being snooped). The snoop state machine (30) sends an invalid snoop to CPU-4 on cache line E.

[0123] This is the main difference compared to locality-saving mode. In locality-saving mode, at address A, a peer snoop is sent to all other CPUs (CPUs 0, 1, 2, 3, and 4). In high-performance mode, only one snoop is sent to CPU 4 at cache line address E. CPU 4's cache line E becomes the victim.

[0124] 15) Then the snoop state machine (30) will update way-0 of entry-5:

[0125] a. Way-0: Tag = A[31:14], Data = 100000 (no other CPU shares this cache line), CPU ID = 5, i.e., CPU-5 has exclusive ownership of cache line A.

[0126] Compared to the "area saving" mode, the "high performance" mode has the following advantages, such as far fewer snoop requests. When there is a miss, the snoop state machine (30) will issue a single "snoop invalidate" (snoop invalidate) request. In the "area saving" mode, a miss in the snoop filter (10) will cause a snoop request to be sent to all other CPUs (except the requesting CPU). Therefore, the "high performance" mode will save bandwidth on the on-chip network. In addition, for the "high performance" mode, when an existing snoop filter (10) entry needs to be replaced because all sets are used, this will result in additional invalidation snoops to remove the cache line from the CPU containing the cache line, which is in contrast to the "area saving" mode, in which the replaced entry is removed without additional invalidation snoops. However, the number of invalidation snoops required will be less because it will only invalidate the CPU containing the cache line instead of invalidating all CPUs.

[0127] For different operations, different snoop filter (10) operation sequences are required, as follows:

[0128] 1. An allocate operation causes the requester's CPU to reserve the cache line through shared or exclusive ownership.

[0129] (a) If the snoop filter (10) misses:

[0130] (i) "Region saving" mode, performs a snoop on all peer CPUs on the request address (to force any CPU that may own the cache line to relinquish ownership of the cache line). If all sets are used, the existing set in the snoop filter (10) entry is replaced with the new tags and cache state. The replaced tags do not need to be invalidated.

[0131] (ii) "Region Saving" mode, where no snooping is required, since a miss in the snoop filter (10) provides certainty that no other CPU's cache contains the cache line. If all sets are used, the existing set in the snoop filter (10) entry is replaced with the new tag and cache state. The replaced tag will cause an invalidation snoop to remove the cache line (== replaced address) from the CPU whose ID == the replaced CPU ID.

[0132] (b) If the snoop filter (10) is hit:

[0133] (i) "Area Saving" and "High Performance" modes, both of which will perform snoops on the CPU indicated in the cache state retrieved from the snoop filter (10). The new cache state is then updated in the snoop filter (10) as required by the allocation operation.

[0134] 2. Release operation, which will cause the eviction of the CPU cache line.

[0135] (a) If the snoop filter (10) misses:

[0136] (i) "Region saving" mode, a snoop is performed on all peer CPUs on the request address (to force any CPU that may have the cache line to evict it). If all sets are used, the existing set in the snoop filter (10) entry is replaced with the new tags and cache state. The replaced tags do not need to be invalidated.

[0137] (ii) "High Performance" mode, no snooping is required, because a miss in the snoop filter (10) provides certainty that no other CPU's cache contains the cache line. No snoop filter (10) update is required, because no other CPU will retain the cache line after this release operation.

[0138] (b) If the snoop filter (10) is hit:

[0139] (i) "Area Saving" and "High Performance" modes, both of which will perform snoops on the CPU indicated in the cache state retrieved from the snoop filter (10). After a release operation, no CPU will retain the cache line; the set in the snoop filter (10) will be updated to an all-zero cache state.

[0140] 3. Cache state change operation: This results in a change in the cache state of the requester CPU or peer CPU based on the operation requirements.

[0141] (a) If the snoop filter (10) misses:

[0142] (i) "Area saving" mode, snoops are performed on all peer CPUs and the way is updated with updated cache status according to the snoop response. If the way is full, the existing way in the snoop filter (10) entry is replaced.

[0143] (ii) In "high performance" mode, no snooping is required; a miss in the snoop filter (10) provides certainty that no other CPU's cache contains the cache line. If the way is full, the existing way in the snoop filter (10) entry is replaced; the replaced entry will cause an invalidation snoop to remove the cache line from the CPU (ID == CPUID) containing the cache line (address = replacement tag).

[0144] (b) If the snoop filter (10) is hit:

[0145] (i) Both “Area Savings” and “High Performance” modes will perform snoops on the CPU containing the cache line as required by the operation and update the cache state accordingly.

[0146] Various modifications to these embodiments will be apparent to those skilled in the art from the description and drawings. The principles associated with the various embodiments described herein may be applied to other embodiments. Therefore, the description is not intended to be limited to the accompanying Figure 1 The present invention is intended to provide the widest scope consistent with the principles and novel and inventive features disclosed or suggested herein, and is therefore intended to retain all such alternatives, modifications and variations that fall within the scope of the present invention and the appended claims.

[0147] In the following claims and foregoing description of the invention, unless the context requires otherwise due to explicit language or necessary implication, the word "comprise" or variations such as "include" or "comprising" are used in an inclusive sense, i.e., to specify the presence of features but not to exclude the presence or addition of other features in various embodiments of the invention.

Claims

1. A consistency system, characterized by: multiple processing units; An interconnect comprising a snoop filter (10), a collision buffer (20) for tracking in-progress or incomplete snoops, and a snoop state machine (30) for managing snoop requests and snoop responses between the snoop filter (10), the collision buffer (20), and the processing unit; wherein the snoop filter (10) is configured to copy cache line data of a cache line read by the processing unit, match a cache line address with a tag of the snoop filter (10), and receive the snoop response; The conflict buffer (20) is configured to indicate a hit or miss status based on a match condition of the snoop filter (10) and to send peer cache snoop requests to different processing units.

2. The consistency system according to claim 1, wherein: The snoop filter (10) includes a plurality of sets (12), a plurality of entries, and a plurality of address bits, and each of the sets (12) includes a tag and a snoop state.

3. The consistency system according to claim 1, wherein: The collision buffer (20) includes a configurable number of entries, each entry including a snoop ID and a plurality of in-progress bits indicating a snoop status.

4. The consistency system according to claim 2 or 3, wherein: The number of bits in progress of the collision buffer (20) corresponds to the number of sets (12) of snoop filters (10).

5. The consistency system according to claim 1, wherein: The snoop filter (10) comprises a number of entries higher than the number of entries of the collision buffer.

6. A method (100) for maintaining cache coherence using the coherence system according to claim 1, the method comprising the following steps: When a processing unit reads a cache line, a query (101) is sent by the snoop state machine to the snoop filter; matching the query address of the snoop filter with the address of the cache line (102); comparing the address of the cache line with all tags of the snoop filter (103); If there is no match with the tag, then indicating a miss result in the snoop filter (104); selecting a set of snoop filters to pass the miss result to the snoop state machine (105); searching for the snoop ID in a conflict buffer having fewer entries than the snoop filter, and if no entry matches, selecting a free entry in the conflict buffer, marking the snoop ID of the selected free entry of the conflict buffer with the value of the query address, and setting an in-progress bit of the entry of the conflict buffer to 1 to indicate that a snoop for the query address is now in progress (106); Sending queries (107) for subsequent cache lines by subsequent processing units; and The step of comparing the address of the subsequent cache line to all tags of the snoop filter for a match is repeated (108).

7. The method (100) according to claim 6, wherein: For the area saving mode, while searching the conflict buffer (20) for snoop ID miss results, the snoop state machine (30) sends a snoop request to other processing units to snoop any processing unit containing the same cache line.

8. The method (100) according to claim 6 or 7, further comprising: When the processing unit requests a duplicate cache line, a snoop filter (10) having a tag matching the cache line address is hit, enabling the corresponding processing unit to send a snoop request.

9. The method (100) according to claim 6 or 7, wherein: The method further comprises the following steps: When the in-progress bits of the entry of the conflict buffer (20) are all 1, delaying a snoop request to other processing units, wherein the snoop query address is equal to the snoop ID of the entry of the conflict buffer; updating an entry of a snoop filter (10) with information of the processing unit and its ownership of the cache line; clearing one of the in-progress bits to 0; Retry the snoop request for the new cache line; updating the same entry of the snoop filter (10) with information of a subsequent processing unit and a subsequent cache line; and Clear the in progress bits to all 0s.

10. The method (100) according to claim 9, wherein: When the in progress bits are all zero, entries of the collision buffer (20) are free to track other entries of the snoop filter (10).

11. The method (100) according to claim 6, wherein: For the high performance mode, the method further includes updating a processing unit that has exclusive ownership of the corresponding cache line.

12. The method (100) according to claim 11, wherein: When the snoop filter (10) of the used entry receives a miss result of a new cache line, a snoop invalidation request is executed to the processing unit to release the exclusive ownership of the corresponding cache line and update the exclusive ownership of the new cache line.

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