An on-chip bus system and data receiving method and apparatus

Abstract

The application provides an on-chip bus system and a data receiving method and device. The on-chip bus system comprises a host end, a slave end and a DBUS bus. The host end and the slave end are connected through the DBUS bus. The host end is used for sending M write data signals to the slave end through the DBUS bus. M is determined based on the data length of target effective data to be transmitted and the bit width of the DBUS bus. The M write data signals comprise the target effective data. The slave end is used for receiving the M write data signals and obtaining the target effective data based on the M write data signals. All data in the first M-1 write data signals is target effective data, and all data or part of data in the Mth write data signal is target effective data. Through the technical scheme, the number of signal lines of the DBUS bus is small, and the hardware cost of the DBUS bus is small.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication, and in particular to an on-chip bus system and a data receiving method and device. BACKGROUND

[0002] An on-chip bus is a group of buses for internal communication of a chip, such as an AXI (Advanced eXtensible Interface) bus and the like. The on-chip bus can be composed of three types of address bus, data bus and control bus, and can realize functions such as address signal transmission, data exchange and operation control. When transmission is performed between a master and a slave based on the on-chip bus, five parts such as a read command, a write command, write data, a write response and read data (read response) are usually involved. The on-chip bus has a large number of signal lines, and the protocol control timing is complex. The hardware overhead of the on-chip bus is large, and the on-chip bus is not suitable for applications with high bandwidth, low power consumption and small area. SUMMARY

[0003] The present application provides an on-chip bus system, which comprises a master, a slave and a DBUS bus, wherein the master and the slave are connected through the DBUS bus.

[0004] The master is configured to send M write data signals to the slave through the DBUS bus, wherein M is determined based on a data length of target effective data to be transmitted and a bit width of the DBUS bus, and wherein the M write data signals comprise the target effective data.

[0005] The slave is configured to receive the M write data signals and obtain the target effective data based on the M write data signals, wherein all data in the first M-1 write data signals is target effective data, and all data or part of the data in the Mth write data signal is target effective data.

[0006] The present application provides a data receiving method of a slave, which comprises the following steps:

[0007] Receiving M write data signals through a DBUS bus, wherein M is determined based on a data length of target effective data to be transmitted and a bit width of the DBUS bus, and wherein the M write data signals comprise the target effective data.

[0008] Obtaining the target effective data based on the M write data signals, wherein all data in the first M-1 write data signals is target effective data, and all data or part of the data in the Mth write data signal is target effective data.

[0009] The present application provides a data receiving device of a slave, which comprises the following steps:

[0010] The receiving module is configured to receive M write data signals through the DBUS bus; wherein M is determined based on a data length of target valid data to be transmitted and a bit width of the DBUS bus; wherein the M write data signals include the target valid data.

[0011] The determining module is configured to acquire target valid data based on the M write data signals; wherein all data in the first M-1 write data signals is target valid data, and all data or part of data in the Mth write data signal is target valid data.

[0012] As can be seen from the above technical solutions, in the embodiments of the present application, a novel on-chip bus, referred to as a DBUS bus (i.e., an on-chip data bus), is designed. The host end and the slave end are connected through the DBUS bus. When transmission is performed between the host end and the slave end based on the DBUS bus, the DBUS bus has fewer signal lines, simple protocol control timing, and smaller hardware overhead, and is suitable for applications with high bandwidth, low power consumption, and small area, i.e., the DBUS bus has the advantages of high bandwidth, low latency, low power consumption, and small area. In system integration, the bus protocol of the DBUS bus is simple and easy to integrate, and is less likely to be erroneous.

[0013] The DBUS bus reduces the mask flag signal (MASK), i.e., the DBUS bus does not need to provide the mask flag signal. Even if the mask flag signal is not provided, the mask function can still be implemented. In this way, the mask flag signal can be saved, so that the DBUS bus has fewer signal lines, simple protocol control timing, and smaller hardware overhead. In the process of implementing the mask function without providing the mask flag signal, the target valid data can be found from all data (such as valid data and invalid data). For example, when the host end transmits M write data signals and the slave end receives the M write data signals, the slave end regards all data in the first M-1 write data signals as valid data, and regards all data or part of data in the Mth write data signal as valid data. In this way, the slave end can find the target valid data. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a structure schematic diagram of an on-chip bus system in an embodiment of the present application;

[0015] Figure 2 FIG. 2 is a structure schematic diagram of an on-chip bus system in an embodiment of the present application;

[0016] Figure 3A FIG. 3 is a write timing schematic diagram of a DBUS bus in an embodiment of the present application;

[0017] Figure 3Bis a flowchart of a data writing method in an embodiment of the present application;

[0018] Figure 3C is a write transmission schematic diagram of a DBUS bus in an embodiment of the present application;

[0019] Figure 4A is a read timing schematic diagram of a DBUS bus in an embodiment of the present application;

[0020] Figure 4B is a flowchart of a data reading method in an embodiment of the present application;

[0021] Figure 4C is a read transmission schematic diagram of a DBUS bus in an embodiment of the present application;

[0022] Figure 5 is a structure schematic diagram of an on-chip bus system in an embodiment of the present application;

[0023] Figure 6 is a flowchart of a slave-end data receiving method in an embodiment of the present application;

[0024] Figure 7 is a structure schematic diagram of a slave-end data receiving device in an embodiment of the present application. DETAILED DESCRIPTION

[0025] An on-chip bus system is provided in the embodiments of the present application, referring to Figure 1 The structure schematic diagram of the on-chip bus system can include: a host end, a slave end and a DBUS (i.e. on-chip data bus) bus. The host end and the slave end are connected through the DBUS bus. The host end is configured to send M write data signals to the slave end through the DBUS bus; wherein M is determined based on the data length of target valid data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals include the target valid data; the slave end is configured to receive the M write data signals and obtain the target valid data based on the M write data signals; wherein all data in the first M-1 write data signals is the target valid data, and all data or part of data in the Mth write data signal is the target valid data. Based on this, the slave end can take all data in the first M-1 write data signals as the target valid data, and the slave end can take all data or part of data in the Mth write data signal as the target valid data.

[0026] The M is an integer, and the target effective data is all or part of the Mth write data signal. The target effective data can include: if the data length of the target effective data is divisible by the bit width of the DBUS bus, then all data in the Mth write data signal can be the target effective data; or if the data length of the target effective data is not divisible by the bit width of the DBUS bus, then N units of data in the Mth write data signal can be the target effective data. The target effective data occupies N units (such as N bytes) of high bits of the Mth write data signal, or the target effective data can occupy N units (such as N bytes) of low bits of the Mth write data signal.

[0027] The M is an integer, and the target effective data is all or part of the Mth write data signal. The target effective data can include: if the data length of the target effective data is divisible by the bit width of the DBUS bus, then all data in the Mth write data signal can be the target effective data; or if the data length of the target effective data is not divisible by the bit width of the DBUS bus, then N units of data in the Mth write data signal can be the target effective data. The target effective data occupies N units (such as N bytes) of high bits of the Mth write data signal, or the target effective data can occupy N units (such as N bytes) of low bits of the Mth write data signal.

[0028] The M is an integer, and the target effective data is all or part of the Mth write data signal. The target effective data can include: if the data length of the target effective data is divisible by the bit width of the DBUS bus, then all data in the Mth write data signal can be the target effective data; or if the data length of the target effective data is not divisible by the bit width of the DBUS bus, then N units of data in the Mth write data signal can be the target effective data. The target effective data occupies N units (such as N bytes) of high bits of the Mth write data signal, or the target effective data can occupy N units (such as N bytes) of low bits of the Mth write data signal.

[0029] Exemplarily, the slave end is further configured to acquire a data length of the configured target valid data; wherein, if the target valid data comprises one row of image data of the image to be transmitted, the data length is a length corresponding to the one row of image data; if the target valid data comprises multiple rows of image data of the image to be transmitted, the data length is a length corresponding to the multiple rows of image data; if the target valid data comprises all image data of the image to be transmitted, the data length is a length corresponding to the image to be transmitted; or, the slave end is further configured to receive a length signal sent by the host end through the DBUS bus, and determine the data length of the target valid data based on the length signal; wherein, the length signal can represent the data length of the target valid data.

[0030] Exemplarily, the slave end is configured to send a write preparation signal to the host end through the DBUS bus, the write preparation signal can represent that the slave end allows to receive a write data signal or does not allow to receive the write data signal; the host end is configured to send a write valid signal to the slave end through the DBUS bus, the write valid signal can represent that the host end allows to send the write data signal or does not allow to send the write data signal. The host end is configured to send M write data signals to the slave end through the DBUS bus when the write preparation signal represents that the slave end allows to receive the write data signal and the write valid signal represents that the host end allows to send the write data signal.

[0031] Exemplarily, the host end is configured to send a read preparation signal to the slave end through the DBUS bus, the read preparation signal represents that the host end allows to receive a read data signal or does not allow to receive the read data signal; the slave end is configured to send a read valid signal to the host end through the DBUS bus, the read valid signal represents that the slave end allows to send the read data signal or does not allow to send the read data signal; the host end is configured to receive the read data signal sent by the slave end through the DBUS bus when the read preparation signal represents that the host end allows to receive the read data signal and the read valid signal represents that the slave end allows to send the read data signal, the read data signal comprises valid data to be read.

[0032] Exemplarily, the host end is configured to send a read-write flag signal, a length signal and a start address signal to the slave end through the DBUS bus; wherein, the read-write flag signal represents that a write data signal or a read data signal is transmitted through the DBUS bus; if the read-write flag signal represents that the write data signal is transmitted through the DBUS bus, the length signal represents a length of target valid data, and the start address signal represents a start address of the target valid data; if the read-write flag signal represents that the read data signal is transmitted through the DBUS bus, the length signal represents a length of valid data to be read, and the start address signal represents a start address of the valid data to be read.

[0033] For example, the host end is configured to send a request signal to the slave end through the DBUS bus, and stop sending the request signal to the slave end through the DBUS bus until a response signal returned by the slave end is received; and the slave end is configured to send a response signal to the host end through the DBUS bus when the request signal is received through the DBUS bus, and send the response signal to the host end through the DBUS bus if the slave end is in an idle state.

[0034] For example, as shown in Figure 2 The in-chip bus system can further include an arbiter, the host end is connected with the arbiter through the DBUS bus, and the arbiter is connected with the slave end through the DBUS bus. Based on this, the host end is configured to send M write data signals to the arbiter through the DBUS bus; and the arbiter is configured to send the M write data signals to the slave end through the DBUS bus.

[0035] For example, the slave end is configured to send a write preparation signal to the arbiter through the DBUS bus; the arbiter is configured to send the write preparation signal to the host end through the DBUS bus; the host end is configured to send a write valid signal to the arbiter through the DBUS bus; the arbiter is configured to send the write valid signal to the slave end through the DBUS bus; the host end is configured to send the M write data signals to the arbiter through the DBUS bus when the write preparation signal indicates that the slave end allows to receive the write data signals and the write valid signal indicates that the host end allows to send the write data signals; and the arbiter is configured to send the M write data signals to the slave end through the DBUS bus.

[0036] Alternatively, the host end is configured to send a read preparation signal to the arbiter through the DBUS bus; the arbiter is configured to send the read preparation signal to the slave end through the DBUS bus; the slave end is configured to send a read valid signal to the arbiter through the DBUS bus; the arbiter is configured to send the read valid signal to the host end through the DBUS bus; the slave end is configured to send a read data signal to the arbiter through the DBUS bus when the read preparation signal indicates that the host end allows to receive the read data signal and the read valid signal indicates that the slave end allows to send the read data signal; and the arbiter is configured to send the read data signal to the host end through the DBUS bus.

[0037] For example, when the target valid data is image data, the target valid data can include one row of image data of an image to be transmitted, or the target valid data can include multiple rows of image data of the image to be transmitted, or the target valid data can include all image data of the image to be transmitted.

[0038] From the above technical solutions, in the embodiment of the application, a new type of on-chip bus is designed, which is called DBUS bus (i.e. on-chip data bus). The host end and the slave end are connected through the DBUS bus. When transmission is performed between the host end and the slave end based on the DBUS bus, the signal lines of the DBUS bus are less, the protocol control timing is simple, the hardware overhead of the DBUS bus is small, and the DBUS bus is suitable for high-bandwidth, low-power, and small-area applications. That is, the DBUS bus has the advantages of high bandwidth, low latency, low power consumption, and small area. In system integration, the bus protocol of the DBUS bus is simple and easy to integrate, and is not prone to errors.

[0039] The DBUS bus reduces the mask flag signal (MASK). That is, the DBUS bus does not need to provide the mask flag signal. Even if the mask flag signal is not provided, the mask function can be realized. In this way, the mask flag signal can be saved, the signal lines of the DBUS bus are less, the protocol control timing is simple, and the hardware overhead is small. In the process of realizing the mask function without providing the mask flag signal, the target valid data can be found from all data (such as valid data and invalid data). For example, when the host end transmits M write data signals and the slave end receives M write data signals, the slave end regards all data in the first M-1 write data signals as valid data, and the slave end regards all data or part of the data in the Mth write data signal as valid data. In this way, the slave end can find the target valid data.

[0040] The above technical solutions of the embodiment of the application are described below in combination with specific application scenarios.

[0041] The on-chip bus is a group of buses for internal communication of a chip, such as AXI bus, AHB (Advanced High-performance Bus), APB (Advanced Peripheral Bus), and the like. The AHB and the APB are not suitable for a large-throughput data transmission scenario. The AXI bus is a relatively mainstream high-speed bus protocol. When transmission is performed between the host end and the slave end based on the AXI bus, five parts such as read command, write command, write data, write response, and read data (read response) are usually involved. The signal lines of the AXI bus are very many, the protocol control timing is complex, and the hardware overhead of the AXI bus is large, which is not suitable for high-bandwidth, low-power, and small-area applications.

[0042] In view of the above finding, a new type of on-chip bus is designed in the embodiment of the application, which is called DBUS bus (i.e. on-chip data bus). The host end and the slave end are connected through the DBUS bus.

[0043] The DBUS bus is suitable for an application scenario of continuous data, that is, all data is valid data without invalid data. For example, in an image processing scenario (such as an infrared image processing scenario), the host end needs to send image data to the slave end, all image data is valid data, that is, there is no invalid data in the image data (invalid data means that some bytes are invalid, such as a CPU instruction or data taking scenario). For another example, in a data packet transmission scenario, the host end needs to send network data packets to the slave end, all data of the network data packet is valid data, that is, there is no invalid data in the network data packet. Of course, the above is only an example, and is not limited thereto, as long as all data is valid data.

[0044] In this embodiment, the host end can be a CPU (Central Processing Unit), and the slave end can be a DRAM (Dynamic Random Access Memory). The host end can be a CPU, and the slave end can be a DMA (Direct Memory Access) controller. The host end can be a CPU, and the slave end can be a Flash memory. Of course, the above is only a few examples, and the host end and the slave end are not limited thereto, as long as the host end and the slave end are located in the chip.

[0045] In this embodiment, the DBUS bus is between the host end and the slave end, and the host end and the slave end can be connected through the DBUS bus. Referring to Table 1, an example of a write operation signal of the DBUS bus is shown, and referring to Table 2, an example of a read operation signal of the DBUS bus is shown. In the subsequent process, the write operation and the read operation can be independently performed, such as only the write operation, only the read operation, or the write operation and the read operation at the same time, that is, the write operation and the read operation can be executed in parallel.

[0046] Table 1

[0047]

[0048] Table 2

[0049]

[0050] In Table 1 and Table 2, dbus_addr (start address signal), dbus_lens (length signal) and dbus_wren (read-write flag signal) can be instruction information, so that the instruction information can include start address information, data length information (which can be in bytes or bits) and read-write flag information, and the read-write flag information can indicate that write data signals or read data signals are transmitted through the DBUS bus. For example, if dbus_wren is a first level, it indicates that write data information is transmitted through the DBUS bus, and if dbus_wren is a second level, it indicates that read data information is transmitted through the DBUS bus. The first level can be a high level, and the second level can be a low level, or the first level can be a low level, and the second level can be a high level.

[0051] dbus_wrdy (write preparation signal), dbus_wvld (write valid signal) and dbus_wdata (write data signal) can be write data information, and if dbus_wren is a first level, these write data information is transmitted through the DBUS bus. dbus_wrdy and dbus_wvld indicate handshake signals of write data, and dbus_wdata can indicate write data, i.e. data that needs to be written. It should be noted that the mask signal of the write data is not involved in the write data information, i.e. the DBUS bus saves a mask flag signal line of multiple bit widths.

[0052] dbus_rrdy (read preparation signal), dbus_rvld (read valid signal) and dbus_rdata (read data signal) can be read data information, and if dbus_wren is a second level, these read data information can be transmitted through the DBUS bus. In the read data information, dbus_rrdy and dbus_rvld can indicate handshake signals of read data, and dbus_rdata can indicate read data, i.e. data that needs to be read.

[0053] In summary, the DBUS bus is divided into three parts of instruction information, write data information and read data information. Thus, compared with the AXI bus, the AXI bus involves five parts of read command, write command, write data, write response and read data (read response), the DBUS bus has fewer signal lines, the protocol control timing is simple, the hardware overhead of the DBUS bus is small, and the bus protocol of the DBUS bus is simple and easy to integrate.

[0054] Referring to Table 1 and Table 2, before transmitting the write data information and the read data information, the host end can also send a dbus_req (request signal) to the slave end, and after receiving the dbus_req, the slave end can also send a dbus_ack (response signal) to the host end. The handshake through the dbus_req and the dbus_ack guarantees the transmission of the write data information and the read data information. For example, the host end will not send the write data information to the slave end until receiving the dbus_ack, or the host end will not send the read data information to the slave end until receiving the dbus_ack. Conversely, the host end will not send the write data information to the slave end before receiving the dbus_ack, or the host end will not send the read data information to the slave end before receiving the dbus_ack.

[0055] The DBUS bus adopts the handshake through the dbus_req and the dbus_ack, and the handshake process is not prone to errors. In the handshake process, the host end initiates the dbus_req actively, and the host end does not need to consider the current state of the slave end when initiating the dbus_req. The slave end only needs to make a reasonable response according to the dbus_req.

[0056] For the data write process, referring to Figure 3A , which is a write timing diagram of the DBUS bus. In combination with the write timing of the DBUS bus, the embodiment of the application proposes a data write method based on the DBUS bus, referring to Figure 3B , which is a flow diagram of the data write method. The method can include the following steps.

[0057] Step 301, the host end sends a request signal (dbus_req) to the slave end through the DBUS bus.

[0058] Step 302, when the slave end receives the request signal through the DBUS bus, if the slave end is in an idle state, the slave end sends a response signal (dbus_ack) to the host end through the DBUS bus.

[0059] For example, before the host end writes data to the slave end, the host end can send a request signal to the slave end through the DBUS bus until the host end receives a response signal returned by the slave end, and then the host end stops sending the request signal to the slave end through the DBUS bus. Before receiving the response signal returned by the slave end, the host end continues to send the request signal to the slave end through the DBUS bus. Referring to Figure 3AAs an example, the request signal is high active (the request signal can also be low active), the host end continuously sends the request signal (dbus_req is high) from time 4 to time 7, and the host end receives the response signal (the response signal is a pulse signal, dbus_ack is high from time 7 to time 8) returned by the slave end. Thus, the host end stops sending the request signal (dbus_req is low) from time 8.

[0060] As an example, the response signal is high active (the response signal can also be low active), the slave end sends the response signal (dbus_ack is high) from time 7, and the response signal can be a pulse signal, that is, only lasts one time, that is, the response signal corresponds to time 7 to time 8. The response signal can also last for multiple times, which is not limited. The slave end stops sending the response signal (dbus_ack is low) from time 8.

[0061] When the slave end receives the request signal through the DBUS bus, if the slave end is in a busy state, the slave end will not send the response signal to the host end through the DBUS bus until the slave end is in an idle state. For example, the idle state of the slave end means that the slave end currently has no task to process and can process the current write task to realize data writing. The busy state of the slave end means that the slave end currently processes a task and cannot process the current write task.

[0062] As an example, the bit width of the request signal can be 1 bit or multiple bits, or 1 byte or multiple bytes, and the bit width of the request signal is not limited. The bit width of the response signal can be 1 bit or multiple bits, or 1 byte or multiple bytes, and the bit width of the response signal is not limited.

[0063] Step 303, the host end sends the read-write flag signal (dbus_wren) to the slave end through the DBUS bus.

[0064] As an example, the read-write flag signal indicates that the write data signal or the read data signal is transmitted through the DBUS bus. For example, for the write data process, the read-write flag signal indicates that the write data signal is transmitted through the DBUS bus, and for the read data process, the read-write flag signal indicates that the read data signal is transmitted through the DBUS bus.

[0065] For example, if the read-write flag signal is at the first level, it can indicate that the write data signal is transmitted through the DBUS bus, and if the read-write flag signal is at the second level, it can indicate that the read data signal is transmitted through the DBUS bus. The first level can be a high level, and the second level can be a low level, or the first level can be a low level, and the second level can be a high level. In this embodiment, it is for the data writing process, so the read-write flag signal is at the first level, and in Figure 3A For example, if the read-write flag signal is at the first level, it can indicate that the write data signal is transmitted through the DBUS bus, and if the read-write flag signal is at the second level, it can indicate that the read data signal is transmitted through the DBUS bus. The first level can be a high level, and the second level can be a low level, or the first level can be a low level, and the second level can be a high level. In this embodiment, it is for the data writing process, so the read-write flag signal is at the first level, and in

[0066] For example, after the host sends the request signal to the slave through the DBUS bus, the host can send the read-write flag signal to the slave through the DBUS bus, i.e., the read-write flag signal is at the low level from time 4. Of course, the host can also send the read-write flag signal to the slave through the DBUS bus after receiving the response signal, i.e., the read-write flag signal is at the low level from time 8. In Figure 3A For example, after the host sends the request signal to the slave through the DBUS bus, the host can send the read-write flag signal to the slave through the DBUS bus, i.e., the read-write flag signal is at the low level from time 4. Of course, the host can also send the read-write flag signal to the slave through the DBUS bus after receiving the response signal, i.e., the read-write flag signal is at the low level from time 8. In

[0067] For example, the bit width of the read-write flag signal can be 1 bit or multiple bits, or 1 byte or multiple bytes, and the bit width of the read-write flag signal is not limited in this embodiment.

[0068] Step 304: The host sends a length signal (dbus_lens) to the slave through the DBUS bus.

[0069] For example, if the read-write flag signal indicates that the write data signal is transmitted through the DBUS bus, the length signal can indicate the length of the target valid data, and the content of the target valid data is described in the subsequent embodiments. For example, after the host sends the request signal to the slave through the DBUS bus, the host can send the length signal to the slave through the DBUS bus, i.e., the length signal starts to transmit the length of the target valid data (denoted as burst_lens) from time 4. Of course, the host can also send the length signal to the slave through the DBUS bus after receiving the response signal, i.e., the length signal starts to transmit the length of the target valid data from time 8. In Figure 3A For example, after the host sends the request signal to the slave through the DBUS bus, the host can send the length signal to the slave through the DBUS bus, i.e., the length signal starts to transmit the length of the target valid data (denoted as burst_lens) from time 4. Of course, the host can also send the length signal to the slave through the DBUS bus after receiving the response signal, i.e., the length signal starts to transmit the length of the target valid data from time 8. In

[0070] When the length signal starts to transmit the length of the target effective data from time 4, the length of the target effective data transmitted by the host end cannot be changed before the response signal is received, so as to avoid transmission abnormality. After the response signal is received, the length of the target effective data transmitted by the host end can be retransmitted, that is, the length of the target effective data can be changed. In addition, when the length signal starts to transmit the length of the target effective data from time 8, the length of the target effective data transmitted by the host end can be changed.

[0071] In the transmission of the length of the target effective data, the length of the target effective data can be in byte units, bit units, or other units, which are not limited.

[0072] For example, the bit width of the length signal is related to the length of the target effective data, and the bit width of the length signal can be denoted as LW. The bit width LW is a parameter related to the length of the target effective data, and the length of the target effective data can be indicated by the length signal. The bit width of the length signal is not limited. For example, the bit width of the length signal supports parameterized configuration, that is, the bit width of the length signal can be configured.

[0073] Step 305, the host end sends a start address signal (dbus_addr) to the slave end through the DBUS bus.

[0074] For example, if the read-write flag signal indicates that the write data signal is transmitted through the DBUS bus, the start address signal indicates the start address of the target effective data. For example, after the host end sends a request signal to the slave end through the DBUS bus, the host end can send a start address signal to the slave end through the DBUS bus, that is, the start address signal starts to transmit the start address (denoted as start_addr) of the target effective data from time 4. Of course, the host end can also send a start address signal to the slave end through the DBUS bus after receiving a response signal, that is, the start address signal starts to transmit the start address of the target effective data from time 8. In Figure 3A In the embodiment, the host end starts to transmit the start address of the target effective data from time 4.

[0075] When the start address signal starts to transmit the start address of the target effective data from time 4, the start address of the target effective data transmitted by the host end cannot be changed before the response signal is received, so as to avoid transmission abnormality. After the response signal is received, the host end can retransmit the start address of the target effective data, that is, the start address can be changed. When the start address signal starts to transmit the start address of the target effective data from time 8, the start address of the target effective data transmitted by the host end can be changed.

[0076] For example, the bit width of the start address signal is related to the start address of the target valid data, and the bit width of the start address signal can be denoted as AW. The bit width AW is a parameter related to the start address of the target valid data, and the start address can be indicated by the start address signal. The bit width is not limited. For example, the bit width of the start address signal supports parameterized configuration, that is, the bit width can be configured.

[0077] In step 306, the host sends a write valid signal (dbus_wvld) to the slave through the DBUS bus. The write valid signal can indicate that the host allows to send a write data signal or does not allow to send a write data signal.

[0078] For example, after the host sends a request signal to the slave through the DBUS bus, the host can send a write valid signal to the slave through the DBUS bus. Taking the case that the write valid signal is high-level valid (the write valid signal can also be low-level valid) as an example, the write valid signal is high from time 4 (the write valid signal can be high at any time after time 4). Of course, the host can also send a write valid signal to the slave through the DBUS bus after receiving a response signal, that is, the write valid signal is high from time 8 (the write valid signal can be high at any time after time 8). In this case, the write valid signal is high from time 9 (this time 9 is only an example), so that the write valid signal can indicate that the host allows to send a write data signal from time 9. Before time 9, the write valid signal can indicate that the host does not allow to send a write data signal. Figure 3A

[0079] For example, the bit width of the write valid signal can be 1 bit or multiple bits, or 1 byte or multiple bytes. The bit width of the write valid signal is not limited in this embodiment.

[0080] In step 307, the slave sends a write ready signal (dbus_wrdy) to the host through the DBUS bus. The write ready signal can indicate that the slave allows to receive a write data signal or does not allow to receive a write data signal.

[0081] For example, after the slave receives a request signal through the DBUS bus, the slave can send a write ready signal to the host through the DBUS bus. Taking the case that the write ready signal is high-level valid (the write ready signal can also be low-level valid) as an example, the write ready signal is high from time 4 (the write ready signal can be high at any time after time 4). The slave can send a write ready signal to the host through the DBUS bus after sending a response signal to the host, that is, the write ready signal is high from time 8 (the write ready signal can be high at any time after time 8). In this case, the write ready signal is high from time 9 (this time 9 is only an example), so that the write ready signal can indicate that the slave allows to receive a write data signal from time 9. Before time 9, the write ready signal can indicate that the slave does not allow to receive a write data signal. Figure 3A ​In the embodiment, the write preparation signal is always high, i.e., the write preparation signal indicates that the slave end always allows to receive the write data signal.

[0082] For example, the bit width of the write preparation signal can be 1 bit or multiple bits, or 1 byte or multiple bytes, and the bit width of the write preparation signal is not limited in the embodiment.

[0083] When the write preparation signal indicates that the slave end allows to receive the write data signal, and the write valid signal indicates that the host end allows to send the write data signal, the host end sends the write data signal (dbus_wdata) to the slave end through the DBUS bus, and the write data signal can include the target valid data.

[0084] For example, the host end does not send the write data signal to the slave end through the DBUS bus before receiving the response signal (dbus_ack). After receiving the response signal, the host end can send the write data signal to the slave end through the DBUS bus, i.e., the response signal indicates that the write data signal is allowed to be sent.

[0085] After receiving the response signal, the host end can query the write preparation signal and the write valid signal. If the write preparation signal indicates that the slave end allows to receive the write data signal (e.g., the write preparation signal is high), and the write valid signal indicates that the host end allows to send the write data signal (e.g., the write valid signal is high), the host end sends the write data signal to the slave end through the DBUS bus. If the write preparation signal indicates that the slave end does not allow to receive the write data signal, and / or the write valid signal indicates that the host end does not allow to send the write data signal, the host end does not send the write data signal to the slave end through the DBUS bus, until the write preparation signal indicates that the slave end allows to receive the write data signal, and the write valid signal indicates that the host end allows to send the write data signal.

[0086] Referring to FIG. 3, Figure 3A The write preparation signal is always high, i.e., the write preparation signal indicates that the slave end always allows to receive the write data signal, and the write valid signal is high from time 9, i.e., the write valid signal indicates that the host end allows to send the write data signal from time 9. On this basis, the host end sends the write data signal to the slave end through the DBUS bus from time 9 (or a certain time after time 9).

[0087] For example, the bit width of the write data signal is related to the actual length of the target valid data, and the bit width of the write data signal can be denoted as DW. The bit width DW is a parameter related to the actual length of the target valid data, and the target valid data can be carried through the write data signal. The bit width DW is not limited. For example, the bit width of the write data signal supports parameterized configuration, i.e., the bit width can be configured.

[0088] In a possible implementation, the effective data to be transmitted is referred to as target effective data, and the target effective data is continuous data, that is, all data contents in the target effective data are effective data. For example, in an image processing scenario (for example, an infrared image processing scenario), the host end needs to send image data to the slave end, all the image data are effective data, and the target effective data can include the image data. For another example, in a data packet transmission scenario, the host end needs to send a network data packet to the slave end, all data of the network data packet are effective data, and the target effective data can include the network data packet.

[0089] Taking the target effective data as image data as an example, the target effective data can include one row of image data of the image to be transmitted. For example, the host end obtains the first row of image data of the image to be transmitted, and sends a write data signal including the first row of image data to the slave end through the DBUS bus. Then, the host end obtains the second row of image data of the image to be transmitted, and sends a write data signal including the second row of image data to the slave end through the DBUS bus. In this way, the host end sends all rows of image data of the image to be transmitted to the slave end through the DBUS bus, and completes the transmission of the image to be transmitted.

[0090] Alternatively, the target effective data can include multiple rows of image data of the image to be transmitted. For example, taking five rows of image data as an example, the host end obtains the first to fifth rows of image data of the image to be transmitted, and sends a write data signal including the first to fifth rows of image data to the slave end through the DBUS bus. Then, the host end obtains the sixth to tenth rows of image data of the image to be transmitted, and sends a write data signal including the sixth to tenth rows of image data to the slave end through the DBUS bus. In this way, the host end sends all rows of image data of the image to be transmitted to the slave end through the DBUS bus, and completes the transmission of the image to be transmitted.

[0091] Alternatively, the target effective data can include all image data of the image to be transmitted. For example, the host end obtains all rows of image data of the image to be transmitted, and sends a write data signal including all rows of image data of the image to be transmitted to the slave end through the DBUS bus.

[0092] For ease of description, it is assumed that the target effective data includes one row of image data of the image to be transmitted.

[0093] It should be noted that when the host end sends the write data signal to the slave end, the actual transmission data will completely include the target valid data, but the length of the actual transmission data is related to the bit width of the write data signal and needs to be an integer multiple of the bit width of the write data signal. Based on this, if the length of the target valid data is exactly an integer multiple of the bit width of the write data signal, the actual transmission data only includes the target valid data, and if the length of the target valid data is not an integer multiple of the bit width of the write data signal, the actual transmission data includes the target valid data and part of the invalid data, and the length of the actual transmission data is an integer multiple of the bit width of the write data signal.

[0094] On this basis, the number of cycles M can be determined based on the data length of the target valid data and the bit width of the DBUS bus, indicating that the host end needs to send the target valid data through M clock cycles, and in each clock cycle, one bit width (the bit width of the DBUS bus) of data can be sent. Through M clock cycles, M bit width of data (M bit width of data represents actual transmission data, that is, the length of the actual transmission data is M times the bit width of the write data signal, if the length of the target valid data is exactly M bit width, the actual transmission data only includes the target valid data, if the length of the target valid data is not M bit width, the actual transmission data includes the target valid data and part of the invalid data). Wherein, M is the integer obtained by rounding up the quotient of the data length of the target valid data and the bit width of the DBUS bus, and M can be a positive integer.

[0095] For example, in the field of image processing, image data can be transmitted by row, so that by splitting by row granularity, the image data of a row of the image to be transmitted can be obtained as the target valid data. Assuming that the data length of the target valid data is 30 bytes (30 Byte), that is, the length signal (dbus_lens) represents 30 bytes, and the bit width of the DBUS bus is set to 32 bits (that is, 4 bytes), then the quotient (30 / 4) of the data length of the target valid data and the bit width of the DBUS bus is rounded up to obtain the number of cycles M as 8, that is, the host end sends 8 bit width of data through 8 clock cycles.

[0096] For example, when the host end sends the write data signal to the slave end through the DBUS bus, M write data signals can be sent to the slave end through the DBUS bus, and then the target valid data is carried through the M write data signals. For example, in 8 clock cycles, the host end sends 8 write data signals to the slave end. For the M write data signals, all the data in the first M-1 write data signals are valid data, and all or part of the data in the Mth write data signal is valid data.

[0097] For example, in the first clock cycle, the host sends a write data signal 1 to the slave through the DBUS bus, and all data in the write data signal 1 is valid data. For example, the target valid data includes 30 bytes of image data, and the write data signal 1 includes the first to fourth bytes of image data. In the second clock cycle, the host sends a write data signal 2 to the slave through the DBUS bus, and all data in the write data signal 2 is valid data. For example, the write data signal 2 includes the fifth to eighth bytes of image data. In the same manner, in the seventh clock cycle, the host sends a write data signal 7 to the slave through the DBUS bus, and all data in the write data signal 7 is valid data. For example, the write data signal 7 includes the twenty-fifth to twenty-eighth bytes of image data. In summary, all data in the preceding seven write data signals is valid data.

[0098] For example, for the Mth write data signal, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all data in the Mth write data signal is valid data. If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, N units (e.g., N bytes) of data in the Mth write data signal are valid data, and the remaining data is invalid data.

[0099] For example, in the field of image processing, image data can be transmitted by row. Therefore, when splitting by row granularity, there are only two possibilities for the total data amount of a row (the data length of the target valid data) in the transmission process, one is that the total data amount of a row is exactly divisible by the bit width of the DBUS bus, and the other is that the total data amount of a row cannot be divided by the bit width of the DBUS bus. These two cases only occur on the last DBUS data in the current transmission, and the remaining DBUS data is all valid data. Based on this, all data in the preceding M-1 write data signals is valid data, and all data or part of the data in the Mth write data signal is valid data.

[0100] For example, in the eighth clock cycle, the host sends a write data signal 8 to the slave through the DBUS bus. If the target valid data includes 32 bytes of image data, all data in the write data signal 8 is valid data, such as the write data signal 8 including the twenty-ninth to thirty-second bytes of image data. In this example, the target valid data includes 30 bytes of image data, and therefore, part of the data in the write data signal 8 is valid data, and the write data signal 8 includes the twenty-ninth to thirtieth bytes of image data. Considering that the write data signal 8 needs to carry 4 bytes of data, the remaining two bytes are filled with invalid data.

[0101] As described above, the data length of the target valid data 30 is divided by the bit width 4 of the DBUS bus, and the remainder is 2. Therefore, the N (2) bytes of data in the write data signal 8 are valid data, and the remaining 2 bytes (the difference between the bit width of the DBUS bus and the N bytes) are invalid data. In the write data signal 8, the target valid data can occupy the low N (2) bytes, and the invalid data can occupy the high 2 bytes, or the target valid data can occupy the high 2 bytes, and the invalid data can occupy the low 2 bytes. In this embodiment, the target valid data occupying the low 2 bytes is taken as an example for description.

[0102] As described above, the host can send M write data signals to the slave through the DBUS bus, and carry the target valid data through the M write data signals. All the data in the first M-1 write data signals are valid data, and all or part of the data in the Mth write data signal is valid data.

[0103] In step 309, the slave receives the M write data signals through the DBUS bus, and obtains the target valid data based on the M write data signals. All the data in the first M-1 write data signals are valid data, and all or part of the data in the Mth write data signal is valid data.

[0104] For example, the slave does not receive the write data signal through the DBUS bus before sending the response signal to the host, and can receive the write data signal through the DBUS bus after sending the response signal to the host. For example, the slave queries the write preparation signal and the write valid signal. If the write preparation signal indicates that the slave is allowed to receive the write data signal, and the write valid signal indicates that the host is allowed to send the write data signal, the slave receives the write data signal through the DBUS bus. If the write preparation signal indicates that the slave is not allowed to receive the write data signal, and / or the write valid signal indicates that the host is not allowed to send the write data signal, the slave does not receive the write data signal through the DBUS bus until the write preparation signal indicates that the slave is allowed to receive the write data signal, and the write valid signal indicates that the host is allowed to send the write data signal.

[0105] Exemplarily, when the slave end receives the length signal through the DBUS bus, the data length of the target valid data can be determined based on the length signal, and the bit width of the DBUS bus is known by the slave end, so that the slave end can determine the number of cycles M based on the data length of the target valid data and the bit width of the DBUS bus. Alternatively, the slave end can obtain the data length of the target valid data configured, that is, the data length of the target valid data is obtained based on the configuration information, so that the length signal does not need to be transmitted through the DBUS bus, thereby saving the length signal and further reducing the number of signal lines of the DBUS bus. When configuring the data length of the target valid data, taking the to-be-transmitted image as an example, if the target valid data includes one row of image data of the to-be-transmitted image, the data length is the length corresponding to one row of image data; if the target valid data includes multiple rows of image data of the to-be-transmitted image, the data length is the length corresponding to the multiple rows of image data; and if the target valid data includes all image data of the to-be-transmitted image, the data length is the length corresponding to the to-be-transmitted image.

[0106] Based on this, after obtaining the number of cycles M, for the first write data signal received by the slave end, all data (such as 4 bytes) in the write data signal are regarded as target valid data. For the second write data signal received by the slave end, all data in the write data signal are regarded as target valid data. Similarly, for the (M-1)th write data signal received by the slave end, all data in the write data signal are regarded as target valid data. As can be seen from the above, all data in the first M-1 write data signals are valid data.

[0107] Exemplarily, the slave end can also calculate the remainder of the data length of the target valid data divided by the bit width of the DBUS bus, if the remainder is 0, for the Mth write data signal received by the slave end, all data in the write data signal are regarded as target valid data. If the remainder is not 0, such as N, for the Mth write data signal received by the slave end, N bytes of data in the write data signal are regarded as target valid data. For example, N bytes of data in the low bit of the write data signal are regarded as target valid data, or N bytes of data in the high bit of the write data signal are regarded as target valid data. Whether N bytes of data in the low bit or N bytes of data in the high bit are regarded as target valid data can be configured at the master end and the slave end. As can be seen from the above, all data or part of the data in the Mth write data signal are valid data.

[0108] In a possible implementation, for the Mth write data signal, the slave can determine the target valid data by generating a mask signal. It should be noted that the mask signal is generated by the slave itself through an algorithm, rather than being sent by the host to the slave. In this way, even if the DBUS bus does not support the mask signal, the slave can itself calculate the mask signal to complete the masking function.

[0109] For example, the slave determines all data in the preceding M-1 write data signals as the target valid data; the slave generates a mask signal corresponding to the Mth write data signal based on the data length of the target valid data and the bit width of the DBUS bus (i.e., the slave itself calculates the mask signal), and determines all data or part of data in the Mth write data signal as the target valid data based on the mask signal.

[0110] For example, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all bits of the mask signal are a first value (e.g., 1), and a first post-operation signal is obtained by performing a masking operation based on the mask signal and the Mth write data signal. Since all bits of the mask signal are the first value, all bits of the first post-operation signal are valid data, and thus all data in the first post-operation signal can be determined as the target valid data. Since all bits of the first post-operation signal are the same as all bits of the Mth write data signal, all data in the Mth write data signal is determined as the target valid data.

[0111] For example, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, all bits of the high N bytes of the mask signal are the first value, and all bits of the remaining bytes are a second value, and a second post-operation signal is obtained by performing a masking operation based on the mask signal and the Mth write data signal.

[0112] Since all bits of the high N bytes of the mask signal are the first value, all bits of the high N bytes of the second post-operation signal are valid data, and thus the high N bytes in the second post-operation signal can be determined as the target valid data. Since all bits of the high N bytes in the second post-operation signal are the same as all bits of the high N bytes of the Mth write data signal, the high N bytes in the Mth write data signal can be determined as the target valid data.

[0113] For example, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, all bits of the low N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value, and a third post-operation signal is obtained by performing a masking operation based on the mask signal and the Mth write data signal.

[0114] Since all bits of the low N bytes of the mask signal are the first value, all bits of the low N bytes of the third operation signal are valid data, so that the low N bytes in the third operation signal can be determined as the target valid data. Since all bits of the low N bytes in the third operation signal are the same as all bits of the low N bytes of the Mth write data signal, the low N bytes in the Mth write data signal can be determined as the target valid data.

[0115] In summary, the target valid data is obtained from the M write data signals at the slave end, the target valid data includes all data in the previous M-1 write data signals, and the target valid data includes all data or part of data in the Mth write data signal. Further, based on the start address of the target valid data transmitted by the start address signal, the slave end can store the target valid data to complete the data writing process.

[0116] In this embodiment, although the DBUS bus does not have a mask flag signal (MASK), the DBUS bus still has a mask function. For example, for the 4 bytes of data transmitted in the Mth (such as the 8th) clock cycle, the slave end calculates the total number of received bytes (such as 8*4=32 bytes, that is, a total of 32 bytes are received in 8 clock cycles) when receiving the Mth write data signal, and compares the total number of received bytes with the data length (dbus_sizes) of the target valid data. If the total number of received bytes is equal to dbus_sizes, the data in the Mth write data signal does not need to be masked, and all data in the Mth write data signal is valid data. If the total number of received bytes is greater than dbus_sizes, it means that the extra number of bytes is invalid data, and the data in the Mth write data signal needs to be masked, such as masking the high 2 bytes in the Mth write data signal, so that correct data transmission can be achieved.

[0117] In summary, in view of the continuity of data in the image processing algorithm, the DBUS bus does not need to provide a mask flag signal (MASK), but calculates the mask flag of the Mth write data signal through internal logic of the bus. The calculation principle is: divide the amount of data in one row of image (the data length of the target valid data) by the bus data bit width, and determine whether the result can be divided by an integer. If it can be divided by an integer, all data in the row is valid, if it cannot be divided by an integer, the mask of the last data is marked as valid and invalid according to the remainder. Since the bus bit width is a multiple of 2, the division can be simply performed by shifting, that is, the remainder of "the data length of the target valid data divided by the bit width of the DBUS bus" can be easily calculated.

[0118] For example, referring to Figure 3CFigure 2 shows a schematic diagram of a DBUS bus write transmission. The host can send address signals (such as a starting address signal) and control command signals (such as read / write flag signals and length signals) to the slave. After the address and control command signals are received by the slave, the host can send multiple write data signals to the slave. These write data signals carry the write data (such as write data D0, write data D1, write data D2, write data D3, write data D4, and write data D5), completing the data write process.

[0119] For the data reading process, see Figure 4A As shown in FIG. 1 , a DBUS bus read timing diagram is shown. In combination with the DBUS bus read timing diagram, a method for reading data based on the DBUS bus is proposed in the embodiment of the present application. Figure 4B FIG. 1 is a flow chart of the data reading method, which may include:

[0120] Step 401: The host sends a request signal (dbus_req) to the slave via the DBUS bus.

[0121] Step 402: When the slave receives the request signal through the DBUS bus, if the slave is in an idle state, the slave sends a response signal (dbus_ack) to the host through the DBUS bus.

[0122] Step 403: The host sends a read / write flag signal (dbus_wren) to the slave via the DBUS bus.

[0123] For example, the read / write flag signal indicates that a write data signal or a read data signal is transmitted via the DBUS bus. For the data reading process, the read / write flag signal indicates that a read data signal is transmitted via the DBUS bus. For example, if the read / write flag signal is at the second level, it indicates that a read data signal is transmitted via the DBUS bus. The second level can be a low level or a high level. Figure 3A In the example, the second level is a high level, that is, the read / write flag signal can be valid at a high level to indicate that the read data signal is transmitted through the DBUS bus.

[0124] For example, after the host sends a request signal to the slave via the DBUS bus, it can then send a read / write flag signal to the slave via the DBUS bus, i.e., the read / write flag signal is high starting at time 4. Of course, the host can also send a read / write flag signal to the slave via the DBUS bus only after receiving a response signal, i.e., the read / write flag signal is high starting at time 8.

[0125] Step 404: The host sends a length signal (dbus_lens) to the slave via the DBUS bus.

[0126] For example, if the read-write flag signal indicates that the read data signal is transmitted through the DBUS bus, the length signal indicates the length of the valid data to be read (denoted as burst_lens in Figure 4A ).

[0127] Step 405, the host sends a start address signal (dbus_addr) to the slave through the DBUS bus.

[0128] For example, if the read-write flag signal indicates that the read data signal is transmitted through the DBUS bus, the start address signal indicates the start address of the valid data to be read (denoted as start_addr in Figure 4A ).

[0129] Step 406, the host sends a read ready signal (dbus_rrdy) to the slave through the DBUS bus, which indicates whether the host allows to receive the read data signal or not.

[0130] For example, after the host sends the request signal to the slave through the DBUS bus, the host can send the read ready signal to the slave through the DBUS bus. For example, the read ready signal is active high (the read ready signal can also be active low), i.e., the read ready signal is high from time 4 (the read ready signal can be high at any time after time 4). Of course, the host can also send the read ready signal to the slave through the DBUS bus after receiving the response signal, i.e., the read ready signal is high from time 8 (the read ready signal can be high at any time after time 8). In Figure 4A , the read ready signal is high from time 11 (this time 11 is only an example), so that the read ready signal can indicate that the host allows to receive the read data signal from time 11.

[0131] For example, the bit width of the read ready signal can be 1 bit or multiple bits, or 1 byte or multiple bytes, and the bit width of the read ready signal is not limited in this embodiment.

[0132] Step 407, the slave sends a read valid signal (dbus_rvld) to the host through the DBUS bus, which indicates whether the slave allows to send the read data signal or not.

[0133] For example, after receiving the request signal through the DBUS bus, the slave end can send the read valid signal to the host end through the DBUS bus, taking the read valid signal being high level valid as an example (the read valid signal can also be low level valid), that is, the read valid signal is high level from time 4 (the read valid signal is high level at any time after time 4). After sending the response signal to the host end, the slave end can send the read valid signal to the host end through the DBUS bus, that is, the read valid signal is high level from time 8 (the read valid signal is high level at any time after time 8). In Figure 4A , the read valid signal is high level from time 11, indicating that the slave end allows sending the read data signal from time 11.

[0134] For example, the bit width of the read valid signal can be 1 bit or multiple bits, or 1 byte or multiple bytes, and the bit width of the read valid signal is not limited in the embodiment.

[0135] When the read preparation signal indicates that the host end allows receiving the read data signal, and the read valid signal indicates that the slave end allows sending the read data signal, the slave end sends the read data signal (dbus_rdata) to the host end through the DBUS bus, and the read data signal can include the valid data to be read.

[0136] For example, the slave end does not send the read data signal to the host end through the DBUS bus before sending the response signal (dbus_ack). After sending the response signal, the slave end can send the read data signal to the host end through the DBUS bus, that is, the response signal indicates that the read data signal is allowed to be sent.

[0137] After sending the response signal, the slave end can query the read preparation signal and the read valid signal. If the read preparation signal indicates that the host end allows receiving the read data signal (for example, the read preparation signal is high level), and the read valid signal indicates that the slave end allows sending the read data signal (for example, the read valid signal is high level), the slave end sends the read data signal to the host end through the DBUS bus. If the read preparation signal indicates that the host end does not allow receiving the read data signal, and / or the read valid signal indicates that the slave end does not allow sending the read data signal, the slave end does not send the read data signal to the host end through the DBUS bus, until the read preparation signal indicates that the host end allows receiving the read data signal, and the read valid signal indicates that the slave end allows sending the read data signal.

[0138] Referring to Figure 4A , the read preparation signal is high level from time 11, and the read valid signal is high level from time 11. On this basis, the slave end can send the read data signal to the host end through the DBUS bus from time 11 (or a certain time after time 11).

[0139] For example, the bit width of the read data signal is related to the actual length of the valid data to be read, and the bit width of the read data signal can be denoted as DW. The bit width DW is a parameter related to the actual length of the valid data to be read, and the valid data to be read can be carried by the read data signal. The bit width DW is not limited. For example, the bit width of the read data signal supports parameterized configuration, that is, the bit width can be configured.

[0140] In a possible implementation, the slave can read data with a data length (burst_lens) from a start address (start_addr) as the valid data to be read, and send the valid data to be read to the host through the read data signal. The data transmission process is not limited. The start address can be obtained based on the start address signal, and the data length can be obtained based on the length signal.

[0141] In step 409, when the read preparation signal indicates that the host allows to receive the read data signal, and the read valid signal indicates that the slave allows to send the read data signal, the host receives the read data signal sent by the slave through the DBUS bus. The read data signal can include the valid data to be read.

[0142] For example, the host does not receive the read data signal through the DBUS bus before receiving the response signal, and the host can receive the read data signal through the DBUS bus after receiving the response signal. For example, the host queries the read preparation signal and the read valid signal. If the read preparation signal indicates that the host allows to receive the read data signal, and the read valid signal indicates that the slave allows to send the read data signal, the host receives the read data signal through the DBUS bus, and then obtains the valid data to be read. If the read preparation signal indicates that the host does not allow to receive the read data signal, and / or the read valid signal indicates that the slave does not allow to send the read data signal, the host does not receive the read data signal through the DBUS bus, until the read preparation signal indicates that the host allows to receive the read data signal, and the read valid signal indicates that the slave allows to send the read data signal.

[0143] For example, as shown in FIG. 8, it is a read transmission diagram of the DBUS bus. The host can send an address signal (such as a start address signal) and a control command signal (such as a read-write flag signal and a length signal) to the slave. After the address signal and the control command signal are received by the slave, the host can wait for the slave to return data. The slave can send a plurality of read data signals to the host, and carry read data (such as read data D0 and read data D1) through the read data signals, so as to complete the read data process. Figure 4C

[0144] ​In a possible implementation, the on-chip bus system can further include an arbiter, the host end is connected with the arbiter through the DBUS bus, and the arbiter is connected with the slave end through the DBUS bus. In this application scenario, it can be understood that the DBUS bus between the host end and the slave end is relayed through the arbiter.

[0145] For the data write process, the host end can send a request signal (dbus_req) to the arbiter through the DBUS bus, and the arbiter can send the request signal (dbus_req) to the slave end through the DBUS bus.

[0146] When the slave end receives the request signal through the DBUS bus, if the slave end is in an idle state, the slave end can send a response signal (dbus_ack) to the arbiter through the DBUS bus, and the arbiter can send the response signal (dbus_ack) to the host end through the DBUS bus.

[0147] The host end can send a read-write flag signal (dbus_wren) to the arbiter through the DBUS bus, and the arbiter can send the read-write flag signal (dbus_wren) to the slave end through the DBUS bus.

[0148] The host end can send a length signal (dbus_lens) to the arbiter through the DBUS bus, and the arbiter can send the length signal (dbus_lens) to the slave end through the DBUS bus.

[0149] The host end can send a start address signal (dbus_addr) to the arbiter through the DBUS bus, and the arbiter can send the start address signal (dbus_addr) to the slave end through the DBUS bus.

[0150] The host end can send a write valid signal (dbus_wvld) to the arbiter through the DBUS bus, and the arbiter can send the write valid signal (dbus_wvld) to the slave end through the DBUS bus.

[0151] The slave end can send a write ready signal (dbus_wrdy) to the arbiter through the DBUS bus, and the arbiter can send the write ready signal (dbus_wrdy) to the host end through the DBUS bus.

[0152] When the write ready signal indicates that the slave end allows receiving the write data signal, and the write valid signal indicates that the master end allows sending the write data signal, the master end can send the write data signal (dbus_wdata) to the arbiter through the DBUS bus, such as M write data signals, and the arbiter can send M write data signals (dbus_wdata) to the slave end through the DBUS bus. On this basis, the slave end can receive M write data signals through the DBUS bus, and obtain target valid data based on the M write data signals.

[0153] For the data reading process, the master end can send a request signal (dbus_req) to the arbiter through the DBUS bus, and the arbiter can send the request signal (dbus_req) to the slave end through the DBUS bus.

[0154] When the slave end receives the request signal through the DBUS bus, if the slave end is in an idle state, the slave end can send a response signal (dbus_ack) to the arbiter through the DBUS bus, and the arbiter can send the response signal (dbus_ack) to the master end through the DBUS bus.

[0155] The master end can send a read-write flag signal (dbus_wren) to the arbiter through the DBUS bus, and the arbiter can send the read-write flag signal (dbus_wren) to the slave end through the DBUS bus.

[0156] The master end can send a length signal (dbus_lens) to the arbiter through the DBUS bus, and the arbiter can send the length signal (dbus_lens) to the slave end through the DBUS bus.

[0157] The master end can send a start address signal (dbus_addr) to the arbiter through the DBUS bus, and the arbiter can send the start address signal (dbus_addr) to the slave end through the DBUS bus.

[0158] The master end can send a read ready signal (dbus_rrdy) to the arbiter through the DBUS bus, and the arbiter can send the read ready signal (dbus_rrdy) to the slave end through the DBUS bus.

[0159] The slave end can send a read valid signal (dbus_rvld) to the arbiter through the DBUS bus, and the arbiter can send the read valid signal (dbus_rvld) to the master end through the DBUS bus.

[0160] When the read preparation signal indicates that the host end allows to receive the read data signal, and the read valid signal indicates that the slave end allows to send the read data signal, the slave end can send the read data signal (dbus_rdata) to the arbitrator through the DBUS bus, and the arbitrator can send the read data signal (dbus_rdata) to the host end through the DBUS bus. On this basis, the host end receives the read data signal through the DBUS bus.

[0161] In a possible implementation, the on-chip bus system can include one host end, one arbitrator and one slave end, that is, the host end is connected with the arbitrator through the DBUS bus, and the slave end is connected with the arbitrator through the DBUS bus. The on-chip bus system can include one host end, multiple arbitrators and multiple slave ends, the host end is connected with each arbitrator through the DBUS bus respectively, the number of arbitrators can be the same as the number of slave ends, and the multiple arbitrators and the multiple slave ends are one-to-one correspondence, for example, the arbitrator 1 is connected with the slave end 1 through the DBUS bus, the arbitrator 2 is connected with the slave end 2 through the DBUS bus, and so on.

[0162] The on-chip bus system can include multiple host ends, one arbitrator and one slave end, the arbitrator is connected with each host end through the DBUS bus respectively, and the arbitrator is connected with the slave end through the DBUS bus.

[0163] The on-chip bus system can include multiple host ends, multiple arbitrators and multiple slave ends, for each host end, the host end is connected with each arbitrator through the DBUS bus respectively. The number of arbitrators can be the same as the number of slave ends, and the multiple arbitrators and the multiple slave ends are one-to-one correspondence, for example, the arbitrator 1 is connected with the slave end 1 through the DBUS bus, the arbitrator 2 is connected with the slave end 2 through the DBUS bus, and so on.

[0164] For the convenience of description, in the embodiment, the on-chip bus system includes multiple host ends, multiple arbitrators and multiple slave ends. Referring to FIG. 1, it is a structure schematic diagram of the on-chip bus system. Figure 5

[0165] The on-chip bus system includes the host end m0, the host end m1, the host end m2, the host end m3, the host end m4, the slave end s0, the slave end s1, the arbitrator WRR0 and the arbitrator WRR1. The arbitrator WRR0 and the slave end s0 are connected through the DBUS bus, the arbitrator WRR1 and the slave end s1 are connected through the DBUS bus. The host end m0, the host end m1, the host end m2, the host end m3 and the host end m4 are connected with the arbitrator WRR0 through the DBUS bus respectively, and the host end m0, the host end m1, the host end m2, the host end m3 and the host end m4 are connected with the arbitrator WRR1 through the DBUS bus respectively.

[0166] ​For example, when the host end m0 writes data to the slave end s0, the host end m0 sends a write data signal (s_w0) to the arbitrator WRR0 through the DBUS bus, and the arbitrator WRR0 sends a write data signal (m_w0) to the slave end s0 through the DBUS bus. When the host end m0 writes data to the slave end s1, the host end m0 sends a write data signal (s_w0) to the arbitrator WRR1 through the DBUS bus, and the arbitrator WRR1 sends a write data signal (m_w1) to the slave end s1 through the DBUS bus.

[0167] When the host end m1 writes data to the slave end s0, the host end m1 sends a write data signal (s_w1) to the arbitrator WRR0 through the DBUS bus, and the arbitrator WRR0 sends a write data signal (m_w0) to the slave end s0 through the DBUS bus. When the host end m1 writes data to the slave end s1, the host end m1 sends a write data signal (s_w1) to the arbitrator WRR1 through the DBUS bus, and the arbitrator WRR1 sends a write data signal (m_w1) to the slave end s1 through the DBUS bus, and so on.

[0168] For example, when the host end m0 reads data from the slave end s0, the slave end s0 sends a read data signal (m_r0) to the arbitrator WRR0 through the DBUS bus, and the arbitrator WRR0 sends a read data signal (s_r0) to the host end m0 through the DBUS bus. When the host end m0 reads data from the slave end s1, the slave end s1 sends a read data signal (m_r1) to the arbitrator WRR1 through the DBUS bus, and the arbitrator WRR1 sends a read data signal (s_r0) to the host end m0 through the DBUS bus.

[0169] When the host end m1 reads data from the slave end s0, the slave end s0 sends a read data signal (m_r0) to the arbitrator WRR0 through the DBUS bus, and the arbitrator WRR0 sends a read data signal (s_r1) to the host end m1 through the DBUS bus. When the host end m1 reads data from the slave end s1, the slave end s1 sends a read data signal (m_r1) to the arbitrator WRR1 through the DBUS bus, and the arbitrator WRR1 sends a read data signal (s_r1) to the host end m1 through the DBUS bus, and so on.

[0170] For example, when multiple host ends write data to the slave end s0 at the same time, the arbitrator WRR0 can select one host end from the multiple host ends, without limitation on the selection manner, and the arbitrator WRR0 allows the selected host end to write data to the slave end s0, and the other host ends do not write data to the slave end s0. When multiple host ends read data from the slave end s0 at the same time, the arbitrator WRR0 can select one host end from the multiple host ends, and the arbitrator WRR0 allows the selected host end to read data from the slave end s0.

[0171] When the host end m0 writes data to the slave end s0 and the host end m1 writes data to the slave end s1 at the same time, the arbitrator WRR0 allows the host end m0 to write data to the slave end s0, and the arbitrator WRR1 allows the host end m1 to write data to the slave end s1. When the host end m0 reads data from the slave end s0 and the host end m1 reads data from the slave end s1 at the same time, the arbitrator WRR0 allows the host end m0 to read data from the slave end s0, and the arbitrator WRR1 allows the host end m1 to read data from the slave end s1.

[0172] When the host end m0 writes data to the slave end s0 and the host end m1 reads data from the slave end s0 at the same time, the arbitrator WRR0 allows the host end m0 to write data to the slave end s0, and the arbitrator WRR0 allows the host end m1 to read data from the slave end s1, that is, the synchronization of data writing and reading to the slave end is supported.

[0173] In summary, in the embodiment, the arbitrator can be applied to a multi-master multi-slave application scenario, the arbitrator can be applied to a one-master multi-slave application scenario, the arbitrator can be applied to a multi-master one-slave application scenario, and the arbitrator can be applied to a one-master one-slave application scenario, and has strong reusability.

[0174] As can be seen from the above technical solutions, in the embodiment of the present application, a DBUS bus is designed, the DBUS bus has fewer signal lines, the protocol control timing is simple, the hardware overhead of the DBUS bus is small, and the DBUS bus is suitable for high-bandwidth, low-power, and small-area applications, that is, the DBUS bus has the advantages of high bandwidth, low latency, low power consumption, and small area. In system integration, the bus protocol of the DBUS bus is simple and easy to integrate, and is not prone to errors. The DBUS bus reduces the mask flag signal, that is, the DBUS bus does not need to provide the mask flag signal. Even if the mask flag signal is not provided, the mask function can be realized, the mask flag signal can be saved, the DBUS bus has fewer signal lines, the protocol control timing is simple, and the hardware overhead is small.

[0175] In the embodiment of the present application, a data receiving method of a slave end is provided, as shown in Figure 6 The method can include the following steps.

[0176] In step 601, M write data signals are received through the DBUS bus; wherein M is determined based on the data length of the target effective data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals include the target effective data.

[0177] In step 602, the target valid data is obtained based on the M write data signals; all data in the first M-1 write data signals is the target valid data, and all or part of data in the Mth write data signal is the target valid data.

[0178] For example, M is the integer obtained by rounding up the quotient of the data length of the target valid data and the bit width of the DBUS bus; if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all data in the Mth write data signal is the target valid data; or if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, N units of data in the Mth write data signal is the target valid data; wherein the target valid data occupies N units of high bits of the Mth write data signal, or the target valid data occupies N units of low bits of the Mth write data signal.

[0179] For example, obtaining the target valid data based on the M write data signals can include: determining all data in the first M-1 write data signals as the target valid data; generating a mask signal corresponding to the Mth write data signal based on the data length of the target valid data and the bit width of the DBUS bus, and determining all or part of data in the Mth write data signal as the target valid data based on the mask signal.

[0180] For example, determining all or part of data in the Mth write data signal as the target valid data based on the mask signal can include: if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all bits of the mask signal are a first value, a first post-operation signal is obtained by performing a mask operation on the mask signal and the Mth write data signal, and all data in the first post-operation signal is determined as the target valid data; if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, all bits of N high bytes of the mask signal are the first value, all bits of the remaining bytes are a second value, a second post-operation signal is obtained by performing a mask operation on the mask signal and the Mth write data signal, and N high bytes of the second post-operation signal are determined as the target valid data; or, all bits of N low bytes of the mask signal are the first value, all bits of the remaining bytes are the second value, a third post-operation signal is obtained by performing a mask operation on the mask signal and the Mth write data signal, and N low bytes of the third post-operation signal are determined as the target valid data.

[0181] For example, the data length of the configured target valid data can also be obtained.

[0182] Alternatively, a length signal is received through the DBUS bus, and a data length of target valid data is determined based on the length signal; wherein the length signal represents the data length of the target valid data.

[0183] An embodiment of the present application provides a data receiving device at a slave end, referring to Figure 7 as shown in a structural schematic diagram of the device. The device comprises:

[0184] The receiving module 71 is configured to receive M write data signals through the DBUS bus; wherein M is determined based on a data length of target valid data to be transmitted and a bit width of the DBUS bus; wherein the M write data signals comprise the target valid data.

[0185] The determining module 72 is configured to acquire the target valid data based on the M write data signals; wherein all data in the first M-1 write data signals is the target valid data, and all data or part of data in the Mth write data signal is the target valid data.

[0186] For example, M is an up-rounded quotient of the data length of the target valid data and the bit width of the DBUS bus; if a remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all data in the Mth write data signal is the target valid data; or if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, N units of data in the Mth write data signal is the target valid data; wherein the target valid data occupies N units of high bits of the Mth write data signal, or the target valid data occupies N units of low bits of the Mth write data signal.

[0187] For example, when the determining module 72 acquires the target valid data based on the M write data signals, it is specifically configured to determine all data in the first M-1 write data signals as the target valid data; generate a mask signal corresponding to the Mth write data signal based on the data length of the target valid data and the bit width of the DBUS bus, and determine all data or part of data in the Mth write data signal as the target valid data based on the mask signal.

[0188] For example, when the determination module 72 determines all or part of the Mth write data signal as the target valid data based on the mask signal, the following specific implementation is used: if the data length of the target valid data divided by the bit width of the DBUS bus has a remainder of 0, all bits of the mask signal are the first value, the mask operation is performed based on the mask signal and the Mth write data signal to obtain a first operation result, and all data in the first operation result is determined as the target valid data; if the data length of the target valid data divided by the bit width of the DBUS bus has a remainder of N, all bits of the first N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value, the mask operation is performed based on the mask signal and the Mth write data signal to obtain a second operation result, and the first N bytes in the second operation result are determined as the target valid data; or, all bits of the last N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value, the mask operation is performed based on the mask signal and the Mth write data signal to obtain a third operation result, and the last N bytes in the third operation result are determined as the target valid data.

[0189] For example, the determination module 72 is further configured to obtain the data length of the target valid data configured; or the receiving module 71 is further configured to receive a length signal through the DBUS bus; and the determination module 72 is further configured to determine the data length of the target valid data based on the length signal, where the length signal indicates the data length of the target valid data.

[0190] The above only describes embodiments of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. An on-chip bus system, characterized by The in-die bus system comprises a host end, a slave end and a DBUS bus, the host end is connected with the slave end through the DBUS bus; The host end is configured to send M write data signals to the slave end through the DBUS bus, wherein M is an up-rounded quotient value of a data length of target effective data to be transmitted and a bit width of the DBUS bus, and the M write data signals comprise the target effective data; The slave end is configured to receive the M write data signals and obtain the target effective data based on the M write data signals, wherein all data in the first M-1 write data signals is the target effective data, and all data or part of data in the Mth write data signal is the target effective data, wherein if a remainder of the data length of the target effective data divided by the bit width of the DBUS bus is 0, all data in the Mth write data signal is the target effective data, or if the remainder of the data length of the target effective data divided by the bit width of the DBUS bus is N, N units of data in the Mth write data signal is the target effective data, wherein the target effective data occupies N units of high bits of the Mth write data signal, or the target effective data occupies N units of low bits of the Mth write data signal.

2. The in-die bus system of claim 1, wherein when the slave end obtains the target effective data based on the M write data signals, the slave end is specifically configured to: determine all data in the first M-1 write data signals as the target effective data; and generate a mask signal corresponding to the Mth write data signal based on the data length of the target effective data and the bit width of the DBUS bus, and determine all data or part of data in the Mth write data signal as the target effective data based on the mask signal.

3. The in-die bus system of claim 2, wherein when the slave end determines all data or part of data in the Mth write data signal as the target effective data based on the mask signal, the slave end is specifically configured to: if the remainder of the data length of the target effective data divided by the bit width of the DBUS bus is 0, all bits of the mask signal are a first value, a first post-operation signal is obtained by performing a mask operation on the mask signal and the Mth write data signal based on the mask signal, and all data in the first post-operation signal is determined as the target effective data. ​ ​ If a remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, all bits of the high N bytes of the mask signal are a first value, and all bits of the remaining bytes are a second value, a mask operation is performed based on the mask signal and the Mth write data signal to obtain a second post-operation signal, and high N bytes in the second post-operation signal are determined as the target valid data; or, all bits of the low N bytes of the mask signal are the first value, and all bits of the remaining bytes are the second value, a mask operation is performed based on the mask signal and the Mth write data signal to obtain a third post-operation signal, and low N bytes in the third post-operation signal are determined as the target valid data.

4. The on-chip bus system according to any one of claims 1-3, wherein the slave end is further configured to obtain the data length of the target valid data configured; or, the slave end is further configured to receive a length signal transmitted by the master end through the DBUS bus, and determine the data length of the target valid data based on the length signal; wherein the length signal indicates the data length of the target valid data.

5. The on-chip bus system according to claim 1, wherein the on-chip bus system further comprises an arbiter, the master end is connected to the arbiter through the DBUS bus, and the arbiter is connected to the slave end through the DBUS bus; the master end is configured to transmit the M write data signals to the arbiter through the DBUS bus; the arbiter is configured to transmit the M write data signals to the slave end through the DBUS bus.

6. A data receiving method at a slave end, characterized in that: The method comprises: receiving M write data signals through the DBUS bus; wherein M is an integer obtained by rounding up a quotient of a data length of target valid data to be transmitted and a bit width of the DBUS bus; wherein the M write data signals comprise the target valid data; obtaining the target valid data based on the M write data signals; wherein all data in the first M-1 write data signals is target valid data, and all or part of data in the Mth write data signal is target valid data; wherein, if a remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all data in the Mth write data signal is the target valid data; or, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, N units of data in the Mth write data signal is the target valid data; wherein the target valid data occupies high N units of the Mth write data signal, or the target valid data occupies low N units of the Mth write data signal.

7. The method according to claim 6, wherein the obtaining the target valid data based on the M write data signals comprises: determining all data in the first M-1 write data signals as the target valid data; Generate a mask signal corresponding to the Mth write data signal based on the data length of the target valid data and the bit width of the DBUS bus, and determine all or part of the data in the Mth write data signal as the target valid data based on the mask signal.

8. The method of claim 7, wherein, The determination of all or part of the data in the Mth write data signal as the target valid data based on the mask signal comprises: If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all bits of the mask signal are of a first value, a first post-operation signal is obtained by performing a mask operation based on the mask signal and the Mth write data signal, and all data in the first post-operation signal is determined as the target valid data; If the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, all bits of the high N bytes of the mask signal are of a first value, all bits of the remaining bytes are of a second value, a second post-operation signal is obtained by performing a mask operation based on the mask signal and the Mth write data signal, and the high N bytes of the second post-operation signal are determined as the target valid data; or, all bits of the low N bytes of the mask signal are of a first value, all bits of the remaining bytes are of a second value, a third post-operation signal is obtained by performing a mask operation based on the mask signal and the Mth write data signal, and the low N bytes of the third post-operation signal are determined as the target valid data.

9. The method according to any one of claims 6-8, characterized in that, The method further comprises: Obtaining the data length of the target valid data configured; Or, receiving a length signal through the DBUS bus and determining the data length of the target valid data based on the length signal; wherein the length signal represents the data length of the target valid data.

10. A data receiving apparatus from a machine end, characterized by, The apparatus comprises: A receiving module configured to receive M write data signals through a DBUS bus; wherein M is an integer obtained by rounding up the quotient of the data length of target valid data to be transmitted and the bit width of the DBUS bus; wherein the M write data signals comprise the target valid data; A determining module configured to obtain target valid data based on the M write data signals; wherein all data in the first M-1 write data signals is target valid data, and all or part of the data in the Mth write data signal is target valid data; wherein, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is 0, all data in the Mth write data signal is the target valid data; or, if the remainder of the data length of the target valid data divided by the bit width of the DBUS bus is N, N units of data in the Mth write data signal are the target valid data; wherein the target valid data occupies the high N units of the Mth write data signal, or the target valid data occupies the low N units of the Mth write data signal.

11. The apparatus of claim 10, The apparatus further comprises: An obtaining module configured to obtain the data length of the target valid data configured; The determination module is specifically configured to: determine all data in the first M-1 write data signals as the target effective data; generate a mask signal corresponding to the Mth write data signal based on a data length of the target effective data and a bit width of the DBUS bus, and determine all data or part of data in the Mth write data signal as the target effective data based on the mask signal. The determination module is specifically configured to: if a remainder of the data length of the target effective data divided by the bit width of the DBUS bus is 0, all bits of the mask signal are a first value, a first post-operation signal is obtained by performing a mask operation based on the mask signal and the Mth write data signal, and all data in the first post-operation signal is determined as the target effective data. If the remainder of the data length of the target effective data divided by the bit width of the DBUS bus is N, all bits of high N bytes of the mask signal are the first value, all bits of the remaining bytes are a second value, a second post-operation signal is obtained by performing a mask operation based on the mask signal and the Mth write data signal, and high N bytes in the second post-operation signal are determined as the target effective data; or all bits of low N bytes of the mask signal are the first value, all bits of the remaining bytes are the second value, a third post-operation signal is obtained by performing a mask operation based on the mask signal and the Mth write data signal, and low N bytes in the third post-operation signal are determined as the target effective data. The determination module is further configured to obtain a data length of the target effective data configured. Alternatively, the receiving module is further configured to receive a length signal through the DBUS bus, and the determination module is further configured to determine the data length of the target effective data based on the length signal, where the length signal indicates the data length of the target effective data.

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