Multi-protocol communication interface chip receiver

Abstract

The invention relates to a multi-protocol communication interface chip receiver. The receiver comprises an RS232 receiver and an input switch resistance circuit, wherein the input end of the RS232 receiver is connected with the input switch resistance circuit; the input switch resistance circuit is used for enabling the input end of the RS232 receiver to be in a determined state voltage under the condition that the chip is turned off, and comprises a driving control circuit, a switch grid control and clamping circuit, a switch circuit and an input resistor; the design problem of a multi-protocol communication interface chip caused by incompatibility of the communication protocols of the RS232 receiver and the RS485 receiver in the aspects of common-mode input impedance and the like is solved, and the design of the multi-protocol communication interface chip can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-protocol communication interface chips, in particular to a multi-protocol communication interface chip receiver. Background Art

[0002] For multi-protocol communication interface chips, due to the multi-mode and multi-channel selectable characteristics, the chip pins will reuse the functions of different protocol communication interfaces, and the communication channels of different protocols will be constantly opened and closed, which makes it inevitable that there will be mutual interference between different mode channels.

[0003] The driver port of the communication interface chip has a high-impedance mode, theoretically allowing for direct connection and reuse. The RS485 receiver typically features a differential input comparator with symmetrical high-resistance common-mode resistors. The receiver's high-precision threshold is between 50mV and 200mV, and theoretically, this structure shouldn't affect the RS232 receiver. However, the RS232 receiver uses a single-ended input. Because the RS232 receiver input port features a 5kΩ pull-down resistor connected to GND, the 5kΩ pull-down resistor in a traditional RS232 receiver is always on. Its unique high-voltage circuit structure makes it difficult to design a shutdown mode. Therefore, when the inputs of different mode receivers on a multi-protocol communication interface chip are shared and operating in RS485 mode, the always-on 5kΩ resistor on the RS232 port will inevitably affect the RS485 receiver's common-mode resistor and high-precision threshold voltage, disrupting normal communication. This issue clearly prevents the sharing or reuse of receiver circuits on communication interface chips supporting different protocols. Summary of the Invention

[0004] Based on this, it is necessary to provide a multi-protocol communication interface chip receiver that can realize the sharing or multiplexing of receiver circuits of communication interface chips of different protocols.

[0005] The present application provides a multi-protocol communication interface chip receiver, which includes an RS232 receiver and an input switch resistor circuit, wherein:

[0006] The input of the RS232 receiver is connected to the input switch resistor circuit;

[0007] The input switch resistor circuit is used to set the input end of the RS232 receiver to a certain voltage when the chip is turned off. It includes a drive control circuit, a switch gate control and clamping circuit, a switch circuit, and an input resistor.

[0008] Among them, the input resistor is connected to the switch circuit and the RS232 receiver input;

[0009] The drive control circuit is connected to the switch gate control and clamping circuit and the switch circuit, and is used to control the on and off of the switch tube in the switch circuit;

[0010] The switch gate control and clamping circuit is connected to the switch circuit and is used to protect the switch tube in the switch circuit when the drive control circuit controls the switch tube in the switch circuit to be turned on, and to ensure that the switch tube in the switch circuit is in the off state when the drive control circuit controls the switch tube in the switch circuit to be turned off;

[0011] The switch circuit connects the input resistor to GND when the drive control circuit controls the switch to be turned on, and disconnects the input resistor from GND when the drive control circuit controls the switch to be turned off.

[0012] In one embodiment, the drive control circuit includes:

[0013] The source of the tenth NMOS tube is connected to GND, the gate of the tenth NMOS tube is connected to the gate of the eleventh PMOS tube and to CTL, the drain of the tenth NMOS tube is connected to the drain of the eleventh PMOS tube, the source of the eleventh PMOS tube is connected to VCC, the source of the twelfth NMOS tube is connected to GND, the drain of the tenth NMOS tube and the drain of the eleventh PMOS are connected to the gate of the twelfth NMOS tube, the gate of the fourteenth PMOS tube, the gate of the seventeenth NMOS tube, and the gate of the nineteenth PMOS tube; the drain of the twelfth NMOS tube is connected to the drain of the thirteenth NMOS tube, the gate and source of the thirteenth NMOS tube are connected to the drain of the fourteenth PMOS tube, the gate of the sixteenth NMOS tube, the gate of the eighteenth NMOS tube, the gate of the twenty-seventh NMOS tube in the switch circuit, and the drain of the twenty-fifth NMOS tube in the switch gate control and clamping circuit, and the source of the fourteenth PMOS tube is connected to V CC, the gate of the fifteenth NMOS tube is connected to CTL, the source of the fifteenth NMOS tube is connected to GND, the drain of the fifteenth NMOS tube is connected to the drain of the sixteenth NMOS tube, the source of the sixteenth NMOS tube is connected to the first end of the fifth resistor, and at the same time, the source of the sixteenth NMOS tube is connected to the gate of the twenty-fifth NMOS tube, the gate of the twenty-sixth NMOS tube, the gate and drain of the twentieth NMOS tube, and the gate of the twenty-fourth NMOS tube in the switch gate control and clamping circuit, and the second end of the fifth resistor is connected to VCC; the source of the seventeenth NMOS tube is connected to GND, the drain of the seventeenth NMOS tube is connected to the drain of the eighteenth NMOS tube, the source of the eighteenth NMOS tube is connected to the drain of the nineteenth PMOS tube, the drain of the twenty-sixth NMOS tube in the switch gate control and clamping circuit, and the gate of the twenty-eighth NMOS tube in the switch circuit, and the source of the nineteenth PMOS tube is connected to VCC.

[0014] In one embodiment, the switch gate control and clamping circuit includes:

[0015] The gate and drain of the 20th NMOS transistor are connected to the source of the 16th NMOS transistor in the drive control circuit and the first end of the fifth resistor. At the same time, the gate and drain of the 20th NMOS transistor are connected to the gate of the 24th NMOS transistor, the gate of the 25th NMOS transistor, and the gate of the 26th NMOS transistor. The source of the 20th NMOS transistor is connected to the gate and drain of the 21st NMOS transistor, the source of the 21st NMOS transistor is connected to the gate and drain of the 22nd NMOS transistor, the source of the 22nd NMOS transistor is connected to the gate and drain of the 23rd NMOS transistor, the source of the 23rd NMOS transistor is connected to the source of the 24th NMOS transistor, and the drain of the 24th NMOS transistor is connected to the source of the 25th NMOS transistor, the source of the 26th NMOS transistor, the source of the 27th NMOS transistor in the switch circuit, and the source of the 28th NMOS transistor.

[0016] In one embodiment, the switching circuit includes:

[0017] The source of the twenty-seventh NMOS tube and the source of the twenty-eighth NMOS tube are connected to the drain of the twenty-fourth NMOS tube, the source of the twenty-fifth NMOS tube, and the source of the twenty-sixth NMOS tube in the switch gate control and clamping circuit, the drain of the twenty-seventh NMOS tube is connected to GND, and the drain of the twenty-eighth NMOS tube is connected to the first end of the input resistor.

[0018] In one embodiment, the input resistor comprises a first resistor, wherein:

[0019] A first end of the first resistor is connected to the drain of the twenty-eighth NMOS transistor, and a second end of the first resistor is connected to the input end of the RS232 receiver.

[0020] In one embodiment, the RS232 receiver includes an upper clamping circuit, a lower clamping circuit, a protection resistor circuit, and an inverter circuit, wherein:

[0021] The first end of the protection resistor circuit is the input end of the RS232 receiver. The protection resistor circuit is connected to the input end of the inverter circuit and is connected to the upper clamping circuit and the lower clamping circuit. The protection resistor circuit is used to limit the input current.

[0022] The inverter circuit, as the threshold circuit of the RS232 receiver, outputs the input voltage after passing through the protection resistor circuit to the module in the chip. The output end of the inverter circuit is the output end of the RS232 receiver.

[0023] The upper clamping circuit is used to clamp the voltage of the gate common terminal in the inverter circuit within the negative withstand voltage range of the MOS tube, and the lower clamping circuit is used to clamp the voltage of the gate common terminal in the inverter circuit within the positive withstand voltage range of the MOS tube.

[0024] In one embodiment, the protection resistor circuit includes a second resistor and a third resistor, wherein:

[0025] The first end of the second resistor is the first end of the protection resistor circuit and is connected to the input end of the RS232 receiver; the second end of the second resistor is connected to the second end of the third resistor, and the second end of the second resistor and the second end of the third resistor are simultaneously connected to the output end of the lower clamping circuit; the first end of the third resistor is connected to the output end of the upper clamping circuit and the input end of the inverter circuit.

[0026] In one embodiment, the lower clamping circuit includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein:

[0027] The gate and drain of the first NMOS transistor serve as the output ends of the lower clamping circuit and are connected to the second end of the second resistor and the second end of the third resistor in the protection resistor circuit. The source of the first NMOS transistor is connected to the gate and drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the gate and drain of the third NMOS transistor, and the source of the third NMOS transistor is connected to GND.

[0028] In one embodiment, the upper clamping circuit includes a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and a fourth resistor, wherein:

[0029] The source of the fourth NMOS transistor is connected to the first end of the third resistor in the protection resistor circuit and the input end of the inverter circuit as the output end of the upper clamping circuit. The gate of the fourth NMOS transistor is connected to the first end of the fourth resistor. The second end of the fourth resistor is connected to GND. The drain of the fourth NMOS transistor is connected to the drain of the fifth PMOS transistor. At the same time, the drain of the fourth NMOS transistor is connected to the gates of the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor. The source of the fifth PMOS transistor is connected to the drain of the sixth PMOS transistor. The source of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor. The source of the seventh PMOS transistor is connected to VCC.

[0030] In one embodiment, the inverter circuit includes an eighth NMOS transistor, a ninth PMOS transistor, and a first inverter, wherein:

[0031] The gate of the eighth NMOS transistor and the gate of the ninth PMOS transistor serve as input terminals of the inverter circuit and are connected to the first terminal of the third resistor in the protection resistor circuit and the output terminal of the upper clamping circuit. The source of the eighth NMOS transistor is connected to GND, the source of the ninth PMOS transistor is connected to VCC, the drain of the eighth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the input terminal of the first inverter is connected to the drain of the eighth NMOS transistor and the drain of the ninth PMOS transistor. The output terminal of the first inverter serves as the output terminal of the RS232 receiver.

[0032] The above-mentioned multi-protocol communication interface chip receiver controls the working state of the RS232 receiver circuit through the protocol selection signal inside the chip, realizes switching control of the input resistance of the RS232 protocol receiver in different working modes, solves the incompatibility problem of traditional RS232 and RS485 receiver communication protocols in terms of common-mode input impedance, and realizes the normal communication function design of the multi-protocol interface chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 It is a traditional RS232 receiver circuit;

[0035] Figure 2 A circuit diagram of a multi-protocol communication interface chip receiver in one embodiment;

[0036] Figure 3 The figure is a circuit diagram of an input switch resistance circuit of a multi-protocol communication interface chip receiver in one embodiment. DETAILED DESCRIPTION

[0037] The RS232 communication standard is a standard for serial data communication. It is primarily applicable to point-to-point data communication between data terminal equipment, data communication equipment, and intelligent instruments and meters. The RS422 standard, developed from the RS232 standard, is a unidirectional, balanced transmission communication interface standard for single-device transmission and multiple-device reception. The RS485 standard, developed based on RS422, adds multipoint transmission and bidirectional communication capabilities, allowing multiple transmitters to communicate on the same bus. It also extends the bus's common-mode range, enhances noise suppression, increases data transmission rates, increases communication distance, and improves communication reliability.

[0038] Typically, computers and other data devices are only equipped with an RS232 interface. To communicate with a computer via the RS485 bus, RS232 / RS485 conversion is required to achieve bidirectional data communication between the RS485 bus interface and the RS232 serial interface. With the rise of Industry 4.0 and the intelligent development of industrial control systems, the demand for multi-protocol communication interface chips is rapidly increasing. The development of intelligent communication interface chips that are compatible with the RS232 / RS422 / RS485 standards, can provide multiple communication interfaces separately or simultaneously, and support mutual conversion, has wide market applications and urgent customer demand.

[0039] For multi-protocol communication interface chips, due to their multi-mode and multi-channel selectability, the chip pins reuse different protocol communication interface functions, and communication channels for different protocols are constantly opening and closing, which inevitably leads to mutual interference between channels in different modes. The driver ports of the communication interface chip have a high-impedance mode, theoretically allowing for direct connection and reuse. As for the receiver of the communication interface chip, the RS485 receiver is typically a differential input comparator with symmetrical high-resistance common-mode resistors. The receiver's high-precision threshold is in the range of 50mV to 200mV, and theoretically, this structure will not affect the RS232 receiver. The RS232 receiver has a single-ended input. Since the RS232 receiver input port has a 5KΩ input pull-down resistor to GND, the 5KΩ input pull-down resistor of the traditional RS232 receiver is always on. Its unique high-voltage resistance circuit structure makes it difficult to design a shutdown mode. Therefore, when the input terminals of different mode receivers of the multi-protocol communication interface chip are shared and work in RS485 mode, the 5KΩ resistor of the RS232 port will inevitably affect the common-mode voltage divider resistor and high-precision threshold voltage of the RS485 receiver, causing interference to the normal communication function. Obviously, this problem makes it impossible to share or reuse the receiver circuits of communication interface chips of different protocols.

[0040] In order to solve the above technical problems, an embodiment of the present application proposes a multi-protocol communication interface chip receiver, including a design of a switch resistor circuit applied to the multi-protocol communication interface chip receiver.

[0041] To facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0042] The terms "first," "second," etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0043] The “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc., if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0044] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0045] Figure 1This is a traditional RS232 receiver circuit. One end of the first resistor R1 is connected to GND, and the other end is connected to the first end of the second resistor R2 and serves as the input end IN of the receiver. The second end of the second resistor R2 is connected to the second end of the third resistor R3 and is also connected to the gate and drain of the first NMOS transistor M1. The source of the first NMOS transistor M1 is connected to the gate and drain of the second NMOS transistor M2. The source of the second NMOS transistor M2 is connected to the gate and drain of the third NMOS transistor M3. The source of the third NMOS transistor M3 is connected to GND. The first end of the third resistor R3 is connected to the source of the fourth NMOS transistor M4 and to the gate of the eighth NMOS transistor M8 and the gate of the ninth PMOS transistor M9. The gate of the fourth NMOS transistor M4 is connected to GND via the fourth resistor R4. The drain of the fourth NMOS transistor M4 is connected to the drain of the fifth PMOS transistor M5 and to the gates of the fifth PMOS transistor M5, the sixth PMOS transistor M6, and the seventh PMOS transistor M7. The source of the fifth PMOS transistor M5 is connected to the drain of the sixth PMOS transistor M6, the source of the sixth PMOS transistor M6 is connected to the drain of the seventh PMOS transistor M7, and the source of the seventh PMOS transistor M7 is connected to VCC. The source of the eighth NMOS transistor M8 is connected to GND, the source of the ninth PMOS transistor M9 is connected to VCC, the drain of the eighth NMOS transistor M8 is connected to the drain of the ninth PMOS transistor M9, and the input of the first inverter. The output of the first inverter serves as the output of the receiver. This circuit is a conventional receiver input circuit for RS232 communication mode. The IN terminal is the input port. The first resistor R1 is a standard RS232 5kΩ input resistor. The input signal from the IN terminal is supplied to an inverter consisting of an eighth NMOS transistor M8 and a ninth PMOS transistor M9 via second and third resistors R2 and R3. The threshold of the inverter is the RS232 input port differential threshold voltage. When the IN terminal input voltage reaches a maximum of 30V, the conduction of the first, second, and third NMOS transistors M1, M2, and M3 clamps the input node voltage, ensuring that the input voltage of the inverter consisting of the eighth NMOS transistor M8 and the ninth PMOS transistor M9 does not exceed the positive withstand voltage range of the MOS transistors. In this case, the output of the inverter consisting of the eighth NMOS transistor M8 and the ninth PMOS transistor M9 is low. When the IN terminal input voltage reaches a minimum of -30V, the conduction of the fourth NMOS transistor M4 clamps the input voltage to no less than the negative withstand voltage range of the MOS transistors. In this case, the output of the inverter consisting of the eighth NMOS transistor M8 and the ninth PMOS transistor M9 is high.

[0046] In a multi-protocol communication interface chip, the RS232 receiver's IN terminal is multiplexed with the RS485 receiver's IN terminal. Since the RS485 receiver is typically a differential input comparator with symmetrical high-resistance common-mode resistors, and the receiver's high-precision threshold is in the 50mV to 200mV range, when the chip operates in RS485 mode, the shared 5KΩ resistor from the RS232 receiver's input terminal to GND will inevitably affect the RS485 receiver, causing RS485 signal transmission anomalies.

[0047] In an exemplary embodiment, the present application provides a multi-protocol communication interface chip receiver, including a design of a switch resistor circuit applied to the multi-protocol communication interface chip receiver. Figure 2 As shown, this circuit is compared with Figure 1 The traditional RS232 receiver circuit will Figure 1 The IN terminal input resistor R1 is replaced by an input switch resistor circuit, the control terminal of the input switch resistor circuit module is CTL, and the input terminal is the input terminal IN of the receiver.

[0048] Specifically, a multi-protocol communication interface chip receiver includes an RS232 receiver and an input switch resistor circuit, wherein:

[0049] The input of the RS232 receiver is connected to the input switch resistor circuit;

[0050] Input switch resistor circuit: When the chip is turned off, the resistor of this module will ensure that the input terminal IN of the receiver is a low voltage in a certain state, which makes the receiver almost have no conduction current. That is, the input switch resistor circuit is used to make the input terminal of the RS232 receiver a certain voltage when the chip is turned off.

[0051] Exemplarily, the RS232 receiver includes an upper clamping circuit, a lower clamping circuit, a protection resistor circuit, and an inverter circuit.

[0052] Among them, the function of the protection resistor circuit is to limit the current of the input path when the input terminal IN of the RS232 receiver is connected to a positive or negative high voltage. The first end of the protection resistor circuit is the input terminal of the RS232 receiver. The protection resistor circuit is connected to the input terminal of the inverter circuit and is connected to the upper clamping circuit and the lower clamping circuit. The inverter circuit serves as the threshold circuit of the RS232 receiver. The input signal of the IN terminal passes through the protection resistor circuit and is output to other modules of the chip after being detected by the inverter circuit. The output end of the inverter circuit is the output end of the RS232 receiver and also the output end of a multi-protocol communication interface chip receiver. Since the eighth NMOS transistor M8 and the ninth PMOS transistor M9 of the internal threshold circuit of the inverter circuit are standard low-voltage circuits, the voltage cannot exceed the operating range of the low-voltage transistor. When the IN terminal is connected to a -30V voltage, the high-voltage transistors, the fourth NMOS transistor M4, the fifth PMOS transistor M5, the sixth PMOS transistor M6, and the seventh PMOS transistor M7, are turned on. Since the gate of M4 is at the GND potential, the common gate terminal of M8 and M9 is clamped within the negative withstand voltage range of the MOS transistor, and the common output terminal of M8 and M9 is high. Since the eighth NMOS transistor M8 and the ninth PMOS transistor M9 in the internal threshold circuit of the inverter circuit are standard low-voltage circuits, the voltage cannot exceed the operating range of the low-voltage transistor. When the IN terminal is connected to a +30V voltage, the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3 are turned on to GND. Therefore, the common gate terminal of M8 and M9 is clamped within the positive withstand voltage range of the MOS transistor, and the common output terminal of M8 and M9 is low.

[0053] Specifically, the protection resistor circuit includes a second resistor R2 and a third resistor R3. The first end of the second resistor R2 is the first end of the protection resistor circuit and is connected to the input of the RS232 receiver. The second end of the second resistor R2 is connected to the second end of the third resistor R3. The second end of the second resistor R2 and the second end of the third resistor R3 are both connected to the output of the lower clamp circuit. The first end of the third resistor R3 is connected to the output of the upper clamp circuit and the input of the inverter circuit.

[0054] Specifically, the lower clamping circuit includes a first NMOS transistor M1, a second NMOS transistor M2, and a third NMOS transistor M3. The gate and drain of the first NMOS transistor M1, serving as output terminals of the lower clamping circuit, are connected to the second end of the second resistor R2 and the second end of the third resistor R3 in the protection resistor circuit. The source of the first NMOS transistor M1 is connected to the gate and drain of the second NMOS transistor M2. The source of the second NMOS transistor M2 is connected to the gate and drain of the third NMOS transistor M3. The source of the third NMOS transistor M3 is connected to GND.

[0055] Specifically, the upper clamping circuit includes a fourth NMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, and a fourth resistor R4. The source of the fourth NMOS transistor M4, as the output end of the upper clamping circuit, is connected to the first end of the third resistor R3 in the protection resistor circuit and the input end of the inverter circuit. The gate of the fourth NMOS transistor M4 is connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to GND. The drain of the fourth NMOS transistor M4 is connected to the drain of the fifth PMOS transistor M5. The drain of the fourth NMOS transistor M4 is connected to the gates of the fifth PMOS transistor M5, the sixth PMOS transistor M6, and the seventh PMOS transistor M7. The source of the fifth PMOS transistor M5 is connected to the drain of the sixth PMOS transistor M6. The source of the sixth PMOS transistor M6 is connected to the drain of the seventh PMOS transistor M7. The source of the seventh PMOS transistor M7 is connected to VCC.

[0056] Specifically, the inverter circuit includes an eighth NMOS transistor M8, a ninth PMOS transistor M9, and a first inverter. The gate M8 of the eighth NMOS transistor and the gate M9 of the ninth PMOS transistor serve as inputs of the inverter circuit, connected to the first end of the third resistor R3 in the protection resistor circuit and the output of the upper clamp circuit. The source of the eighth NMOS transistor M8 is connected to GND, the source of the ninth PMOS transistor M9 is connected to VCC, the drain of the eighth NMOS transistor M8 is connected to the drain of the ninth PMOS transistor M9, and the input of the first inverter is connected to the drain of the eighth NMOS transistor M8 and the drain of the ninth PMOS transistor M9. The output OUT of the first inverter serves as the output of the RS232 receiver.

[0057] In an exemplary embodiment, the internal circuit diagram of the input switch resistor circuit is as follows: Figure 3 As shown, it includes a drive control circuit, a switch gate control and clamping circuit, a switch circuit, and an input resistor.

[0058] Specifically, CTL in the drive control circuit is a protocol mode selection signal. The CTL signal controls the on / off switching of the two switching transistors in the switch circuit through the drive control circuit. The drive control circuit in this application has a high-voltage resistance function. The drive control circuit includes: a source of a tenth NMOS transistor M10 connected to GND, a drain of the tenth NMOS transistor M10 connected to the drain of the eleventh PMOS transistor M11, a source of the eleventh PMOS transistor M11 connected to VCC, and a gate of the tenth NMOS transistor M10 and a drain of the eleventh PMOS transistor M11 connected to the gate of the twelfth NMOS transistor M12, the gate of the fourteenth PMOS transistor M14, the gate of the seventeenth PMOS transistor M17, and the gate of the nineteenth PMOS transistor M19. The drain of the twelfth NMOS transistor M12 is connected to the drain of the thirteenth NMOS transistor M13, the gate and source of the thirteenth NMOS transistor M13 are connected to the drain of the fourteenth PMOS transistor M14, the gate of the sixteenth NMOS transistor M16, the gate of the eighteenth NMOS transistor M18, the gate of the twenty-seventh NMOS transistor M27 in the switch circuit, and the drain of the twenty-fifth NMOS transistor M25 in the switch gate control and clamping circuit, the source of the fourteenth PMOS transistor is connected to VCC, the gate of the fifteenth NMOS transistor M15 is connected to CTL, and the gate of the fifteenth NMOS transistor M16 is connected to CTL. The source of the MOS transistor M15 is connected to GND, the drain of the fifteenth NMOS transistor M15 is connected to the drain of the sixteenth NMOS transistor M16; the source of the sixteenth NMOS transistor M16 is connected to the first end of the fifth resistor R5, and the sixteenth NMOS transistor M16 is connected to the gate of the twenty-fifth NMOS transistor M25, the gate of the twenty-sixth NMOS transistor M26, the gate and drain of the twentieth NMOS transistor M20, and the gate of the twenty-fourth NMOS transistor M24 in the switch gate control and clamping circuit. The second end of the fifth resistor R5 is connected to VCC. The source of the seventeenth NMOS transistor M17 is connected to GND, the drain of the seventeenth NMOS transistor M17 is connected to the drain of the eighteenth NMOS transistor M18, the source of the eighteenth NMOS transistor M18 is connected to the drain of the nineteenth PMOS transistor M19, the drain of the twenty-sixth NMOS transistor M26 in the switch gate control and clamping circuit, and the gate of the twenty-eighth NMOS transistor M28 in the switch circuit, and the source of the nineteenth PMOS transistor M19 is connected to VCC.

[0059] Specifically, the function of the switch gate control and clamping circuit is that when the switch tube in the switch circuit is controlled to be turned on by the drive control circuit, this circuit clamps the gate-source voltage of the switch tube to prevent the gate-source voltage from exceeding its maximum withstand voltage; when the switch tube in the switch circuit is controlled to be turned off by the drive control circuit, this circuit short-circuits the gate-source of the switch tube to ensure that the switch tube is in a completely off state. The circuit includes: a source of a 20th NMOS transistor M20 connected to a gate and a drain of a 21st NMOS transistor M21, a source of the 21st NMOS transistor M21 connected to a gate and a drain of a 22nd NMOS transistor M22, a source of the 22nd NMOS transistor M22 connected to a gate and a drain of a 23rd NMOS transistor M23, a source of the 23rd NMOS transistor M23 connected to a source of a 24th NMOS transistor M24, and a drain of the 24th NMOS transistor M24 connected to a source of a 25th NMOS transistor M25, a source of a 26th NMOS transistor M26, a source of a 27th NMOS transistor M27 in the switch circuit, and a source of a 28th NMOS transistor M28.

[0060] Specifically, the switch circuit functions as follows: when the switch circuit is on, the lower end of the input resistor is connected to GND, allowing the input resistor to function as a normal pull-down resistor; when the switch circuit is off, the lower end of the input resistor is disconnected, and the input resistor no longer functions as a pull-down resistor. The switch circuit includes: the source of the twenty-seventh NMOS transistor M27 and the source of the twenty-eighth NMOS transistor M28 are connected to the drain of the twenty-fourth NMOS transistor M24, the source of the twenty-fifth NMOS transistor M25, and the source of the twenty-sixth NMOS transistor M26 in the switch gate control and clamping circuit; the drain of the twenty-seventh NMOS transistor M27 is connected to GND, and the source of the twenty-eighth NMOS transistor M28 is connected to the first end of the input resistor R1.

[0061] Specifically, the input resistor is a pull-down resistor of the receiver input terminal IN, and the input resistor includes a first resistor R1. The first end of the first resistor R1 is connected to the drain of the twenty-eighth NMOS transistor M28, and the second end of the first resistor R1 is connected to the input terminal IN of the RS232 receiver.

[0062] Furthermore, for Figure 1 In the conventional RS232 receiver circuit shown, when the chip works in RS485 mode, since the IN terminal of the RS232 receiver circuit is shared with the IN terminal of the RS485 receiver, when an RS485 signal is input to the chip, the RS485 receiver input terminal in the transmission state has a high resistance divider, and the 5KΩ low input resistance of the shared RS232 receiver circuit port will cause the RS485 receiver voltage divider to deviate, affecting the normal input threshold of the RS485 receiver, and thus affecting the normal signal transmission function of the RS485 receiver.

[0063] In order to solve the above problems, Figure 2 As shown, the input switch resistor circuit, when the chip works in RS485 mode, due to the multiplexing of the port, Figure 1 The 5KΩ input resistor R1 of the RS232 receiver will affect the signal transmission in RS485 mode and cause signal interference. Therefore, the connection of R1 resistor needs to be disconnected in RS485 mode. Since the input voltage range of the RS232 input port is ±30V, the design of the switch circuit that disconnects R1 resistor needs to consider the positive and negative high voltage withstand conditions.

[0064] The internal circuit diagram of the input switch resistor circuit is as follows Figure 3 As shown in the figure, resistor R1 in this circuit is the 5KΩ resistor at the input end. M27 and M28 transistors act as switching transistors for R1. When M27 and M28 transistors are on, R1 resistor is connected to GND. When M27 and M28 transistors are off, R1 resistor is left floating. M27 and M28 transistors are connected in a source-to-source connection. The main purpose of this connection method is to connect the parasitic diodes back to back to prevent the parasitic diodes from being turned on under any circumstances.

[0065] For example, different working modes and input voltage conditions are described. Figure 2 The specific operating principle of the receiver circuit of the multi-protocol communication interface chip is shown below. When the chip is operating in RS232 mode, the CTL signal is high, turning on transistors M15, M10, and M14, while the gate voltage of transistor M27 is high. M16 is on, while the gate voltages of transistors M25 and M26 are low. M25 and M26 are off. M17 is off, M19 is on, and the gate voltage of transistor M28 is high. Since the gate voltages of transistors M27 and M28 are both high, transistors M27 and M28 are turned on. At this point, the upper end of resistor R1 is connected to the receiver input, while the lower end of resistor R1 is pulled to GND by transistors M27 and M28. Regardless of the input voltage at the upper end of R1, the voltage at the lower end of R1 remains at GND. R1 functions as a pull-down resistor, and this module circuit is free of high-voltage risks.

[0066] When the chip operates in RS485 mode, the CTL signal is low, M15 is off, M11 is on, M12 is on, the gate voltage of M27 is low, M16 is off, and the gates of M25 and M26 are pulled high by resistor R5, turning M25 and M26 on. M17 is on, the parasitic diode of M18 is conducting, M19 is off, and the gate voltage of M28 is low. Since the gate voltages of M27 and M28 are both low, M27 and M28 are turned on. Furthermore, M25 and M26 are turned on, shorting the gate and source of M27 and M28, ensuring that M27 and M28 are completely off. At this point, if the voltage at the upper end of resistor R1 is 30V, because M28 is off and its parasitic diode is reverse biased, there will be no high voltage in the internal circuit of this module. If the voltage at the top of resistor R1 is -30V, the source voltage of M28 is approximately -29V due to the conduction of the back diode of transistor M28. At this time, transistors M25 and M26 are conductive, and the gate voltages of M27 and M28 are both -29V. Transistors M20, M21, M22, M23, and M24 are also conductive. The gate and source voltages of M25 and M26 are clamped by transistors M20, M21, M22, M23, and M24. The source voltage of M16 is approximately -25V, and the gate voltage of M16 is equal to the gate voltage of M27. The gate-source voltage difference of M16 does not exceed its withstand voltage range, so there is no risk of breakdown. The source and gate voltages of M18 are both approximately -29V, so there is no risk of breakdown. The entire switch resistor module realizes the function of disconnecting the pull-down resistor at the RS232 receiver input in different working modes when the input voltage is ±30, ensuring normal communication of the multi-protocol interface chip and ensuring that there is no high-voltage breakdown risk inside the module when there are positive and negative high voltages at the input end.

[0067] This application solves the problem of multi-protocol communication interface chip design caused by the incompatibility of traditional RS232 and RS485 receiver communication protocols in terms of common-mode input impedance, etc. by controlling the input impedance and circuit operating status of the communication interface chip RS232 receiver. The present invention can realize the design of a multi-protocol communication interface chip.

[0068] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0069] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A multi-protocol communication interface chip receiver, characterized in that: The receiver includes an RS232 receiver and an input switch resistor circuit, wherein: The input of the RS232 receiver is connected to the input switch resistor circuit; The input switch resistor circuit is used to set the input end of the RS232 receiver to a certain voltage when the chip is turned off. It includes a drive control circuit, a switch gate control and clamping circuit, a switch circuit, and an input resistor. Among them, the input resistor is connected to the switch circuit and the RS232 receiver input; The drive control circuit is connected to the switch gate control and clamping circuit and the switch circuit, and is used to control the on and off of the switch tube in the switch circuit; The switch gate control and clamping circuit is connected to the switch circuit and is used to protect the switch tube in the switch circuit when the drive control circuit controls the switch tube in the switch circuit to be turned on, and to ensure that the switch tube in the switch circuit is in the off state when the drive control circuit controls the switch tube in the switch circuit to be turned off; The switch circuit connects the input resistor to GND when the drive control circuit controls the switch to be turned on, and disconnects the input resistor from GND when the drive control circuit controls the switch to be turned off.

2. A multi-protocol communication interface chip receiver according to claim 1, characterized in that: The drive control circuit includes: The source of the tenth NMOS tube is connected to GND, the gate of the tenth NMOS tube is connected to the gate of the eleventh PMOS tube and to CTL, the drain of the tenth NMOS tube is connected to the drain of the eleventh PMOS tube, the source of the eleventh PMOS tube is connected to VCC, the source of the twelfth NMOS tube is connected to GND, the drain of the tenth NMOS tube and the drain of the eleventh PMOS are connected to the gate of the twelfth NMOS tube, the gate of the fourteenth PMOS tube, the gate of the seventeenth NMOS tube, and the gate of the nineteenth PMOS tube; the drain of the twelfth NMOS tube is connected to the drain of the thirteenth NMOS tube, the gate and source of the thirteenth NMOS tube are connected to the drain of the fourteenth PMOS tube, the gate of the sixteenth NMOS tube, the gate of the eighteenth NMOS tube, the gate of the twenty-seventh NMOS tube in the switch circuit, and the drain of the twenty-fifth NMOS tube in the switch gate control and clamping circuit, and the source of the fourteenth PMOS tube is connected to V CC, the gate of the fifteenth NMOS tube is connected to CTL, the source of the fifteenth NMOS tube is connected to GND, the drain of the fifteenth NMOS tube is connected to the drain of the sixteenth NMOS tube, the source of the sixteenth NMOS tube is connected to the first end of the fifth resistor, and at the same time, the source of the sixteenth NMOS tube is connected to the gate of the twenty-fifth NMOS tube, the gate of the twenty-sixth NMOS tube, the gate and drain of the twentieth NMOS tube, and the gate of the twenty-fourth NMOS tube in the switch gate control and clamping circuit, and the second end of the fifth resistor is connected to VCC; the source of the seventeenth NMOS tube is connected to GND, the drain of the seventeenth NMOS tube is connected to the drain of the eighteenth NMOS tube, the source of the eighteenth NMOS tube is connected to the drain of the nineteenth PMOS tube, the drain of the twenty-sixth NMOS tube in the switch gate control and clamping circuit, and the gate of the twenty-eighth NMOS tube in the switch circuit, and the source of the nineteenth PMOS tube is connected to VCC.

3. The multi-protocol communication interface chip receiver according to claim 2, characterized in that: The switch gate control and clamping circuit includes: The gate and drain of the 20th NMOS transistor are connected to the source of the 16th NMOS transistor in the drive control circuit and the first end of the fifth resistor. At the same time, the gate and drain of the 20th NMOS transistor are connected to the gate of the 24th NMOS transistor, the gate of the 25th NMOS transistor, and the gate of the 26th NMOS transistor. The source of the 20th NMOS transistor is connected to the gate and drain of the 21st NMOS transistor, the source of the 21st NMOS transistor is connected to the gate and drain of the 22nd NMOS transistor, the source of the 22nd NMOS transistor is connected to the gate and drain of the 23rd NMOS transistor, the source of the 23rd NMOS transistor is connected to the source of the 24th NMOS transistor, and the drain of the 24th NMOS transistor is connected to the source of the 25th NMOS transistor, the source of the 26th NMOS transistor, the source of the 27th NMOS transistor in the switch circuit, and the source of the 28th NMOS transistor.

4. The multi-protocol communication interface chip receiver according to claim 3, characterized in that: The switching circuit comprises: The source of the twenty-seventh NMOS tube and the source of the twenty-eighth NMOS tube are connected to the drain of the twenty-fourth NMOS tube, the source of the twenty-fifth NMOS tube, and the source of the twenty-sixth NMOS tube in the switch gate control and clamping circuit, the drain of the twenty-seventh NMOS tube is connected to GND, and the drain of the twenty-eighth NMOS tube is connected to the first end of the input resistor.

5. The multi-protocol communication interface chip receiver according to claim 4, characterized in that: The input resistance includes a first resistance, wherein: A first end of the first resistor is connected to the drain of the twenty-eighth NMOS transistor, and a second end of the first resistor is connected to the input end of the RS232 receiver.

6. The multi-protocol communication interface chip receiver according to claim 5, characterized in that: The RS232 receiver includes an upper clamping circuit, a lower clamping circuit, a protection resistor circuit, and an inverter circuit, wherein: The first end of the protection resistor circuit is the input end of the RS232 receiver. The protection resistor circuit is connected to the input end of the inverter circuit and is connected to the upper clamping circuit and the lower clamping circuit. The protection resistor circuit is used to limit the input current. The inverter circuit, as the threshold circuit of the RS232 receiver, outputs the input voltage after passing through the protection resistor circuit to the module in the chip. The output end of the inverter circuit is the output end of the RS232 receiver. The upper clamping circuit is used to clamp the voltage of the gate common terminal in the inverter circuit within the negative withstand voltage range of the MOS tube, and the lower clamping circuit is used to clamp the voltage of the gate common terminal in the inverter circuit within the positive withstand voltage range of the MOS tube.

7. The multi-protocol communication interface chip receiver according to claim 6, characterized in that: The protection resistor circuit includes a second resistor and a third resistor, wherein: The first end of the second resistor is the first end of the protection resistor circuit and is connected to the input end of the RS232 receiver; the second end of the second resistor is connected to the second end of the third resistor, and the second end of the second resistor and the second end of the third resistor are simultaneously connected to the output end of the lower clamping circuit; the first end of the third resistor is connected to the output end of the upper clamping circuit and the input end of the inverter circuit.

8. The multi-protocol communication interface chip receiver according to claim 7, characterized in that: The lower clamping circuit includes a first NMOS transistor, a second NMOS transistor and a third NMOS transistor, wherein: The gate and drain of the first NMOS transistor serve as the output ends of the lower clamping circuit and are connected to the second end of the second resistor and the second end of the third resistor in the protection resistor circuit. The source of the first NMOS transistor is connected to the gate and drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the gate and drain of the third NMOS transistor, and the source of the third NMOS transistor is connected to GND.

9. The multi-protocol communication interface chip receiver according to claim 8, characterized in that: The upper clamping circuit includes a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor and a fourth resistor, wherein: The source of the fourth NMOS transistor is connected to the first end of the third resistor in the protection resistor circuit and the input end of the inverter circuit as the output end of the upper clamping circuit. The gate of the fourth NMOS transistor is connected to the first end of the fourth resistor. The second end of the fourth resistor is connected to GND. The drain of the fourth NMOS transistor is connected to the drain of the fifth PMOS transistor. At the same time, the drain of the fourth NMOS transistor is connected to the gates of the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor. The source of the fifth PMOS transistor is connected to the drain of the sixth PMOS transistor. The source of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor. The source of the seventh PMOS transistor is connected to VCC.

10. The multi-protocol communication interface chip receiver according to claim 9, characterized in that: The inverter circuit includes an eighth NMOS transistor, a ninth PMOS transistor and a first inverter, wherein: The gate of the eighth NMOS transistor and the gate of the ninth PMOS transistor serve as input terminals of the inverter circuit and are connected to the first terminal of the third resistor in the protection resistor circuit and the output terminal of the upper clamping circuit. The source of the eighth NMOS transistor is connected to GND, the source of the ninth PMOS transistor is connected to VCC, the drain of the eighth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the input terminal of the first inverter is connected to the drain of the eighth NMOS transistor and the drain of the ninth PMOS transistor. The output terminal of the first inverter serves as the output terminal of the RS232 receiver.

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