A method and system for improving I2C bus read and write efficiency and reliability

Abstract

The present invention discloses a method and system for improving the read and write efficiency and reliability of an I2C bus, and relates to the field of I2C bus communication technology. The present invention adjusts the reading process of the I2C bus, and performs mode selection before the I2C bus starts working to determine a read operation or a write operation. This not only avoids the redundant operation of performing a pseudo-write during the read operation, simplifies the communication process, greatly reduces the timing delay of the read operation, improves the communication efficiency and data transmission rate of the bus, but also makes it unnecessary for the device address to reserve one bit for the read mode or the write mode, so that the device address covers all 8 bits, greatly increases the address space utilization of the bus, and greatly enhances the scalability and flexibility of the I2C bus when connecting a large number of devices. After the read and write data interaction is completed, the present invention also performs parity data checking to achieve error detection, thereby ensuring the stability of communication transmission.

Description

Technical Field

[0001] The present invention relates to the field of I2C bus communication technology, and more specifically to: 1. a method for improving the read and write efficiency and reliability of an I2C bus; 2. a system for improving the read and write efficiency and reliability of an I2C bus. Background Art

[0002] The I2C bus is a commonly used serial communication protocol used in CMOS (image sensor) interface circuits. The I2C bus uses two wires for communication: a data line (SDA) and a clock line (SCL). The host synchronizes data transmission by controlling the clock line, while data is transmitted bit by bit on the data line. This communication method is simple and low-cost, as it requires only a few pins to enable communication between multiple devices, significantly conserving chip pin resources. Furthermore, the I2C bus supports multi-master and multi-slave communication mode, allowing multiple masters and slaves to share the same bus. Address recognition is used to distinguish between different devices, providing high communication flexibility.

[0003] See Figure 1 When executing a read, the traditional I2C bus must first perform a write device address operation (that is, a dummy write is required) before executing the read device address operation, which increases the complexity and time overhead of the communication process, and there is room for improvement in read and write efficiency; and the traditional I2C bus is prone to limited address resources in multi-device scenarios, and data is easily interfered with during transmission, resulting in low reliability. Summary of the Invention

[0004] Based on this, it is necessary to provide a method and system for improving the read and write efficiency and reliability of the I2C bus to address the problems of the traditional I2C bus read and write efficiency, limited address resources, and low reliability.

[0005] The present invention is achieved by adopting the following technical solutions:

[0006] In a first aspect, the present invention discloses a method for improving the read and write efficiency and reliability of an I2C bus, comprising:

[0007] Step 1: Select the mode before the I2C bus starts working;

[0008] If the mode is selected as a write operation, proceed to step 2 after the I2C bus starts working;

[0009] If the mode is selected as a read operation, proceed to step 3 after the I2C bus starts working;

[0010] Step 2: The host and the slave exchange device address, unit address 1, unit address 2, write data, and parity check through the I2C bus until the I2C bus operation is completed.

[0011] Step 3: The host and the slave exchange device address, unit address 1, unit address 2, read data, and parity check through the I2C bus until the I2C bus operation is completed.

[0012] The device address has an 8-bit specification; the unit address 1 and unit address 2 have high 8 bits and low 8 bits, respectively.

[0013] This method of improving the read and write efficiency and reliability of the I2C bus implements the method or process according to the embodiment of the present disclosure.

[0014] In a second aspect, the present invention discloses a system for improving the read and write efficiency and reliability of an I2C bus, comprising: an I2C bus and a selection circuit.

[0015] The system for improving the read and write efficiency and reliability of the I2C bus uses the method for improving the read and write efficiency and reliability of the I2C bus disclosed in the first aspect.

[0016] The system for improving the read and write efficiency and reliability of the I2C bus implements the method or process according to the embodiments of the present disclosure.

[0017] In a third aspect, the present invention discloses a computer program product, comprising a computer program. When executed by a processor, the computer program implements the steps of the method for improving the read and write efficiency and reliability of the I2C bus as disclosed in the first aspect.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. The present invention adjusts the read process of the I2C bus. Before the I2C bus starts working, a mode selection is performed to determine whether the read operation or the write operation is performed. This not only avoids the redundant operation of performing a pseudo-write during the read operation, simplifies the communication process, significantly reduces the timing delay of the read operation, and improves the communication efficiency and data transmission rate of the bus. In addition, the device address no longer needs to reserve one bit for the read mode or the write mode, so that the device address covers all 8 bits, greatly increasing the address space utilization of the bus and greatly enhancing the scalability and flexibility of the I2C bus when connecting a large number of devices. After the read and write data exchanges are completed, the present invention also performs parity data checking to achieve error detection and ensure the stability of communication transmission.

[0020] 2. The present invention designs a selection circuit, which is constructed based on components such as a D flip-flop, an inverter, a switch, and an AND gate. It cleverly utilizes the clock synchronization capability, data storage function, low power consumption, and high reliability of the D flip-flop, which not only achieves precise control of data read and write operations, but also reduces circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 It is a flow chart of the traditional I2C bus in the background technology;

[0023] Figure 2 Flowchart of a method for improving I2C bus read and write efficiency and reliability provided in Example 1 of the present invention;

[0024] Figure 3 A structural diagram of the I2C bus provided in Example 1 of the present invention;

[0025] Figure 4 A signal sequence diagram of a method for improving I2C bus read and write efficiency and reliability provided in Example 1 of the present invention;

[0026] Figure 5 This is a circuit diagram of the selection circuit provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0028] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] First, see Figure 1 , which shows the process of reading and writing operations on the traditional I2C bus.

[0031] 1. The write operation process of the traditional I2C bus can be summarized as follows:

[0032] Start → 8-bit write device address interaction → upper 8-bit unit address interaction → lower 8-bit unit address interaction → write data interaction → end.

[0033] It should be noted that the 8-bit write device address includes: 7-bit device address and 1-bit write mode (0).

[0034] 2. The read operation process of the traditional I2C bus can be summarized as follows:

[0035] Start → 8-bit write device address interaction → upper 8-bit unit address interaction → lower 8-bit unit address interaction → 8-bit read device address interaction → write data interaction → end.

[0036] It should be noted that the 8-bit write device address interaction in the traditional I2C bus read operation process is the pseudo write mentioned in the background art. Similar to the 8-bit write device address, the 8-bit read device address includes: 7-bit device address and 1-bit read mode (1).

[0037] Therefore, the traditional I2C bus has a six-step write operation process and a seven-step read operation process, lacking a process to ensure data transmission reliability. Furthermore, the last bit of the 8-bit write and 8-bit read device addresses controls write and read operations. This reduces the device address from 8 bits to 7 bits, limiting the number of controllable addresses to 128, and reducing address space utilization.

[0038] Based on the above analysis, the present invention is designed from the perspective of changing the read and write mode operation and adding data verification to obtain a method and system for improving the read and write efficiency and reliability of the I2C bus.

[0039] Example 1

[0040] refer to Figure 1 , shows a flow chart of the method for improving the read and write efficiency and reliability of the I2C bus provided in this embodiment 1. In general, see Figure 2, this method comprises the following steps:

[0041] Step 1: Select the mode before the I2C bus starts working;

[0042] If the mode is selected as a write operation, proceed to step 2 after the I2C bus starts working;

[0043] If the mode is selected as a read operation, then step 3 is performed after the I2C bus starts working.

[0044] Step 2: The host and the slave perform device address interaction, unit address one interaction, unit address two interaction, write data interaction, and parity check interaction through the I2C bus in sequence until the I2C bus operation is completed.

[0045] Step 3: The host and the slave perform device address interaction, unit address one interaction, unit address two interaction, data reading interaction, and parity check interaction through the I2C bus in sequence until the I2C bus operation is completed.

[0046] Among them, the specifications of unit address 1 and unit address 2 are high 8 bits and low 8 bits respectively;

[0047] It should be noted that since step one performs mode selection to determine whether the subsequent operation is a read operation or a write operation, if the subsequent operation is a read operation, there is no need to perform a dummy write (i.e., the operation of writing the device address is reduced), which significantly simplifies the communication process, reduces the complexity of communication, and greatly reduces the timing delay of the read operation.

[0048] Moreover, regardless of whether the subsequent operation is a read operation or a write operation, there is no need to reserve one bit for read mode or write mode in the device address interaction, so that the device address specification is restored to 8 bits, and the number of controllable device addresses is increased from 128 to 256, which improves the address space utilization of the bus and greatly enhances the scalability and flexibility of the system when connecting a large number of devices.

[0049] In step 2 and step 3, after the read and write data interactions are completed, the method performs parity data checking to achieve error detection, effectively ensuring the stability of communication transmission.

[0050] In order to further illustrate the operating mechanism of this method, this embodiment 1 provides Figure 3 The I2C bus structure diagram shown in Figure 4 Signal sequence diagram of the method described.

[0051] See Figure 3 The I2C bus is equipped with two double-pole single-throw switches S2~S3 for response mode selection.

[0052] S2 and S3 are set in parallel. Figure 3As shown, the I2C bus includes one data line, SDA, and one clock line, SCL. Input 1 of S2 is connected to the I2C bus's clock line, SCL, forming a connection node, I1. Input 2 is connected to the I2C bus's data line, SDA, forming a connection node, I2. Output 1 is connected to SCL, forming a connection node, O1. Output 2 is connected to SDA, forming a connection node, O2. Input 1 of S3 is connected to SCL, forming a connection node, I3. Input 2 is connected to SDA, forming a connection node, I4. Output 1 is connected to SCL, forming a connection node, O3. Output 2 is connected to SDA, forming a connection node, O4.

[0053] It should be noted that I1, I3, O3, and O1 are set in sequence; I2, I4, O4, and O2 are set in sequence.

[0054] Then, when both S2 and S3 are disconnected, the I2C bus does not work;

[0055] When S2 is closed and S3 is open, the I2C bus is used for write operations; when S2 is open and S3 is closed, the I2C bus is used for read operations; this can avoid interference between read and write operations.

[0056] Of course, S2 and S3 can be replaced by two synchronously working single-pole single-throw switches to achieve the above operation.

[0057] It should be noted that S2 and S3 can be directly controlled to achieve mode selection; or a selection circuit can be used to adjust S2 and S3 in combination with the signal change of SDA to achieve mode selection. The selection circuit is described in Example 2 and will not be expanded here.

[0058] Then, based on Figure 3 The I2C bus shown is as follows Figure 4 The signal sequence is:

[0059] 1. Before the I2C bus starts working, S2 and S3 are both disconnected;

[0060] If S2 is closed and S3 is open, the mode selection is write operation:

[0061] 101, the host sends an 8-bit device address to the slave. After receiving the 8-bit device address, the slave returns a response signal ACK1 to the host. The host receives ACK1, and the device address interaction is completed.

[0062] 102. The host sends the upper 8 bits of the unit address 1 to the slave. After receiving the upper 8 bits of the unit address 1, the slave returns a response signal ACK2 to the host. The host receives ACK2, and the unit address 1 interaction is completed.

[0063] 103. The host sends the lower 8 bits of the unit address 2 to the slave. After receiving the lower 8 bits of the unit address 2, the slave returns a response signal ACK3 to the host. The host receives ACK3, and the exchange of the unit address 2 ends.

[0064] 104. The host sends write data to the slave (the host also performs parity check on the write data and generates a parity check code on the host side). After receiving the write data, the slave returns a response signal ACK4 to the host. The host receives ACK4, and the write data interaction is completed.

[0065] 105, the slave performs a parity check on the written data and generates a parity check code on the slave side;

[0066] The slave sends the parity code on the slave side to the host. The host receives the parity code on the slave side and compares it with the parity code on the host side. If the two are consistent, it means that the write data interaction is correct and the I2C bus operation is terminated. Otherwise, the write data interaction is incorrect and the write data interaction is repeated. If the number of times the write data interaction is repeated exceeds the preset threshold, the slave will be sent back to the host. P , then return to re-interact with the device address.

[0067] certainly, P The value can be adjusted according to actual conditions.

[0068] 2. Before the I2C bus starts working, S2 and S3 are both disconnected;

[0069] If S2 is open and S3 is closed, the mode is selected as read operation:

[0070] 201, the host sends an 8-bit device address to the slave. After receiving the 8-bit device address, the slave returns a response signal ACK1 to the host. The host receives ACK1, and the device address exchange is completed.

[0071] 202, the host sends the upper 8 bits of the unit address 1 to the slave. After receiving the upper 8 bits of the unit address 1, the slave returns a response signal ACK2 to the host. The host receives ACK2, and the unit address 1 interaction is completed.

[0072] 203, the host sends the lower 8 bits of the unit address 2 to the slave. After receiving the lower 8 bits of the unit address 2, the slave returns a response signal ACK3 to the host. The host receives ACK3, and the exchange of the unit address 2 ends.

[0073] 204 , the slave sends read data to the master (the slave performs parity check on the read data and generates a parity check code on the slave side). After receiving the read data, the master returns a response signal ACK4 to the slave. The slave receives ACK4, and the read data interaction is completed.

[0074] 205, the host performs a parity check on the read data and generates a parity check code on the host side;

[0075] The slave sends the parity code on the slave side to the host. The host receives the parity code on the slave side and compares it with the parity code on the host side. If the two are consistent, it means that the read data interaction is correct and the I2C bus operation is terminated. Otherwise, the read data interaction is incorrect and the read data interaction is repeated. If the number of times the read data interaction is repeated exceeds the preset threshold, the slave will be sent back to the host. Q , then return to re-interact with the device address.

[0076] certainly, Q The value can be adjusted according to actual conditions.

[0077] In addition, it should be noted that the parity check code generated by the above process is 1 bit, which can reduce transmission consumption when the verification is satisfied.

[0078] Example 2

[0079] This embodiment 2 provides a model switching circuit for regulating S2 and S3 in combination with the signal change of SDA to achieve mode selection.

[0080] like Figure 5 As shown, the model switching circuit includes a main control unit; of course, when automatic reset is required, the model switching circuit may also include a reset unit.

[0081] ① The main control unit is designed to regulate S2 and S3 in combination with the signal changes of SDA. It includes: 4 inverters L1~L4, 1 D flip-flop F1, 1 AND gate A1, and 1 single-pole single-throw switch S1.

[0082] The first end of S1 is connected to SDA and forms a connection node X1, the second end is connected to the input end of L1, and the control end is connected to the output end of A1; the timing control end of F1 is connected to the output end of L1, the D input end is connected to the control signal MODE, and the Q output end is connected to the input end of L2, the input end of L4, and the control end of S3; the output end of L2 is connected to the input end of L3 and the control end of S2; the output end of L3 is connected to input end 1 of A1; the output end of L4 is connected to input end 2 of A1.

[0083] It should be noted that X1, I2, I4, O4, and O2 are set in sequence; F1 is set to pull low to trigger.

[0084] Then, we have:

[0085] Ⅰ. When the I2C bus is not working, S1 is closed and S2 and S3 are open.

[0086] Ⅱ. When SCL is high and SDA jumps from high to low, it means that the I2C bus starts to work. The low jump of SDA will trigger F1, and F1 starts to work.

[0087] If MODE is 0, the Q output of F1 is 0, and the output of L2 is 1, S2 is closed and S3 is open, thereby activating the data write channel, indicating that the mode selection is a write operation. Subsequent operations can be carried out according to the method described in Example 1. It should be noted that F1 is a D flip-flop, and its edge-triggered characteristics ensure that data is written synchronously under the control of SCL, effectively avoiding metastable problems and improving the reliability of data writing.

[0088] If MODE is 1, the Q output of F1 is 1, and the output of L2 is 0, S2 is opened and S3 is closed, thereby activating the read data channel, indicating that the mode is selected as a read operation. Subsequent operations can be carried out in the manner described in Example 1. It should be noted that F1 is a flip-flop, and its stable storage characteristics ensure that data can be stably read from the storage unit during the read operation, avoiding data errors caused by input signal fluctuations.

[0089] In addition, no matter whether MODE is 0 or 1, while controlling S2 and S3, the two inputs of A1 are 0 and 1, and the output is 0, then S1 is disconnected, so that it no longer works during read and write operations to reduce the power consumption of the circuit.

[0090] Of course, S1-S3 can use additional reset signals to control when the I2C bus ends. For example, the control end of S1 is connected to the reset signal Res1, and the control ends of S2-S3 are connected to the reset signal Res2. In this way, when SDA jumps from a low level to a high level, it indicates that the I2C bus has ended. At this time, Res1 is 1 and Res2 is 0, then S1 is closed and S2-S3 are opened, achieving a reset.

[0091] ② The reset section is used to automatically reset S1~S3.

[0092] Among them, in the reset state, S1 is closed, S2 and S3 are open;

[0093] The reset section includes: a D flip-flop F2, an AND gate A2, and an inverter L3;

[0094] The timing control terminal of F2 is connected to SDA and forms a connection node X2, the D input terminal is connected to the power supply VDD, and the Q output terminal is connected to the input terminal 1 of A2; the input terminal 2 of A2 is connected to SCL and forms a connection node X3; the output terminal of A2 is connected to the control terminal of S1 and the input terminal of L3; the output terminal of L3 is connected to the control terminals of S2 and S3.

[0095] It should be noted that I1, I3, O3, O1, and X3 are set in sequence; X1, I2, I4, O4, O2, and X2 are set in sequence; and F2 is set to pull-high trigger.

[0096] That is, the output end of A2 is used to output Res1, and the output end of L3 is used to output Res2.

[0097] Then, we have:

[0098] Ⅲ. When SCL is high and SDA jumps from low to high, it means that the I2C bus work is completed; the high jump of SDA triggers F2, and F2 starts working.

[0099] The Q output of F2 is 1, SCL is high, the output of A2 is 1, S1 is closed; the output of L3 is 0, S2 and S3 are disconnected, thereby achieving reset and waiting for the next I2C work to start.

[0100] In addition, the design of this model switching circuit also fully utilizes the low power consumption and high reliability advantages of the D flip-flop: in the static state, the power consumption of the D flip-flop is almost negligible, which can reduce the power consumption of the entire circuit; at the same time, the simple logical structure and clear working principle of the D flip-flop make it highly reliable in practical applications and can work stably in complex circuit environments.

[0101] Example 3

[0102] This embodiment 3 provides a system for improving the read and write efficiency and reliability of the I2C bus, which uses the method for improving the read and write efficiency and reliability of the I2C bus provided in embodiment 1.

[0103] The system for improving the read and write efficiency and reliability of an I2C bus includes: the I2C bus disclosed in Example 1 and the model switching circuit disclosed in Example 2.

[0104] Since this system uses the method for improving the read and write efficiency and reliability of the I2C bus in Example 1 and the model switching circuit in Example 2, it also has the same effect and will not be repeated here.

[0105] Example 4

[0106] This embodiment 4 discloses a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the steps of the method for improving the read and write efficiency and reliability of the I2C bus disclosed in embodiment 1.

[0107] Computer devices can be either mobile or fixed terminals. Examples of the former include mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals). Examples of the latter include digital TVs and desktop computers.

[0108] This embodiment 4 also discloses a readable storage medium, which stores computer program instructions. When the computer program instructions are read and executed by a processor, the steps of the method for improving the read and write efficiency and reliability of the I2C bus disclosed in embodiment 1 are executed.

[0109] Among them, the readable storage medium may include, but is not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0110] This embodiment 4 further discloses a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the method for improving the read and write efficiency and reliability of the I2C bus disclosed in embodiment 1 are implemented.

[0111] It should be noted that the computer program for executing the above-mentioned instructions can be written in one or more programming languages, or a combination thereof. These programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar programming languages. The above-mentioned computer program can be executed entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN). The above-described embodiments represent only a few implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art will be able to make numerous variations and modifications without departing from the spirit of the present invention, and these variations and modifications fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for improving I2C bus read and write efficiency and reliability, characterized by: It includes: Step 1: Select the mode before the I2C bus starts working; The I2C bus is equipped with two double-pole single-throw switches S2 and S3. S2 and S3 are connected in parallel. When both S2 and S3 are disconnected, the I2C bus does not work. When S2 is closed and S3 is disconnected, the I2C bus is used for write operations. When S2 is disconnected and S3 is closed, the I2C bus is used for read operations. If the mode is selected as a write operation, proceed to step 2 after the I2C bus starts working; If the mode is selected as a read operation, proceed to step 3 after the I2C bus starts working; Step 2: The host and the slave exchange device address, unit address 1, unit address 2, write data, and parity check through the I2C bus until the I2C bus operation is completed. Step 3: The host and the slave exchange device address, unit address 1, unit address 2, read data, and parity check through the I2C bus until the I2C bus operation is completed. The device address has an 8-bit specification; the unit address 1 and unit address 2 have high 8 bits and low 8 bits, respectively.

2. The method for improving I2C bus read / write efficiency and reliability according to claim 1, wherein: Input terminal 1 of S2 is connected to the clock line SCL of the I2C bus and forms a connection node I1, input terminal 2 is connected to the data line SDA of the I2C bus and forms a connection node I2, output terminal 1 is connected to SCL and forms a connection node O1, and output terminal 2 is connected to SDA and forms a connection node O2; Input terminal 1 of S3 is connected to SCL and forms a connection node I3, input terminal 2 is connected to SDA and forms a connection node I4, output terminal 1 is connected to SCL and forms a connection node O3, output terminal 2 is connected to SDA and forms a connection node O4; Among them, I1, I3, O3, and O1 are set in sequence; I2, I4, O4, and O2 are set in sequence.

3. The method for improving I2C bus read / write efficiency and reliability according to claim 2, wherein: In S1, a selection circuit is used in combination with the signal change of SDA to regulate S2 and S3 to achieve mode selection.

4. The method for improving I2C bus read / write efficiency and reliability according to claim 3, wherein: The selection circuit includes: a main control unit; the main control unit includes: four inverters L1 to L4, a D flip-flop F1, an AND gate A1, and a single-pole single-throw switch S1; The first end of S1 is connected to SDA and forms a connection node X1. The second end is connected to the input end of L1, and the control end is connected to the output end of A1. The timing control end of F1 is connected to the output end of L1, the D input end is connected to the control signal MODE, and the Q output end is connected to the input end of L2, the input end of L4, and the control end of S3. The output end of L2 is connected to the input end of L3 and the control end of S2. The output end of L3 is connected to the input end 1 of A1; the output end of L4 is connected to the input end 2 of A1. X1, I2, I4, O4, and O2 are set in sequence. F1 is a pull-down trigger. When MODE is 0, the mode is selected as a write operation; when MODE is 1, the mode is selected as a read operation.

5. The method for improving the read / write efficiency and reliability of the I2C bus according to claim 4, wherein: The selection circuit further includes: a reset unit, which is used to automatically reset S1 to S3; wherein, in the reset state, S1 is closed, and S2 and S3 are open; The reset section includes: a D flip-flop F2, an AND gate A2, and an inverter L3; The timing control end of F2 is connected to SDA and forms a connection node X2, the D input end is connected to the power supply VDD, and the Q output end is connected to the input end 1 of A2; the input end 2 of A2 is connected to SCL and forms a connection node X3; the output end of A2 is connected to the control end of S1 and the input end of L3; the output end of L3 is connected to the control ends of S2 and S3; I1, I3, O3, O1, and X3 are set in sequence; X1, I2, I4, O4, O2, and X2 are set in sequence; F2 is a pull-up trigger.

6. The method for improving I2C bus read / write efficiency and reliability according to claim 1, wherein: In step 2, when writing data, the host performs parity check on the written data and generates a parity check code on the host side; Methods for parity interaction include: After completing the write data interaction, the slave performs parity check on the written data and generates a parity check code on the slave side; The slave sends the parity code on the slave side to the master. The master receives the parity code on the slave side and compares it with the parity code on the master side. If the two are consistent, it means that the write data interaction is correct. Otherwise, the write data interaction is incorrect and returns to retry the write data interaction. If the number of times the data is written again exceeds the preset threshold, P , then return to re-interact with the device address.

7. The method for improving I2C bus read / write efficiency and reliability according to claim 1, wherein: In step 3, when reading data, the slave performs parity check on the read data and generates a parity check code on the slave side; Methods for parity interaction include: After completing the read data interaction, the host performs parity check on the read data and generates a parity check code on the host side; The slave sends the parity code on the slave side to the master. The master receives the parity code on the slave side and compares it with the parity code on the master side. If the two are consistent, it means that the read data interaction is correct. Otherwise, the read data interaction is incorrect and returns to repeat the read data interaction. If the number of read data interactions exceeds the preset threshold, Q , then return to re-interact with the device address.

8. A system for improving I2C bus read and write efficiency and reliability, characterized in that: It includes: An I2C bus and a selection circuit use the method for improving the reading and writing efficiency and reliability of the I2C bus according to any one of claims 3 to 7.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for improving the read and write efficiency and reliability of the I2C bus are implemented as described in any one of claims 1 to 7.

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