A method for reducing reverse recovery loss of a bidirectional conduction GaN power device

Abstract

The application provides a method for reducing reverse recovery loss of a bidirectional conduction GaN power device, and belongs to the technical field of chip design. The application analyzes the Miller capacitance value generated in the gate-drain overlapping area through finite element simulation. Then, gate and drain structures with different sizes are designed, the spacing parameters are accurately controlled, and the overlapping rate is calculated. A double field plate structure is adopted, and Nash equilibrium game model is applied to analyze the relationship between the field plate length and the parasitic capacitance. A multi-finger gate structure is used to reduce the gate resistance value per unit area and disperse the parasitic capacitance. The reverse recovery characteristics are measured through a test circuit, the capacitance charging and discharging current waveform is analyzed, and the influence factor of the parasitic capacitance on the reverse recovery loss is calculated. Based on the test data, an optimization model is established, and the parameter decision space is constructed by applying the Pareto optimization method. The reverse recovery loss and the conduction resistance are optimized, and the technical problem of high reverse recovery loss of the bidirectional conduction GaN power device is solved.

Description

Technical Field

[0001] This invention belongs to the field of chip design technology, and more specifically, relates to a method for reducing reverse recovery loss in bidirectional GaN power devices. Background Technology

[0002] Bidirectional gallium nitride (GaN) power devices are widely used in power electronic conversion systems due to their high-frequency switching performance and low on-resistance characteristics. Traditional bidirectional GaN power device design primarily focuses on forward conduction performance and breakdown voltage. By optimizing the device structure to reduce on-resistance and increase breakdown voltage, various technical approaches have emerged, including enhancement-mode high electron mobility transistors (E-HEMTs) and gate-injected transistors (GITs). These devices show great promise for applications in high-frequency power systems, automotive electronics, and industrial control.

[0003] However, traditional GaN power devices suffer from significant power loss during reverse recovery. This is primarily due to the Miller effect generated by the parasitic capacitance (Cgd) between the gate and drain during high-voltage switching, leading to additional current paths and energy consumption during the reverse recovery phase. Particularly in high-frequency switching applications, the proportion of reverse recovery loss to total power loss increases significantly, becoming a bottleneck limiting device efficiency improvements.

[0004] Existing technologies attempt to address this issue by modifying the gate structure or adding field plate structures, but these approaches often compromise the overall solution, making it difficult to maintain low on-resistance while reducing reverse recovery losses. In particular, the lack of a systematic approach for precise control of the gate-drain overlap region, and an in-depth analysis of the relationship between the reverse recovery mechanism and parasitic capacitance, makes it difficult for existing technologies to effectively solve the technical problem of excessively high reverse recovery losses in bidirectional GaN power devices. Summary of the Invention

[0005] In view of this, the present invention provides a method for reducing the reverse recovery loss of bidirectional GaN power devices, which can solve the technical problem of excessive reverse recovery loss in bidirectional GaN power devices in the prior art.

[0006] This invention is implemented as follows: A method for reducing reverse recovery loss in bidirectional GaN power devices includes: establishing an accurate electrical model of the bidirectional GaN power device and analyzing the Miller capacitance value generated in the gate-drain overlap region; designing multiple gate-drain structures, controlling the gate-drain spacing parameter, measuring the parasitic capacitance value, and calculating the ratio of necessary overlap rate to unnecessary overlap rate; using a dual-field plate structure technology to form an optimized electric field distribution region, and analyzing the relationship between the field plate length and parasitic capacitance using a Nash equilibrium game model; utilizing extended gate structure technology to design the gate as a multi-finger structure; constructing a test circuit to measure the reverse recovery characteristics of the device; analyzing the capacitor charging and discharging current waveform; establishing a reverse recovery loss optimization model; preparing device samples and verifying the effectiveness of the optimized structure; iteratively optimizing and finally determining the process parameters to guide the reduction of reverse recovery loss in bidirectional GaN power devices.

[0007] The establishment of an accurate electrical model for a bidirectional gallium nitride power device and the analysis of the Miller capacitance value generated in the gate-drain overlap region refer to the analysis of the Miller capacitance value generated in the gate-drain overlap region through finite element simulation. The Miller capacitance value refers to the negative feedback effect caused by the overlap capacitance between the gate and drain during high-voltage switching. The Miller capacitance value will cause additional current paths to be generated during switching, increasing power loss.

[0008] The design of multiple gate and drain structures, control of gate and drain spacing parameters, measurement of parasitic capacitance values, and calculation of the necessary overlap rate to unnecessary overlap rate ratio refers to precisely controlling the gate and drain spacing parameters from 25μm to 75μm, measuring the corresponding parasitic capacitance values, and calculating the necessary overlap rate to unnecessary overlap rate ratio.

[0009] The necessary overlap ratio refers to the ratio of the minimum overlap area that must be maintained between the gate and drain to the total overlap area in order to ensure the basic electrical characteristics and reliability of bidirectional gallium nitride power devices. The necessary overlap ratio is used to determine the lower limit value of the gate-drain spacing parameter.

[0010] The unnecessary overlap rate refers to the ratio of the reduced overlap area between the gate and drain to the total overlap area through optimized design without affecting the basic function of the device. The unnecessary overlap rate is used to determine the optimization space for the gate-drain spacing parameter.

[0011] The use of dual-field plate structure technology to form an optimized electric field distribution region, and the analysis of the relationship between the field plate length and parasitic capacitance through a Nash equilibrium game model, refers to setting a first field plate and a second field plate with a length of 5μm to 15μm on the source side and the gate side, respectively, to form an optimized electric field distribution region, and analyzing the relationship between the field plate length and parasitic capacitance through a Nash equilibrium game model.

[0012] The Nash equilibrium game model refers to the design of a field plate structure in which reverse recovery performance and pressure resistance are regarded as two rational players, each of whom tries to maximize their own utility function and reach an equilibrium state without cooperation. The Nash equilibrium game model is used to determine the optimal parameter combination of the field plate structure.

[0013] The use of extended gate structure technology to design the gate as a multi-finger structure refers to designing the gate as a multi-finger structure, controlling the gate finger width within the range of 2μm to 6μm, and maintaining the gate finger spacing between 3μm and 8μm, thereby reducing the gate resistance value per unit area and the dispersed parasitic capacitance value.

[0014] The multi-finger structure refers to dividing a single wide gate into multiple parallel narrow gate fingers. By increasing the total perimeter of the gate, the gate resistance per unit area is reduced, and the parasitic capacitance between the gate and the drain is dispersed. The multi-finger structure is used to improve the switching characteristics of the device.

[0015] The construction of the test circuit to measure the reverse recovery characteristics of the device refers to constructing a bidirectional conduction test circuit to measure the reverse recovery time and reverse recovery loss of the device under different structural designs at 350V / 10A operating conditions, and analyzing the carrier migration characteristics through the Coulomb scattering relaxation time equation.

[0016] This invention systematically solves the problem of excessive reverse recovery loss by establishing a precise electrical model, optimizing the gate-drain structure, employing dual-field plate technology, and extending the gate structure. This method precisely controls the gate-drain spacing, scientifically analyzes the ratio of necessary to unnecessary overlap, and combines a Nash equilibrium game model to determine the optimal field plate parameters, forming a complete device structure optimization strategy.

[0017] By employing a multi-finger gate structure design and Coulomb scattering relaxation time analysis, this invention effectively reduces the gate resistance per unit area and disperses parasitic capacitance distribution, significantly reducing power loss caused by the Miller effect. The application of the Pareto optimization method balances the two mutually constraining parameters of reverse recovery loss and on-resistance, achieving comprehensive optimization of device performance. This solves the technical problem of excessively high reverse recovery loss in bidirectional GaN power devices, significantly reducing energy consumption under high-frequency switching conditions and improving device efficiency. Attached Figure Description

[0018] Figure 1 This is a flowchart of the method of the present invention.

[0019] Figure 2 This is a schematic diagram of the overall structure of the bidirectional GaN power device in Example 2.

[0020] Figure 3 This is a schematic diagram of the field plate structure of the bidirectional GaN power device in Example 2.

[0021] Figure 4 This is a top view schematic diagram of the multi-finger gate structure of the bidirectional GaN power device in Example 2.

[0022] Figure 5 This is a cross-sectional schematic diagram of the multi-finger gate structure of the bidirectional GaN power device in Example 2.

[0023] Figure 6 This is a detailed schematic diagram of the gate-drain overlap region of the bidirectional GaN power device in Example 2.

[0024] Figure 7 This is a schematic diagram of the reverse recovery characteristic test circuit for the bidirectional GaN power device in Example 2. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0026] like Figure 1 The diagram shown is a flowchart of a method for reducing reverse recovery loss in a bidirectional GaN power device according to the present invention. This method includes the following steps:

[0027] S01. Finite element analysis: Establish an accurate electrical model of the bidirectional gallium nitride power device, and analyze the Miller capacitance value generated in the gate-drain overlap region through finite element simulation.

[0028] S02. Determine the gate and drain structure: Design multiple gate and drain structures of different sizes, and measure the corresponding parasitic capacitance C by precisely controlling the gate and drain spacing parameter from 25μm to 75μm. gd The value is calculated as the ratio of necessary overlap to unnecessary overlap, where necessary overlap is defined as the percentage of gate-drain overlap area required to maintain the basic function of the device to the total overlap area, and unnecessary overlap is defined as the percentage of overlap area eliminated through structural optimization to the total overlap area.

[0029] S03. Determine the optimal parameter combination: Employ a dual-field plate structure technology, setting a first and second field plate with lengths of 5μm to 15μm on the source and gate sides respectively, forming an optimized electric field distribution region. The relationship between the field plate length and the parasitic capacitance C is analyzed using a Nash equilibrium game model. gd The relationship between the reverse recovery loss E rrThe optimal parameter combination of the field plate structure is determined by finding the optimal solution of the utility functions of both parties, with the pressure resistance capacity as the utility function of the two game participants.

[0030] S04, Gate Structure Extension: Utilizing extended gate structure technology, the gate is designed as a multi-finger structure, with the gate finger width controlled within the range of 2μm to 6μm and the gate finger spacing maintained between 3μm and 8μm, reducing the gate resistance per unit area and the dispersed parasitic capacitance C. gd value;

[0031] S05. Reverse Testing: Construct a bidirectional conduction test circuit to measure the reverse recovery time t of devices with different structural designs under 350V / 10A operating conditions. rr and reverse recovery loss E rr The carrier migration characteristics were analyzed using the Coulomb scattering relaxation time equation.

[0032] S06. Data Analysis: Analyze the capacitor charging and discharging current waveforms during the reverse recovery process, and calculate the parasitic capacitance C under different structural designs. gd Value and reverse recovery loss E rr The correlation coefficient between them is used to obtain the parasitic capacitance C. gd Value of reverse recovery loss E rr Influence factors;

[0033] S07. Optimization Solution: Based on the test data, establish a reverse recovery loss optimization model, construct the parameter decision space using the Pareto optimization method, and simultaneously optimize the reverse recovery loss E. rr With on-resistance R DS(on) Two mutually constraining objectives determine the optimal gate-drain spacing parameters, field plate length parameters, and gate finger structure parameters.

[0034] S08. Experimental verification: Based on the optimized model, bidirectional gallium nitride power device samples with reduced reverse recovery loss were designed and fabricated. The optimal gate-drain spacing parameters, the field plate length parameters, and the gate finger structure parameters were applied to the device fabrication process, and experimental verification was carried out under 350V / 20A conditions.

[0035] S09. Obtaining the optimal process parameters: By comparing and analyzing the total loss of the samples at different switching frequencies, the effectiveness of the optimized structure in reducing the reverse recovery loss E is verified. rr The effectiveness of the verification is evaluated, and the results are fed back to the precise electrical model in step S01 for iterative optimization. Finally, the process parameters are determined to guide the reduction of reverse recovery loss in bidirectional GaN power devices.

[0036] The Miller capacitance value specifically refers to the negative feedback effect caused by the overlap capacitance between the gate and drain during high-voltage switching. This Miller capacitance value can lead to an additional current path during switching, increasing power loss.

[0037] Among them, parasitic capacitance C gd Specifically, the value refers to the numerical value of the parasitic capacitance formed between the gate and drain, wherein the parasitic capacitance C gd The value is obtained by measurement in step S02 and used as a key parameter for structural optimization analysis in steps S03 to S07.

[0038] Among them, the reverse recovery time t rr Specifically, the reverse recovery time t refers to the delay caused by the minority carrier storage effect during the transition of a bidirectional gallium nitride power device from the on state to the off state. rr The value is obtained through testing in step S05 and used to calculate the reverse recovery loss E in step S06. rr .

[0039] Among them, the reverse recovery loss E rr Specifically, it refers to the power loss generated during the reverse recovery process of bidirectional gallium nitride power devices, the reverse recovery loss E rr By measuring the product of the reverse recovery current and the drain-source voltage over the reverse recovery time t... rr The integral obtained within the range is used as the optimization objective in steps S05 to S09.

[0040] Among them, the on-resistance R DS(on) Specifically, it refers to the resistance value between the drain and source of a bidirectional gallium nitride power device in the on-state, the on-resistance R. DS(on) In step S04, it is affected by the gate finger structure, and in step S07, it is used as one of the optimization objectives.

[0041] Specifically, the necessary overlap ratio refers to the ratio of the minimum overlap area that must be maintained between the gate and the drain to the total overlap area in order to ensure the basic electrical characteristics and reliability of bidirectional gallium nitride power devices. The necessary overlap ratio is calculated in step S02 and is used to determine the lower limit value of the gate-drain spacing parameter.

[0042] Specifically, the unnecessary overlap rate refers to the ratio of the reduced overlap area between the gate and drain to the total overlap area through optimized design without affecting the basic function of the device. The unnecessary overlap rate is calculated in step S02 and is used to determine the optimization space for the gate-drain spacing parameter.

[0043] Specifically, the multi-finger structure refers to dividing a single wide gate into multiple parallel narrow gate fingers. By increasing the total perimeter of the gate, the gate resistance per unit area is reduced, while simultaneously dispersing the parasitic capacitance C between the gate and drain. gd The multi-finger structure is designed and implemented in step S04 to improve the switching characteristics of the device.

[0044] The Coulomb scattering relaxation time equation specifically refers to the physical equation describing the scattering behavior of charge carriers in gallium nitride semiconductor materials under a high electric field and its influence on reverse recovery characteristics. The inputs to this equation include five parameters: charge carrier concentration, lattice temperature, impurity concentration, electric field strength, and the dielectric constant of the material. The outputs are the effective mobility of charge carriers and the Coulomb scattering relaxation time. These output parameters are used to analyze the minority carrier recombination rate and parasitic capacitance C during the reverse recovery process. gd The charge and discharge characteristics of the value.

[0045] Specifically, the influencing factor refers to the parasitic capacitance C. gd Value change affects reverse recovery loss E rr The sensitivity coefficient of the change, the influence factor, is obtained by calculation in step S06 and used for weight allocation in step S07.

[0046] Specifically, the Pareto optimization method refers to finding a set of solutions in a multi-objective optimization problem such that improvement in any one objective necessarily leads to the deterioration of at least one other objective. In step S07, the Pareto optimization method is used to simultaneously optimize the back-recovery loss E. rr With on-resistance R DS(on) Two mutually constraining parameters.

[0047] Specifically, the Nash equilibrium game model refers to the design of a field plate structure in which reverse recovery performance and pressure resistance are regarded as two rational players, each of whom tries to maximize their own utility function and reach an equilibrium state without cooperation. The Nash equilibrium game model is used in step S03 to determine the optimal parameter combination of the field plate structure.

[0048] Specifically, the gate-drain spacing parameter refers to the physical distance between the gate edge and the drain edge. The gate-drain spacing parameter is designed in step S02, the optimal value is determined through optimization in step S07, and it is applied to device fabrication in step S08.

[0049] Specifically, the field plate length parameter refers to the physical length values ​​of the first field plate and the second field plate. The field plate length parameter is designed in step S03, the optimal value is determined through optimization in step S07, and it is applied to device fabrication in step S08.

[0050] Specifically, the gate finger structure parameters refer to the numerical combination of gate finger width and gate finger spacing in the multi-finger structure. The gate finger structure parameters are designed in step S04, the optimal value is determined through optimization in step S07, and applied to device fabrication in step S08.

[0051] The specific implementation methods of the above steps are described in detail below.

[0052] The specific implementation of step S01 is as follows: A three-dimensional model of a bidirectional gallium nitride (GaN) power device is constructed using finite element analysis software. First, the device's geometric parameters are imported, including gate width, thickness, drain size, source location, and GaN material layer thickness. Next, material physical parameters are set, including GaN dielectric constant, carrier mobility, saturation velocity, and other physical quantities. Then, a finite element mesh subdivision algorithm is applied to mesh the model, focusing on refining the mesh density in the gate-drain overlap region, with the mesh cell size controlled below 0.1 μm. Subsequently, an electric field distribution calculation model is established, and the potential distribution is calculated using a Poisson equation solver. The electric field distribution in the gate-drain overlap region is determined based on the potential gradient. Finally, the Miller capacitance value is calculated based on the electric field distribution. This capacitance value exhibits a non-linear relationship with the gate-drain voltage; under conditions of a gate voltage of 2V and a drain voltage of 200V, the typical Miller capacitance value ranges from 50 to 120 pF. This step utilizes the finite element method to accurately simulate the electric field distribution in the device and calculate the Miller capacitance, providing a theoretical basis for subsequent structural optimization.

[0053] The specific implementation of step S02 is as follows: six sets of structures with gate-drain spacing distances of 25μm, 35μm, 45μm, 55μm, 65μm, and 75μm are designed, and test samples are fabricated; an impedance analyzer is used to apply a small-signal excitation voltage of 0.1V at a frequency of 1MHz to measure the parasitic capacitance C under different gate-drain spacing distances. gd Value; based on the measurement results, establish the relationship between the gate-drain spacing and the parasitic capacitance C. gd The relationship curve between the values ​​was analyzed; the gate-drain overlap region was analyzed using the electromagnetic field boundary element method, dividing the total overlap area into the necessary overlap region required to maintain basic functions and the unnecessary overlap region that can be eliminated through structural optimization; the ratio of the necessary overlap rate to the unnecessary overlap rate was calculated. When the gate-drain spacing was 45 μm, the necessary overlap rate was approximately 40%, and the unnecessary overlap rate was approximately 60%; based on the calculation results, the optimal range for the gate-drain spacing was determined to be 40–50 μm. This step, through systematic measurement and analysis, determined the influence of the gate-drain spacing on parasitic capacitance, providing data support for structural optimization.

[0054] The specific implementation of step S03 is as follows: A first field plate with lengths of 5μm, 10μm, and 15μm is designed on the source side, and a second field plate with lengths of 5μm, 10μm, and 15μm is designed on the gate side, forming nine different combinations of dual-field plate structures; the electric field distribution under different field plate structures is calculated using electric field simulation software, with a focus on analyzing the electric field peak value and electric field distribution uniformity at the field plate edges; the breakdown voltage and parasitic capacitance C of the device under different field plate structures are measured. gd Value; Establish a Nash equilibrium game model, and determine the reverse recovery loss E. rr The voltage withstand capability is used as the utility function of the first player, and the strategy space for both players is defined as the combination of field plate length parameters. The utility values ​​for both players under each strategy combination are calculated, and a utility matrix is ​​constructed. An iterative approximation algorithm is used to solve for the Nash equilibrium point, yielding a parameter combination where the optimal length of the first field plate is 10 μm and the optimal length of the second field plate is 8 μm. At this point, the peak electric field is reduced by 32%, and the parasitic capacitance C... gd The increase should not exceed 15%. This step uses game theory to analyze the impact of the field plate structure on device performance and finds a balance between withstand voltage and parasitic capacitance.

[0055] The specific implementation of step S04 is as follows: Nine multi-finger gate structures with gate finger widths of 2μm, 4μm, and 6μm, and gate finger pitches of 3μm, 5μm, and 8μm are designed; a layout model of the multi-finger gate is established using semiconductor process design software, and the total gate perimeter under different gate finger structures is calculated; a distributed gate resistor network model is used to analyze the influence of the multi-finger structure on the gate resistance; and the on-resistance R of the device under different gate finger structures is measured. DS(on) and parasitic capacitance C gd Values; using a high-frequency equivalent circuit model, the influence of the multi-finger structure on the parasitic capacitance distribution is analyzed; according to the measurement results, when the gate finger width is 4μm and the gate finger spacing is 5μm, the gate resistance per unit area decreases by 42%, and the parasitic capacitance C gd The optimal dispersion effect results in a 25% increase in switching speed. This step improves device switching performance by optimizing the gate finger structure, reducing gate resistance, and dispersing parasitic capacitance.

[0056] The specific implementation of step S05 is as follows: Design a bidirectional conduction test circuit, including a main circuit power supply, a resistive load, a test sample, and a drive circuit; set the test conditions as follows: drain-source voltage 350V, conduction current 10A, gate-source drive voltage 0V to 15V, and switching frequency 100kHz; use a high-bandwidth oscilloscope and a current probe to measure the drain-source voltage V during the reverse recovery process. DS and drain current I D Waveform; record the reverse recovery time t rr This refers to the time interval from when the reverse current begins to decrease until it drops to 10% of its peak value; the peak reverse recovery current I is measured.rrm and reverse recovery charge Q rr The carrier migration characteristics are analyzed using the Coulomb scattering relaxation time equation, with input parameters including carrier concentration 10. 17 cm -3 lattice temperature 25℃, impurity concentration 5×10 16 cm -3 An electric field strength of 3 MV / cm and a gallium nitride dielectric constant of 8.9 were used to calculate the effective carrier mobility and Coulomb scattering relaxation time, and to analyze the carrier behavior during the reverse recovery process. Measurements were performed on samples with different structural designs, and the reverse recovery characteristic parameters were recorded. This step obtains reverse recovery characteristic data of the device through actual testing, providing a basis for subsequent optimization.

[0057] The specific implementation of step S06 is as follows: Collect the capacitor charging and discharging current waveforms of samples with different structural designs during the reverse recovery process; use a spectrum analyzer to perform a Fourier transform on the current waveforms and analyze their frequency domain characteristics; calculate the reverse recovery loss E based on the current and voltage waveforms. rr That is, the integral of the product of current and voltage over the reverse recovery time; establish the parasitic capacitance C. gd Value and reverse recovery loss E rr The dataset; using the Pearson correlation coefficient method, the parasitic capacitance C is calculated. gd Value and reverse recovery loss E rr The correlation coefficient between them, when the parasitic capacitance C gd When the value varies within the range of 50–150 pF, the correlation coefficient reaches 0.86, indicating a significant positive correlation between the two. Linear regression analysis was used to determine the parasitic capacitance C. gd Value of reverse recovery loss E rr The influence factor is 0.78, i.e., the parasitic capacitance C. gd For every 10% decrease in value, the reverse recovery loss E rr On average, it reduced by 7.8%. This step, through correlation analysis, quantifies the impact of parasitic capacitance on reverse recovery loss, guiding the direction of structural optimization.

[0058] The specific implementation of step S07 is as follows: Integrate the test data obtained in the preceding steps, and establish a system that includes three input variables—gate-drain spacing parameters, field plate length parameters, and gate finger structure parameters—and the reverse recovery loss E. rr and on-resistance R DS(on) A multivariate mathematical model with two output variables is constructed; the response surface methodology is applied to construct the objective function surface in the parameter space; the Pareto optimization method is introduced to optimize the back recovery loss E. rr With on-resistance R DS(on) As two mutually constraining optimization objectives, the reverse recovery loss E is set. rrThreshold not exceeding 100μJ, on-resistance R DS(on) The threshold is no more than 150mΩ; a Pareto optimal solution set is obtained using a multi-objective optimization algorithm, such as a non-dominated sorting genetic algorithm; through decision weight analysis, the optimal parameter combination is determined: gate-drain spacing of 45μm, first field plate length of 10μm, second field plate length of 8μm, gate finger width of 4μm, and gate finger spacing of 5μm. This step utilizes multi-objective optimization theory to find a balance between reverse recovery loss and on-resistance, thus determining the optimal structural parameter combination.

[0059] The specific implementation of step S08 is as follows: Based on the optimal parameters determined in step S07, design the layout of the bidirectional gallium nitride power device; fabricate device samples using standard semiconductor process flows, including epitaxial layer growth, source / drain ion implantation, gate metal deposition, and electrode formation; package the device using a TO-247 package with low parasitic inductance; establish a 350V / 20A test platform, including a high-precision voltage source, electronic load, high-speed drive circuit, and precision measurement equipment; design a test scheme, including static parameter testing and dynamic parameter testing; measure the device's static parameters such as withstand voltage, leakage current, and on-resistance; measure the device's dynamic parameters such as switching time, switching loss, and reverse recovery characteristics; and record the optimized device's reverse recovery time t. rr and reverse recovery loss E rr This step involves preparing actual device samples based on the optimization results and conducting performance testing to verify them.

[0060] The specific implementation of step S09 is as follows: Design a multi-frequency switching test circuit with a frequency range of 50kHz to 500kHz, using the same voltage and current operating conditions; measure the total loss of the optimized structure device and the control device at different switching frequencies; the total loss includes three parts: conduction loss, switching loss, and reverse recovery loss; use a thermal imager to measure the temperature rise of the device to verify the heat loss distribution; analyze the trend of total loss with frequency to verify the advantages of the optimized structure in high-frequency applications; calculate the reverse recovery loss E. rr The proportion of total loss, at 100kHz, is the reverse recovery loss E before optimization. rr The initial loss was 32% of the total loss, which was reduced to 18% after optimization. The test data was compared with the electrical model established in step S01 to analyze the sources of error. Based on the verification results, parameters in the electrical model were corrected, such as the capacitance nonlinearity coefficient and the carrier mobility temperature coefficient. An iterative optimization method was used to run steps S01 to S08 again to further optimize the process parameters. After two rounds of iterative optimization, the optimal combination of process parameters was finally determined: gate-drain spacing of 48 μm, first field plate length of 11 μm, second field plate length of 7 μm, gate finger width of 3.5 μm, and gate finger spacing of 6 μm. At this point, the reverse recovery loss E...rr Reduced by 45%, on-resistance R DS(on) With an increase of only 5%, the overall performance is optimal. This step verifies the optimization effect through experiments, further optimizes the parameters through iterative adjustments, and finally determines the optimal process parameters to guide the production process in reducing the reverse recovery loss of bidirectional GaN power devices.

[0061] The mathematical model or calculation process involved in this invention will be described in detail below.

[0062] In step S01, when establishing an accurate electrical model of the bidirectional gallium nitride power device, the potential distribution is calculated by solving the Poisson equation using the finite element method, as shown below:

[0063]

[0064] In the formula, ε is the gradient operator; ε is the dielectric constant of gallium nitride, with a value of 8.9. ρ is the potential distribution function; ρ is the charge density function.

[0065] The charge density function ρ is determined by the following equation:

[0066] ρ=q(p-n+N D -N A );

[0067] In the formula, q is the elementary charge, with a value of 1.602 × 10⁻⁶. -19 Coulomb; p is hole concentration; n is electron concentration; N D N represents the donor impurity concentration. A This represents the concentration of acceptor impurities.

[0068] Electron and hole concentrations are solved using the carrier continuity equation:

[0069]

[0070] In the formula, J n and J p G represents the current density of electrons and holes, respectively; n and G p R represents the generation rates of electrons and holes, respectively. n and R p These represent the recombination rates of electrons and holes, respectively.

[0071] Current density was calculated using a drift-diffusion model:

[0072]

[0073] In the formula, μ n and μ pThese represent the mobilities of electrons and holes, respectively; D n and D p Here, represents the diffusion coefficients of electrons and holes, respectively, which are related to mobility via the Einstein relation: k B is the Boltzmann constant, with a value of 1.38 × 10⁻⁶. -23 Joules / Kelvin; T is absolute temperature, measured in Kelvin.

[0074] Miller capacitance is calculated using the electric field distribution in the gate-drain overlap region:

[0075]

[0076] In the formula, Q gd V is the charge between the gate and drain. gd denoted as Ω, where Ω is the gate-drain voltage; E is the electric field strength; and S is the area of ​​the gate-drain overlap region.

[0077] The parameters for calculating the Miller capacitance value are obtained as follows: the area S of the gate-drain overlap region is determined through device layout design; the electric field strength E is obtained by solving the Poisson equation using finite element method; and the gate-drain voltage V... gd The voltage is set by applying an external voltage.

[0078] In step S02, the equation for calculating the ratio of necessary overlap rate to unnecessary overlap rate is specifically expressed as follows:

[0079]

[0080] In the formula, η ratio η is the ratio of the necessary overlap rate to the unnecessary overlap rate. essential η is the necessary overlap rate. non-essential Unnecessary overlap rate; A essential The overlap area required to maintain basic functionality; A non-essential A represents the overlap area that can be optimized and eliminated. total This represents the total overlapping area.

[0081] Necessary overlapping area A essential The calculation equation is as follows:

[0082]

[0083] In the formula, C gd，min The minimum parasitic capacitance required to maintain the basic function of the device is determined through circuit simulation; d is the dielectric thickness of the gate-drain overlap region; ε is the dielectric constant of the dielectric.

[0084] Total overlapping area A total Unnecessary overlap area A non-essential The relationship is:

[0085] A total =A essential +A non-essential ;

[0086] The parameters for necessary and unnecessary overlap ratios are obtained as follows: the parasitic capacitance distribution under different gate-drain spacing distances is analyzed using the electromagnetic field boundary element method; the minimum parasitic capacitance value C required to maintain the basic function of the device is determined through circuit simulation. gd，min The geometric dimensions of overlapping areas are obtained through layout measurements.

[0087] In step S03, the Nash equilibrium game model is applied to analyze the relationship between the plate length and the parasitic capacitance C. gd Construct a utility function matrix based on the relationships between them:

[0088]

[0089] In the formula, U is the utility function matrix; This represents the i-th strategy of the first player (reverse recovery loss), corresponding to the first field plate length values ​​of 5μm, 10μm, and 15μm; This represents the j-th strategy of the second player (resilience), corresponding to the second field plate length values ​​of 5μm, 10μm, and 15μm; Indicates the strategy chosen by both sides in the game. The utility value at that time.

[0090] The utility function of the first player (reverse recovery loss) is:

[0091]

[0092] In the formula, For the first player in the strategy combination The utility value below; E represents the reverse recovery loss under the corresponding strategy. rr，max and E rr，min These are the maximum and minimum values ​​of the reverse recovery loss, respectively; C represents the parasitic capacitance value under the corresponding strategy. gd，max and C gd，min α1 and β1 are the maximum and minimum values ​​of the parasitic capacitance, respectively; α1 and β1 are weighting coefficients, satisfying α1 + β1 = 1.

[0093] The utility function of the second player (resilience) is:

[0094]

[0095] In the formula, For the second player in the strategy combination The utility value below; BV represents the breakdown voltage under the corresponding strategy. max and BV min These are the maximum and minimum breakdown voltages, respectively. E represents the peak electric field under the corresponding strategy. peak，max and E peak，min α and β are the maximum and minimum values ​​of the electric field peak, respectively; α2 and β2 are weighting coefficients, satisfying α2 + β2 = 1.

[0096] The equation for solving the Nash equilibrium point is:

[0097] For any s1∈S1;

[0098] For any s2∈S2;

[0099] In the formula, S1 represents the Nash equilibrium point; S2 and S1 represent the strategy sets of the two players, respectively.

[0100] The method for obtaining the parameters of the Nash equilibrium game model is as follows: calculate the electric field distribution and breakdown voltage under different field plate structures using electric field simulation software; measure the reverse recovery loss and parasitic capacitance under different field plate structures using a test circuit; and determine the values ​​of the weighting coefficients α1, β1, α2, and β2 through expert evaluation. By default, α1 = α2 = 0.618 and β1 = β2 = 0.382.

[0101] In step S04, the effect of the multi-finger structure on the gate resistance is calculated using a distributed resistor network model:

[0102]

[0103] In the formula, R gate ρ is the total gate resistance; g L represents the resistivity of the gate metal. g W is the gate lead length. g t is the gate lead width; g R is the gate metal thickness; contact Contact resistance; L finger Where n is the gate finger length; n is the gate finger quantity; W finger This refers to the width of the gate.

[0104] Multi-finger structure affects parasitic capacitance C gd The dispersion effect is calculated using the following equation:

[0105]

[0106] In the formula, C gd，total C is the total parasitic capacitance. gd，iC is the parasitic capacitance corresponding to the i-th gate finger; gd，unit The parasitic capacitance per unit gate finger is related to the gate finger width and gate finger spacing.

[0107] Unit gate finger parasitic capacitance C gd，unit The relationship with the gate finger structure parameters is as follows:

[0108]

[0109] In the formula, A overlap W represents the overlap area between the unit gate finger and the drain. finger L is the gate width; overlap d is the overlap length between the gate finger and the drain; gd The dielectric thickness between the gate and drain.

[0110] The method for obtaining parameters of the multi-finger structure is as follows: establish a layout model of the multi-finger gate using semiconductor process design software, and measure the geometric dimensions of the gate fingers; measure the gate resistance using a resistance tester; and measure the parasitic capacitance using an impedance analyzer.

[0111] In step S05, the Coulomb scattering relaxation time equation is used to analyze carrier migration characteristics:

[0112]

[0113] In the formula, τ c m is the Coulomb scattering relaxation time; * ε is the effective mass of charge carriers; k is the semiconductor dielectric constant; ε is the effective mass of charge carriers; ε is the effective mass of charge carriers; k is the effective mass of charge carriers ... B Where is Boltzmann constant; T is absolute temperature; q is elementary charge; n is carrier concentration; β is shielding parameter, calculated by the following formula:

[0114]

[0115] In the formula, E F It is the Fermi level and is related to the carrier concentration.

[0116] Effective carrier mobility is calculated using relaxation time:

[0117]

[0118] In the formula, μ is the effective carrier mobility.

[0119] Considering the high electric field effect, the carrier mobility is corrected as follows:

[0120]

[0121] In the formula, μ e V is the effective mobility under high electric field; μ0 is the mobility under low electric field; E is the electric field strength; vsat This represents the carrier saturation velocity.

[0122] The parameters of the Coulomb scattering relaxation time equation are obtained as follows: carrier concentration n is determined by Hall effect measurement; lattice temperature T is measured by thermocouple; impurity concentration is measured by secondary ion mass spectrometry; electric field strength E is calculated through device simulation; gallium nitride dielectric constant is taken as 8.9; and effective carrier mass m... * Take 0.2 times the electron rest mass; carrier saturation velocity v sat Take 2.5 × 10 7 cm / s.

[0123] In step S06, the reverse recovery loss E rr Calculated by the following integral:

[0124]

[0125] In the formula, V DS (t) represents the drain-source voltage during the reverse recovery process; I D (t) represents the drain current during the reverse recovery process; t rr This is the reverse recovery time.

[0126] Parasitic capacitance C gd Value and reverse recovery loss E rr The correlation coefficient between them is calculated using the Pearson formula:

[0127]

[0128] In the formula, r is the correlation coefficient; C gd，i Let be the parasitic capacitance value of the i-th sample; E represents the average value of the parasitic capacitance. rr，i Let be the reverse recovery loss of the i-th sample; is the average value of the reverse recovery loss; m is the number of samples.

[0129] Parasitic capacitance C gd Value of reverse recovery loss E rr The influencing factors were determined through linear regression analysis:

[0130] E rr =k·C gd +b+ε;

[0131] In the formula, k is the influence factor; b is a constant term; and ε is the error term, which ranges from ±5%.

[0132] The correlation coefficient and influencing factor parameters were obtained by measuring the parasitic capacitance and reverse recovery loss of samples with different structural designs using a test circuit; and by performing correlation analysis and linear regression analysis using statistical software.

[0133] In step S07, the Pareto optimization method is used to simultaneously optimize the reverse recovery loss E. rr and on-resistance R DS(on) :

[0134] The objective function to be optimized is:

[0135] minF(x)=[minf1(x), minf2(x)];

[0136] In the formula, F(x) is a multi-objective optimization function; f1(x) = E rr f(x) is the objective function for reverse recovery loss; f2(x) = R DS(on) (x) is the objective function for on-resistance; x is the design parameter vector, x = [d gd L fp1 L fp2 W finger S finger ], where d gd L is the gate-drain spacing. fp1 L is the length of the first plate. fp2 W is the length of the second plate. finger S is the gate width. finger This represents the grid finger spacing.

[0137] The constraints are:

[0138] 25μm≤d gd ≤75μm;

[0139] 5μm≤L fp1 ≤15μm;

[0140] 5μm≤L fp2 ≤15μm;

[0141] 2μm≤W finger ≤6μm;

[0142] 3μm≤S finger ≤8μm;

[0143] E rr (x)≤E rr，threshold =100μJ;

[0144] R DS(on) (x)≤R DS(on)，threshold =150mΩ;

[0145] The Pareto solution set is defined as:

[0146] If there does not exist x′∈Ω such that And there exists at least one j∈{1,2} such that fj (x′) <f j If (x), then x is the Pareto optimal solution, and Ω is the feasible solution space.

[0147] The method for obtaining Pareto optimal parameters is as follows: establish a relationship model between design parameters and objective function using response surface methodology; and solve for the Pareto optimal solution set using multi-objective optimization algorithms, such as non-dominated sorting genetic algorithms.

[0148] The construction principle and significance of the above equations are as follows:

[0149] 1. The Poisson equation is used to calculate the potential distribution. Its principle is that the electric field divergence is proportional to the charge density. It takes into account the spatial variation of the dielectric constant and can accurately reflect the electric field distribution at the interface of different materials. It is suitable for analyzing the electric field distribution of GaN devices with heterostructures.

[0150] 2. The carrier continuity equation takes into account the generation, recombination, and transport processes of electrons and holes, enabling the model to reflect the transient behavior of carriers in semiconductors. This is crucial for understanding the dynamic changes of minority carriers during reverse recovery.

[0151] 3. The Miller capacitance calculation equation is based on the definition of capacitance and calculates the capacitance value from the microscopic charge distribution. It is more accurate than the traditional parallel plate capacitance model and can reflect the nonlinear characteristics of capacitance.

[0152] 4. The equation for calculating the ratio of necessary overlap to unnecessary overlap quantifies the optimization space, provides direction and limits for structural optimization, and helps determine the optimal range of gate-drain spacing.

[0153] 5. The Nash equilibrium game model treats reverse recovery performance and resilience as two players, quantitatively describes the trade-off between them through a utility function, and finds the equilibrium point where neither can be improved alone. It is suitable for solving multi-objective optimization problems.

[0154] 6. The distributed resistor network model considers the contribution of the resistance of each part in the multi-finger structure, can accurately calculate the gate resistance of complex structures, and guide the design of gate finger structures.

[0155] 7. The Coulomb scattering relaxation time equation describes the carrier scattering process from a microphysical perspective, taking into account the effects of carrier concentration, temperature, and electric field strength on mobility. It can accurately predict carrier migration characteristics under high electric fields and is crucial for understanding carrier behavior in the reverse recovery process.

[0156] 8. The Pearson correlation coefficient calculation equation quantifies the degree of linear correlation between two variables, helps determine the strength of the relationship between parasitic capacitance and reverse recovery loss, and guides the direction of structural optimization.

[0157] 9. The Pareto optimization method seeks the optimal balance point among multiple mutually constraining objectives. It is suitable for simultaneously optimizing the two contradictory objectives of reverse recovery loss and on-resistance, and finally obtains the design parameter combination with the best overall performance.

[0158] Specifically, the principle of this invention is as follows: The principle of reducing reverse recovery loss in bidirectional GaN power devices is based on the precise analysis and optimization of the relationship between device structural parameters and electrical characteristics. The energy loss in the reverse recovery process of bidirectional GaN power devices mainly originates from the charging and discharging process of the parasitic capacitance Cgd between the gate and drain. During high-voltage switching, this parasitic capacitance generates an additional current path through the Miller effect, leading to increased power loss. Therefore, this invention, by precisely controlling the structural parameters of the gate and drain, specifically reduces unnecessary overlap areas, fundamentally reducing the parasitic capacitance value.

[0159] The design principle of the dual-field plate structure lies in optimizing the electric field distribution of the device. The first and second field plates form extended regions on the source and gate sides, making the electric field distribution more uniform and reducing electric field concentration between the gate and drain. This redistribution of the electric field reduces parasitic capacitance in the space charge region while maintaining the device's breakdown voltage. This invention innovatively applies a Nash equilibrium game model, treating reverse recovery loss and breakdown voltage as two competing objectives to find the optimal balance point, ensuring that parasitic capacitance is reduced without sacrificing the device's fundamental performance.

[0160] The multi-finger gate structure is another key principle of this invention. By dividing a single wide gate into multiple narrow gate fingers, the total perimeter of the gate is increased, effectively reducing the gate resistance per unit area. Simultaneously, this structure disperses the parasitic capacitance Cgd, reducing local electric field concentration and mitigating the Miller effect. Precise control of the gate finger width and spacing creates an optimal electric field distribution pattern, further optimizing the device's switching characteristics.

[0161] This invention establishes a mathematical model relating reverse recovery loss and parasitic capacitance, and analyzes carrier migration characteristics using the Coulomb scattering relaxation time equation, thus revealing the physical mechanism of the reverse recovery process. The application of the Pareto optimization method enables the finding of the optimal solution in multi-parameter, multi-objective optimization problems, maintaining low on-resistance while reducing reverse recovery loss, achieving a comprehensive improvement in device performance. Finally, experimental verification and feedback iteration ensure the effectiveness and reliability of the optimization method.

[0162] The following provides a specific embodiment 1 of the present invention, and the specific implementation of each step in this embodiment 1 is described in detail below.

[0163] The specific implementation of step S01 is as follows: A three-dimensional model of a bidirectional gallium nitride power device is constructed using finite element analysis software. First, the device's geometric parameters are imported, including gate width, thickness, drain size, source location, and gallium nitride material layer thickness. Next, material physical parameters are set, including gallium nitride dielectric constant, carrier mobility, saturation velocity, and other physical quantities. Then, a finite element mesh subdivision algorithm is applied to mesh the model, focusing on refining the mesh density in the gate-drain overlap region, with the mesh cell size controlled below 0.1 μm. Subsequently, an electric field distribution calculation model is established, and the potential distribution is calculated using a Poisson equation solver. Its mathematical expression is: In the formula, Here, ε is the gradient operator, and ε is the dielectric constant of gallium nitride, with a value of 8.9. Let ρ be the potential distribution function, and ρ be the charge density function; the charge density function is determined by the following equation: ρ=q(p-n+N) D -N A In the formula, q is the elementary charge, with a value of 1.602 × 10⁻⁶. -19 Coulomb, p is the hole concentration, n is the electron concentration, N D N represents the donor impurity concentration. A The acceptor impurity concentration is given; the electron and hole concentrations are solved using the carrier continuity equation. and In the formula, J n and J p G represents the current density of electrons and holes, respectively. n and G p R represents the generation rates of electrons and holes, respectively. n and R p These are the recombination rates of electrons and holes, respectively; the Miller capacitance is calculated using the electric field distribution, and its formula is as follows: In the formula, Q gd V is the amount of charge between the gate and drain. gd Let E be the gate-drain voltage, E be the electric field strength, and S be the area of ​​the gate-drain overlap region. Based on the calculation results, under the conditions of a gate voltage of 2V and a drain voltage of 200V, the typical Miller capacitance ranges from 50 to 120pF. This step utilizes the finite element method to accurately simulate the electric field distribution in the device and calculate the Miller capacitance, providing a theoretical basis for subsequent structural optimization.

[0164] The specific implementation of step S02 is as follows: six sets of structures with gate-drain spacing distances of 25μm, 35μm, 45μm, 55μm, 65μm, and 75μm are designed, and test samples are fabricated; an impedance analyzer is used to apply a small-signal excitation voltage of 0.1V at a frequency of 1MHz to measure the parasitic capacitance C under different gate-drain spacing distances. gdValue; based on the measurement results, establish the relationship between the gate-drain spacing and the parasitic capacitance C. gd The relationship curve between the values; the gate-drain overlap region is analyzed using the electromagnetic field boundary element method, dividing the total overlap area into the necessary overlap region required to maintain basic functions and the unnecessary overlap region that can be eliminated through structural optimization; the ratio of the necessary overlap rate to the unnecessary overlap rate is calculated using the following equation: In the formula, η ratio η is the ratio of the necessary overlap rate to the unnecessary overlap rate. essential For the necessary overlap rate, η non-essential For unnecessary overlap, A essential To maintain the overlap area required for basic functions, A non-essential For the overlap area that can be optimized and eliminated, A total The total overlapping area is given by the following equation: In the formula, C gd，min To maintain the minimum parasitic capacitance required for the basic function of the device, the value was determined through circuit simulation. Here, d represents the dielectric thickness of the gate-drain overlap region, and ε is the dielectric constant of the dielectric. The relationship between the total overlap area and the unnecessary overlap area is: A total =A essential +A non-essential When the gate-drain spacing is 45 μm, the necessary overlap rate is approximately 40%, and the unnecessary overlap rate is approximately 60%. Based on the calculation results, the optimal range for the gate-drain spacing is determined to be 40–50 μm. This step, through systematic measurement and analysis, determines the influence of the gate-drain spacing on parasitic capacitance, providing data support for structural optimization.

[0165] The specific implementation of step S03 is as follows: A first field plate with lengths of 5μm, 10μm, and 15μm is designed on the source side, and a second field plate with lengths of 5μm, 10μm, and 15μm is designed on the gate side, forming nine different combinations of dual-field plate structures; the electric field distribution under different field plate structures is calculated using electric field simulation software, with a focus on analyzing the electric field peak value and electric field distribution uniformity at the field plate edges; the breakdown voltage and parasitic capacitance C of the device under different field plate structures are measured. gd Value; Establish a Nash equilibrium game model, and determine the reverse recovery loss E. rr The utility function of the first player is used as the utility function of the second player; the resilience is defined as the utility function of the second player; the strategy space of the two players is defined as a combination of field plate length parameters; the utility function matrix is ​​constructed as follows: In the formula, U is the utility function matrix. This represents the i-th strategy of the first player, corresponding to the first board length values ​​of 5μm, 10μm, and 15μm. This represents the j-th strategy of the second player, corresponding to the second board length values ​​of 5μm, 10μm, and 15μm. Indicates the strategy chosen by both sides in the game. The utility value at that time; the utility function of the first player is: In the formula, For the first player in the strategy combination The utility value below, E represents the reverse recovery loss under the corresponding strategy. rr，max and E rr，min These are the maximum and minimum values ​​of the reverse recovery loss, respectively. C represents the parasitic capacitance value under the corresponding strategy. gd，max and C gd，min Let α1 and β1 be the maximum and minimum values ​​of the parasitic capacitance, respectively, and let α1 and β1 be the weighting coefficients, satisfying α1 + β1 = 1; the utility function of the second player is: In the formula, For the second player in the strategy combination The utility value below, BV represents the breakdown voltage under the corresponding strategy. max and BV min These are the maximum and minimum breakdown voltages, respectively. E represents the peak electric field under the corresponding strategy. peak，max and E peak，min Let α and β be the maximum and minimum values ​​of the electric field peak, respectively, and let α2 and β2 be weighting coefficients, satisfying α2 + β2 = 1; the equation for solving the Nash equilibrium point is: For any s1∈S1; For any s2∈S2, in the formula, Let S1 and S2 be the strategy sets of the two players, representing the Nash equilibrium point. Using an iterative approximation algorithm, the Nash equilibrium point is solved, yielding a parameter combination where the optimal length of the first plate is 10 μm and the optimal length of the second plate is 8 μm. At this point, the peak electric field is reduced by 32%, and the parasitic capacitance C... gd The increase should not exceed 15%. This step uses game theory to analyze the impact of the field plate structure on device performance and finds a balance between withstand voltage and parasitic capacitance.

[0166] The specific implementation of step S04 is as follows: Nine multi-finger gate structures with gate finger widths of 2μm, 4μm, and 6μm, and gate finger pitches of 3μm, 5μm, and 8μm are designed; a layout model of the multi-finger gate is established using semiconductor process design software, and the total gate perimeter under different gate finger structures is calculated; a distributed gate resistor network model is used to analyze the influence of the multi-finger structure on the gate resistance, and the calculation formula is as follows: In the formula, R gate ρ is the total gate resistance.g L is the resistivity of the gate metal. g W is the gate lead length. g t is the gate lead width. g R is the gate metal thickness. contact For contact resistance, L finger Where n is the gate finger length and W is the gate finger quantity. finger The gate finger width; the multi-finger structure affects the parasitic capacitance C. gd The dispersion effect is calculated using the following equation: In the formula, C gd，total For the total parasitic capacitance, C gd，i C is the parasitic capacitance corresponding to the i-th gate finger. gd，unit Let be the parasitic capacitance of the unit gate finger; the relationship between the parasitic capacitance of the unit gate finger and the gate finger structural parameters is as follows: In the formula, A overlap W represents the overlap area between the unit gate finger and the drain. finger L is the gate width. overlap d is the overlap length between the gate finger and the drain. gd The dielectric thickness between the gate and drain; the on-resistance R of the device under different gate finger structures is measured. DS(on) and parasitic capacitance C gd Value; According to the measurement results, when the gate finger width is 4μm and the gate finger pitch is 5μm, the gate resistance per unit area decreases by 42%, and the parasitic capacitance C gd The optimal dispersion effect results in a 25% increase in switching speed. This step improves device switching performance by optimizing the gate finger structure, reducing gate resistance, and dispersing parasitic capacitance.

[0167] The specific implementation of step S05 is as follows: Design a bidirectional conduction test circuit, including a main circuit power supply, a resistive load, a test sample, and a drive circuit; set the test conditions as follows: drain-source voltage 350V, conduction current 10A, gate-source drive voltage 0V to 15V, and switching frequency 100kHz; use a high-bandwidth oscilloscope and a current probe to measure the drain-source voltage V during the reverse recovery process. DS and drain current I D Waveform; record the reverse recovery time t rr This refers to the time interval from when the reverse current begins to decrease until it drops to 10% of its peak value; the peak reverse recovery current I is measured. rrm and reverse recovery charge Q rr Analysis of carrier migration characteristics using the Coulomb scattering relaxation time equation: In the formula, τ c Let m be the Coulomb scattering relaxation time. * Let ε be the effective mass of the charge carriers, ε be the dielectric constant of the semiconductor, and k be the effective mass of the charge carriers. BWhere is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, n is the carrier concentration, and β is the shielding parameter; the effective carrier mobility is calculated using the relaxation time. In the formula, μ is the effective carrier mobility; considering the high electric field effect, the carrier mobility is corrected as follows: In the formula, μ e V is the effective mobility under high electric field, μ0 is the mobility under low electric field, E is the electric field strength, and v is the effective mobility under high electric field. sat The carrier saturation velocity; the input parameters required for calculation and analysis include carrier concentration 10. 17 cm -3 lattice temperature 25℃, impurity concentration 5×10 16 cm -3 The electric field strength was 3 MV / cm, and the dielectric constant of gallium nitride was 8.9. Measurements were performed on samples with different structural designs, and the reverse recovery characteristic parameters were recorded. This step obtained reverse recovery characteristic data of the device through actual testing, providing a basis for subsequent optimization.

[0168] The specific implementation of step S06 is as follows: Collect the capacitor charging and discharging current waveforms of samples with different structural designs during the reverse recovery process; use a spectrum analyzer to perform a Fourier transform on the current waveforms and analyze their frequency domain characteristics; calculate the reverse recovery loss E based on the current and voltage waveforms. rr The integral formula is used: In the formula, V DS (t) represents the drain-source voltage during the reverse recovery process, I D (t) represents the drain current during the reverse recovery process, t rr For the reverse recovery time; establish the parasitic capacitance C gd Value and reverse recovery loss E rr The dataset; using the Pearson correlation coefficient method, the parasitic capacitance C is calculated. gd Value and reverse recovery loss E rr Correlation coefficient between them: In the formula, r is the correlation coefficient, and C gd，i Let be the parasitic capacitance value of the i-th sample. E is the average value of the parasitic capacitance. rr，i Let i be the reverse recovery loss of the i-th sample. The average reverse recovery loss is given by m, where m is the number of samples. The parasitic capacitance C is determined through linear regression analysis. gd Value of reverse recovery loss E rr Impact factor: E rr =k·C gd +b+ε, where k is the influence factor, b is a constant term, and ε is the error term, with a range of ±5%; when the parasitic capacitance C gdWhen the value varies within the range of 50–150 pF, the correlation coefficient reaches 0.86, indicating a significant positive correlation between the two. The parasitic capacitance C is calculated to be... gd Value of reverse recovery loss E rr The influence factor is 0.78, i.e., the parasitic capacitance C. gd For every 10% decrease in value, the reverse recovery loss E rr On average, it reduced by 7.8%. This step, through correlation analysis, quantifies the impact of parasitic capacitance on reverse recovery loss, guiding the direction of structural optimization.

[0169] The specific implementation of step S07 is as follows: Integrate the test data obtained in the preceding steps, and establish a system including three input variables—gate-drain spacing parameters, field plate length parameters, and gate finger structure parameters—and the reverse recovery loss E. rr and on-resistance R DS(on) A multivariate mathematical model with two output variables is constructed; the response surface methodology is applied to construct the objective function surface in the parameter space; the Pareto optimization method is introduced to optimize the back recovery loss E. rr With on-resistance R DS(on) As two mutually constraining optimization objectives, the reverse recovery loss E is set. rr Threshold not exceeding 100μJ, on-resistance R DS(on) The threshold does not exceed 150mΩ; the optimization objective function is: minF(x)=[minf1(x), minf2(x)], where F(x) is a multi-objective optimization function, f1(x)=E rr f2(x) is the objective function for reverse recovery loss, where f2(x) = R. DS(on) (x) is the objective function for on-resistance, x is the design parameter vector, and x = [d gd L fp1 L fp2 W finger S finger ], where d gd L is the gate-drain spacing. fp1 L is the length of the first plate. fp2 W is the length of the second plate. finger S is the gate width. finger The gate finger spacing is 25μm ≤ d; the constraint condition is: 25μm ≤ d gd ≤75μm, 5μm≤L fp1 ≤15μm, 5μm≤L fp2 ≤15μm, 2μm≤W finger ≤6μm, 3μm≤S finger ≤8μm, E rr (x)≤E rr，threshold =100μJ, R DS(on) (x)≤R DS(on)，threshold=150mΩ; The Pareto solution set is defined as: if there is no x′∈Ω such that And there exists at least one j∈{1,2} such that f j (x′) <f j If x is the Pareto optimal solution and Ω is the feasible solution space, then x is the Pareto optimal solution. Using a multi-objective optimization algorithm, such as a non-dominated sorting genetic algorithm, the Pareto optimal solution set is obtained. Through decision weight analysis, the optimal parameter combination is determined: gate-drain spacing of 45 μm, first field plate length of 10 μm, second field plate length of 8 μm, gate finger width of 4 μm, and gate finger spacing of 5 μm. This step utilizes multi-objective optimization theory to find a balance between reverse recovery loss and on-resistance, thus determining the optimal structural parameter combination.

[0170] The specific implementation of step S08 is as follows: Based on the optimal parameters determined in step S07, design the layout of the bidirectional gallium nitride power device; fabricate device samples using standard semiconductor process flows, including epitaxial layer growth, source / drain ion implantation, gate metal deposition, and electrode formation; package the device using a TO-247 package with low parasitic inductance; establish a 350V / 20A test platform, including a high-precision voltage source, electronic load, high-speed drive circuit, and precision measurement equipment; design a test scheme, including static parameter testing and dynamic parameter testing; measure the device's static parameters such as withstand voltage, leakage current, and on-resistance; measure the device's dynamic parameters such as switching time, switching loss, and reverse recovery characteristics; and record the optimized device's reverse recovery time t. rr and reverse recovery loss E rr This step involves preparing actual device samples based on the optimization results and conducting performance testing to verify them.

[0171] The specific implementation of step S09 is as follows: Design a multi-frequency switching test circuit with a frequency range of 50kHz to 500kHz, using the same voltage and current operating conditions; measure the total loss of the optimized structure device and the control device at different switching frequencies; the total loss includes three parts: conduction loss, switching loss, and reverse recovery loss; use a thermal imager to measure the temperature rise of the device to verify the heat loss distribution; analyze the trend of total loss with frequency to verify the advantages of the optimized structure in high-frequency applications; calculate the reverse recovery loss E. rr The proportion of total loss, at 100kHz, is the reverse recovery loss E before optimization. rrThe initial loss was 32% of the total loss, which was reduced to 18% after optimization. The test data was compared with the electrical model established in step S01 to analyze the sources of error. Based on the verification results, parameters in the electrical model were corrected, such as the capacitance nonlinearity coefficient and the carrier mobility temperature coefficient. An iterative optimization method was used to run steps S01 to S08 again to further optimize the process parameters. After two rounds of iterative optimization, the optimal combination of process parameters was finally determined: gate-drain spacing of 48 μm, first field plate length of 11 μm, second field plate length of 7 μm, gate finger width of 3.5 μm, and gate finger spacing of 6 μm. At this point, the reverse recovery loss E... rr Reduced by 45%, on-resistance R DS(on) An increase of only 5% yields optimal overall performance. This step verifies the optimization effect through experiments, further optimizes parameters through iterative adjustments, and finally determines the optimal process parameters.

[0172] To better understand and implement this invention, the following is an embodiment 2 of a specific application scenario: Researchers conducted a series of bidirectional gallium nitride power device structure optimization experiments based on the method of this invention, aiming to reduce reverse recovery loss. The overall structure of the bidirectional GaN power device and its field plate structure are as follows: Figure 2-3 As shown in the figure. First, a three-dimensional electric field distribution model was established using ANSYS Maxwell software, with the minimum mesh element size set to 0.08 μm, focusing on refining the gate-drain overlap region. By solving the Poisson equation, under the conditions of a gate voltage of 2V and a drain voltage of 250V, the Miller capacitance value was calculated to be 87pF. This value differs from the measured value by no more than 5%, verifying the effectiveness of the model.

[0173] Subsequently, the researchers designed six sets of samples with different gate-drain spacing parameters and conducted tests. As shown in Table 1:

[0174] Table 1. Test results of parasitic capacitance for different gate-drain spacings.

[0175]

[0176] As can be seen from the data in Table 1, with the increase of the gate-drain spacing, the parasitic capacitance C... gd The value decreases significantly, and the reverse recovery loss also decreases accordingly. However, when the spacing exceeds 45 μm, the decreasing trend of parasitic capacitance and reverse recovery loss slows down. Based on the calculation results of necessary overlap rate and unnecessary overlap rate, 45–55 μm was determined as the optimal gate-drain spacing range. For an explanation of the overlap region, please refer to [link to relevant documentation]. Figure 6 .

[0177] Next, the researchers designed nine combinations of dual-field plate structures, as shown in Table 2:

[0178] Table 2. Influence of different field plate structural parameters on device performance

[0179]

[0180]

[0181] The data in Table 2 were analyzed using a Nash equilibrium game model, with reverse recovery loss and withstand voltage capability as the two game players, and utility values ​​were calculated. The results show that the combination of a first plate length of 10 μm and a second plate length of 8 μm achieves the optimal equilibrium point, with a utility value of 0.78. At this point, the peak electric field decreases by 2.86 MV / cm, the breakdown voltage increases to 675 V, and the parasitic capacitance C... gd The value is 96pF, and the reverse recovery loss is 71μJ.

[0182] Subsequently, the researchers designed and tested the multi-finger gate structure. As shown in Table 3:

[0183] Table 3 Test results of different gate finger structure parameters

[0184]

[0185] According to the data in Table 3, when the gate finger width is 4μm and the gate finger pitch is 5μm, the gate resistance and parasitic capacitance C gd Value and on-resistance R DS(on) Achieving a good balance, this structure boasts the fastest switching speed at 24ns. Calculations using a distributed resistor network model show that this structure reduces the gate resistance per unit area by 42%, significantly improving high-frequency switching performance compared to traditional structures. Figure 4-5 A top view and a cross-sectional view of the multi-finger gate structure of a bidirectional GaN power device are provided to facilitate understanding of the experimental data above.

[0186] Researchers constructed a bidirectional conduction test circuit, specifically a reverse recovery characteristic test circuit, such as... Figure 7 As shown, the reverse recovery characteristics of the device before and after optimization were measured under operating conditions of 350V / 10A. An oscilloscope with a bandwidth of 1GHz and a current probe with an accuracy of 0.1A were used in the test, with a sampling rate set to 5GS / s. See Table 4 for details.

[0187] Table 4 Comparison of reverse recovery characteristics of devices before and after optimization

[0188] parameter Device before optimization Optimized device Improvement rate (%) <![CDATA[Reverse recovery time t rr (ns)]]> 48 32 33.3 <![CDATA[Reverse recovery peak current I rrm (A)]]> 8.6 5.7 33.7 <![CDATA[Reverse recovery charge Q rr (nC)]]> 152 85 44.1 <![CDATA[Reverse recovery loss E rr (μJ)]]> 89 52 41.6

[0189] By applying the Coulomb scattering relaxation time equation to analyze the carrier migration characteristics, it was found that the effective carrier mobility of the optimized device was increased by 28% and the scattering relaxation time was shortened by 35%. This is the microscopic physical mechanism that improves the reverse recovery performance.

[0190] The parasitic capacitance C was calculated using the Pearson correlation coefficient method. gd Value and reverse recovery loss E rr The correlation coefficient between the two is 0.89, indicating a strong positive correlation. Linear regression analysis yields an influence factor of 0.81, i.e., the parasitic capacitance C. gd For every 10% reduction, the reverse recovery loss E rr The average decrease was 8.1%.

[0191] Based on all the test data, the researchers applied the Pareto optimization method to simultaneously optimize the reverse recovery loss E. rr With on-resistance R DS(on) Two mutually constraining objectives. As shown in Table 5:

[0192] Table 5. Partial solutions in the Pareto optimal solution set.

[0193]

[0194] Finally, the parameters in group 4 of Table 5 were selected as the optimal solution, namely, a gate-drain spacing of 48 μm, a first field plate length of 11 μm, a second field plate length of 7 μm, a gate finger width of 3.5 μm, and a gate finger spacing of 6 μm. Experimental verification under 350V / 20A conditions showed that this structure reduced the reverse recovery loss E of the device. rr It was reduced by 45%, while the on-resistance R DS(on) It only increased by 5%.

[0195] Tests at different switching frequencies further validated the effectiveness of the optimized structure. See Table 6 for details.

[0196] Table 6 Comparison of total losses at different switching frequencies

[0197]

[0198] Traditional methods for reducing reverse recovery losses in bidirectional GaN power devices primarily involve decreasing the drain doping concentration, increasing the drift region length, or increasing the channel width. While these methods can reduce reverse recovery losses, they typically lead to a significant increase in on-resistance, a decrease in current density, and a negative impact on the device's high-frequency performance. For example, reducing the drain doping concentration can lower reverse recovery losses by about 25%, but it increases on-resistance by more than 30%; increasing the drift region length can reduce reverse recovery losses by about 20%, but it increases the device area by about 35%, significantly increasing cost.

[0199] In contrast, this invention addresses the reverse recovery loss problem from the perspective of parasitic capacitance by optimizing the gate-drain spacing, field plate structure, and gate finger structure, reducing reverse recovery loss by 45% while increasing on-resistance by only 5%, maintaining excellent static characteristics. The advantages of this invention are particularly significant in high-frequency applications, reducing total loss by 42% at a 500kHz switching frequency, far exceeding the approximately 20% reduction achieved by traditional methods. Furthermore, the Nash equilibrium game model and Pareto optimization method introduced in this invention achieve systematic optimization of electrical and thermal performance, avoiding the blind spots and limitations of traditional empirical design, improving design efficiency, and providing theoretical guidance and design methods for the development of bidirectional GaN power devices.

[0200] It should be noted that the variables involved in this invention are explained in detail in Tables 7 and 8 below.

[0201] Table 7. Variable Explanation Table (Part 1)

[0202]

[0203]

[0204] Table 8. Variable Explanation Table (Part Two)

[0205]

[0206] Table 9. Variable Explanation Table (Part 3)

[0207]

[0208]

[0209] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for reducing reverse recovery loss of a bidirectional conduction GaN power device, characterized in that, The application relates to a method for reducing reverse recovery loss of a bidirectional conduction gallium nitride (GaN) power device. The application comprises the following steps: An accurate electrical model of the bidirectional conduction gallium nitride power device is established, and the Miller capacitance value generated in the gate-drain overlap region is analyzed; A plurality of gate-drain structures are designed, the gate-drain spacing distance parameter is controlled, the parasitic capacitance value is measured, and the necessary overlap rate and the unnecessary overlap rate ratio are calculated; a double field plate structure technology is adopted to form an electric field distribution optimization region, and a Nash equilibrium game model is used to analyze the relationship between the field plate length and the parasitic capacitance; An extended gate structure technology is used to design the gate as a multi-finger structure; a test circuit is constructed to measure the reverse recovery characteristics of the device; and the capacitor charging and discharging current waveform is analyzed; 2. The method of reducing reverse recovery loss of a bidirectional GaN power device of claim 1, wherein, An optimization model of the reverse recovery loss is established; a device sample is prepared, and the effectiveness of the optimized structure is verified; process parameters are iteratively optimized and finally determined, so as to guide the reduction of the reverse recovery loss of the bidirectional conduction GaN power device; the necessary overlap rate is the ratio of the minimum overlap area between the gate and the drain to the total overlap area, which is required to ensure the basic electrical characteristics and reliability of the bidirectional conduction gallium nitride power device, and is used to determine the lower limit value of the gate-drain spacing distance parameter; the unnecessary overlap rate is the ratio of the overlap area between the gate and the drain to the total overlap area, which is reduced through optimization design without affecting the basic function of the device, and is used to determine the optimization space of the gate-drain spacing distance parameter.

3. The method of reducing reverse recovery loss of a bidirectional GaN power device of claim 2, wherein, The accurate electrical model of the bidirectional conduction gallium nitride power device is established, and the Miller capacitance value generated in the gate-drain overlap region is analyzed, that is, the Miller capacitance value generated in the gate-drain overlap region is analyzed through finite element simulation, wherein the Miller capacitance value is the numerical value of the negative feedback effect caused by the overlap capacitance between the gate and the drain in the high-voltage switching process, and the Miller capacitance value can cause an additional current path in the switching process, thereby increasing the power loss.

4. The method of reducing reverse recovery loss of a bidirectional GaN power device of claim 3, wherein, The plurality of gate-drain structures are designed, the gate-drain spacing distance parameter is controlled, the parasitic capacitance value is measured, and the necessary overlap rate and the unnecessary overlap rate ratio are calculated, that is, the gate-drain spacing distance parameter is accurately controlled from 25 mu m to 75 mu m, the corresponding parasitic capacitance value is measured, and the ratio of the necessary overlap rate to the unnecessary overlap rate is calculated.

5. The method of reducing reverse recovery loss of a bidirectional GaN power device of claim 4, wherein, The double field plate structure technology is adopted to form an electric field distribution optimization region, and a Nash equilibrium game model is used to analyze the relationship between the field plate length and the parasitic capacitance, that is, a first field plate and a second field plate with lengths of 5 mu m to 15 mu m are respectively arranged on the source side and the gate side to form an electric field distribution optimization region, and the relationship between the field plate length and the parasitic capacitance is analyzed through the Nash equilibrium game model. The Nash equilibrium game model refers to the fact that, in the field plate structure design, the reverse recovery performance and the withstand voltage capability are regarded as two rational game parties, each game party tries to maximize its utility function, and a balance state is reached without cooperation, and the Nash equilibrium game model is used to determine the best parameter combination of the field plate structure.

6. The method of reducing reverse recovery loss of a bidirectional GaN power device of claim 5, wherein, The gate is designed as a multi-finger structure by using the extended gate structure technology, which means that the gate is designed as a multi-finger structure, the gate finger width is controlled in the range of 2-6 μm, the gate finger spacing is maintained between 3-8 μm, the gate resistance per unit area and the stray capacitance are reduced.

7. The method of reducing reverse recovery loss of a bidirectional GaN power device of claim 6, wherein, The multi-finger structure means that a single wide gate is divided into multiple narrow gate fingers arranged in parallel, the total length of the gate is increased, the gate resistance per unit area is reduced, and the stray capacitance between the gate and the drain is dispersed, and the multi-finger structure is used to improve the switching characteristics of the device.

8. The method of reducing reverse recovery loss of a bidirectional conducting GaN power device according to claim 7, wherein, The reverse recovery characteristics of the device are measured by constructing a test circuit, which means that a bidirectional conduction test circuit is constructed to measure the reverse recovery time and reverse recovery loss of the device under different structural designs under the working condition of 350 V / 10 A, and the carrier transport characteristics are analyzed by the Coulomb scattering relaxation time equation.

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