A method for extracting parameters of nonlinear current model of E-mode devices considering gate current effect

Abstract

The present invention discloses a method for extracting nonlinear current model parameters of an E-mode device that takes into account gate current effects, and relates to the technical field of enhanced device modeling. The method comprises: establishing a nonlinear current model of the E-mode device; extracting transistor parasitic resistance; removing the influence of transistor parasitic resistance, calculating the intrinsic gate-source and gate-drain node voltages in the nonlinear current model, and obtaining intrinsic gate-source voltage and drain-source voltage; extracting intrinsic gate current model parameters; integrating the influence of the gate current component from the measured drain-source current of the transistor to obtain the intrinsic drain-source current component; extracting intrinsic nonlinear drain-source current model parameters; and substituting the intrinsic nonlinear drain-source current model parameter values ​​into the intrinsic nonlinear drain-source current model equation for verification. The present invention introduces gate current component calculation into the traditional nonlinear current model parameter extraction method to accurately extract intrinsic nonlinear current source parameters.

Description

Technical Field

[0001] The present invention relates to the technical field of enhancement mode device modeling, and in particular to a method for extracting parameters of a nonlinear current model of an E-mode device taking gate current effects into consideration. Background Art

[0002] Transistor models are mathematical and physical abstractions of real-world transistor characteristics. They are the foundation of integrated circuit (IC) EDA technology and crucial for precise IC design. Enhancement-mode (E-mode) devices offer significant advantages, such as high switching speed and low on-resistance, effectively improving circuit performance and reducing power consumption, making them a key development in power electronics. However, E-mode devices typically operate with a positive gate-source voltage bias (Vgs>0), resulting in significant gate current effects. This not only affects the device's static power consumption but also degrades device characteristics, further impacting the device's nonlinear current characteristics. Model parameter extraction is a core step in device modeling. For E-mode device nonlinear current model parameter extraction, simply copying the traditional parameter extraction algorithm for depletion-mode (D-mode) devices, which ignores gate current effects, results in a model that fails to accurately characterize the gate current effect on the device's linear current characteristics.

[0003] Traditional nonlinear current models include Curtice, Angelov, and EEHEMT. The Angelov model is widely used in industry due to its excellent convergence and ability to accurately predict transconductance and its higher-order terms. Currently, scholars at home and abroad have conducted extensive research on parameter extraction from Angelov's nonlinear current models. In 2012, Zhou Hui of the University of Electronic Science and Technology of China proposed a new Angelov-based block extraction method for GaN HEMT large-signal IV models. This method uses a tanh function to fit the knee voltage in the linear region to extract relevant parameters. The method then uses the least squares method to extract initial values ​​for the remaining parameters, and optimizes these initial values ​​using a genetic algorithm. In the same year, M. Deepti used extensive measurement data to analyze equations related to DC parameters for Angelov model parameter extraction. He established a parameter extraction process that extracts transconductance-related parameters first and then IV-related parameters. Peak voltage and current parameters are directly extracted from the transconductance curve, while the remaining model parameters are extracted by fitting the IV data using DC formulas. In 2013, I. Angelov et al. from Chalmers University of Technology proposed a hybrid measurement-based method for extracting parameters from microwave transistor large-signal models that combines direct extraction and numerical optimization. This method first directly extracts relevant parameters from the IV linear and saturation regions based on static measurements. Then, numerical optimization is performed based on dynamic time-domain measurements to achieve accurate large-signal model parameter extraction. This model demonstrates excellent predictive capabilities at high frequencies. In 2018, Wen Zhang from the University of Electronic Science and Technology of China proposed a fully streamlined parameter extraction method for the Angelov drain-source current Ids model. This method first partitions parameters representing self-heating and trapping effects based on their significance. It then extracts these parameters by fitting pulsed IV transfer curves at different static bias points, achieving a step-by-step extraction of each parameter in the Ids model. In 2019, Zhang WY et al. from Tsinghua University proposed a modified Angelov large-signal field-effect transistor model that ignores dispersion branches. They established a distributed parameter extraction process for directly extracting all key model parameters from hybrid measurement data, including DC and RF characteristics. In 2021, Bi Lei from Tianjin University proposed a step-by-step method for extracting the IV parameters of the Angelov model. Combining the piecewise function idea of ​​the EEHEMT1 model, the predicted value of the transconductance curve in the entire area was improved by increasing the fitting parameters. The test data was used to extract the physically meaningful parameters and empirical parameters in the model. After that, the initial values ​​and ranges of the extracted parameters were set, and the fitting parameters were extracted with the help of optimization tools.

[0004] Existing nonlinear current model parameter extraction methods are mainly carried out for D-mode devices. Since the gate current of D-mode devices is small and has limited impact on device characteristics, in order to simplify the extraction process, traditional methods usually only remove the influence of parasitic resistance and do not integrate the influence of the gate current component from the measured drain-source current of the transistor. The gate current effect is ignored, resulting in the inability to directly extract modeling parameters for E-mode devices with significant gate current effects.

[0005] Therefore, it is an urgent problem for those skilled in the art to propose a method for extracting parameters of a nonlinear current model of an E-mode device taking into account the gate current effect to solve the difficulties existing in the prior art. Summary of the Invention

[0006] In view of this, the present invention provides a method for extracting the nonlinear current model parameters of an E-mode device taking into account the gate current effect. The gate current component calculation is introduced into the traditional nonlinear current model parameter extraction method to achieve accurate extraction of the intrinsic nonlinear current source parameters.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effects includes:

[0009] S1. Establish a nonlinear current model for E-mode devices and measure the transistor's multi-bias static DCIV characteristics, pulse PIV characteristics, and transistor S parameters.

[0010] S2, extract transistor parasitic resistance;

[0011] S3. Remove the influence of transistor parasitic resistance, calculate the gate-source and gate-drain node voltages in the intrinsic region of the nonlinear current model, and obtain the intrinsic gate-source voltage and drain-source voltage;

[0012] S4, extracting intrinsic gate current model parameters;

[0013] S5, obtaining the intrinsic drain-source current component by integrating the influence of the gate current component from the measured drain-source current of the transistor;

[0014] S6, extracting intrinsic nonlinear drain-source current model parameters;

[0015] S7. Substitute the extracted intrinsic nonlinear drain-source current model parameter values ​​into the intrinsic nonlinear drain-source current model equation to verify the model.

[0016] In the above method, optionally, the nonlinear current model in S1 is any one or more of the Curtice model, the Angelov model, or the EEHEMT model;

[0017] The multi-bias static DCIV characteristics and pulse PIV characteristics of the transistor under test are measured at room temperature; the transistor S parameters are measured in the cold pinch-off state and the cold unbiased state.

[0018] In the above method, optionally, in S2, the S parameter is converted into an impedance parameter - a Z parameter, and the resistance component is extracted through an equivalent circuit model to obtain the parasitic resistance.

[0019] The above method optionally calculates the intrinsic gate-source voltage and drain-source voltage in S3, specifically:

[0020] The external bias voltage of the transistor, the gate-source current and the drain-source current of the transistor are measured, and the influence of the parasitic resistance is removed according to the parasitic resistance obtained in step S2 to obtain the intrinsic gate-source voltage and drain-source voltage.

[0021] In the above method, optionally, the gate current model in S4 includes: a gate-source forward conduction current model and a gate-drain reverse breakdown current model;

[0022] Extract intrinsic gate current model parameters based on the intrinsic gate-source voltage, drain-source voltage, and measured gate current data obtained in step S3 to obtain a gate-source forward conduction current model and a gate-drain reverse breakdown current model;

[0023] Among them, the fitting parameters of the forward conduction current model between gate and source are extracted by the least squares method through the measured forward conduction current between gate and source - the measured bias voltage data of the transistor external; the fitting parameters of the reverse breakdown model between gate and drain are extracted by the least squares method through the measured reverse breakdown current between gate and drain - the measured bias voltage data of the transistor external.

[0024] The above method is optional. In S5, after the gate current is fused, the intrinsic transistor measured drain-source current is minus the transistor external measured bias voltage. When the transistor external measured bias voltage = 0V, the transistor measured drain-source current has no negative value area, and the gate current fusion is successful.

[0025] In the above method, optionally, the intrinsic nonlinear drain-source current model parameters in S6 are divided into three blocks, namely, a self-heating and trap-independent parameter block, a trap effect-related parameter block, and a self-heating effect-related parameter block;

[0026] Among them, the self-heating and trap-independent parameters are: the static bias is fitted using the least squares method at each fixed transistor external measured bias voltage: V gsq =0V, at V gsq = 0V device pulse current curve to extract the self-heating and trap-independent parameters in the nonlinear current model;

[0027] Trap effect related parameters: combined with different static bias V gsq =0V, V dsq =0V; V gsq =-4V, V dsq =0V; V gsq =-4V, V dsq =2V pulse current curve, the least squares curve fitting method is used to extract the parameters related to the trap effect;

[0028] Parameters related to self-heating effect: Combined with the static current-voltage test data, the least squares method is used to fit the transfer characteristic curves under different external bias voltages of the transistor to complete the extraction of parameters related to the self-heating effect.

[0029] The above method is optional, and the model is verified in S7, specifically:

[0030] Substitute the extracted intrinsic nonlinear drain-source current model parameter values ​​into the intrinsic nonlinear drain-source current model equation to obtain the model calculation results and compare them with the measured data; wherein, the intrinsic nonlinear drain-source current model equation is obtained by the nonlinear current model of the E-mode device established in step S1.

[0031] It can be seen from the above technical solution that, compared with the prior art, the present invention provides a method for extracting parameters of a nonlinear current model of an E-mode device taking into account the gate current effect, which has the following beneficial effects:

[0032] The present invention introduces a gate current component calculation step into the traditional nonlinear current model parameter extraction algorithm for D-mode devices, thereby accurately extracting the intrinsic nonlinear current source parameters taking into account the gate current effect, and further realizing precise modeling of E-mode devices. Compared with the model obtained based on the traditional parameter extraction algorithm, the present invention has higher accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0034] Figure 1A flow chart of a method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effects provided by the present invention;

[0035] Figure 2 An Angelov model topology diagram in a specific embodiment of a method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effect provided by the present invention;

[0036] Figure 3 A comparison diagram before and after fusion of gate current components in a specific embodiment of a method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effects provided by the present invention;

[0037] Figure 4 A diagram showing the optimization results of the nonlinear current model using a traditional method in a specific embodiment of a method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effects provided by the present invention;

[0038] Figure 5 This is a diagram of the nonlinear current model optimization results of the method of the present invention in a specific embodiment of a method for extracting nonlinear current model parameters of an E-mode device considering gate current effect provided by the present invention. DETAILED DESCRIPTION

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0040] In this application, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. The terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or apparatus comprising the element.

[0041] Reference Figure 1 As shown, the present invention discloses a method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effects, comprising:

[0042] S1. Establish a nonlinear current model for E-mode devices and measure the transistor's multi-bias static DCIV characteristics, pulse PIV characteristics, and transistor S parameters.

[0043] S2, extract transistor parasitic resistance;

[0044] S3. Remove the influence of transistor parasitic resistance, calculate the gate-source and gate-drain node voltages in the intrinsic region of the nonlinear current model, and obtain the intrinsic gate-source voltage and drain-source voltage;

[0045] S4, extracting intrinsic gate current model parameters;

[0046] S5, obtaining the intrinsic drain-source current component by integrating the influence of the gate current component from the measured drain-source current of the transistor;

[0047] S6, extracting intrinsic nonlinear drain-source current model parameters;

[0048] S7. Substitute the extracted intrinsic nonlinear drain-source current model parameter values ​​into the intrinsic nonlinear drain-source current model equation to verify the model.

[0049] Furthermore, the nonlinear current model in S1 is any one or more of the Curtice model, the Angelov model or the EEHEMT model;

[0050] The multi-bias static DCIV characteristics and pulse PIV characteristics of the transistor under test are measured at room temperature; the transistor S parameters are measured in the cold pinch-off state and the cold unbiased state.

[0051] Furthermore, in S1, the multi-bias static DCIV characteristics and pulse PIV characteristics of the transistor under test are performed at room temperature (25°C):

[0052] In the static DCIV test, the gate-source bias voltage range is V gsq =-0.3~1.5V (step: 0.1V), the drain-source bias voltage range is V ds =0~2.8V (step: 0.2V), the test is completed to obtain different gate-source bias voltages under static bias V gs and drain-source bias voltage V ds Drain-source current I ds The characteristic curve is the static DCIV characteristic curve;

[0053] In the pulse PIV test, the gate-source and drain-source static bias points are V gsq =0V,V dsq =0V; V gsq =-4V, V dsq =0V; V gsq =-4V, V dsq =2V; dynamic gate-source bias voltage range is V gs =-0.3~1.5V (step: 0.1V), the dynamic drain-source bias voltage range is V ds =0~2.8V (step: 0.2V), pulse width is 500ns, duty cycle is 0.1%. After the test is completed, different gate-source dynamic bias voltages can be obtained. V gs and drain-source dynamic bias voltage V ds Drain-source current under I ds The characteristic curve is the pulse PIV characteristic curve;

[0054] Furthermore, the S parameter test includes two bias voltages, where the drain-source bias voltage is V ds =0V, and the gate-source bias voltages are V gs =-0.5V and V gs =0V; the S parameter frequency range at each bias point is 0.4GHz~50GHz (step: 0.4 GHz), and the different gate-source bias voltages can be obtained after the test is completed V gs and drain-source bias voltage V ds The S parameters under .

[0055] Furthermore, in S2, the S parameters are converted into impedance parameters - Z parameters, and the resistance components are extracted through the equivalent circuit model to obtain the parasitic resistance.

[0056] Furthermore, the intrinsic gate-source voltage and drain-source voltage in S3 are calculated as follows:

[0057] The external bias voltage of the transistor, the gate-source current and the drain-source current of the transistor are measured, and the influence of the parasitic resistance is removed according to the parasitic resistance obtained in step S2 to obtain the intrinsic gate-source voltage and drain-source voltage.

[0058] Furthermore, the gate current model in S4 includes: a forward conduction current model between gate and source and a reverse breakdown current model between gate and drain;

[0059] Extract intrinsic gate current model parameters based on the intrinsic gate-source voltage, drain-source voltage, and measured gate current data obtained in step S3 to obtain a gate-source forward conduction current model and a gate-drain reverse breakdown current model;

[0060] Among them, the fitting parameters of the forward conduction current model between gate and source are extracted by the least squares method through the measured forward conduction current between gate and source - the measured bias voltage data of the transistor external; the fitting parameters of the reverse breakdown model between gate and drain are extracted by the least squares method through the measured reverse breakdown current between gate and drain - the measured bias voltage data of the transistor external.

[0061] Furthermore, in S5, after the gate current is fused, the intrinsic transistor measured drain-source current is equal to the transistor external measured bias voltage. When the transistor external measured bias voltage = 0V, the transistor measured drain-source current has no negative value region, and the gate current fusion is successful at this time.

[0062] Furthermore, the intrinsic nonlinear drain-source current model parameters in S6 are divided into three blocks, namely, the self-heating and trap-independent parameter block, the trap effect-related parameter block, and the self-heating effect-related parameter block;

[0063] Among them, the self-heating and trap-independent parameters are: the static bias is fitted using the least squares method at each fixed transistor external measured bias voltage: V gsq =0V, at V gsq = 0V device pulse current curve to extract the self-heating and trap-independent parameters in the nonlinear current model;

[0064] Trap effect related parameters: combined with different static bias V gsq =0V, V dsq =0V; V gsq =-4V, V dsq =0V; V gsq =-4V, V dsq =2V pulse current curve, the least squares curve fitting method is used to extract the parameters related to the trap effect;

[0065] Parameters related to self-heating effect: Combined with the static current-voltage test data, the least squares method is used to fit the transfer characteristic curves under different external bias voltages of the transistor to complete the extraction of parameters related to the self-heating effect.

[0066] Furthermore, the model is verified in S7, specifically:

[0067] Substitute the extracted intrinsic nonlinear drain-source current model parameter values ​​into the intrinsic nonlinear drain-source current model equation to obtain the model calculation results and compare them with the measured data; wherein, the intrinsic nonlinear drain-source current model equation is obtained by the nonlinear current model of the E-mode device established in step S1.

[0068] In a specific embodiment, taking the Angelov model as an example, referring to Figure 2 As shown in the model topology, the parasitic resistors are connected as follows: Gate parasitic resistance (R g ) is connected in series between the external gate input terminal (G) and the intrinsic gate port (g_int), and the drain parasitic resistance (R d ) is connected in series between the external drain output terminal (D) and the intrinsic part drain port (d_int), and the source parasitic resistance (R s ) is connected in series between the external source terminal (S) and the intrinsic source terminal (s_int); cold pinch-off state (biased to V gs <V off , V ds =0V, where V off is the pinch-off voltage) and in the cold unbiased state (bias is V gs =0V, V ds = 0V) to extract the parasitic resistance, convert the S parameters into impedance parameters - Z parameters, and extract the resistance component through the equivalent circuit model to obtain the parasitic resistance.

[0069] like Figure 2 As shown, the gate-source and gate-drain nodes (g_int, d_int, s_int) of the intrinsic region are different from the external test nodes (G, S, D). It is necessary to remove the influence of parasitic resistance to obtain the intrinsic gate-source voltage ( ) and drain-source voltage ( ), specifically combined with the extracted parasitic resistance R g 、 R s and R d , and calculate to get:

[0070] ,

[0071] ,

[0072] in, and They are Figure 2 The intrinsic gate-source voltage and drain-source voltage in; V gs and Vds are the external measured bias voltages of the transistors respectively; I gs 、 I ds These are the measured data of transistor gate-source current and drain-source current respectively.

[0073] The gate current model includes the gate-source forward current model I gs and gate-drain reverse breakdown model I gd :

[0074] ,

[0075] ,

[0076] in, V jg 、 P g 、 I j for I gs Model and I gd The fitting parameters of the model can be combined with the measured I gs -V gs Data and I gd -V gs The data were extracted using the least squares method.

[0077] Before extracting nonlinear model parameters, it is also necessary to measure the drain-source current of the transistor. I ds Medium fusion gate current I gd The influence of the component obtains the drain-source current component of the intrinsic part ;according to Figure 2 Topology, we can get the following relationship:

[0078] ;

[0079] The comparison of drain-source current before and after fusion of gate current components is shown in the figure below. Figure 3 As shown, the blue circle is the actual measurement after deducting only the parasitic resistance I ds The red line is the discrete current component under each bias after further integrating the gate current component on the basis of deducting the parasitic resistance. I ds ; It can be seen that after the fusion gate current, the intrinsic I ds-V ds exist V ds = No obvious I ds In the negative area, it can be seen that the gate current fusion calculation is successful.

[0080] In this embodiment, the proposed parameter extraction algorithm is verified by using a GaAs pHEMT transistor with a size of 4×150 μm. The extracted model parameter values ​​are substituted into the intrinsic nonlinear drain-source current model equation to obtain the model calculation results and compare them with the measured data. In order to reflect the advantages of the extraction method of the present invention, a set of model parameter values ​​are extracted using a traditional parameter extraction algorithm and substituted into the model equation for comparison and verification. Figure 4 The figure shows the optimization result of the nonlinear current model using the traditional method. Figure 5 As shown in the figure, the nonlinear current model optimization results of the method of the present invention are shown in the figure. The gate-source bias voltage range is V gs =-0.3~1.5V (step: 0.1V), the drain-source bias voltage range is V ds =0~2.8V (step: 0.2V);

[0081] Calculate the error between the two sets of current models using the following formula:

[0082] ,

[0083] in, P simu Represents the model calculation under each bias I ds result, P meas Represents the actual measurement under each bias I ds result;

[0084] The results show that the average accuracy of the proposed method under multiple bias conditions is greater than 99.83%, a 10.42% improvement over the 89.41% of the traditional model. The results further demonstrate that the proposed transistor nonlinear current modeling method, which considers gate current effects, can more accurately simulate current characteristics under different bias conditions, especially in the linear region, compared to traditional models, significantly improving model accuracy.

[0085] Each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without expending creative work.

[0086] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effect, characterized in that: include: S1. Establish a nonlinear current model for E-mode devices and measure the transistor's multi-bias static DCIV characteristics, pulse PIV characteristics, and transistor S parameters. S2, extract transistor parasitic resistance; S3. Remove the influence of transistor parasitic resistance, calculate the gate-source and gate-drain node voltages in the intrinsic region of the nonlinear current model, and obtain the intrinsic gate-source voltage and drain-source voltage; S4, extracting intrinsic gate current model parameters; The gate current model includes: the forward conduction current model between gate and source and the reverse breakdown current model between gate and drain; Extract intrinsic gate current model parameters based on the intrinsic gate-source voltage, drain-source voltage, and measured gate current data obtained in step S3 to obtain a gate-source forward conduction current model and a gate-drain reverse breakdown current model; Among them, the gate-source forward conduction current model fitting parameters are extracted by the least square method through the measured gate-source forward conduction current-transistor external measured bias voltage data; the gate-drain reverse breakdown model fitting parameters are extracted by the gate-drain reverse breakdown current-transistor external measured bias voltage data using the least square method; S5. Integrating the influence of the gate current component into the measured drain-source current of the transistor to obtain the intrinsic drain-source current component; S6, extracting intrinsic nonlinear drain-source current model parameters; S7. Substitute the extracted intrinsic nonlinear drain-source current model parameter values ​​into the intrinsic nonlinear drain-source current model equation to verify the model.

2. The method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effect according to claim 1, characterized in that: The nonlinear current model in S1 is any one or more of the Curtice model, Angelov model or EEHEMT model; The multi-bias static DCIV characteristics and pulse PIV characteristics of the transistor under test are measured at room temperature; the transistor S parameters are measured in the cold pinch-off state and the cold unbiased state.

3. The method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effect according to claim 1, characterized in that: In S2, the S parameters are converted into impedance parameters - Z parameters, and the resistance components are extracted through the equivalent circuit model to obtain the parasitic resistance.

4. The method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effect according to claim 1, characterized in that: The intrinsic gate-source voltage and drain-source voltage in S3 are calculated as follows: The external bias voltage of the transistor, the gate-source current and the drain-source current of the transistor are measured, and the influence of the parasitic resistance is removed according to the parasitic resistance obtained in step S2 to obtain the intrinsic gate-source voltage and drain-source voltage.

5. The method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effect according to claim 1, characterized in that: In S5, after the gate current is fused, the intrinsic transistor measured drain-source current is equal to the transistor external measured bias voltage. When the transistor external measured bias voltage = 0V, the transistor measured drain-source current has no negative value area, and the gate current fusion is successful at this time.

6. The method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effect according to claim 1, characterized in that: The intrinsic nonlinear drain-source current model parameters in S6 are divided into three blocks, namely the self-heating and trap-independent parameter block, the trap effect related parameter block, and the self-heating effect related parameter block; Among them, the self-heating and trap-independent parameters are: the static bias is fitted using the least squares method at each fixed transistor external measured bias voltage: V gsq =0V, at V gsq = 0V device pulse current curve to extract the self-heating and trap-independent parameters in the nonlinear current model; Trap effect related parameters: combined with different static bias V gsq =0V, V dsq =0V; V gsq =-4V, V dsq =0V; V gsq =-4V, V dsq =2V pulse current curve, the least squares curve fitting method is used to extract the parameters related to the trap effect; Parameters related to self-heating effect: Combined with the static current-voltage test data, the least squares method is used to fit the transfer characteristic curves under different external bias voltages of the transistor to complete the extraction of parameters related to the self-heating effect.

7. The method for extracting parameters of a nonlinear current model of an E-mode device considering gate current effect according to claim 1, characterized in that: The model is verified in S7, specifically: Substitute the extracted intrinsic nonlinear drain-source current model parameter values ​​into the intrinsic nonlinear drain-source current model equation to obtain the model calculation results and compare them with the measured data; wherein, the intrinsic nonlinear drain-source current model equation is obtained by the nonlinear current model of the E-mode device established in step S1.

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