Display control method, display module and electronic equipment

Abstract

The embodiment of the invention provides a display control method, a display module and electronic equipment, which are used for improving the problem that a display screen refreshed by regions is easy to cause uneven brightness and the like. The method comprises the following steps: outputting a first pulse control signal of a first frequency, wherein the first pulse control signal is used for controlling a first pixel circuit to write first data according to the first frequency; outputting a second pulse control signal of a second frequency, wherein the second pulse control signal is used for controlling a second pixel circuit to write second data according to the second frequency; the first pixel circuit and the second pixel circuit are pixel circuits located in different rows, the first frequency is larger than the second frequency, and the pulse width of the first pulse control signal is smaller than that of the second pulse control signal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display control method, a display module, and an electronic device. Background Art

[0002] For display modules that support zoned refresh, the refresh rates of different zones vary, meaning the switching transistors in the pixel circuits are turned on at different frequencies. The higher the refresh rate, the longer the switching transistors are turned on. The switching transistors, which can be oxide thin-film transistors (TFTs), are continuously affected by positive bias temperature stress (PBTS) when turned on under forward bias. The longer the on-time, the greater the impact of PBTS, causing the threshold voltage of the switching transistor to drift (move in the positive direction), thereby affecting the voltage written to the driver transistor and causing the brightness of the light-emitting device to vary. Summary of the Invention

[0003] Embodiments of the present application provide a display control method, a display module, and an electronic device for improving the problem of uneven brightness that is prone to occur in a display module that is refreshed in different areas.

[0004] In a first aspect, an embodiment of the present application provides a display control method, the method comprising: outputting a first pulse control signal of a first frequency, the first pulse control signal being used to control a first pixel circuit to write first data according to the first frequency; outputting a second pulse control signal of a second frequency, the second pulse control signal being used to control a second pixel circuit to write second data according to the second frequency; the first pixel circuit and the second pixel circuit are pixel circuits in different rows, the first frequency is greater than the second frequency, and the pulse width of the first pulse control signal is less than the pulse width of the second pulse control signal.

[0005] The method provided in the embodiment of the present application adjusts the pulse width of the pulse control signal of the pixel circuits with different refresh rates, that is, adjusts the conduction time of the switching transistors with different refresh rates. Since the conduction time of the switching transistor with a high refresh rate is often greater than the conduction time of the switching transistor with a low refresh rate, the solution provided in the embodiment of the present application reduces the pulse width of the pulse control signal of the pixel circuit with a high refresh rate, reduces the conduction time of the switching transistor with a high refresh rate, reduces the difference in the degree of influence of PBTS between the two, reduces the difference in the total conduction time of the switching transistor of the pixel circuit with a high refresh rate and the conduction time of the switching transistor of the pixel circuit with a low refresh rate, and avoids brightness differences between different pixel circuits or different partitions of the display screen.

[0006] In one possible implementation, the pulse width of the first pulse control signal and the pulse width of the second pulse control signal satisfy the following relationship: X2·T2 / X1≤Y1<Y2, where Y1 is the pulse width of the first pulse control signal, Y2 is the pulse width of the second pulse control signal, X1 is the first frequency, and X2 is the second frequency. Since the on-time of a high-refresh-rate switching transistor is generally longer than the on-time of a low-refresh-rate switching transistor, the solution provided in the embodiment of the present application reduces the on-time of the high-refresh-rate switching transistor, and at the very least, the on-time of the high-refresh-rate switching transistor can be the same as the on-time of the low-refresh-rate switching transistor. In this way, the degree of threshold drift caused by the PBTS is also the same, and no brightness difference occurs.

[0007] In one possible implementation, when the first frequency and the second frequency satisfy: X1 ≥ 12·X2, the pulse width of the first pulse control signal also satisfies: X2·Y2 / X1≤Y1≤Y2 / 12. In some cases, the difference between the first frequency and the second frequency may be relatively large. For example, if X1 is 120Hz and X2 is 1Hz, due to process limitations, the pulse width Y1 of the first pulse control signal cannot reach 1 / 120 of the pulse width Y2 of the second pulse control signal. Therefore, in cases such as X1>12X2, the pulse width Y1 of the first pulse control signal and the pulse width Y2 of the second pulse control signal can be set to meet the above-mentioned size relationship. Although it is not possible to completely achieve the same total conduction time of the switching transistors of pixel circuits with different refresh rates, the gap between them can be narrowed to avoid the problem of uneven display brightness.

[0008] In a possible implementation, the first pixel circuit includes a switching transistor and a storage capacitor. When the switching transistor of the first pixel circuit is turned on in response to a high level of the first pulse control signal, the first data is written into the storage capacitor of the first pixel circuit.

[0009] In one possible implementation, the second pixel circuit includes a switching transistor and a storage capacitor. When the switching transistor of the second pixel circuit is turned on in response to the second pulse control signal being at a high level, the second data is written into the storage capacitor of the second pixel circuit.

[0010] In a possible implementation, outputting a first pulse control signal of a first frequency includes: acquiring a first scanning signal and a first pulse width modulation signal of a first frequency; modulating the first scanning signal using the first pulse width modulation signal, and outputting a first pulse control signal of a first frequency.

[0011] In one possible implementation, outputting a second pulse control signal of a second frequency includes: acquiring a second scanning signal and a second pulse width modulation signal of a second frequency; modulating the second scanning signal using the second pulse width modulation signal, and outputting a second pulse control signal of a second frequency, wherein a duty cycle of the second pulse width modulation signal is greater than a duty cycle of the first pulse width modulation signal.

[0012] In one possible implementation, the method also includes: adjusting the voltages of the first pulse control signal and the second pulse control signal, and adjusting the reset signal voltage output to the first electrode of the switching transistor of the first pixel circuit and the first electrode of the switching transistor of the second pixel circuit, so as to reduce the voltage difference between the control electrode and the first electrode of the switching transistor of the first pixel circuit and the second pixel circuit.

[0013] In a second aspect, an embodiment of the present application provides a display module, comprising: multiple rows of pixels, each row of pixels comprising multiple pixel circuits; multiple partition refresh control circuits, each partition refresh control circuit being coupled to a row of pixel circuits; wherein, a first partition refresh control circuit among the multiple partition refresh control circuits is coupled to a first pixel circuit, and a second partition refresh control circuit among the multiple partition refresh control circuits is coupled to a second pixel circuit, and the first pixel circuit and the second pixel circuit are pixel circuits located in different rows; the first partition refresh control circuit is used to output a first pulse control signal of a first frequency, and the first pulse control signal is used to control the first pixel circuit to write first data according to the first frequency; the second partition refresh control circuit is used to output a second pulse control signal of a second frequency, and the second pulse control signal is used to control the second pixel circuit to write second data according to the second frequency; wherein the first frequency is greater than the second frequency, and the pulse width of the first pulse control signal is less than the pulse width of the second pulse control signal.

[0014] In one possible implementation, the pulse width of the first pulse control signal and the pulse width of the second pulse control signal satisfy: X2·T2 / X1≤Y1<Y2, where Y1 is the pulse width of the first pulse control signal, Y2 is the pulse width of the second pulse control signal, X1 is the first frequency, and X2 is the second frequency.

[0015] In a possible implementation, when the first frequency and the second frequency satisfy: X1 ≥ 12·X2, the pulse width of the first pulse control signal also satisfies: X2·Y2 / X1 ≤ Y1 ≤ Y2 / 12.

[0016] In a possible implementation, the first pixel circuit includes a switching transistor and a storage capacitor. When the switching transistor of the first pixel circuit is turned on in response to a high level of the first pulse control signal, the first data is written into the storage capacitor of the first pixel circuit.

[0017] In one possible implementation, the second pixel circuit includes a switching transistor and a storage capacitor. When the switching transistor of the second pixel circuit is turned on in response to the second pulse control signal being at a high level, the second data is written into the storage capacitor of the second pixel circuit.

[0018] In a possible implementation, the first partition refresh control circuit is used to obtain a first scan signal and a first pulse width modulation signal of a first frequency, modulate the first scan signal using the first pulse width modulation signal, and output a first pulse control signal of a first frequency.

[0019] In one possible implementation, the second partition refresh control is used to obtain a second scanning signal and a second pulse width modulation signal of a second frequency, modulate the second scanning signal using the second pulse width modulation signal, and output a second pulse control signal of a second frequency, wherein the duty cycle of the second pulse width modulation signal is greater than the duty cycle of the first pulse width modulation signal.

[0020] In one possible implementation, the display module also includes a reset circuit, which is used to output a reset signal to the first electrode of the switching transistor of the first pixel circuit or the first electrode of the switching transistor of the second pixel circuit; the first partition refresh control circuit is also used to adjust the voltage of the first pulse control signal, and the reset circuit is used to adjust the voltage of the reset signal output to the first electrode of the switching transistor of the first pixel circuit to reduce the voltage difference between the control electrode and the first electrode of the switching transistor of the first pixel circuit; the second partition refresh control circuit is also used to adjust the voltage of the second pulse control signal, and the reset circuit is used to adjust the voltage of the reset signal output to the first electrode of the switching transistor of the second pixel circuit to reduce the voltage difference between the control electrode and the first electrode of the switching transistor of the second pixel circuit.

[0021] In a third aspect, an embodiment of the present application further provides an electronic device, including a display module and a housing, wherein the display module is the display module provided in the second aspect and any implementation thereof, and the display module is connected to the housing. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a display module provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0024] Figure 3 A timing diagram of a frame of image display provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of the structure of a display module provided in an embodiment of the present application;

[0026] Figure 5A schematic diagram of a display module partition refresh display provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of the structure of a display module with partition refresh provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the structure of a partition refresh control circuit provided in an embodiment of the present application;

[0029] Figure 8 A schematic diagram of the working principle of the display module provided in an embodiment of the present application;

[0030] Figure 9 A schematic diagram comparing the on-times of switching transistors with different refresh rates provided in an embodiment of the present application;

[0031] Figure 10 A schematic structural diagram of another display module provided in an embodiment of the present application;

[0032] Figure 11 A schematic diagram of adjusting the conduction time of a switching transistor for different refresh rates according to an embodiment of the present application;

[0033] Figure 12 A schematic diagram comparing the on-times of switching transistors at different refresh rates provided in an embodiment of the present application;

[0034] Figure 13 A schematic diagram of the working principle of another display module provided in an embodiment of the present application;

[0035] Figure 14 A schematic structural diagram of another display module provided in an embodiment of the present application;

[0036] Figure 15 A flow chart of the display control method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0038] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0039] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0040] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "electrically connected" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0041] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0042] The technical solutions provided in the embodiments of the present application can be applied to various electronic devices including display modules. The electronic devices are, for example, consumer electronic products with display functions, home electronic products, vehicle-mounted electronic products, and financial electronic equipment products. Consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soymilk machines, sweeping robots), etc. Vehicle-mounted electronic products include car navigation systems, car high-density digital video discs (DVDs), etc. Financial electronic equipment products include automated teller machines (ATMs), self-service electronic devices, etc. The embodiments of the present application do not impose any special restrictions on the specific forms of the above-mentioned electronic devices.

[0043] Taking a mobile phone as an example, the electronic device includes a display module, a middle frame, and a housing. The display module and the housing are located on either side of the middle frame, with the back of the display module facing the housing. The display module and the housing can be connected through the middle frame.

[0044] like Figure 1 As shown, the display module 1 includes a display screen 10 and a display driver 20. The display driver 20 is used to provide control signals, reset voltages, and data signals required for luminescence to the pixel circuits in the display screen 10. The display driver 20 is, for example, a display driver integrated circuit (DDIC). Figure 1 The electronic device 1 is taken as an example of a straight-screen mobile phone, which is only an illustration in the embodiment of the present application.

[0045] In some embodiments, the display screen may be a display screen based on an organic light emitting diode (OLED), a mini organic light emitting diode (micro OLED) display screen, a quantum dot light emitting diode (QLED) display screen, or the like that can achieve self-luminescence.

[0046] For any of the above-mentioned display screens, the display screen includes an active display area (AA) and a non-display area BB located around the active display area AA. The active display area AA is used to display an image, and the active display area AA includes a plurality of pixels. For example, the plurality of pixels are arranged in a matrix form into a plurality of rows and columns. For example, pixels arranged in a row along the horizontal direction X are referred to as a row of pixels, and pixels arranged in a row along the vertical direction Y are referred to as a column of pixels.

[0047] Each pixel is provided with a pixel circuit. Figure 2 This is a structural diagram of the pixel circuit 11 provided in an embodiment of the present application. The pixel circuit 11 generally includes a driving circuit composed of multiple transistors and a light-emitting device. The driving circuit generates a driving current to drive the light-emitting device to emit light, thereby realizing the light-emitting of the pixel circuit 11.

[0048] For example, see Figure 2 The driving circuit may include transistors T1 to T8 and a storage capacitor Cst.

[0049] In some embodiments of the present application, transistor T1 can be configured to be electrically connected to a data voltage terminal DATA, a first power supply terminal ELVDD, a node N1 (i.e., a first node), and a node N3 (i.e., a third node). A first electrode (which can be a source) of transistor T1, a second electrode of transistor T5, and a second electrode of transistor T6 are coupled to node N4. A first electrode of transistor T6 is connected to the data voltage terminal DATA, and a first electrode of transistor T5 is connected to the first power supply terminal ELVDD. A control electrode (which can be a gate) of transistor T1 can be electrically connected to node N1 (the gate voltage of transistor T1 can be equal to the voltage of node N1), and a second electrode (which can be a drain or gate) of transistor T1 can be configured to be electrically connected to node N3.

[0050] The transistor T2 can be electrically connected to the node N3, the light-emission control signal terminal CEM, and the light-emitting device OLED. A first electrode (which can be a source or a drain) of the transistor T2 can be electrically connected to the node N3, and a control electrode (which can be a gate) of the transistor T2 can be electrically connected to the light-emission control signal terminal CEM. A second electrode (which can be a drain or a gate) of the transistor T2 can be electrically connected to the anode of the light-emitting device OLED, and a cathode of the light-emitting device OLED can be electrically connected to the second power supply terminal ELVSS.

[0051] The transistor T3 can be configured to be electrically connected to the node N1, the first control signal terminal C1, and the node N2 (i.e., the second node). The first electrode (which can be a drain) of the transistor T3 can be configured to be electrically connected to the node N1, the control electrode (which can be a gate) of the transistor T3 can be configured to be electrically connected to the first control signal terminal C1, and the second electrode (which can be a source) of the transistor T3 can be configured to be electrically connected to the node N2.

[0052] The transistor T4 can be configured to be electrically connected to the node N2, the second control signal terminal C2, and the first reset circuit Vp1. A first electrode (which can be a drain) of the transistor T4 can be configured to be electrically connected to the node N2, a control electrode (which can be a gate) of the transistor T4 can be configured to be electrically connected to the second control signal terminal C2, and a second electrode (which can be a source) of the transistor T4 can be configured to be electrically connected to the first reset circuit Vp1.

[0053] The storage capacitor Cst may be configured to be electrically connected to the first power terminal ELVDD and the node N1 (that is, the storage capacitor Cst may be electrically connected between the first power terminal ELVDD and the node N1 ).

[0054] The voltage Vdd input to the first power supply terminal ELVDD can be a DC voltage. The storage capacitor Cst has the function of isolating the DC voltage. When the driving circuit drives the light-emitting device OLED, the voltage Vdd input to the first power supply terminal ELVDD is blocked by the storage capacitor Cst and has no effect on the voltage of the node N1.

[0055] In some other embodiments, the node N2 may be electrically connected to the node N3, and the voltage of the node N2 is equal to the voltage of the node N3.

[0056] The control electrode of the transistor T5 is connected to the light emitting control signal terminal CEM, and the control electrode of the transistor T6 is connected to the third control signal terminal C3.

[0057] The first electrode (which may be a source electrode) of transistor T7 is electrically connected to the anode of the light-emitting device OLED, and the second electrode (which may be a drain electrode) of transistor T7 can be electrically connected to the second reset circuit Vp2. The first electrode (which may be a drain electrode) of transistor T8 can be electrically connected to the third reset circuit Vp3, and the second electrode (which may be a source electrode) of transistor T8 can be electrically connected to node N3. The control electrode of transistor T7 and the control electrode of transistor T8 are each electrically connected to the fourth control signal terminal C4. In other words, the control electrodes of transistors T7 and T8 can be connected to the same control signal terminal (i.e., the fourth control signal terminal C4).

[0058] In some embodiments of the present application, transistor T1, transistor T2, transistor T5, transistor T6, transistor T7, and transistor T8 can be low-temperature polysilicon thin film transistors (LTPS TFTs), referred to as LTPS transistors. Of course, these transistors can also be other types of transistors, which are not limited in the embodiments of the present application. Transistor T3 and transistor T4 can be oxide thin film transistors (oxide TFTs), respectively. Of course, transistor T3 and transistor T4 can also be other types of transistors, which are not limited in the embodiments of the present application.

[0059] According to the above electrical connection relationship, we can further obtain:

[0060] The storage capacitor Cst can be used to store the data voltage Vdata of the data voltage terminal DATA. It is understood that when the storage capacitor Cst stores the data voltage Vdata, the transistors T1, T2, and T3 are in the on state.

[0061] Transistor T1 can be used to control the voltage at node N3 based on the data voltage Vdata stored in storage capacitor Cst and the power supply voltage Vdd of the first power supply terminal ELVDD. It will be understood that transistor T1 is a driving transistor, transistor T6 is a switching transistor, and node N3 is electrically connected to transistors T1 and T2. When transistor T2 is in the on state, transistor T1 controls the voltage at node N3, thereby controlling the anode voltage of the light-emitting device OLED.

[0062] The transistor T2 can be used to control the driving current of the light emitting device OLED according to the light emitting control signal EM of the light emitting control signal terminal CEM and the voltage of the node N3. It can be understood that since the transistor T2 can be an LTPS transistor, when the light emitting control signal EM is at a low level, the transistor T2 is in the on state; when the light emitting control signal EM is at a high level, the transistor T2 is in the off state. When the transistor T2 is in the on state, the current between the drain and source of the transistor T1 (which can be expressed as I ds ) can be the driving current of the light-emitting device OLED.

[0063] The transistor T4 may be configured to control the voltage of the node N2 according to the control signal S2n of the second control signal terminal C2 and the voltage of the first reset signal Vref1 provided by the first reset circuit Vp1.

[0064] It is understood that since transistor T4 can be an oxide thin film transistor, when the control signal S2n is at a high level, transistor T4 is in an on state; when the control signal S2n is at a low level, transistor T4 is in an off state. When transistor T4 is in the on state, the voltage at node N2 can be equal to the voltage of the first reset signal Vref1 provided by the first reset circuit Vp1.

[0065] It can also be understood that, since the voltage of node N2 can be equal to the voltage of node N3 and transistor T1 and transistor T4 are not in the on state at the same time, the voltage of node N2 can be controlled by transistor T1 or transistor T4.

[0066] The transistor T3 can be used to control the control electrode voltage (i.e., gate voltage, which can be expressed as V) of the transistor T1 according to the control signal S1n (also called row scanning signal) of the first control signal terminal C1 and the voltage of the node N4. g denoted by Vth1), the threshold voltage of the transistor T1 is compensated according to the control signal S1n and the data voltage Vdata (the threshold voltage of the transistor T1 compensated by the transistor T3 can be denoted by Vth1).

[0067] Since the transistor T3 may be an oxide thin film transistor, when the control signal S1n is at a high level, the transistor T3 is in an on state; when the control signal S1n is at a low level, the transistor T3 is in an off state.

[0068] When transistor T3 is in the on state, the voltage at node N2 can be equal to the voltage at node N1. The functions of transistor T3 can be divided into the following two aspects:

[0069] On the one hand, the transistor T3 and the transistor T4 are both in the on state, and the voltage of the node N1 can be controlled by the voltage of the first reset signal Vref1 provided by the first reset circuit Vp1, that is, the control electrode voltage V g .

[0070] The control voltage V of transistor T1 is controlled by transistor T3 and transistor T4. g The process can be understood as the initialization phase t2 of the driving circuit (refer to the following introduction).

[0071] The control electrode voltage V g During the process, the transistor T3 and the transistor T4 are respectively in the on state.

[0072] On the other hand, when transistor T3 is in the on state and transistor T4 is in the off state, the data voltage Vdata can be written into the storage capacitor Cst through transistor T2, transistor T1 and transistor T3, completing the writing of the data voltage and compensating the threshold voltage of transistor T1.

[0073] In one example, the current I between the drain and source of the transistor T1 is ds It can be expressed by the following formula (1):

[0074] I ds =k(V gs -V th2 ) 2 Formula (1)

[0075] In formula (1), k is the coefficient, V gs represents the voltage between the drain and source of transistor T1, V th2 represents the threshold voltage of transistor T1 (ie, the turn-on voltage of transistor T1).

[0076] Since V gs =V g -V s , and V g =Vdata+V th1 , we can have the following formula (2):

[0077] I ds =k(V gs -V th2 ) 2 =k(Vdata+V th1 -Vdd-V th2 ) 2 Formula (2)

[0078] Since the threshold voltage V of transistor T1 compensated by transistor T3th1 Can be compared with the turn-on voltage V of transistor T1 th2 Cancel, so we can have the following formula (3):

[0079] I ds =k(Vdata-V DD ) 2 Formula (3)

[0080] From formula (3), we can see that the turn-on voltage V of transistor T1 is th2 There is no current I between the drain and source of transistor T1 d That is, the turn-on voltage V th2 There is no impact on the driving current of the light-emitting device OLED.

[0081] From the function of the above-mentioned transistor T3, it can be seen that each driving circuit can compensate the threshold voltage of the internal transistor T1 according to the internal transistor T3. Different driving circuits can eliminate the difference in the turn-on voltage of the corresponding light-emitting device OLED, so that the display brightness of the display device is uniform, that is, the display brightness is as consistent as possible.

[0082] Transistor T5 can be used to control the voltage of node N3 according to the emission control signal EM and the power supply voltage Vdd of the first power supply terminal ELVDD. That is, when transistor T5 is in the on state according to the emission control signal EM, the voltage of node N4 can be equal to the power supply voltage Vdd of the first power supply terminal ELVDD.

[0083] The transistor T6 can be used to control the voltage of the node N4 according to the control signal S3n provided by the third control signal terminal C3 and the data voltage Vdata. When the transistor T6 is turned on according to the control signal S3n, the voltage of the node N4 can be equal to the data voltage Vdata.

[0084] Since transistors T5 and T6 can each be an LTPS transistor, when the light emission control signal EM is at a low level, transistor T5 can be in an on state; when the light emission control signal EM is at a high level, transistor T5 can be in an off state. Similarly, when the third control signal is at a low level, transistor T6 can be in an on state; when the third control signal is at a high level, transistor T6 can be in an off state.

[0085] According to formula (3) above, the driving current of the light-emitting device OLED can be related to the data voltage Vdata. Since the light-emitting device OLED only emits light under the action of the driving current, during the light-emitting phase of the light-emitting device OLED, transistors T1 and T2 can be in an on state, and transistor T5 can also be in an on state, and the voltage at node N4 can be equal to the power supply voltage Vdd of the first power supply terminal ELVDD. Furthermore, transistor T1 can control the voltage at node N3 based on the voltage at node N4 and the control electrode voltage of transistor T1.

[0086] Although both transistors T5 and T6 control the voltage at node N4, they are not turned on at the same time. When transistor T5 is turned on, the voltage at node N4 can be equal to the power supply voltage Vdd of the first power supply terminal ELVDD. When transistor T6 is turned on, the voltage at node N4 can be equal to the data voltage Vdata.

[0087] The transistor T7 can be used to control the anode voltage of the light-emitting device OLED based on the control signal S4n provided by the fourth control signal terminal C4 and the voltage of the second reset signal Vref2 provided by the second reset circuit Vp2. In other words, when the transistor T7 is turned on based on the fourth control signal S4n, the anode voltage of the light-emitting device OLED can be equal to the voltage of the second reset signal Vref2.

[0088] Transistor T8 can be used to control the voltage of node N3 according to the control signal S4n and the voltage of the third reset signal Vref3 provided by the third reset circuit Vp3. That is, when transistor T8 is in the on state according to the control signal S4n, the voltage of node N3 can be equal to the voltage of the third reset signal Vref3.

[0089] The transistor T7 and the transistor T8 can be LTPS transistors, so refer to Figure 2 When the control signal S4n is at a low level, the transistor T7 and the transistor T8 can be in a turned-on state respectively; when the control signal S4n is at a high level, the transistor T7 and the transistor T8 can be in a turned-off state respectively.

[0090] For example, the embodiment of the present application is described by taking the transistors T1, T2, T5, T6, T7, and T8 as LTPS transistors and the transistors T3 and T4 as oxide thin film transistors. Figure 2 The control timing of the driving circuit 11 is provided.

[0091] In one possible implementation, combining Figure 2 and Figure 3The entire process of driving the light-emitting device OLED by the driving circuit can be divided into a first initialization stage t1, a second initialization stage t2, a threshold compensation stage t3, a third initialization stage t4 and a light-emitting stage t5 (the light-emitting stage t5 is only partially shown). The specific timing diagram can be shown as follows: Figure 3 shown.

[0092] (1) In the first initialization phase t1, the light-emission control signal EM and the control signal S3n are both at high levels, and thus, transistors T2, T5, and T6 are turned off. The control signal S1n and the control signal S2n are both at low levels, and thus, transistors T3 and T4 are turned off. The control signal S4n changes from high to low, and then from low to high. Thus, transistors T7 and T8 change from off to on, and from on to off, respectively.

[0093] It can be seen that in the first initialization stage t1, the transistor T7 and the transistor T8 are turned on, which realizes the control of the node N3 voltage (making the voltage of the node N3 the voltage of the third reset signal Vref3) and the control of the anode voltage of the light-emitting device OLED (making the anode voltage of the light-emitting device OLED the voltage of the second reset signal Vref2), that is, the node N3 voltage and the anode voltage of the light-emitting device OLED are reset or reset (or understood as initialization).

[0094] (2) In the second initialization phase t2, the control signal S1n and the control signal S2n change from a low level to a high level, and then from a high level to a low level. Thus, the transistors T3 and T4 change from being off to being on, and then from being on to being off. The light-emitting control signal EM, the control signal S3n, and the control signal S4n remain at a high level. Thus, the transistors T2, T5, T6, T7, and T8 are turned off.

[0095] It can be seen that in the second initialization phase t2, transistors T1, T3, and T4 are turned on, respectively, to achieve voltage control of node N2 and voltage control of node N1. Since transistors T3 and T4 act as switches, node N1 is electrically connected to the control electrode of transistor T1, and node N2 is electrically connected to node N3, thus achieving voltage control of the control electrode of transistor T1, node N1, node N2, and node N3 (making the control electrode voltage of transistor T1, the voltage of node N1, the voltage of node N2, and the voltage of node N3 respectively equal to the voltage of the first reset signal Vref1), that is, achieving the reset or resetting (or understanding as initialization) of the control electrode voltage of transistor T1, the voltage of node N1, the voltage of node N2, and the voltage of node N3.

[0096] (3) In the threshold compensation phase t3, the control signal S1n changes from a low level to a high level, and then from a high level to a low level. Thus, the transistor T3 changes from off to on, and then from on to off. The control signal S3n changes from a high level to a low level, and then from a low level to a high level. Thus, the transistor T6 changes from on to off, and then from off to on. The light-emitting control signal EM and the control signal S4n remain at a high level, respectively, and the control signal S2n remains at a low level. Thus, the transistors T2, T4, T5, T7, and T8 are respectively turned off.

[0097] It can be seen that in the threshold compensation stage t3, the transistor T6, the transistor T3 and the transistor T1 are turned on respectively, so that the data voltage V data The voltage stored in the storage capacitor Cst also compensates the threshold voltage of the transistor T1. The threshold voltage compensation process of the transistor T1 can be considered as the process of the transistor T1 changing from the on state to the off state.

[0098] (4) In the third initialization phase t4, the control signal S4n changes from a high level to a low level, and then from a low level to a high level. Thus, the transistors T7 and T8 change from being off to being on, and then from being on to being off, respectively. The light-emitting control signal EM and the control signal S3n remain at a high level, respectively, and the control signal S1n and the control signal S2n remain at a low level, respectively. Thus, the transistors T1, T2, T3, T4, T5, and T6 are all turned off.

[0099] It can be seen that in the third initialization stage t4, the transistor T7 and the transistor T8 are respectively turned on, realizing the voltage control of the node N3 (making the voltage of the node N3 the voltage of the third reset signal Vref3) and the anode voltage control of the light-emitting device OLED (making the anode voltage of the light-emitting device OLED the voltage of the second reset signal Vref2), that is, the node N3 voltage and the anode voltage of the light-emitting device OLED are reset or reset (or understood as initialization).

[0100] (5) In the light-emitting stage t5, the light-emitting control signal EM changes from a high level to a low level, and transistors T2 and T5 are turned on. The control signals S1n and S2n are low levels, and transistors T3 and T4 are turned off. The control signals S3n and S4n are high levels, and transistors T6, T7, and T8 are turned off.

[0101] In the light emitting stage t5 , the transistor T5 , the transistor T1 and the transistor T2 are turned on respectively, thereby controlling the driving current of the light emitting device OLED, that is, driving the light emitting device OLED, so that the light emitting device OLED emits light.

[0102] The display module includes multiple rows of pixel circuits, and the working mode of the multiple rows of pixel circuits is row-by-row refresh, that is, after the first row of pixel circuits executes the above-mentioned first initialization stage t1, second initialization stage t2, threshold compensation stage t3, third initialization stage t4 and light-emitting stage t5, the second row of pixel circuits enters the above-mentioned first initialization stage t1, second initialization stage t2, threshold compensation stage t3, third initialization stage t4 and light-emitting stage t5, and then each subsequent row of pixel circuits repeats the above-mentioned first initialization stage t1, second initialization stage t2, threshold compensation stage t3, third initialization stage t4 and light-emitting stage t5, and so on, row by row from top to bottom.

[0103] The following is a schematic description of the origins of the control signals received by the first control signal terminal C1 , the second control signal terminal C2 , the third control signal terminal C3 , the fourth control signal terminal C4 , and the light emitting control signal terminal EM in the pixel circuit.

[0104] like Figure 1 As shown, in some embodiments, the display module further includes a plurality of first integrated gate circuits (gate onarrays) GOA1, each first integrated gate circuit GOA1 is used to provide a control signal S1n to a first control signal terminal C1 of one row or more pixel circuits.

[0105] Example, combined Figure 1 and Figure 4 Multiple first integrated gate circuits GOA1 are cascaded. The first integrated gate circuit GOA1 of the first stage receives the first-row start control signal GSTV and outputs a control signal S1n to the first control signal terminal C1 of the pixel circuit of the first row of pixels L1. Starting from the second stage of first integrated gate circuit GOA1, the first integrated gate circuit GOA1 of each stage receives the control signal output by the first integrated gate circuit GOA1 of the previous stage and outputs a control signal S1n to the first control signal terminal C1 coupled to the first integrated gate circuit GOA1 of the current stage, thereby providing the control signal S1n to the first control signal terminal C1 of the pixel circuits of multiple rows row by row.

[0106] like Figure 1 As shown, in some embodiments, the display module further includes a plurality of second integrated gate circuits GOA2 , each second integrated gate circuit GOA2 being configured to provide a control signal S2n to the second control signal terminal C2 of one or more rows of pixel circuits 11 .

[0107] In some embodiments, the display module further includes a plurality of third integrated gate circuits GOA3, each of which is configured to provide a control signal S3n to a third control signal terminal C3 of one or more rows of pixel circuits 11. Of course, each third integrated gate circuit GOA3 may also provide a third control signal to the third control signal terminals C3 of some pixel circuits 11 in a row of pixel circuits 11, and each row of pixel circuits 11 may correspond to a plurality of third integrated gate circuits GOA3.

[0108] In some embodiments, the display module further includes a plurality of fourth integrated gate circuits GOA4 , each of which is configured to provide a control signal S4 n to a fourth control signal terminal C4 of one or more rows of pixel circuits 11 .

[0109] In some embodiments, the display module further includes a plurality of fifth integrated gate circuits GOA5 , and each fifth integrated gate circuit GOA6 is configured to provide a light emission control signal EM to a light emission control signal terminal CEM of a row of pixel circuits 11 .

[0110] By pulling up and down the first integrated gate circuit GOA1, the second integrated gate circuit GOA2, the third integrated gate circuit GOA3, the fourth integrated gate circuit GOA4, and the fifth integrated gate circuit GOA5 at different times, the multiple rows of pixel circuits 11 enter the above-mentioned first initialization stage t1, second initialization stage t2, threshold compensation stage t3, third initialization stage t4, and light-emitting stage t5 row by row.

[0111] It should be understood that Figure 1 The first integrated gate circuit GOA1, the second integrated gate circuit GOA2, the third integrated gate circuit GOA3, the fourth integrated gate circuit GOA4 and the fifth integrated gate circuit GOA5 shown in FIG are distributed on both sides of multiple rows of pixels along the row direction to generate control signals. Figure 1 The arrangement positions of the first integrated gate circuit GOA1 , the second integrated gate circuit GOA2 , the third integrated gate circuit GOA3 , the fourth integrated gate circuit GOA4 and the fifth integrated gate circuit GOA5 in the display module are only for illustration and are not intended to be limiting.

[0112] The display screen includes multiple data voltage terminals DATA. Pixel circuits 11 in the same column are coupled to the same data voltage terminal DATA. A display driver 20 is coupled to the multiple data voltage terminals DATA of the display screen to provide data voltages Vdata to the multiple data voltage terminals DATA.

[0113] The display module also includes multiple reset circuits, see Figure 2 As shown, in the embodiment of the present application, a display module including a first reset circuit Vp1, a second reset circuit Vp2 and a third reset circuit Vp3 is taken as an example for illustration.

[0114] The display driver 20 is coupled to the first reset circuit Vp1, the second reset circuit Vp2, and the third reset circuit Vp3, and is configured to provide reset signals to the first reset circuit Vp1, the second reset circuit Vp2, and the third reset circuit Vp3. The first reset circuit Vp1, the second reset circuit Vp2, and the third reset circuit Vp3 are each coupled to multiple rows of pixel circuits 11 in the display module, and are configured to provide the aforementioned reset signals to the multiple rows of pixel circuits 11 in the display module.

[0115] As mentioned in the above example, since oxide thin-film transistors have the characteristics of low leakage current and LTPS transistors have the characteristics of high electron mobility, the driving circuit provided in the embodiment of the present application combines oxide thin-film transistors and LTPS transistors to support multiple different refresh rates at the same time.

[0116] As can be seen from the preceding example, when transistor T3 is turned on in response to a high-level control signal S1n, the data voltage Vdata is stored in the storage capacitor Cst. This can be considered a refresh of the pixel circuit. Therefore, the refresh rate of the pixel circuit or display screen can be determined by the control signal S1n input to the pixel circuit by the first integrated gate circuit GOA1.

[0117] For example, if the frequency at which the first integrated gate circuit GOA1 outputs the control signal S1n to the pixel circuit is 60 Hz, the transistor T3 of the pixel circuit will be turned on 60 times per second, meaning that data in the pixel circuit will be repeatedly written 60 times, resulting in a refresh rate of 60 Hz. If the frequency at which the first integrated gate circuit GOA1 outputs the control signal S1n to the pixel circuit is 120 Hz, the refresh rate will be 120 Hz.

[0118] With the development of display technology and the emergence of foldable screens, the application scenarios of display modules are expanding, and user demands for display modules are becoming increasingly diverse. Multitasking is also becoming more and more common. However, adjusting the full-screen refresh rate is no longer sufficient to meet user needs. The industry has developed solutions that can control the refresh rate of display modules in different areas, allowing different refresh rates for different areas of the display module.

[0119] like Figure 5 As shown in Figure A, in some cases, a dynamic game interface can be displayed in the upper part of the display screen and a static background area can be displayed in the lower part of the display screen at the same time. The refresh rate of the display screen partition displaying the game interface is higher, such as 120Hz, and the refresh rate of the display screen partition displaying the background area is lower, such as 120Hz. The partitions here are not fixed, but can be dynamically adjusted according to display requirements, for example, combined with Figure 5As shown in Figure B, in other cases, a static background image can be displayed in the upper area of the display screen, a playing video can be displayed in the middle area of the display screen, and a background area can be displayed in the lower area of the display screen. The refresh rate of the display screen partition displaying the background image and the background area is relatively low, for example, 1 Hz, and the refresh rate of the display screen partition displaying the playing video is relatively high, for example, 60 Hz.

[0120] To achieve partitioned refresh, the display module provided in an embodiment of the present application further includes a partitioned refresh control circuit. Exemplarily, the partitioned refresh control circuit can be used to control the refresh rate of the pixel circuit of the display module. For example, taking the first integrated gate circuit GOA1 as an example, a partitioned refresh control circuit is provided between the first integrated gate circuit GOA1 and the pixel circuit. The partitioned refresh control circuit can adjust the frequency of the control signal output by the first integrated gate circuit GOA1 to the driver circuit based on a variable frequency enable (VFE) signal control signal output by the DDIC.

[0121] For example, combined Figure 6 The partition refresh control circuit is arranged between the first integrated gate circuit GOA1 and the pixel circuit. The partition refresh control circuit can adjust the refresh rate of the pixel circuit according to the variable frequency enable (VFE) signal output by the DDIC.

[0122] Taking the control signal output by the first integrated gate circuit GOA1 as an example, for example, the first integrated gate circuit GOA1 outputs a control signal with a frequency of 120Hz. When the VFE signal is at a high level (VGH), the partition refresh control circuit maintains the output waveform of the first integrated gate circuit GOA1 and outputs it to the first control signal terminal C1 of the pixel circuit, and the pixel circuit is refreshed at a frequency of 120Hz; when the VFE signal is at a low level (VGL), the partition refresh control circuit shapes the output signal of the first integrated gate circuit GOA1 into a constant low level and outputs it to the first control signal terminal C1 of the pixel circuit, and the pixel circuit will not be refreshed.

[0123] Figure 7A schematic diagram of a first integrated gate circuit GOA1 and a partition refresh control circuit is shown, wherein the first integrated gate circuit GOA1 omits most circuit connection relationships and is collectively referred to as a control unit. There are many ways to implement the control unit, which are not limited or exemplified here. The first integrated gate circuit GOA1 includes a control unit, a transistor M1, and a transistor M2. The control unit includes a first clock terminal CLK1, a second clock terminal CLK2, an input signal terminal STV_S1, a pull-up (PU) node, and a pull-down (PD) node. The control unit is configured to output a signal at the pull-up node or the pull-down node based on signals from the first clock terminal CLK1, the second clock terminal CLK2, and the input signal terminal STV_S1. The control electrode of the transistor M1 is coupled to the pull-up node, a first electrode of the transistor M1 inputs a high voltage (VGH), and a second electrode of the transistor M1 is connected to a cascade signal terminal, which is configured to connect to the next-stage first integrated gate circuit GOA1. The control electrode of the transistor M2 is coupled to the pull-down node, a first electrode of the transistor M2 is connected to the cascade signal terminal, and a second electrode of the transistor M2 inputs a low voltage (VGL).

[0124] The partition refresh control circuit includes transistors M3 and M4, wherein the control electrode of transistor M3 is connected to the pull-up node of the first integrated gate circuit GOA1, the first electrode of transistor M3 inputs the frequency selection signal, and the second electrode of transistor M3 is connected to the first control signal terminal C1 of the pixel circuit for obtaining the control signal S1n; the control electrode of transistor M4 is connected to the pull-down node of the first integrated gate circuit GOA1, the first electrode of transistor M4 is connected to the first control signal terminal C1, and the second electrode of transistor M4 inputs a low level (voltage low, VGL). Transistors M1 and M3 can be N-type conductive LTPS TFTs, and transistors M2 and M4 can be P-type conductive LTPS TFTs.

[0125] The control unit of the first integrated gate circuit GOA1 can output a signal at the pull-up node or the pull-down node according to the signals of the first clock terminal CLK1, the second clock terminal CLK2, and the input signal terminal STV_S1, for example, output a high-level signal at the pull-up node or output a low-level signal at the pull-down node. When a high-level signal is output at the pull-up node, the transistor M1 is turned on, the transistor M2 is turned off, and the first integrated gate circuit GOA1 outputs a high-level signal to the next-level first integrated gate circuit GOA1; when a low-level signal is output at the pull-down node, the transistor M2 is turned on, the transistor M1 is turned off, and the first integrated gate circuit GOA1 outputs a low-level signal to the next-level first integrated gate circuit GOA1.

[0126] When the first integrated gate circuit GOA1 outputs a high-level signal, the transistor M3 is turned on and the transistor M4 is turned off. The output of the partition refresh control circuit is the VFE signal input to the first electrode of the transistor M3. At this time, if the VFE signal is a low-level signal, the partition refresh control circuit shapes the high-level signal output by the first integrated gate circuit GOA1 into a low-level signal and outputs it to the first control signal terminal C1 of the pixel circuit. The transistor T3 of the pixel circuit is in the off state, and the pixel circuit will not write data to refresh; if the VFE signal is a high-level signal at this time, the partition refresh control circuit maintains the high-level signal output by the first integrated gate circuit GOA1 unchanged and outputs it to the first control signal terminal C1 of the pixel circuit. The transistor T3 of the pixel circuit is in the on state, and data can be written to the storage capacitor Cst of the pixel circuit to refresh the display.

[0127] When the first integrated gate circuit GOA1 outputs a low level signal, the transistor M4 is turned on, the transistor M3 is turned off, and the output of the partition refresh control circuit is the low level (voltage low, VGL) input to the second electrode of the transistor M4.

[0128] Therefore, the partitioned refresh control circuit can be used to adjust the frequency of the control signal output by the first integrated gate circuit GOA1 to the pixel circuit, thereby controlling whether the pixel circuit is refreshed. The above-described partitioned refresh control circuit structure is only an example. The partitioned refresh control circuit can also have other structures and can also be applied to other integrated gate circuits besides the first integrated gate circuit GOA1.

[0129] Combine Figure 6 and Figure 8 , Figure 8 A schematic diagram of the working principle of the display module of an embodiment of the present application is shown. First, the first integrated gate circuit GOA1 of the first stage outputs a control signal to the pixel circuit of the first row of pixels L1 and the first integrated gate circuit GOA1 of the second stage according to the first row scanning signal GSTV output by DDIC, which is recorded as the first control signal.

[0130] The partitioned refresh control circuit, disposed between the first integrated gate circuit GOA1 of the first stage and the first row of pixels L1, frequency-modulates the first control signal according to the frequency gating signal (VFE) and outputs the frequency-modulated first control signal (i.e., control signal S1n) to the first row of pixels L1. For example, if the frequency gating signal is at a high level, the partitioned refresh control circuit maintains the waveform of the first control signal and outputs it to the pixel circuit of the first row of pixels L1, refreshing the display of the pixel circuit of the first row of pixels L1. If the frequency gating signal is at a low level, the partitioned refresh control circuit reshapes the first control signal to a low level and outputs it to the first row of pixels L1, and the pixel circuit of the first row of pixels L1 does not refresh.

[0131] The first integrated gate circuit GOA1 of the second stage outputs a second control signal to the pixel circuits of the second row of pixels L2 and the first integrated gate circuit GOA1 of the third stage according to the first control signal output by the first integrated gate circuit GOA1 of the first stage.

[0132] The partitioned refresh control circuit, disposed between the first integrated gate circuit GOA1 of the second stage and the second row of pixels L2, frequency-modulates the second control signal output by the first integrated gate circuit GOA1 of the second stage according to the frequency gating signal (VFE), and outputs the frequency-modulated second control signal (i.e., control signal S1n) to the second row of pixels L2. For example, if the frequency gating signal is at a high level, the partitioned refresh control circuit maintains the waveform of the second control signal and outputs it to the pixel circuit of the second row of pixels L2, causing the pixel circuit of the second row of pixels L2 to refresh and display; if the frequency gating signal is at a low level, the partitioned refresh control circuit shapes the second control signal to a low level and outputs it to the second row of pixels L2, causing the pixel circuit of the second row of pixels L2 to not refresh.

[0133] In this way, the display is displayed line by line until the display of the last row of pixels is completed (refreshed or not), thus realizing the partition refresh of the display screen.

[0134] Setting a partition refresh control circuit between the first integrated gate circuit GOA1 and the pixel circuit can realize that different partitions of the display screen are displayed at different refresh rates, for example, Figure 9 , one part of the area is displayed at a high refresh rate, such as 120Hz, another part of the area is displayed at a medium refresh rate, such as 60Hz, and another part of the area is displayed at a low refresh rate, such as 30Hz. For the display area refreshed at 120Hz, the transistor T3 of the pixel circuit is turned on 120 times per second; for the display area refreshed at 60Hz, the transistor T3 of the pixel circuit is turned on 60 times per second; for the display area refreshed at 30Hz, the transistor T3 of the pixel circuit is turned on 30 times per second.

[0135] Combine Figure 9 , the switching frequency of the transistor T3 of the pixel circuit is consistent with the refresh rate of the pixel circuit, so the on-time of the transistor T3 will increase with the increase of the refresh rate. The higher the refresh rate, the longer the on-time of the transistor T3. For example, if Figure 9The width of each pulse is t. Within the time range T shown in the figure, the total on-time of transistor T3 in the pixel circuit with a refresh rate of 120Hz is 8t, the total on-time of transistor T3 in the pixel circuit with a refresh rate of 60Hz is 4t, and the total on-time of transistor T3 in the pixel circuit with a refresh rate of 30Hz is 2t. When transistor T3 is turned on under forward bias, it will be continuously affected by positive bias temperature stress (PBTS). The longer the on-time, the greater the impact of PBTS, causing the threshold voltage of transistor T3 to drift (move forward), thereby affecting the voltage written to the drive transistor, resulting in changes in the brightness of the light-emitting device OLED.

[0136] When the refresh rates at different locations on the display screen continue to differ significantly, the threshold voltages of the transistors T3 of the pixel circuits at different locations will vary significantly, resulting in uneven brightness when displaying images of the same brightness due to the difference in threshold voltages.

[0137] In order to improve the above problem, an embodiment of the present application provides a new solution to improve the problem that the threshold voltage of the transistor T3 of the pixel circuit in the partitions of the display screen displaying at different refresh rates has obvious differences and the display effect is reduced.

[0138] The transistor T3 of the pixel circuit with a high refresh rate has a longer on-time and is greatly affected by PBTS, resulting in a more severe threshold voltage drift. The transistor T3 of the pixel circuit with a low refresh rate has a shorter on-time and is less affected by PBTS, resulting in a less severe threshold voltage drift. Therefore, the solution provided in the embodiment of the present application adjusts the pulse width of the control signal output to the first control signal terminal C1 of the pixel circuit, so that the pulse width of the control signal of the first control signal terminal C1 of the pixel circuit with different refresh rates is different. For example, while maintaining the control signal provided to the first control signal terminal C1 of the pixel circuit with a low refresh rate When the pulse width remains unchanged, the pulse width of the control signal provided to the first control signal terminal C1 of the pixel circuit with a high refresh rate is reduced, so that the conduction time of the transistor T3 of the pixel circuits with different refresh rates is as consistent as possible, or the difference in the conduction time of the transistor T3 of the pixel circuits with different refresh rates is reduced, so that the transistor T3 of the pixel circuits with different refresh rates is affected to a similar extent by PBTS, thereby preventing obvious differences in the threshold voltages of the transistor T3 of the pixel circuits with different refresh rates or at different positions, and improving the problem of uneven brightness of different partitions common in display modules that support refresh of different regions at different frequencies.

[0139] For example, Figure 10This is a schematic diagram of a display module provided in an embodiment of the present application. The display module includes multiple rows of pixels, and each row of pixels includes multiple pixel circuits. For the sake of simplicity, Figure 10 Taking the first pixel circuit and the second pixel circuit as an example, the first pixel circuit and the second pixel circuit are pixel circuits in different rows of the display module. For example, the first pixel circuit is located in the first partition of the display module refreshed at a first frequency, and the second pixel circuit is located in the second partition of the display module refreshed at a second frequency.

[0140] The display module also includes a first GOA circuit, a first partition refresh control circuit, a second GOA circuit and a second partition refresh control circuit, combined with Figure 4 , the first GOA circuit and the second GOA circuit here refer to first integrated gate circuits GOA1 of different levels (or different rows), wherein the first GOA circuit is used to output a control signal to the first control signal terminal C1 of the first pixel circuit, the first control signal terminal C1 of the pixel circuit is connected to the control electrode of the transistor T3, and the first partition refresh control circuit is arranged between the first GOA circuit and the first pixel circuit, for modulating the frequency and pulse width of the control signal output by the first GOA circuit to the control electrode of the transistor T3 of the first pixel circuit, and outputting the modulated control signal (first pulse control signal) to the first control signal terminal C1 of the first pixel circuit to control the refresh display of the first pixel circuit. For the sake of distinction, in the embodiment of the present application, the control signal output by the first GOA circuit is referred to as the first scanning signal, and the control signal output by the first partition refresh control circuit after modulation is referred to as the first pulse control signal.

[0141] The second GOA circuit is used to output a second scanning signal to the first control signal terminal C1 of the second pixel circuit. The first control signal terminal C1 of the second pixel circuit is connected to the control electrode of the transistor T3. The second partition refresh control circuit is arranged between the second GOA circuit and the second pixel circuit, and is used to modulate the frequency and pulse width of the second scanning signal output by the second GOA circuit to the control electrode of the transistor T3 of the second pixel circuit, and output the modulated second pulse control signal to the first control signal terminal C1 of the second pixel circuit to control the refresh display of the second pixel circuit.

[0142] The first partition refresh control circuit is used to modulate the first scanning signal output by the first GOA circuit according to the first pulse width modulation signal, and output a first pulse control signal of a first frequency to the first pixel circuit, and the first pulse control signal is used to control the first pixel circuit to write the first data at the first frequency; the second partition refresh control circuit is used to modulate the second scanning signal output by the second GOA circuit according to the second pulse width modulation signal, and output a second pulse control signal of a second frequency to the second pixel circuit, and the second pulse control signal is used to control the second pixel circuit to write the second data according to the second frequency, and the first frequency is greater than the second frequency, for example, the first frequency is 120Hz and the second frequency is 30Hz, that is, the conduction frequency of the transistor T3 of the pixel circuit of the first partition of the display module (for example, the first pixel circuit) is greater than the conduction frequency of the transistor T3 of the pixel circuit of the second partition of the display screen (for example, the second pixel circuit), and the pulse width of the first pulse control signal is less than the pulse width of the second pulse control signal. In this way, the total conduction time of the transistor T3 of the first pixel circuit with a higher refresh frequency can be as close as possible to the conduction time of the transistor T3 of the second pixel circuit with a lower refresh frequency, so that the degree of influence of the PBTS on the two is as similar as possible, and the degree of threshold drift is comparable, thereby avoiding brightness differences between different pixel circuits or different partitions of the display screen. In an embodiment of the present application, the pulse width modulation signal can be a VFE signal.

[0143] In order to make the degree to which the transistor T3 of the first pixel circuit and the transistor T3 of the second pixel circuit are affected by PBTS as close as possible, that is, the conduction time of the transistor T3 of the first pixel circuit and the transistor T3 of the second pixel circuit need to be as similar as possible, in the embodiment of the present application, the first frequency is recorded as X1, the second frequency is recorded as X2, the pulse width of the first pulse control signal is recorded as Y1, the pulse width of the second pulse control signal is recorded as Y2, the conduction time of the transistor T3 of the first pixel circuit is X1*Y1, and the conduction time of the transistor T3 of the second pixel circuit is X2*Y2.

[0144] Since the first frequency is greater than the second frequency, that is, X1 is greater than X2, when Y1=Y2, X1*Y1 is greater than X2*Y2, so it is necessary to reduce the pulse width Y1 of the first pulse control signal so that the pulse width Y1 of the first pulse control signal is smaller than the pulse width Y2 of the second pulse control signal.

[0145] The transistor T3 of the first pixel circuit is turned on at a first frequency, and the transistor T3 of the second pixel circuit is turned on at a second frequency. If the pulse width of the first pulse control signal is the same as the pulse width of the second pulse control signal, that is, each time the transistor T3 of the first pixel circuit is turned on is the same as each time the transistor T3 of the second pixel circuit is turned on, then the total on-time of the transistor T3 of the first pixel circuit will be longer than the on-time of the transistor T3 of the second pixel circuit. In the embodiment of the present application, the pulse width of the first pulse control signal is smaller than the pulse width of the second pulse control signal, thereby reducing the difference between the total on-time of the transistor T3 of the first pixel circuit with a higher refresh frequency and the on-time of the transistor T3 of the second pixel circuit with a lower refresh frequency, reducing the difference in the degree of influence of the PBTS between the two, and avoiding brightness differences in different pixel circuits or different partitions of the display screen.

[0146] In one possible implementation, X1*Y1 can be made equal to X2*Y2, that is, Y1=(Y2·X2) / X1. In this way, the total on-time of the transistor T3 of the second pixel circuit with a low refresh rate and the first pixel circuit with a high refresh rate is the same, and the degree of threshold drift caused by the influence of PBTS is also the same, so there will be no brightness difference.

[0147] In the case where X1*Y1 is equal to X2*Y2, if the pulse width of the first pulse control signal continues to decrease, for example, Y1<(Y2·X2) / X1, the total on-time of the transistor T3 of the second pixel circuit with a low refresh rate will be longer than the total on-time of the transistor T3 of the first pixel circuit with a high refresh rate, which will lead to the problem of uneven brightness. Therefore, in the embodiment of the present application, the lower limit of the pulse width Y1 of the first pulse control signal is:

[0148] Y1≥(Y2·X2) / X1

[0149] The pulse width of the first pulse control signal needs to be smaller than the pulse width of the second pulse control signal, that is, the pulse width Y1 of the first pulse control signal can be in the range of:

[0150] (Y2·X2) / X1≤Y1<Y2

[0151] However, the refresh rates of different zones of the display screen vary. In some cases, the difference between the first frequency and the second frequency may be small. For example, the first frequency may be 120Hz and the second frequency may be 90Hz. In this case, it is relatively easy to achieve the situation where Y1 = (Y2·X2) / X1. However, in some cases, the difference between the first frequency and the second frequency may be relatively large. For example, if X1 is greater than 12X2, for example, if X1 is 120Hz and X2 is 1Hz, due to process limitations, the pulse width Y1 of the first pulse control signal cannot reach 1 / 120 of the pulse width Y2 of the second pulse control signal. Therefore, in cases such as X1>12X2, the pulse widths Y1 and Y2 of the first pulse control signal can be set to satisfy the following conditions:

[0152] (Y2·X2) / X1≤Y1<Y2 / 12

[0153] When Y1 is less than Y2 / 12, although the total conduction time of the transistor T3 of the pixel circuits with different refresh rates cannot be completely made the same, the difference can be narrowed to avoid the problem of uneven display brightness.

[0154] In summary, in the embodiment of the present application, the partition refresh control circuit uses a pulse width control signal to adjust the pulse width of the first pulse control signal and the second pulse control signal, so that when the first pixel circuit is refreshed at the first frequency and the second pixel circuit is refreshed at the second frequency, the difference in the total conduction time of the transistor T3 of the first pixel circuit and the transistor T3 of the second pixel circuit is reduced, so that the degree to which the transistor T3 of the first pixel circuit and the transistor T3 of the second pixel circuit are affected by PBTS is as similar as possible, so that the threshold drift degrees of different transistors T3 are also similar, which can avoid the display screen from having obvious brightness differences due to obvious differences in the threshold values of the transistor T3 of the pixel circuits at different positions.

[0155] The structure and principle of the GOA circuit and the partition refresh control circuit have been described in detail in the above examples and will not be repeated here. In the embodiment of the present application, when the VFE signal is at a high level, the partition refresh control circuit can output the scanning signal output by the GOA circuit as a pulse control signal to the pixel circuit, and the transistor T3 of the pixel circuit can be turned on to refresh the displayed content; when the VFE signal is at a low level, the partition refresh control circuit shapes the scanning signal output by the GOA circuit into a constant low-level signal output, and the transistor T3 of the pixel circuit will not be turned on. Therefore, the VFE signal can be used to adjust the frequency of the pulse control signal of different pixel circuits to achieve the effect of adjusting the refresh rate of different pixel circuits.

[0156] The first partition refresh control circuit can modulate the first scan signal using the first pulse width modulation signal VFE1 to obtain a first pulse control signal, and the second partition refresh control circuit can modulate the second scan signal using the second pulse width modulation signal VFE2 to obtain a second pulse control signal. The frequency of the first pulse width modulation signal VFE1 is greater than the frequency of the second pulse width modulation signal VFE2. For example, the frequency of the first pulse width modulation signal VFE1 is the first frequency, and the frequency of the second pulse width modulation signal VFE2 is the second frequency. The solution provided in the embodiment of the present application can also adjust the pulse width of the pulse control signal by adjusting the high-level duty cycle of the VFE signal.

[0157] For example, the first partition refresh control circuit uses the first pulse width modulation signal VFE1 of the first frequency to modulate the pulse width and frequency of the first scanning signal, and the second partition refresh control circuit uses the second pulse width modulation signal VFE2 of the second frequency to modulate the pulse width and frequency of the second scanning signal. The high-level duty cycle of the first pulse width modulation signal VFE1 is smaller than the high-level duty cycle of the second pulse width modulation signal VFE2, so that the pulse width of the first pulse control signal can be modulated to be smaller than the pulse width of the second pulse control signal.

[0158] For example, combining Figure 11 If the display screen includes a partition refreshed at a high frequency of 120 Hz, a partition refreshed at a medium frequency of 60 Hz, and a partition refreshed at a low frequency of 30 Hz, the pulse width of the pulse control signal S1n in the high frequency zone is smaller than the pulse width of the pulse control signal S1n in the medium frequency zone, and the pulse width of the pulse control signal S1n in the medium frequency zone is smaller than the pulse width of the pulse control signal S1n in the low frequency zone.

[0159] Accordingly, combined Figure 11 and Figure 12 The frequency of the pulse width modulation signal VFE in the high frequency region is greater than the frequency of the pulse width modulation signal VFE in the intermediate frequency region, and the high-level duty cycle of the pulse width modulation signal VFE in the high frequency region is lower than the high-level duty cycle of the pulse width modulation signal VFE in the intermediate frequency region; the frequency of the pulse width modulation signal VFE in the intermediate frequency region is greater than the frequency of the pulse width modulation signal VFE in the low frequency region, and the high-level duty cycle of the pulse width modulation signal VFE in the intermediate frequency region is lower than the high-level duty cycle of the pulse width modulation signal VFE in the low frequency region.

[0160] For example, if the display screen includes a partition refreshed at a high frequency of 120Hz, a partition refreshed at a medium frequency of 60Hz, and a partition refreshed at a low frequency of 1Hz, without adopting the pulse width modulation scheme of this scheme, the pulse width of the pulse control signal of the pixel circuits of different refresh rate partitions is the same, usually between 6H and 100H (H is the row scanning time, usually around 1 to 2us), for example 50H, that is, the duration of each turn-on of the transistor T3 of the pixel circuits of different refresh rate partitions is 50H, then within 1 second, the total turn-on time of the transistor T3 of the pixel circuit in the high-frequency refresh area is 120*50H=6000H; the total turn-on time of the transistor T3 of the pixel circuit in the medium-frequency refresh area is 60*50H=3000H; and the total turn-on time of the transistor T3 of the pixel circuit in the low-frequency refresh area is 1*50H=50H. It can be seen that the total conduction time of the transistor T3 in the pixel circuits in the high refresh area, medium refresh area and low refresh area varies greatly. The transistor T3 in the pixel circuits in the high frequency refresh area, medium frequency refresh area and low frequency refresh area is significantly affected by PBTS, causing threshold drift and resulting in uneven display brightness of the display screen.

[0161] The solution provided by the embodiment of the present application modulates the pulse width of the pulse control signal in the high-frequency refresh zone through the VFE signal, for example, reducing 50H to 10H, and modulates the pulse width of the pulse control signal in the medium-frequency refresh zone through the VFE signal, for example, reducing 50H to 20H. The pulse width of the pulse control signal in the low-frequency refresh zone can remain unchanged at 50H. Then, within 1s, the total turn-on time of the transistor T3 of the pixel circuit in the high-frequency refresh zone is 120*10H=1200H; the total turn-on time of the transistor T3 of the pixel circuit in the medium-frequency refresh zone is 60*20H=1200H; and the total turn-on time of the transistor T3 of the pixel circuit in the low-frequency refresh zone is 1*50H=50H, which greatly reduces the difference in the turn-on time of the transistor T3 of the pixel circuits in the high-frequency refresh zone, the medium-frequency refresh zone, and the low-frequency refresh zone, and also reduces the difference in the transistor T3 affected by PBTS, thereby improving the problem of uneven display.

[0162] For example, the first pulse width modulation signal and the second pulse width modulation signal can be different signals. For example, for multiple rows of pixels, Figure 13As shown in the figure, for 16 rows of pixel circuits, the partition refresh control circuits corresponding to the 1st to 4th rows of pixel circuits can be connected to the same pulse width modulation signal, such as VFE1, and output pulse control signals S1n-1 to S1n-4 to the 1st to 4th rows of pixel circuits respectively; the partition refresh control circuits corresponding to the 5th to 8th rows of pixel circuits can be connected to the same pulse width modulation signal, such as VFE2, and output pulse control signals S1n-5 to S1n-8 to the 5th to 8th rows of pixel circuits respectively; the partition refresh control circuits corresponding to the 9th to 12th rows of pixel circuits can be connected to the same pulse width modulation signal, such as VFE3, and output pulse control signals S1n-9 to S1n-12 to the 9th to 12th rows of pixel circuits respectively; the partition refresh control circuits corresponding to the 13th to 16th rows of pixel circuits can be connected to the same pulse width modulation signal, such as VFE4, and output pulse control signals S1n-13 to S1n-16 to the 13th to 16th rows of pixel circuits respectively; in this way, the partition refresh control of 16 rows of pixels can be achieved using 4 groups of VFE signals.

[0163] In other possible implementations, more VFE signals can be used to implement partitioned refresh control of pixels, or fewer VFE signals can be used to implement partitioned refresh control of the display screen. For example, two groups of VFE signals can be used to implement partitioned refresh control of 16 rows of pixel circuits.

[0164] In addition, the above example introduces that the pulse width and frequency of the pulse control signal output to the pixel circuit are adjusted by the same pulse width modulation signal. In some other embodiments, the pulse width and frequency of the control signal output to the pixel circuit can also be modulated separately by two signals. For example, one signal is used to adjust the frequency of the control signal to achieve partition refresh control, and the other pulse width modulation signal is used to pulse width modulate the control signal after the frequency is adjusted to improve the problem of uneven display brightness caused by the uneven influence of PBTS on the transistor T3 of the pixel circuit in different refresh rate partitions.

[0165] Combine Figure 6 and Figure 14 , Figure 14 A schematic diagram of the working principle of the display screen of an embodiment of the present application is shown. First, the first integrated gate circuit GOA1 of the first stage outputs a control signal to the pixel circuit of the first row of pixels L1 and the first integrated gate circuit GOA1 of the second stage according to the first row scanning signal GSTV output by DDIC, which is recorded as the first control signal.

[0166] The partitioned refresh control circuit, disposed between the first integrated gate circuit GOA1 of the first stage and the first row of pixels L1, modulates the frequency and pulse width of the first control signal according to the VFE signal, and outputs the frequency-modulated first control signal (i.e., control signal S1n) to the first row of pixels L1. For example, if the frequency selection signal is at a high level, the partitioned refresh control circuit maintains the waveform of the first control signal, modulates the pulse width of the first control signal based on the duty cycle of the VFE signal, and outputs the modulated first control signal to the pixel circuit of the first row of pixels L1, causing the pixel circuit of the first row of pixels L1 to refresh its display. If the frequency selection signal is at a low level, the partitioned refresh control circuit shapes the first control signal to a low level and outputs it to the first row of pixels L1, causing the pixel circuit of the first row of pixels L1 to not refresh.

[0167] The first integrated gate circuit GOA1 of the second stage outputs a second control signal to the pixel circuits of the second row of pixels L2 and the first integrated gate circuit GOA1 of the third stage according to the first control signal output by the first integrated gate circuit GOA1 of the first stage.

[0168] The partitioned refresh control circuit, disposed between the first integrated gate circuit GOA1 of the second stage and the second row of pixels L2, modulates the frequency and pulse width of the second control signal output by the first integrated gate circuit GOA1 of the second stage according to the VFE signal, and outputs the frequency- and pulse-width-modulated second control signal (i.e., control signal S1n) to the second row of pixels L2. For example, if the frequency selection signal is at a high level, the partitioned refresh control circuit maintains the waveform of the second control signal, modulates the pulse width of the second control signal based on the duty cycle of the VFE signal, and outputs the modulated second control signal to the pixel circuit of the second row of pixels L2, causing the pixel circuit of the second row of pixels L2 to refresh and display. If the frequency selection signal is at a low level, the partitioned refresh control circuit shapes the second control signal to a low level and outputs it to the second row of pixels L2, causing the pixel circuit of the second row of pixels L2 to not refresh.

[0169] In this way, the display is displayed line by line until the display of the last row of pixels is completed (refreshed or not), thereby realizing the partitioned refresh of the display screen and adjusting the opening time of the transistor T3 of the pixel circuit with different refresh rates.

[0170] The above example introduces how to adjust the pulse width of the pulse control signal of the pixel circuit with different refresh rates in a display screen that supports partitioned refresh control, thereby improving the threshold voltage drift problem caused by the influence of PBTS when the transistor T3 of the display screen works at different frequencies, and the resulting display unevenness problem. In addition, the threshold voltage of the transistor T3 of the pixel circuit can also be reset by a reset signal to avoid the problem of uneven display of the display screen caused by its threshold voltage drift.

[0171] The first partition refresh control circuit is further configured to adjust the voltage of the first pulse control signal, and the reset circuit is configured to adjust the voltage of the reset signal output to the first electrode of the switching transistor of the first pixel circuit to reduce the voltage difference between the control electrode and the first electrode of the switching transistor of the first pixel circuit. The second partition refresh control circuit is further configured to adjust the voltage of the second pulse control signal, and the reset circuit is configured to adjust the voltage of the reset signal output to the first electrode of the switching transistor of the second pixel circuit to reduce the voltage difference between the control electrode and the first electrode of the switching transistor of the second pixel circuit.

[0172] For example, combined Figure 2 The pixel circuit shown in the display module includes a reset circuit, which is used to provide a reset signal to the pixel circuit. The reset signal can reset the transistor T3, for example Figure 2 The third reset circuit Vp3 shown in FIG. 1 is connected to the first electrode (e.g., the source electrode) of the transistor T3, and the second electrode of the transistor T3 is connected to the node N1 or the storage capacitor Cst. Exemplarily, the third reset circuit Vp3 can also adjust the voltage of the third reset signal output to the first electrode (e.g., the source electrode) of the transistor T3, and the partition refresh control circuit can appropriately reduce the voltage of the pulse control signal output to the control electrode (e.g., the gate electrode) of the transistor T3, thereby compensating for the Vgs voltage difference of the transistor T3, thereby reducing the difference in PBTS experienced by the switching transistors in different pixel circuits.

[0173] The above-mentioned method of adjusting the pulse control signal voltage and adjusting the reset signal voltage can be used alone to compensate the transistor T3, or can be used in combination with the pulse width modulation scheme introduced in the above example.

[0174] In combination with the display module provided in the above example, the embodiment of the present application further provides a display control method. Figure 15 A schematic diagram of a control method provided in an embodiment of the present application, the method comprising:

[0175] S21: Output a first pulse control signal of a first frequency, where the first pulse control signal is used to control the first pixel circuit to write first data according to the first frequency.

[0176] S22: Output a second pulse control signal of a second frequency, where the second pulse control signal is used to control the second pixel circuit to write second data according to the second frequency. The first pixel circuit and the second pixel circuit are pixel circuits located in different rows. The first frequency is greater than the second frequency, and the pulse width of the first pulse control signal is less than the pulse width of the second pulse control signal.

[0177] The first pixel circuit and the second pixel circuit are pixel circuits located in different rows. For example, the first pixel circuit is located in a first sub-area of a display screen refreshed at a first frequency, and the second pixel circuit is located in a second sub-area of a display screen refreshed at a second frequency. The switching transistor of the first pixel circuit (for example, the switching transistor may be the aforementioned Figure 2 The transistor T3 in the pixel circuit provided in the illustrated example can be turned on in response to a first pulse control signal. When the switching transistor of the first pixel circuit is turned on, the first data can be written into the storage capacitor of the first pixel circuit, that is, the data of the first pixel circuit can be refreshed. The switching transistor of the second pixel circuit can be turned on in response to a second pulse control signal. When the switching transistor of the second pixel circuit is turned on, the second data can be written into the storage capacitor of the second pixel circuit, that is, the data of the second pixel circuit can be refreshed.

[0178] The first frequency is greater than the second frequency, for example, the first frequency is 120 Hz and the second frequency is 30 Hz, that is, the conduction frequency of the transistor T3 of the pixel circuit of the first partition of the display screen (for example, the first pixel circuit) is greater than the conduction frequency of the transistor T3 of the pixel circuit of the second partition of the display screen (for example, the second pixel circuit). For example, within 1 second, the switching transistor of the first pixel circuit is turned on 120 times, and the switching transistor of the second pixel circuit is turned on 30 times. In order to make the degree to which the switching transistor of the first pixel circuit and the switching transistor of the second pixel circuit are affected by PBTS as close as possible, that is, the conduction duration of the switching transistor of the first pixel circuit and the switching transistor of the second pixel circuit are required to be as similar as possible, in the embodiment of the present application, the first frequency is denoted as X1, the second frequency is denoted as X2, the pulse width of the first pulse control signal is denoted as Y1, the pulse width of the second pulse control signal is denoted as Y2, the conduction duration of the switching transistor of the first pixel circuit is X1*Y1, and the conduction duration of the switching transistor of the second pixel circuit is X2*Y2. Since the first frequency is greater than the second frequency, that is, X1 is greater than X2, Y1 needs to be smaller than Y2, that is, the pulse width of the first pulse control signal is smaller than the pulse width of the second pulse control signal.

[0179] The first frequency is greater than the second frequency. If the pulse width of the first pulse control signal is the same as the pulse width of the second pulse control signal, that is, the time for each turn-on of the switching transistor of the first pixel circuit is the same as the time for each turn-on of the switching transistor of the second pixel circuit, then the total turn-on time of the switching transistor of the first pixel circuit will be much longer than the turn-on time of the switching transistor of the second pixel circuit. The pulse width of the first pulse control signal in the embodiment of the present application is smaller than the pulse width of the second pulse control signal. In this way, the total turn-on time of the switching transistor of the first pixel circuit with a higher refresh frequency and the turn-on time of the switching transistor of the second pixel circuit with a lower refresh frequency can be as close as possible, so that the two are affected by PBTS to the same extent as possible, avoiding brightness differences in different pixel circuits or different partitions of the display screen.

[0180] Exemplarily, the pulse width of the first pulse control signal and the pulse width of the second pulse control signal satisfy:

[0181] (Y2·X2) / X1≤Y1<Y2

[0182] However, the refresh rates of different partitions of the display screen vary. In some cases, the difference between the first frequency and the second frequency may be small. For example, the first frequency may be 120Hz and the second frequency may be 90Hz. In this case, it is relatively easy to achieve the situation where Y1 = (Y2·X2) / X1. However, in some cases, the difference between the first frequency and the second frequency may be relatively large. For example, if X1 is 120Hz and X2 is 1Hz, due to process limitations, the pulse width Y1 of the first pulse control signal cannot reach 1 / 120 of the pulse width Y2 of the second pulse control signal. Therefore, in cases such as X1>12X2, the pulse width Y1 of the first pulse control signal and the pulse width Y2 of the second pulse control signal can be set to meet the following conditions:

[0183] (Y2·X2) / X1≤Y1<Y2 / 12

[0184] The relationship between the pulse width Y1 of the first pulse control signal and the pulse width Y2 of the second pulse control signal has been derived in detail in the aforementioned example and will not be repeated here.

[0185] Exemplarily, the partition refresh control circuit can use the VFE signal to adjust the frequency of the pulse control signal output to the pixel circuit. In the embodiment of the present application, the VFE signal can also be used to adjust the pulse width of the pulse control signal output to the pixel circuit.

[0186] Exemplarily, S21: outputting a first pulse control signal of a first frequency includes:

[0187] S21-1: Acquire a first scanning signal and a first pulse width modulation signal with a first frequency;

[0188] S21 - 2 : Modulate the first scanning signal using the first pulse width modulation signal to output a first pulse control signal with a first frequency.

[0189] In the embodiment of this application, Figure 7 and Figure 10 When the first pulse width modulation signal is at a high level, the first partition refresh control circuit can output the first scanning signal output by the first GOA circuit as a pulse control signal to the first pixel circuit, and the switching transistor of the first pixel circuit can be turned on to refresh the displayed content; when the first pulse width modulation signal is at a low level, the first partition refresh control circuit shapes the first scanning signal output by the first GOA circuit into a low-level signal output, and the transistor of the first pixel circuit will not be turned on. The solution provided in the embodiment of the present application can utilize the duty cycle of the high-level signal of the first pulse width modulation signal to adjust the pulse width of the first pulse control signal.

[0190] Exemplarily, S22: outputting a second pulse control signal of a second frequency to a switching transistor of a second pixel circuit includes:

[0191] S22-1: Acquire a second scanning signal and a second pulse width modulation signal of a second frequency;

[0192] S22 - 2 : Modulate the second scanning signal using the second pulse width modulation signal to output a second pulse control signal with a second frequency.

[0193] The second pulse width modulation signal can adjust the frequency of the second pulse control signal. The embodiment of the present application also adds pulse width modulation, and uses the second pulse width modulation signal to modulate the pulse width of the second pulse control signal so that the pulse widths of the first pulse control signal and the second pulse control signal satisfy: (Y2·X2) / X1≤Y1<Y2 or (Y2·X2) / X1≤Y1<Y2 / 12.

[0194] Exemplarily, the duty cycle of the high level of the second pulse width modulation signal is greater than the duty cycle of the high level of the first pulse width modulation signal, so that the pulse width of the first pulse control signal is smaller than the pulse width of the second pulse control signal.

[0195] In one possible implementation, the display control method provided in the embodiment of the present application further includes:

[0196] S23: Adjust the voltages of the first pulse control signal and the second pulse control signal, and adjust the reset signal voltage output to the first electrode of the switching transistor of the first pixel circuit and the first electrode of the switching transistor of the second pixel circuit, so as to reduce the voltage difference between the control electrode and the first electrode of the switching transistor of the first pixel circuit and the second pixel circuit.

[0197] For example, combined Figure 2 The display module includes a reset circuit, which is used to provide a reset signal to the pixel circuit. The reset signal can reset the transistor T3, for example Figure 2 The third reset circuit Vp3 shown in FIG is connected to the first electrode (e.g., the source electrode) of the transistor T3, and the second electrode of the transistor T3 is connected to the node N1 or the storage capacitor Cst. For example, by increasing the voltage of the third reset signal provided to the first electrode of the transistor T3 by the third reset circuit Vp3 and appropriately reducing the voltage of the pulse control signal output to the control electrode of the transistor T3, the voltage difference (Vgs voltage difference) between the control electrode and the first electrode of the transistor T3 can be compensated, thereby reducing the difference in the effect of PBTS on the transistors T3 in different pixel circuits.

[0198] An embodiment of the present application further provides an electronic device, which includes a housing and the display module provided in the aforementioned example. The display module is connected to the housing, and the housing is used to support and protect the display module.

[0199] The above is merely an embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be included in the scope of protection of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection of the claims.

Claims

1. A display control method, characterized in that: The method comprises: outputting a first pulse control signal of a first frequency, wherein the first pulse control signal is used to control the first pixel circuit to write first data according to the first frequency; outputting a second pulse control signal of a second frequency, wherein the second pulse control signal is used to control the second pixel circuit to write second data according to the second frequency; The first pixel circuit and the second pixel circuit are pixel circuits located in different rows, the first frequency is greater than the second frequency, and the pulse width of the first pulse control signal is smaller than the pulse width of the second pulse control signal.

2. The method according to claim 1, characterized in that The pulse width of the first pulse control signal and the pulse width of the second pulse control signal satisfy: X2·Y2 / X1≤Y1<Y2 Wherein, Y1 is the pulse width of the first pulse control signal, Y2 is the pulse width of the second pulse control signal, X1 is the first frequency, and X2 is the second frequency.

3. The method according to claim 2, characterized in that When the first frequency and the second frequency satisfy: X1≥12·X2, the pulse width of the first pulse control signal also satisfies: X2·Y2 / X1≤Y1≤Y2 / 12.

4. The method according to any one of claims 1 to 3, characterized in that The first pixel circuit includes a switching transistor and a storage capacitor. When the switching transistor of the first pixel circuit is turned on in response to the first pulse control signal being at a high level, the first data is written into the storage capacitor of the first pixel circuit.

5. The method according to any one of claims 1 to 3, characterized in that The second pixel circuit includes a switching transistor and a storage capacitor. When the switching transistor of the second pixel circuit is turned on in response to the second pulse control signal being at a high level, the second data is written into the storage capacitor of the second pixel circuit.

6. The method according to any one of claims 1 to 5, characterized in that The output of the first pulse control signal of the first frequency includes: Acquire a first scanning signal and a first pulse width modulation signal of a first frequency; The first scanning signal is modulated by using the first pulse width modulation signal to output a first pulse control signal with a first frequency.

7. The method according to claim 6, characterized in that The second pulse control signal outputting the second frequency includes: Acquire a second scanning signal and a second pulse width modulation signal of a second frequency; The second scanning signal is modulated by the second pulse width modulation signal to output a second pulse control signal of a second frequency, wherein the duty cycle of the second pulse width modulation signal is greater than the duty cycle of the first pulse width modulation signal.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: Adjust the voltages of the first pulse control signal and the second pulse control signal, and adjust the reset signal voltage output to the first electrode of the switching transistor of the first pixel circuit and the first electrode of the switching transistor of the second pixel circuit, so as to reduce the voltage difference between the control electrode and the first electrode of the switching transistor of the first pixel circuit and the second pixel circuit.

9. A display module, characterized in that: include: a plurality of rows of pixels, each row of pixels including a plurality of pixel circuits; a plurality of partition refresh control circuits, each of the partition refresh control circuits being coupled to a row of pixel circuits; wherein a first partition refresh control circuit among the plurality of partition refresh control circuits is coupled to a first pixel circuit, and a second partition refresh control circuit among the plurality of partition refresh control circuits is coupled to a second pixel circuit, the first pixel circuit and the second pixel circuit being located in different rows; The first partition refresh control circuit is used to output a first pulse control signal with a first frequency, and the first pulse control signal is used to control the first pixel circuit to write the first data according to the first frequency; The second partition refresh control circuit is used to output a second pulse control signal with a second frequency, and the second pulse control signal is used to control the second pixel circuit to write second data according to the second frequency; The first frequency is greater than the second frequency, and a pulse width of the first pulse control signal is smaller than a pulse width of the second pulse control signal.

10. The display module according to claim 9, wherein: The pulse width of the first pulse control signal and the pulse width of the second pulse control signal satisfy: X2·Y2 / X1≤Y1<Y2 Wherein, Y1 is the pulse width of the first pulse control signal, Y2 is the pulse width of the second pulse control signal, X1 is the first frequency, and X2 is the second frequency.

11. The display module according to claim 10, wherein: When the first frequency and the second frequency satisfy: X1≥12·X2, the pulse width of the first pulse control signal also satisfies: X2·Y2 / X1≤Y1≤Y2 / 12.

12. The display module according to any one of claims 9 to 11, wherein: The first pixel circuit includes a switching transistor and a storage capacitor. When the switching transistor of the first pixel circuit is turned on in response to the first pulse control signal being at a high level, the first data is written into the storage capacitor of the first pixel circuit.

13. The display module according to any one of claims 9 to 11, characterized in that: The second pixel circuit includes a switching transistor and a storage capacitor. When the switching transistor of the first pixel circuit is turned on in response to the second pulse control signal being at a high level, the storage capacitor of the second pixel circuit is written with the second data.

14. The display module according to any one of claims 9 to 13, wherein: The first partition refresh control circuit is used to obtain a first scanning signal and a first pulse width modulation signal of a first frequency, modulate the first scanning signal using the first pulse width modulation signal, and output a first pulse control signal of the first frequency.

15. The display module according to claim 14, wherein: The second partition refresh control circuit is used to obtain a second scanning signal and a second pulse width modulation signal of a second frequency, modulate the second scanning signal using the second pulse width modulation signal, and output a second pulse control signal of the second frequency, wherein the duty cycle of the second pulse width modulation signal is greater than the duty cycle of the first pulse width modulation signal.

16. The display module according to any one of claims 11 to 15, characterized in that: The display module further includes a reset circuit, configured to output a reset signal to a first electrode of a switch transistor of the first pixel circuit or a first electrode of a switch transistor of the second pixel circuit; The first partition refresh control circuit is further configured to adjust the voltage of the first pulse control signal, and the reset circuit is configured to adjust the voltage of the reset signal output to the first electrode of the switching transistor of the first pixel circuit to reduce the voltage difference between the control electrode and the first electrode of the switching transistor of the first pixel circuit; The second partition refresh control circuit is also used to adjust the voltage of the second pulse control signal, and the reset circuit is used to adjust the voltage of the reset signal output to the first electrode of the switching transistor of the second pixel circuit to reduce the voltage difference between the control electrode and the first electrode of the switching transistor of the second pixel circuit.

17. An electronic device, characterized in that: It comprises a display module and a shell, wherein the display module is the display module according to any one of claims 9 to 16, and the display module is connected to the shell.

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