Perceptual amplification circuit of high-margin magnetic memory

Abstract

The invention discloses a high-margin magnetic memory sensing amplification circuit, and relates to the technical field of computer storage, and the high-margin magnetic memory sensing amplification circuit mainly comprises a spin-orbit torque magnetic random access memory, a delay control unit, a sampling holding unit and an amplification latch unit; the spin-orbit torque magnetic random access memory, the delay control unit, the sampling and holding unit and the amplification latch unit are electrically connected in sequence. By implementing the high-margin magnetic memory sensing amplification circuit provided by the invention, the sensing margin of the high-margin magnetic memory can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer storage technology, and more particularly to a high-margin magnetic storage sensing amplifier circuit. Background Art

[0002] Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM), a third-generation magnetic storage technology, achieves high-speed, low-power non-volatile storage through the spin-orbit torque effect. Its core mechanism is as follows: SOT-MRAM uses spin-orbit torque (SOT) driven by in-plane current to change the magnetization direction of the magnetic tunnel junction (MTJ) to enable data writing. Its core device has a three-terminal structure that separates the read and write paths, avoiding the lifespan limitations of traditional STT-MRAM caused by current passing through the tunnel junction. Regarding spin current generation, the spin Hall effect or Rashba effect in heavy metal layers (such as tungsten and platinum) converts ordinary current into spin-polarized current, which then applies torque to flip the magnetization direction of the free layer. This process requires no external magnetic field, significantly reducing power consumption. Its reading principle involves measuring the difference in tunnel magnetoresistance (TMR) across the MTJ (high and low resistance states correspond to "0" and "1"), combined with dynamic sensing techniques (such as time-domain or voltage-domain detection) to improve read reliability. It offers high read and write speeds, low power consumption, high endurance, and compatibility with advanced CMOS processes (such as 14nm and 28nm), supporting high-density storage (such as 32Mb embedded chips). SOT-MRAM is not only suitable for traditional embedded storage and cache, but also shows potential in in-memory computing and neuromorphic computing, with particular demand in automotive electronics, high-performance computing (HPC), and AI chips. SOT-MRAM, thanks to its high speed, low power consumption, and non-volatility, is gradually moving toward industrialization. However, low TMR and process sensitivity remain key obstacles to its commercialization. Through material innovation, process optimization, and system-level design, it is expected to achieve large-scale application in HPC, automotive electronics, and AI chips in the future, becoming a key breakthrough in the evolution of storage technology.

[0003] Among the existing technical solutions, the literature “Kim J, Jang Y, Kim T, et al. A dual-domain dynamic reference sensing for reliable read operation in SOT-MRAM[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(5): 2049-2059.” shows that the dynamic reference voltage adjustment and dual-domain compensation mechanism effectively alleviate the read reliability problem of SOT-MRAM caused by process fluctuations, low TMR and temperature changes, providing a feasible solution for the industrialization of high-density, low-power SOT-MRAM; its innovation lies in combining analog circuit design with digital control logic to balance performance, power consumption and area, which has important reference value for the development of next-generation magnetic storage technology; the literature “Li N, Liu X, Chen W, et al. Dynamic Time-Domain Sensing Scheme for Spin-Orbit Torque MRAM[J]. IEEE Transactions on Electron Devices, 2024." On the surface, through time-domain response measurement and dynamic compensation mechanism, the dependence of SOT-MRAM on TMR value has been broken, the read reliability and energy efficiency have been significantly improved, and new ideas have been provided for the industrialization of high-density, low-power SOT-MRAM. Its innovation lies in extending the sensing dimension from the voltage / current domain to the time domain, and combining it with a dynamic adjustment strategy, it has opened up a new direction for the performance optimization of next-generation magnetic storage technology. It can be seen that spin-orbit torque magnetic random access memory (SOT-MRAM) is one of the strong candidates for the next generation of embedded memory, but the low tunnel magnetoresistance ratio (TMR) and the decrease in read margin caused by process variations have always been issues of concern. Summary of the Invention

[0004] The object of the present invention is to provide a high-margin magnetic memory sensing amplifier circuit, which can improve the sensing margin of the high-margin magnetic memory.

[0005] The present invention provides a high-margin magnetic memory sensing amplifier circuit, which includes a spin-orbit torque magnetic random access memory, a delay control unit, a sampling and holding unit, and an amplifying latch unit; the spin-orbit torque magnetic random access memory, the delay control unit, the sampling and holding unit, and the amplifying latch unit are electrically connected in sequence.

[0006] Furthermore, the spin-orbit torque magnetic random access memory includes a data unit and a reference unit, the data unit is the smallest unit for storing actual data, and the reference unit includes two columns of spin-orbit torque units connected in parallel, wherein the first column is composed of a P-state unit and an AP-state unit connected in series, and the second column is composed of an AP-state unit and a P-state unit connected in series, and the two columns are connected in parallel to form an intermediate resistance between the P-state resistance and the AP-state resistance.

[0007] Furthermore, the delay control unit includes a data branch, a reference branch and a control circuit.

[0008] Furthermore, the control circuit includes a NAND gate, a first capacitor C1, a second capacitor C2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first PMOS transistor P3, and a second PMOS transistor P4.

[0009] Furthermore, the data branch includes a first inverter I1, a first current-deficient inverter CSI1, a third inverter I3, and a fifth inverter I5 connected in series in sequence; the first current-deficient inverter includes an inverter, a fifth NMOS transistor N5, and a third PMOS transistor P5.

[0010] Furthermore, the reference branch includes a second inverter I2, a second current-deficient inverter CSI2, a fourth inverter I4, and a sixth inverter I6 connected in series in sequence; the second current-deficient inverter includes an inverter, a sixth NMOS transistor N6, and a fourth PMOS transistor P6.

[0011] Furthermore, the gate of the fifth NMOS transistor N5 takes the output voltage of the reference unit of the spin-orbit torque magnetic random access memory as input, and the gate of the third PMOS transistor P5 takes the output voltage of the first PMOS transistor P3 as input.

[0012] Furthermore, the gate of the sixth NMOS transistor N6 takes the output voltage of the data unit of the spin-orbit torque magnetic random access memory as input, and the gate of the fourth PMOS transistor P6 takes the output voltage of the second PMOS transistor P4 as input.

[0013] Furthermore, the sampling and holding unit includes a first transmission gate S1, a second transmission gate S2, a first sampling capacitor C3, and a second sampling capacitor C4; and the sampling and holding unit is controlled by the output of the delay control unit.

[0014] The implementation of the high-margin magnetic memory sensing amplifier circuit provided by the present invention has the following beneficial effects: The present invention combines voltage-domain and time-domain sensing to dynamically change the reference voltage to increase the sensing margin. Specifically, the present invention can provide reliable read operations and shorter read latency in SOT-MRAM. The present invention uses a delay control module and a sample-and-hold module to sample the voltages of data cells and reference cells at different times. Compared with traditional solutions, the sensing margin of the high-margin magnetic memory sensing amplifier circuit proposed in the present invention is almost tripled. In addition, because the proposed sensing does not require additional phases and requires a shorter bit line (BL) discharge time to sample the appropriate voltage difference, the read latency is not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which: Figure 1 This is an electrical schematic diagram of a high-margin magnetic memory sensing amplifier circuit provided by the present invention; Figure 2 This is a basic structural principle diagram of the current-deficient inverter provided by the present invention; Figure 3 The present invention provides a flip delay waveform of a current-short inverter under different bias voltages; Figure 4 The sampling time and voltage margin waveform of the high-margin magnetic memory sensing amplifier circuit provided by the present invention when the data unit is in the P state and the AP state; Figure 5 It is the relevant timing of each module provided by the present invention; Figure 6 This is a basic structural principle diagram of the preamplifier and latch provided by the present invention. DETAILED DESCRIPTION

[0016] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described in detail with reference to the accompanying drawings.

[0017] Figure 1 A schematic diagram of a high-margin magnetic memory sensing amplifier circuit according to this embodiment is shown. In this embodiment, the high-margin magnetic memory sensing amplifier circuit includes a spin-orbit torque magnetic random access memory (STM), a delay control unit, a sample-and-hold unit, and an amplifying latch unit; the STM, delay control unit, sample-and-hold unit, and amplifying latch unit are electrically connected in sequence.

[0018] In an exemplary embodiment, the spin-orbit torque magnetic random access memory includes a data unit and a reference unit, wherein the data unit is the smallest unit for storing actual data, and the reference unit includes two columns of spin-orbit torque units connected in parallel, wherein the first column is composed of a P-state unit and an AP-state unit connected in series, and the second column is composed of an AP-state unit and a P-state unit connected in series, and the two columns are connected in parallel to form an intermediate resistance between the P-state resistance and the AP-state resistance.

[0019] In an exemplary embodiment, the delay control unit includes a data branch, a reference branch, and a control circuit.

[0020] In an exemplary embodiment, the control circuit includes a NAND gate, a first capacitor C1, a second capacitor C2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first PMOS transistor P3, and a second PMOS transistor P4.

[0021] In an exemplary embodiment, the data branch includes a first inverter I1, a first current-deficient inverter CSI1, a third inverter I3, and a fifth inverter I5 connected in series in sequence; the first current-deficient inverter includes an inverter, a fifth NMOS transistor N5, and a third PMOS transistor P5.

[0022] In an exemplary embodiment, the reference branch includes a second inverter I2, a second current-deficient inverter CSI2, a fourth inverter I4, and a sixth inverter I6 connected in series in sequence; the second current-deficient inverter includes an inverter, a sixth NMOS transistor N6, and a fourth PMOS transistor P6.

[0023] In an exemplary embodiment, the gate of the fifth NMOS transistor N5 takes the output voltage of the reference cell of the spin-orbit torque magnetic random access memory as input, and the gate of the third PMOS transistor P5 takes the output voltage of the first PMOS transistor P3 as input.

[0024] In an exemplary embodiment, the gate of the sixth NMOS transistor N6 receives the output voltage of the data unit of the spin-orbit torque magnetic random access memory as input, and the gate of the fourth PMOS transistor P6 receives the output voltage of the second PMOS transistor P4 as input.

[0025] In an exemplary embodiment, the sampling and holding unit includes a first transmission gate S1, a second transmission gate S2, a first sampling capacitor C3, and a second sampling capacitor C4; the sampling and holding unit is controlled by the output of the delay control unit.

[0026] In some embodiments, the high-margin magnetic memory sense amplifier circuit described above may also be implemented in the following manner.

[0027] In this embodiment, the high-margin magnetic memory sensing amplifier circuit includes a SOT-MRAM, a delay control unit, a sample-and-hold unit, and an amplifier latch unit. The SOT-MRAM includes a data unit and a reference unit (composed of two columns of P-state and AP-state spin-orbit torque (SOT) units connected in parallel); the delay control unit is composed of inverters (I1-I6), current-deficient inverters (CSI1, CSI2), and a control unit (NAND gates, C1, C2, N1, N2, N3, N4, P3, P4); Figure 1 As shown, the gates of N5 and P5 transistors of the current-deficient inverter of the data branch are respectively V BLR and V P3 As input, the gates of N6 and P6 transistors of the reference branch's short-circuit inverter are respectively V BLD and V P4 As input; the sample and hold unit is controlled by the output of the delay control unit (VD3, VD4, VR3, VR4), and consists of a transmission gate (S1, S2) and a sampling capacitor (C3, C4). Figure 1 The specific structures of the delay control module and the sample-and-hold module are presented in detail, and the principles and implementation methods of dynamic delay control and cross-bias design are explained. It should be noted that in the delay control module, through the design of the inverter chain and the current-deficient inverter, the cross-bias method is used to realize the dynamic adaptation of the delay signal between the data unit and the reference unit; and the sampling and holding module samples and holds the bit line voltage under the timing generated by the previous stage; the organic combination of the control module and the sampling and holding module can not only accurately capture the subtle changes in the bit line voltage during the decline process, but also implement different sampling strategies for units with different voltage change speeds, thereby greatly improving the reading margin and achieving higher reliability.

[0028] Figure 2 It is the basic structure of the current-deficient inverter. It is composed of an additional PMOS tube and an NMOS tube on the basis of the inverter. An inverter is connected to the back stage to restore the signal level and improve the driving capability.

[0029] Figure 3 The flipping delay of the current-deficient inverter under different bias voltages is given. It can be seen that as the bias voltage decreases, the flipping delay of the current-deficient inverter gradually increases.

[0030] Figure 4 The sampling time and voltage margin waveform of the high-margin magnetic memory sensing amplifier circuit when the data unit is in the P state and AP state are given.

[0031] Figure 5 The timing diagram of the read operation of the high-margin magnetic memory sense amplifier circuit is given when the data cell is in the P state. In the read operation, the BL, like the traditional read circuit, first charges the data bit line and the reference bit line to VDD. Then there is the BL development phase and the sampling phase. In the BL development phase, the BL is discharged. When the stored data is "P", due to Figure 1 The resistance of the data cell is smaller than the reference resistance, so the current on VBLD is greater than the current on VBLR, and the VBLD voltage drops faster than VBLR. Consequently, the bias voltage of the current-deficient inverter on the reference branch is lower than that on the data branch, resulting in a longer inverter flipping delay in the reference branch. Therefore, VD4 flips to a low level before VR4. The control unit, comprised of components such as the NAND gate and holding capacitors (C1 and C2), ensures that the bias voltage stabilizes as it falls, allowing the circuit to conduct properly. After VD4 flips to a low voltage, transmission gate S2 opens, and C4 samples and holds the VBLR voltage at that time. This occurs at time t1. After VR4 drops to a low level, transmission gate S1 opens, and C3 samples and holds the VBLD voltage at that time. This occurs at time t2. The sampled and held voltages VR and VD are then amplified by the preamplifier in the amplification and latch unit, and then compared and latched in the latch. Figure 5 The relevant timing of each module is shown.

[0032] Figure 6 This is the basic structure of a preamplifier and latch. After delay control and sample-and-hold, the voltage difference between VD and VR is approximately 380mV. After preamplification, it can basically reach a voltage difference of 1V. Because the latch is a positive feedback structure, the larger the voltage difference, the shorter the time required for latch comparison. After amplification, the voltage can be compared and latched in a very short time.

[0033] In the circuit design of this embodiment, the UMC-55LP process library was selected to ensure device performance and manufacturing process stability. Specifically, the MOS transistor models used were N_12_LPLVT (N-type MOS transistor) and P_12_LPLVT (P-type MOS transistor), as well as the associated resistors and capacitors.

[0034] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A high-margin magnetic memory sense amplifier circuit, characterized in that: The invention comprises a spin-orbit torque magnetic random access memory, a time delay control unit, a sampling and holding unit and an amplifying latch unit; the spin-orbit torque magnetic random access memory, the time delay control unit, the sampling and holding unit and the amplifying latch unit are electrically connected in sequence.

2. The high-margin magnetic memory sense amplifier circuit according to claim 1, wherein: The spin-orbit torque magnetic random access memory includes a data unit and a reference unit. The data unit is the minimum unit for storing actual data. The reference unit includes two columns of spin-orbit torque units connected in parallel, wherein the first column is composed of a P-state unit and an AP-state unit connected in series, and the second column is composed of an AP-state unit and a P-state unit connected in series. The two columns are connected in parallel to form an intermediate resistance between the P-state resistance and the AP-state resistance.

3. The high-margin magnetic memory sense amplifier circuit according to claim 1, wherein: The delay control unit includes a data branch, a reference branch and a control circuit.

4. The high-margin magnetic memory sense amplifier circuit according to claim 3, wherein: The control circuit includes a NAND gate, a first capacitor C1, a second capacitor C2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first PMOS transistor P3, and a second PMOS transistor P4.

5. The high-margin magnetic memory sense amplifier circuit according to claim 4, characterized in that: The data branch includes a first inverter I1, a first short-circuit inverter CSI1, a third inverter I3, and a fifth inverter I5 connected in series in sequence; the first short-circuit inverter includes an inverter, a fifth NMOS transistor N5, and a third PMOS transistor P5.

6. The high-margin magnetic memory sense amplifier circuit according to claim 4, wherein: The reference branch includes a second inverter I2, a second current-deficient inverter CSI2, a fourth inverter I4, and a sixth inverter I6 connected in series in sequence; the second current-deficient inverter includes an inverter, a sixth NMOS transistor N6, and a fourth PMOS transistor P6.

7. The high-margin magnetic memory sense amplifier circuit according to claim 5, characterized in that: The gate of the fifth NMOS transistor N5 receives the output voltage of the reference cell of the spin-orbit torque magnetic random access memory as input, and the gate of the third PMOS transistor P5 receives the output voltage of the first PMOS transistor P3 as input.

8. The high-margin magnetic memory sense amplifier circuit according to claim 6, wherein: The gate of the sixth NMOS transistor N6 receives the output voltage of the data unit of the spin-orbit torque magnetic random access memory as input, and the gate of the fourth PMOS transistor P6 receives the output voltage of the second PMOS transistor P4 as input.

9. The high-margin magnetic memory sense amplifier circuit according to claim 1, wherein: The sampling and holding unit includes a first transmission gate S1, a second transmission gate S2, a first sampling capacitor C3, and a second sampling capacitor C4; the sampling and holding unit is controlled by the output of the delay control unit.

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