Semiconductor device, memory system and operating method thereof

Abstract

The invention provides a semiconductor device, a memory system and an operating method thereof. In one aspect, a semiconductor device includes a logic unit associated with an identifier. The logic unit includes a control logic and a feedback unit coupled to the control logic. The semiconductor device also includes a control interface coupled to the feedback unit. The control logic is configured to: receive an enumeration command in an iteration from the control interface; driving one or more bits of the identifier to a control interface using a feedback unit; and in response to determining that the bit received from the control interface does not match the driven bit of the identifier, stopping driving the one or more additional bits of the identifier to the control interface.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a logic unit in a semiconductor device or a memory system and an operating method thereof. Background Art

[0002] Due to the demand for large amounts of data storage capacity, the density of storage cells in memory devices has increased over the past few decades. High-density memory devices, such as NAND flash memory devices, typically include one or more logic cells. Each logic cell can be fabricated as a die, with multiple memory cells accessed as a single page. For memory devices with a large number of logic cells, the logic cells are often stacked on top of each other, forming a vertical structure. Summary of the Invention

[0003] This disclosure describes techniques for managing logical units of a memory device.

[0004] A first aspect of the present invention features a semiconductor device comprising: a logic unit associated with an identifier (ID), the logic unit including control logic and a feedback unit coupled to the control logic; and a control interface coupled to the feedback unit. The control logic is configured to: receive an enumeration command in an iteration from the control interface, drive one or more bits of the identifier to the control interface using the feedback unit, and, in response to determining that a received bit received from the control interface does not match a driven bit of the identifier, stop driving one or more additional bits of the identifier to the control interface.

[0005] In some embodiments, the control logic is configured to: in response to determining that a plurality of received bits received from the control interface match a plurality of driven bits of the identifier, store the logic unit index in the control logic according to a number of iterations.

[0006] In some implementations, the control logic is configured to: in response to determining that the plurality of received bits received from the control interface match the plurality of driven bits of the identifier, cease driving the plurality of bits of the identifier in one or more sequence iterations.

[0007] In some embodiments, the control logic includes at least one of the following: a non-volatile fuse configured to store the logical unit index, or a volatile register configured to store the logical unit index.

[0008] In some embodiments, the logic unit is configured to receive information for accessing data stored in the logic unit, and the information includes a logic unit index, an address of the logic unit, and a data access command.

[0009] In some implementations, the enumeration command includes a number of iterations.

[0010] In some embodiments, the feedback unit includes a comparator configured to compare the plurality of received bits with the plurality of driven bits of the identifier, and wherein the control logic is configured to determine whether the plurality of received bits matches the plurality of driven bits of the identifier based on an output of the comparator.

[0011] In some embodiments, the feedback unit is coupled to the control interface via an open drain circuit.

[0012] In some embodiments, the identifier includes at least one of the following: a serial number of the logic unit, or a physical unclonable function (PUF) of the logic unit.

[0013] In some embodiments, the logic unit includes at least one of a NAND flash memory die or a NOR flash memory die.

[0014] In some embodiments, the logic unit is configured to: receive information configured to access data stored in the logic unit from a control interface, wherein the information includes a target identifier, a data access command, and an address; compare the identifier with the target identifier; and access the data according to the data access command in response to determining that the identifier matches the target identifier.

[0015] In some embodiments, the logic unit is further configured to: receive special access information from the control interface, and execute a response action according to the special access information.

[0016] A second aspect of the present invention features a method for operating a logic unit in a semiconductor device. The method includes: receiving an enumeration command in iterations from a control interface of the semiconductor device; driving one or more bits of an identifier associated with the logic unit to the control interface; and, in response to determining that a received bit received from the control interface does not match a driven bit of the identifier, ceasing to drive the one or more additional bits of the identifier to the control interface.

[0017] In some embodiments, the logic unit is a first logic unit, the identifier is a first identifier, and the semiconductor device further includes a second logic unit associated with a second identifier. The operating method further includes: receiving a second enumeration command in a second iteration from the control interface; driving one or more bits of the second identifier associated with the second logic unit to the control interface; and in response to determining that a plurality of received bits received from the control interface match a plurality of driven bits of the second identifier, storing a logic unit index for the second logic unit in the control logic according to a number of the second iterations, and stopping driving the plurality of bits of the second identifier in one or more sequence iterations.

[0018] In some embodiments, storing the logical unit index includes storing the logical unit index in at least one of a non-volatile fuse or a volatile register.

[0019] In some embodiments, the operating method further includes: accessing data stored in the second logical unit according to the information, wherein the information includes a logical unit index, an address of the second logical unit, and a data access command.

[0020] In some implementations, the enumeration command includes the number of the second iteration.

[0021] In some embodiments, determining whether a plurality of received bits received from the control interface match a plurality of driven bits of the second identifier includes determining whether the plurality of received bits received from the control interface match a plurality of driven bits of the second identifier based on an output of a comparator, the output being a result of the comparator comparing the plurality of received bits with the plurality of driven bits of the second identifier.

[0022] In some embodiments, the operating method further includes: receiving information configured to access data stored in the logic unit from the control interface, wherein the information includes a target identifier, a data access command, and an address; comparing the identifier with the target identifier; and accessing the data according to the data access command in response to determining that the identifier matches the target identifier.

[0023] In some embodiments, the operating method further includes: receiving special access information from the control interface; and performing a response action according to the special access information.

[0024] Another aspect of the present invention features a memory system comprising: a semiconductor device including an array of a plurality of memory cells; and a controller coupled to the semiconductor device and configured to control the semiconductor device. The semiconductor device includes a logic unit associated with an identifier, the logic unit including control logic and a feedback unit coupled to the control logic; and a control interface coupled to the feedback unit. The control logic is configured to receive an enumeration command in iterations from the control interface, drive one or more bits of the identifier to the control interface using the feedback unit, and, in response to determining that a received bit received from the control interface does not match a driven bit of the identifier, stop driving one or more additional bits of the identifier to the control interface.

[0025] In some embodiments, the control logic is configured to: in response to determining that a plurality of received bits received from the control interface match a plurality of driven bits of the identifier, store the logic unit index in the control logic according to a number of iterations, and stop driving the plurality of bits of the identifier in one or more sequence iterations.

[0026] In some embodiments, the logic unit is configured to receive information for accessing data stored in the logic unit, and the information includes a logic unit index, an address of the logic unit, and a data access command.

[0027] In some embodiments, the logic unit is configured to: receive information for accessing data stored in the logic unit from a control interface, wherein the information includes a target identifier, a data access command, and an address; compare the identifier with the target identifier; and access the data according to the data access command in response to determining that the identifier matches the target identifier.

[0028] Another aspect of the present invention features a semiconductor device. The semiconductor device includes a logic unit associated with an identifier. The logic unit includes control logic and a feedback unit coupled to the control logic. The semiconductor device also includes a control interface coupled to the feedback unit. The control logic is configured to receive an enumeration command in iterations from the control interface. The control logic is configured to sequentially drive one or more bits of the identifier to the control interface using the feedback unit. The control logic is configured to determine whether the received bits received from the control interface match the one or more bits of the identifier. The control logic is configured to store a logic unit index in the control logic according to the number of iterations.

[0029] In some embodiments, the logic unit is a first logic unit, the identifier is the first identifier, the control logic is the first control logic, and the feedback unit is the first feedback unit. The semiconductor device further includes a second logic unit associated with the second identifier. The second logic unit includes second control logic and a second feedback unit. The second feedback unit is coupled to the second control logic and the control interface. The second control logic is configured to: receive an enumeration command in iterations from the control interface; sequentially drive one or more bits of the second identifier to the control interface via the second feedback unit; determine if one or more received bits from the control interface do not match at least one of the one or more bits of the second identifier; and stop driving one or more additional bits of the second identifier to the control interface.

[0030] In some embodiments, the control logic includes non-volatile fuses that store a logic unit index.

[0031] In some embodiments, the control logic includes a volatile register for storing the logic unit index, wherein the volatile register is configured to be reset when power is cycled.

[0032] In some embodiments, the logic unit is configured to receive information for accessing data stored in the logic unit, the information including a logic unit index, an address of the logic unit, and a data access command.

[0033] In some implementations, the enumeration command includes a number of iterations.

[0034] In some embodiments, the feedback unit includes a comparator that compares the one or more received bits with the one or more bits of the identifier, and the control logic is configured to determine whether the one or more received bits match the one or more bits of the identifier based on an output of the comparator.

[0035] In some embodiments, the feedback unit is coupled to the control interface via an open-drain circuit.

[0036] In some embodiments, the control interface includes at least one of the following: an addressing pad, or a ready-busy interface.

[0037] In some embodiments, the identifier includes at least one of the following: a serial number of the logical unit, or a physical unclonable function of the logical unit.

[0038] In some embodiments, the logic unit includes at least one of the following: a NAND flash memory die, or a NOR flash memory die.

[0039] Another aspect of the present invention features a semiconductor device. The semiconductor device includes a logic unit associated with an identifier. The logic unit includes a control interface coupled to the logic unit. The logic unit is configured to receive information from the control interface for accessing data stored in the logic unit. The information includes a target identifier, a data access command, and an address. The logic unit is configured to compare the identifier with the target identifier. In response to determining that the identifier matches the target identifier, the logic unit is configured to access the data according to the data access command.

[0040] In some embodiments, the logic unit is further configured to: receive special access information from the control interface, and execute a response action according to the special access information.

[0041] Another aspect of the present invention features a method for operating a logic unit in a semiconductor device. The method includes receiving an enumeration command in iterations from a control interface of the semiconductor device. The method includes sequentially driving one or more bits associated with an identifier of the logic unit to the control interface. The method includes determining whether one or more received bits from the control interface match one or more bits of the identifier. The method includes storing a logic unit index according to a number of iterations.

[0042] In some embodiments, the logic unit is a first logic unit, and the identifier is a first identifier. The semiconductor device further includes a second logic unit associated with a second identifier. The second logic unit is configured to receive an enumeration command in iterations from a control interface and sequentially drive one or more bits of the second identifier to the control interface. The operating method further includes causing the second logic unit to determine that one or more received bits received from the control interface do not match at least one of the one or more bits of the second identifier, and causing the second logic unit to stop driving one or more additional bits of the second identifier to the control interface.

[0043] In some embodiments, storing the logical unit index includes storing the logical unit index using a non-volatile fuse.

[0044] In some embodiments, storing the logical unit index includes storing the logical unit index in a volatile register.

[0045] In some embodiments, the operating method further includes resetting the volatile register before initiating a power cycle.

[0046] In some embodiments, the operating method further includes accessing data stored in the logical unit according to information, wherein the information includes a logical unit index, an address of the logical unit, and a data access command.

[0047] In some implementations, the enumeration command includes a number of iterations.

[0048] In some embodiments, determining whether one or more received bits received from the control interface match one or more bits of the identifier includes receiving an output of a comparator configured to compare the one or more received bits received from the control interface with the one or more bits of the identifier.

[0049] Another aspect of the present invention features a method for operating a logic unit in a semiconductor device. The method includes receiving information configured to access data stored in the logic unit from a control interface. The information includes a target identifier, a data access command, and an address. The method includes comparing the identifier with the target identifier. In response to determining that the identifier matches the target identifier, the method accesses the data according to the data access command.

[0050] In some embodiments, the operating method further includes: receiving special access information from the control interface; and performing a response action according to the special access information.

[0051] Another aspect of the present invention features a memory device. The memory device includes a controller. The memory device includes a logic unit associated with an identifier. The logic unit includes control logic and a feedback unit coupled to the control logic. A semiconductor device includes a control interface coupled to the feedback unit and the controller. The control logic is configured to receive an enumeration command in iterations from the controller via the control interface. The control logic is configured to sequentially drive one or more bits of the identifier to the control interface via the feedback unit. The control logic is configured to determine whether one or more received bits received from the control interface match one or more bits of the identifier. The control logic is configured to store a logic unit index in the control logic according to the number of iterations.

[0052] In some embodiments, the logic unit is a first logic unit, the identifier is the first identifier, the control logic is the first control logic, and the feedback unit is the first feedback unit. The semiconductor device further includes a second logic unit associated with the second identifier. The second logic unit includes second control logic and a second feedback unit, the second feedback unit being coupled to the second control logic and the control interface. The second control logic is configured to: receive an enumeration command in iterations from the control interface; sequentially drive one or more bits of the second identifier to the control interface via the second feedback unit; determine if one or more received bits from the control interface do not match at least one of the one or more bits of the second identifier; and stop driving one or more additional bits of the second identifier to the control interface.

[0053] Details of one or more disclosed embodiments are set forth in the accompanying drawings and the examples below. Other features, aspects, and advantages will become more apparent through the examples, drawings, and claims. To better understand these and other aspects of the present invention, the following examples are specifically described with reference to the accompanying drawings and are described in detail as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic diagram of an example system in accordance with one or more embodiments of the present invention is shown.

[0055] Figure 2A A schematic diagram illustrating an example system for addressing logic cells in a memory device according to one or more embodiments of the present invention is shown.

[0056] Figure 2B FIG. 1 is a schematic diagram illustrating an exemplary structure of multiple logic units in a memory device according to one or more embodiments of the present invention.

[0057] Figure 2C A schematic diagram illustrating an example circuit of a logic unit coupled to an addressing interface in a memory device according to one or more embodiments of the present invention is shown.

[0058] Figure 3 A flowchart illustrating an example process for managing logical units of a memory device according to one or more embodiments of the present invention is shown.

[0059] Figure 4A and Figure 4B Schematic diagrams of exemplary information structures according to one or more embodiments of the present invention are respectively shown.

[0060] Figure 5A and Figure 5B Flowcharts illustrating exemplary methods according to one or more embodiments of the present invention are respectively shown.

[0061] Description of reference numerals:

[0062] 100: System

[0063] 110: Device

[0064] 112: Device controller

[0065] 113: Processor

[0066] 114: Internal memory

[0067] 116: Memory

[0068] 120: Host

[0069] 122: Host controller

[0070] 200: Memory device

[0071] 201:CE_0

[0072] 202:CE_1

[0073] 203: Control or data bus

[0074] 204: RCLK

[0075] 205: Feedback pin

[0076] 210: Controller

[0077] 212a: LUN register A

[0078] 212b: LUN register B

[0079] 220: Memory

[0080] 220a: Memory cell A

[0081] 220b: Memory cell B

[0082] 224a: LUN_0

[0083] 224b: LUN_1

[0084] 226: Interface

[0085] 230: Address pad

[0086] 232: Data pad

[0087] 240: Structure

[0088] 277: ACK

[0089] 279: GND

[0090] 280: Circuit

[0091] 282: Control Logic

[0092] 284: Trigger node

[0093] 286: Driver Node

[0094] 288: Matching result node

[0095] 290: Feedback unit

[0096] 291: Pull-up unit

[0097] 292: Buffer

[0098] 294: Transistor

[0099] 296: Buffer

[0100] 298: Comparator

[0101] 300: Program

[0102] 302, 304, 306, 308, 310, 312, 314, 316, 318, 502, 504, 506, 508,

[0103] 522, 524, 526: Steps

[0104] 400A, 400B: Information Structure

[0105] 500A, 500B: Method DETAILED DESCRIPTION

[0106] A memory device typically has one or more memory cells (e.g., memory chips), each of which has one or more logic units (LUNs). Each LUN can be used to store data and can be manufactured as a die, such as a NAND flash die or a NOR flash die. As the density of LUNs in semiconductor devices increases, it has become common to stack multiple dies on top of each other in the same memory cell package. The stacking of LUNs makes routing wires to each LUN challenging. Some existing technologies use multiple LUN addressing pads with through-silicon vias (vias) that connect the LUNs to a power supply (e.g., VCC or ground (GND)), with each LUN associated with a different pattern of connection points. Therefore, a host (e.g., a computer) can access a LUN by providing signals corresponding to the pattern of connection points attached to that LUN. However, when the number of LUNs in a memory cell is large, manufacturing LUNs with a large number of patterns of address pads and bonding wires to support the connection points becomes challenging and / or increases costs.

[0107] The present invention provides techniques for managing LUNs in memory devices, using a LUN addressing method that enables access to a large number of LUNs within a memory chip while reducing costs and / or structural challenges (e.g., on the mask or substrate). As discussed below, various embodiments of the present invention allow LUNs to be accessed based on signals received from a control interface without requiring a large number of addressing pads or a complex pattern of connection points. Thus, various embodiments of the present invention advantageously streamline the LUN access process while reducing complexity and manufacturing costs.

[0108] Figure 1A schematic diagram of an example system 100 is shown. System 100 includes a device 110 and a host 120. Device 110 includes a device controller 112 and a memory 116. Device controller 112 includes a processor 113 and internal memory 114. In some embodiments, device 110 includes multiple memories 116 coupled to device controller 112. Memory 116 includes multiple blocks. Host 120 includes a host controller 122, which may include at least one processor and at least one memory coupled to the at least one processor and storing programmed instructions for the at least one processor to execute one or more corresponding operations.

[0109] Device controller 112 is a general-purpose microprocessor or a dedicated microcontroller. In some embodiments, device controller 112 is a memory controller for device 110. The following description is based on various techniques in embodiments where device controller 112 is a memory controller. However, the various techniques described below are also applicable to embodiments where device controller 112 is a controller other than a memory controller.

[0110] Processor 113 is configured to execute instructions and process data. Instructions include firmware instructions and / or other programming instructions, which are stored as firmware code and / or other programming code in auxiliary memory. Data includes programming data corresponding to the firmware and / or other programming executed by the processor, along with other suitable data. In some embodiments, processor 113 is a general-purpose microprocessor or a dedicated microcontroller.

[0111] Processor 113 accesses instructions and data from internal memory 114. In some embodiments, internal memory 114 is static random access memory (SRAM) or dynamic random access memory (DRAM), or a combination thereof. For example, in some embodiments, when device 110 is an embedded multimedia card (eMMC), an SD (Security Digit) card, or a smartwatch, internal memory 114 is SRAM. In some embodiments, when device 110 is a digital camera or a media player, internal memory 114 is DRAM.

[0112] In some embodiments, the internal memory 114 is a cache memory included in the device controller 112, such as Figure 1 The internal memory 114 stores instruction codes corresponding to instructions executed by the processor 113 and / or data required by the processor 113 during operation.

[0113] Device controller 112 transfers command codes and / or data from memory 116 to internal memory 114 or to host 120. Memory 116 may be a semiconductor device. In some embodiments, memory 116 is a non-volatile memory configured for long-term storage of commands and / or data, such as a NAND or NOR flash memory device, or other suitable non-volatile memory device. In some embodiments where memory 116 is NAND flash memory, device 110 is a flash memory device, such as a flash memory card, and device controller 112 is a NAND flash memory controller. For example, in some embodiments, when device 110 is an eMMC or SD card, memory 116 is NAND flash memory.

[0114] The memory 116 includes a plurality of blocks. The memory 116 may be a two-dimensional (2D) memory having two-dimensional memory blocks. The memory 116 may also be a three-dimensional (3D) memory having three-dimensional memory blocks.

[0115] In some embodiments, memory 116 includes one or more memory units. Each memory unit may include one or more LUNs. A LUN may include a memory chip or a memory die. Each LUN may include several memory arrays and their surrounding circuits. The memory array may include several planes, each plane including several physical blocks of memory units. Each physical block may include several pages of memory units capable of storing several sectors of data.

[0116] Figure 2A FIG. 1 is a schematic diagram illustrating an exemplary system for addressing logic cells in a memory device 200 according to one or more embodiments of the present invention. The memory device 200 may include a controller 210 (e.g., Figure 1 device controller 112 or host controller 122) and memory 220 (e.g. Figure 1 Memory device 200 may be Figure 1 device 110.

[0117] like Figure 2A As shown in FIG, memory 220 includes one or more storage units, such as memory unit A 220a and memory unit B 220b. Each memory unit may include one or more LUNs, such as LUN_0 224a and LUN_1 224b of memory unit A 220a. For illustrative purposes only, memory unit A 220a is described as an example of a memory unit.

[0118] like Figure 2AAs shown in FIG, memory unit A 220a includes LUN_0 224a and LUN_1 224b, coupled to an interface 226, which may include one or more pins and / or buses. Controller 210 may have a corresponding interface including one or more pins and / or buses corresponding to one or more pins and / or buses in interface 226 of memory unit A 220a. For example, interface 226 may include chip enable (CE) pins CE_0 201 and CE_1 202 for LUN_0 224a and LUN_1 224b, respectively. Interface 226 may also include a control or data bus 203, via which controller 210 can communicate with each of LUN_0 224a and LUN_1 224b. Control or data bus 203 may have a bandwidth of multiple bits. For example, when the control or data bus 203 is implemented according to a NAND flash memory access protocol, such as ONFI (Open NAND Flash Interface), the control or data bus 203 may have an 8-bit bandwidth. The controller 210 may be configured to access the memory 220 according to a data access command lasting one or more clock cycles. As an example, a data access command may use five cycles to specify the column address, row address, and LUN address of the data to be accessed in the memory 220.

[0119] Interface 226 may include a feedback clock pin (RCLK 204), through which controller 210 can transmit a clock signal to memory 220 as a reference clock for synchronization. Interface 226 may further include a feedback pin 205, which, in some embodiments, provides information to controller 210 regarding the status of LUN_0 224a and LUN_1 224b (e.g., busy and inaccessible). For example, if all LUNs are ready (e.g., accessible), feedback pin 205 may be asserted to a logic "1." If one or more LUNs are busy (e.g., inaccessible), feedback pin 205 may be de-asserted to a logic "0." In these embodiments, feedback pin 205 may be referred to as a ready-busy (R / B#) pin or a ready-busy interface. In some other embodiments, feedback pin 205 provides an acknowledgment (ACK) to queries or commands sent by controller 210. In these embodiments, the feedback pin 205 may be referred to as an ACK pin. The feedback pin 205 may be coupled to a feedback circuit that facilitates status feedback or responds to inquiries or commands.

[0120] Controller 210 has one or more registers, such as LUN register A 212a and LUN register B 212b. LUN register A 212a and LUN register B 212b can store information obtained by controller 210 from memory 220. Example information includes the ready or busy status of a LUN in a memory unit, information provided by a memory unit in response to a query or command, or pre-loaded manufacturing information (e.g., a serial number) of a LUN.

[0121] Figure 2B A schematic diagram illustrates an example structure 240 of multiple logical units (LUN0 to LUN3) in a memory device according to one or more embodiments of the present invention. According to the structure 240, multiple LUNs are stacked one on top of another to form a 3-dimensional (3D) configuration. The structure 240 can be used to configure Figure 2A LUN_0 224a and LUN_1 224b in the memory 220.

[0122] Multiple LUNs (LUN 0 to LUN 3) may have one or more data pads 232 connected to data pins DQ0 to DQ2. Therefore, when a LUN is accessed by a controller, the LUN may receive data from the controller or provide data to the controller via the data pins.

[0123] Multiple LUNs (LUN 0 to LUN 3) may have one or more addressing pads 230. As shown in structure 240, each LUN has a two-bit addressing pad that is wired to the power supply VCC, and the wiring pattern of each LUN corresponds to a 2-bit address. For example, LUN 0 has two pads connected to VCC, so the wiring pattern corresponds to "11". LUN 1 and LUN 2 each have one pad connected to VCC, so the wiring patterns correspond to "10" and "01", respectively. LUN 3 has no pad connected to VCC, so the wiring pattern corresponds to "00". With such an addressing mechanism, the controller can access the LUN by providing the corresponding 2-bit address of the LUN. In a structure with more LUNs stacked, the number of addressing pads can be different.

[0124] As the number of stacked LUNs increases, manufacturing and routing address pads becomes more challenging. Accordingly, some embodiments use one or more different addressing mechanisms to reduce the number of address pads. These embodiments will be referred to in Figures 2C to 5B illustrate.

[0125] Figure 2C FIG2 is a schematic diagram illustrating an example circuit 280 coupled to a logic unit (LUN_0 to LUN_N) of an addressing interface in a memory device according to one or more embodiments of the present invention. The circuit 280 may be used in Figure 2AEach LUN is individually and separately coupled to a control interface having one or more pins, including a feedback pin ACK 277 (which may be Figure 2A The circuit 280 for LUN_0 to LUN_N can be the same. Therefore, this description focuses only on LUN_0 as a representative LUN.

[0126] like Figure 2C As shown in FIG, LUN_0 includes control logic 282 and a feedback unit 290. The control logic 282 is coupled to the feedback unit 290 via a trigger node 284, a driver node 286, and a matching result node 288. The control logic 282 can be configured to sequentially drive (e.g., transmit) a series of bits to the feedback unit 290 via the driver node 286. The control logic 282 can be configured to output a trigger signal via the trigger node 284 based on the input value of the matching result node 288. For example, if the input value of the matching result node 288 is logic "1", the control logic 282 can output a logic "1" via the trigger node 284. Conversely, if the input value of the matching result node 288 is logic "0", the control logic 282 can output a logic "0" via the trigger node 284.

[0127] Feedback unit 290 includes buffer 292, transistor 294, comparator 298, and buffer 296. Buffer 292 can be enabled / disabled based on a trigger signal from trigger node 284. When enabled, buffer 292 allows data driven from drive node 286 to pass to the gate terminal of transistor 294. Figure 2C In other embodiments, the buffer 292 is a non-inverting buffer.

[0128] Continue to Figure 2CTransistor 294 may be a metal oxide semiconductor (MOS) transistor, such as an N-type MOS (NMOS) transistor as shown. Transistor 294 includes a gate terminal coupled to the output of buffer 292, a first terminal (e.g., a drain terminal) coupled to a common feedback pin 277, and a second terminal (e.g., a source terminal) coupled to GND 279. A pull-up unit 291 (e.g., one or more pull-up resistors) is coupled to the feedback pin 277 and a node between the plurality of LUNs. When the transistors 294 of all LUNs are turned off, the path from the feedback pin 277 to GND 279 is disconnected, and the pull-up unit 291 is configured to pull up the voltage at the feedback pin 277 to a high level, such as a logic "1." Conversely, when the transistor 294 of any LUN is turned on, the path from the feedback pin 277 to GND 279 is opened, and the voltage at the feedback pin 277 is maintained at a low level, such as a logic "0." This mechanism of coupling multiple LUNs to the control interface is called open-drain coupling, and transistor 294 is called an open-drain transistor.

[0129] Comparator 298 in feedback unit 290 can be an XNOR gate that outputs a logic "1" if the logic values of its two inputs are equal. For example, when the logic value at the drain terminal of transistor 294 (which is equivalent to the logic value of feedback pin 277) is the same as the logic value of drive node 286, comparator 298 outputs a logic "1." Otherwise, comparator 298 outputs a logic "0." As an input to match result node 288 of control logic 282, the output of comparator 298 thus indicates whether the value driven by control logic 282 matches the value received by control logic 282 from the control interface.

[0130] In an exemplary operation, when buffer 292 is enabled, control logic 282 drives a bit to buffer 292. If the driven bit is a logic "0", buffer 292 outputs a logic "1", turning on transistor 294, causing the value at feedback pin 277 to be pulled down to a logic "0". If the driven bit is a logic "1", buffer 292 outputs a logic "0", turning off transistor 294 and causing the value at feedback pin 277 to be pulled up to a logic "1". Accordingly, Figure 2C In the circuit shown, the feedback unit 290 is configured to pass the same value driven from the driving node 286 to the feedback pin 277 .

[0131] When other LUNs perform the same operation, each driving a bit to feedback pin 277, this can create a race. For example, any LUN driving a logic "0" to feedback pin 277 may pull down the value of feedback pin 277. Consequently, the other LUNs are no longer able to drive multiple logic "1s" to feedback pin 277 due to the path from feedback pin 277 to GND 279. Consequently, for those LUNs attempting to drive multiple logic "1s," their respective comparators 298 output a logic "0" to indicate that the driven value on drive node 286 does not match the received value on feedback pin 277. When a LUN detects a mismatch at drive node 288, the LUN deasserts trigger node 284, causing no additional bits to be driven from drive node 286 to the gate of transistor 294. In other words, if a LUN detects a mismatch at match result node 288, that LUN exits the race. The remaining LUNs can continue the race with other individual bits in another round. If each LUN has a unique set of bits to drive, then after a finite number of rounds of competition, only one LUN from LUN_0 to LUN_N can win.

[0132] The mechanism for this operation is not limited to Figure 2C For example, in Figure 2C In a variation of the circuit, a non-inverting buffer may be used in place of buffer 292, and an XOR gate may be used as comparator 298 in place of an NXOR gate. Figure 2C In other variations of the circuit, a non-inverting buffer may be used in place of buffer 292, and a P-type MOS (PMOS) transistor may be used as transistor 294 instead of an NMOS transistor.

[0133] In some embodiments, each LUN is associated with a unique identifier (ID), such as a serial number or a physical unclonable function (PUF) assigned by the manufacturer. The identifier may comprise a series of bits. Using the competition mechanism described above, multiple LUNs in the memory unit can be sorted according to their identifiers, and each LUN can obtain an index indicating its sorted position. For example, a host can iteratively send an enumeration command to multiple LUNs in the memory unit via a controller. Upon receiving the enumeration command during an iteration, the multiple LUNs can compete to sequentially drive their respective unique identifiers to the control interface. Because each identifier is unique, only one LUN can win each iteration, while the other LUNs may drop out in some rounds. The winning LUN can then obtain an index to stop participating in subsequent iterations of the competition. Therefore, as the iterations continue, fewer and fewer LUNs participate, and eventually each LUN obtains an index indicating its sorted position among all LUNs in the memory unit.

[0134] As an example, for a storage unit with four LUNs, the host can send the enumeration command in four iterations, causing each LUN to receive an index (index 1, 2, 3, and 4). The host can send the enumeration command a fifth time, with no LUNs participating in the competition, so that the host knows that all LUNs of the storage unit have been assigned an index.

[0135] During the enumeration process described above, the control logic for each LUN can keep track (e.g., using a counter) of the current iteration number. Alternatively or additionally, the host can provide the current iteration number within the enumeration command. The winning LUN in each iteration can reference its own counter or the number provided in the enumeration command to determine its index.

[0136] In some embodiments, the LUN stores an index in a non-volatile (NV) fuse in the control logic. The storage of the LUN index in the NV fuse may occur at the time the memory cell is manufactured and initialized. In some embodiments where the LUN does not have an available NV fuse, the LUN stores an index in a volatile register in the control logic so that the controller and multiple LUNs can perform an enumeration procedure at the beginning of each power cycle. With each LUN assigned an index, the host can access the LUN by specifying the index of the target LUN, and the LUN with the specified index can respond to the access requested by the host. The addressing of the LUN can be accomplished through a control interface between the controller and the multiple LUNs, for example, through only one address pad coupled to the control interface. In this method, compared to structure 240, fewer address pads are required in the memory device and the complexity of wiring the address pads is reduced.

[0137] Figure 3 FIG. 1 is a flow chart illustrating an example process 300 for managing logical units of a memory device according to one or more embodiments of the present invention. The process 300 may be executed by a LUN of a memory unit. One or more operational steps of the process 300 are similar to those of FIG. Figure 2C The described operation.

[0138] At step 302, the LUN determines whether it has an NV fuse. If so, process 300 proceeds to step 304 to determine whether the NV fuse already stores the LUN index. If the LUN index is found in the NV fuse, the LUN can then load the existing LUN index at step 306, and process 300 can proceed to the end.

[0139] If either step 302 or step 304 returns because of a negative result, then process 300 moves to step 308 to start the LUN enumeration process. To start the enumeration process, the LUN resets the LUN index (in the NV fuse or in the volatile register) to 0, indicating that the next iteration is the first iteration.

[0140] At step 310, the LUN waits until an enumeration command is received from the host. When the enumeration command is received, the process 300 moves to step 312, where the LUN begins to sequentially drive multiple bits of its identifier to the control interface (e.g., Figure 2C feedback pin).

[0141] In step 314, the control logic of the LUN (eg Figure 2C The control logic 282) is based on the feedback unit (e.g. Figure 2CThe comparator output of the feedback unit 290 (of the control interface) determines whether the received bit from the control interface matches the driven bit. If the result is no match (No), the LUN then exits the race. Upon exiting, the LUN increments the index by 1 in step 316 and waits for another enumeration command in the next iteration.

[0142] If the result of step 314 is a match (yes), then the LUN remains in the race and moves to step 318. In step 318, the LUN determines whether all bits of its identifier have been driven. If so (yes), then the LUN considers the current iteration to be over and that the LUN has won. In some embodiments, the LUN proceeds directly to the end process 300 without storing its current index. In some embodiments, the LUN stores its current index and proceeds to the end process 300. The controller (e.g. Figure 2A The controller 210 can store the corresponding index of the LUN, for example, by checking the status of the LUN, such as whether the LUN has completed driving all bits of the LUN identifier. In some embodiments, after the controller receives all bits of the LUN identifier, it stores the LUN identifier. If not (No), then it means that there are additional bits to be driven before the iteration ends. The LUN then repeats step 312 to continue driving the remaining bits.

[0143] Figure 4A and Figure 4B Schematic diagrams of exemplary information structures 400A and 400B according to one or more embodiments of the present invention are shown. A host can be coupled to a memory unit via a controller and access one or more LUNs of the memory unit by sending information having information structure 400A or information structure 400B to the controller.

[0144] like Figure 4A As shown in FIG, information structure 400A includes a command field that specifies the type of access requested by the host, such as read, write, and reset. Information structure 400A also includes one or more fields that specify the address of the memory unit and the index of the LUN within the memory unit. Upon receiving the information, each LUN can compare the received LUN index with the index obtained during the enumeration process. The LUN with the specified LUN index can respond to the host's access request.

[0145] like Figure 4BAs shown in FIG, information structure 400B includes a command field that specifies the type of access requested by the host, such as read, write, and reset. Information structure 400B also includes a field that specifies the address of the memory unit. Unlike information structure 400A, which specifies the index of a LUN, information structure 400B includes a field that specifies the unique identifier of the LUN. For example, a host can obtain a list of serial numbers for all LUNs in a memory unit and request a memory access on that LUN by specifying the serial number of that LUN. The host can obtain the list of serial numbers from LUNs, such as during the enumeration process in which each LUN reports its serial number to the control interface.

[0146] The host can use information structure 400A, information structure 400B, or similar information structures to provide special access information to a LUN. As an example, the host can set the LUN index to 0xFF in the information according to information structure 400A, even if no LUN in the storage unit has an index of 0xFF. Upon receiving the special access information, the control logic of the plurality of LUNs recognizes the special access information and performs a predefined response action. The response action to the special access information can include, for example, erasing all data, clearing all stored LUN indexes, restoring to factory settings, executing pre-loaded diagnostic programming, etc.

[0147] Figure 5A and Figure 5B Flowcharts illustrating exemplary methods 500A and 500B according to one or more embodiments of the present invention are shown. Methods 500A and 500B may be performed by a LUN of a memory unit. One or more operational steps of methods 500A and 500B are similar to those of reference numerals 500A and 500B. Figure 2C and Figure 3 The described operation.

[0148] Beginning with method 500A, at step 502 , a LUN receives an enumeration command from a control interface.

[0149] In step 504 of method 500A, the LUN sequentially drives one or more bits associated with an identifier of the LUN to the control interface. The identifier may be driven by a feedback unit of the LUN.

[0150] In step 506 of method 500A, the LUN determines whether one or more received bits received from the control interface match one or more bits of the identifier. A match may indicate that the LUN has won the competition with the other LUN after one or more rounds have been completed.

[0151] In step 508 of method 500A, the LUN stores a LUN index based on the number of iterations of the enumeration command. As previously described, after a LUN wins one or more rounds of the competition, the LUN stores the number of iterations as its LUN index. A host can access the LUN by specifying the LUN index in a data access command.

[0152] Continuing with method 500B, in step 522, the LUN receives information from the control interface for accessing data stored in the LUN. The information may include a target identifier (e.g., the serial number of the target LUN to be accessed), a data access command (e.g., read, write, or reset), and the address of the LUN in the memory unit.

[0153] At step 524 of method 500B, the LUN compares the target identifier to its unique identifier.

[0154] In step 526 of method 500B, in response to determining that the unique identifier of the LUN matches the target identifier, the LUN accesses the data stored therein according to the data access command.

[0155] The present invention and other embodiments may be implemented as one or more computer programming products, for example, one or more modules of computer programming instructions encoded on a computer-readable medium for execution by a data processing apparatus or to control the operation of the data processing apparatus. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or one or more combinations thereof. The term "data processing apparatus" includes all devices, means, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, such apparatus may include programming code that establishes an execution environment for the computer programming in question, for example, programming code constituting processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0156] A system may include all devices, equipment, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, such a system may include programming code that establishes an execution environment for the computer program in question, such as programming code constituting processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0157] Computer programming (also known as programming, software, software application programming, instruction code, or programming code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. Computer programming does not necessarily correspond to files in a file system. Programming can be stored as part of a file that stores other programming or data (for example, one or more instruction codes stored in a markup language document), in a single file dedicated to the programming in question, or in multiple coordinated files (for example, files storing one or more modules, subprograms, or portions of programming code). Computer programming can be configured to execute on one computer or on multiple computers. The multiple computers can be located at one site or distributed across multiple sites and interconnected by a communication network.

[0158] The procedures and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The procedures and logic flows may also be performed by, and the apparatus may also be implemented by, special purpose logic circuitry, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0159] Processors suitable for executing computer programs include, for example, both general-purpose and special-purpose microprocessors, and any one or more processors of any type of digital computer. Generally, a processor receives instructions and data from read-only memory, random-access memory, or both. The basic elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer may also include or be operatively coupled to one or more mass storage devices for storing data, receiving data from or transferring data to the one or more mass storage devices, or both. Examples of such one or more mass storage devices include magnetic disks, magneto-optical disks, or optical disks. However, a computer need not include such devices. Computer-readable media suitable for storing computer programming instructions and data may include all forms of non-volatile memory, media, and storage devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; and magnetic disks. The processor and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0160] Although many details may be described herein, these details should not be construed as limitations on the claimed or claimable scope of the invention, but rather as descriptions of features specific to particular embodiments. Certain features described herein in separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although several features may be described above as functioning in certain combinations and even initially claimed as such, one or more features from the claimed combinations may in some cases be excluded from the described combinations, and the claimed combinations may be directed to subcombinations or variations of subcombinations. Similarly, although several operations are depicted in a particular order in the drawings, it should not be understood that these operations must be performed in the particular order shown or in a sequential order, or that all described operations must be performed to achieve the desired result.

[0161] In summary, although the present invention has been disclosed above with reference to the embodiments, these are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor device comprising: a logic unit associated with an identifier (ID), the logic unit comprising a control logic and a feedback unit coupled to the control logic; as well as a control interface coupled to the feedback unit, The control logic is configured to: receiving an enumeration command in an iteration from the control interface; driving one or more bits of the identifier to the control interface using the feedback unit; and In response to determining that a received bit received from the control interface does not match a driven bit of the identifier, driving one or more additional bits of the identifier to the control interface is stopped.

2. The semiconductor device according to claim 1 , wherein the control logic is configured to: In response to determining that a plurality of received bits received from the control interface match a plurality of driven bits of the identifier, a logic unit index is stored in the control logic according to a number of the iterations.

3. The semiconductor device according to claim 2, wherein the control logic is configured to: In response to determining that the received bits received from the control interface match the driven bits of the identifier, driving the bits of the identifier is stopped in one or more sequence iterations.

4. The semiconductor device according to claim 2, wherein the control logic comprises at least one of the following: A non-volatile fuse configured to store the logical unit index, or A volatile register is configured to store the logical unit index. 5 . The semiconductor device according to claim 2 , wherein the logic unit is configured to receive information for accessing data stored in the logic unit, and wherein the information includes the logic unit index, an address of the logic unit, and a data access command. The semiconductor device according to claim 2 , wherein the enumeration command includes the number of the iterations.

7. The semiconductor device of claim 2 , wherein the feedback unit comprises a comparator configured to compare the received bits with the driven bits of the identifier, and wherein the control logic is configured to determine whether the received bits match the driven bits of the identifier based on an output of the comparator. 8 . The semiconductor device according to claim 1 , wherein the feedback unit is coupled to the control interface via an open drain circuit.

9. The semiconductor device according to claim 1, wherein the identifier comprises at least one of the following: A serial number of the logical unit, or A physical unclonable function (PUF) of the logic unit. 10 . The semiconductor device of claim 1 , wherein the logic unit comprises at least one of a NAND flash memory die or a NOR flash memory die.

11. The semiconductor device according to claim 1 , wherein the logic unit is configured to: receiving from the control interface a message configured to access data stored in the logic unit, wherein the message includes a target identifier, a data access command, and an address; comparing the identifier to the target identifier; and In response to determining that the identifier matches the target identifier, the data is accessed according to the data access command.

12. The semiconductor device according to claim 11, wherein the logic unit is further configured to: receiving a special access message from the control interface; and A response action is executed according to the special access information.

13. A method for operating a logic unit in a semiconductor device, the method comprising: receiving an enumeration command in an iteration from a control interface of the semiconductor device; driving one or more bits associated with an identifier of the logic unit to the control interface; as well as In response to determining that a received bit received from the control interface does not match a driven bit of the identifier, driving one or more additional bits of the identifier to the control interface is stopped.

14. The operating method according to claim 13, wherein the logic unit is a first logic unit, the identifier is a first identifier, and wherein the semiconductor device further comprises a second logic unit associated with a second identifier, and wherein the operating method further comprises: receiving a second enumeration command in a second iteration from the control interface; driving one or more bits of the second identifier associated with the second logic unit to the control interface; as well as In response to determining that a plurality of received bits received from the control interface match a plurality of driven bits of the second identifier, a logic unit index for the second logic unit is stored in a control logic according to a number of the second iterations, and driving the plurality of bits of the second identifier is stopped in one or more sequence iterations.

15. The operating method according to claim 14, wherein storing the logical unit index comprises: The logic unit index is stored in at least one of a non-volatile fuse or a volatile register.

16. The operating method according to claim 14, further comprising: Data stored in the second logical unit is accessed according to information, wherein the information includes the logical unit index, an address of the second logical unit and a data access command.

17. The operating method according to claim 13, further comprising: receiving from the control interface a message configured to access data stored in the logic unit, wherein the message includes a target identifier, a data access command, and an address; comparing the identifier to the target identifier; and In response to determining that the identifier matches the target identifier, the data is accessed according to the data access command.

18. The operating method according to claim 17, further comprising: receiving a special access message from the control interface; as well as A response action is executed according to the special access information.

19. A memory system comprising: A semiconductor device comprising an array of a plurality of memory cells; as well as a controller coupled to the semiconductor device and configured to control the semiconductor device, The semiconductor device comprises: a logic unit associated with an identifier, the logic unit comprising a control logic and a feedback unit coupled to the control logic; and a control interface coupled to the feedback unit, The control logic is configured to: receiving, in an iteration, an enumerated command from the control interface; driving one or more bits of the identifier to the control interface using the feedback unit; and In response to determining that a received bit received from the control interface does not match a driven bit of the identifier, driving one or more additional bits of the identifier to the control interface is stopped.

20. The memory system of claim 19, wherein the control logic is configured to: In response to determining that a plurality of received bits received from the control interface match a plurality of driven bits of the identifier, a logic unit index is stored in the control logic according to a number of the iterations, and driving the plurality of bits of the identifier is stopped in one or more sequence iterations.

Images