Data write circuit and memory chip

Abstract

This invention provides a data writing circuit and a memory chip. Based on the existing data writing circuit architecture, the single-ended transmission circuit of the data input node I / O coupled to a memory such as DRAM or PSRAM is replaced with a double-ended transmission circuit (which has a single data input terminal and two data output terminals). Thus, when the double-ended transmission circuit is turned on, the potential of the first bit node b1 or the second bit node b1 can be quickly pulled down by rapidly pulling down the potential of the LIOT node or LIOB node of the memory. This allows the first bit node b1 and the second bit node b1 to quickly separate a larger voltage difference, thereby increasing the speed of writing "0" and "1" to the memory cell and greatly reducing the speed difference when writing "0" and "1" to the memory (making the speed of writing "0" and "1" approximately the same). This improves the performance of the memory and enables it to meet the requirements of higher performance products.

Description

Technical Field

[0001] This invention relates to the field of memory chip technology, and in particular to a data writing circuit and a memory chip. Background Technology

[0002] Memory such as dynamic random access memory (DRAM) or pseudo static random access memory (PSRAM) can store each bit of data using only one capacitor and one transistor. Therefore, memory such as DRAM or PSRAM has the advantages of high capacity per unit volume and low cost, and is widely used in various fields.

[0003] In today's rapidly evolving technological landscape, various fields, from financial transactions and complex scientific calculations to high-definition video processing, large-scale game operation, and AI applications, all require DRAM, PSRAM, and other memory devices with extremely fast and reliable read / write speeds to ensure stable system operation and provide users with a smooth experience. However, due to the difference in speed between writing "0" and writing "1" in existing DRAM, PSRAM, and other memory technologies, current DRAM and PSRAM technologies are insufficient to meet these demands. Summary of the Invention

[0004] The purpose of this invention is to provide a data writing circuit and memory chip that can greatly reduce the speed difference between writing "0" and writing "1" to memory such as DRAM and PSRAM, thereby improving the performance of the memory and enabling it to meet the needs of higher performance products.

[0005] To achieve the above objectives, the present invention provides a data writing circuit, comprising a dual-ended transmission circuit, a column gating circuit, and a bit line sensing amplification circuit coupled sequentially, wherein the bit line sensing amplification circuit is coupled to the memory array of the memory; wherein:

[0006] The dual-ended transmission circuit has a single data input terminal and two data output terminals. Its data input terminal is coupled to the data input node of the memory, and one of the data output terminals is coupled to a first local input / output line node, and the other data output terminal is coupled to a second local input / output line node. The dual-ended transmission circuit is used to be turned on under the control of a write enable signal and to transmit the data received by the data input node to the first local input / output line node and the second local input / output line node in a complementary manner.

[0007] The column gating circuit is used to transmit the data of the first local input / output line node and the second local input / output line node to the complementary first bit line node and the second bit line node inside the bit line sensing amplifier circuit.

[0008] The bit line sensing amplifier circuit is used to write the data or data opposite to the data into the corresponding storage cell in the storage array through at least one of the first bit line node and the second bit line node.

[0009] Optionally, the dual-ended transmission circuit includes a first switch, a second switch, and a third switch. The gates of the first switch and the third switch are both coupled to the write enable signal. The source of the first switch is coupled to the first local input / output line node. The drain of the first switch and the gate of the second switch are both coupled to the data input node. The drain of the second switch is coupled to the second local input / output line node. The source of the second switch is coupled to the drain of the third switch.

[0010] Alternatively, the dual-ended transmission circuit includes a first switch, a second switch, a third switch, and an inverting circuit. The gate of the first switch and the input of the inverting circuit are both coupled to the data input node. The drain of the first switch is coupled to the second local input / output line node. The gate of the second switch is coupled to the output of the inverting circuit. The drain of the second switch is coupled to the first local input / output line node. The sources of the first and second switches are both coupled to the drain of the third switch. The gate of the third switch is coupled to the write enable signal.

[0011] Optionally, the first switch, the second switch, and the third switch are all n-type transistors.

[0012] Optionally, the column gating circuit includes:

[0013] The first gating switch has its gate coupled to the column gating signal, its source coupled to the first local input / output line node, and its drain coupled to the first bit line node.

[0014] The second strobe switch has its gate coupled to the column strobe signal, its source coupled to the second local input / output line node, and its drain coupled to the second bit line node.

[0015] Optionally, both the first and second gating switches are n-type transistors.

[0016] Optionally, the data writing circuit further includes:

[0017] A first pre-charge circuit, coupled to a pre-charge control signal and the first local input / output line node, is used to pre-charge the potential of the first local input / output line node to a first preset potential under the control of the pre-charge control signal before the dual-ended transmission circuit is turned on for data transmission; and / or,

[0018] The second pre-charge circuit is coupled to the pre-charge control signal and the second local input / output line node, and is used to pre-charge the potential of the second local input / output line node to the first preset potential under the control of the pre-charge control signal before the dual-ended transmission circuit is turned on for data transmission.

[0019] Optionally, the first pre-charge circuit includes a first pre-charge switch, the gate of which is coupled to the pre-charge control signal, the source of which is coupled to the first preset potential, and the drain of which is coupled to the first local input / output line node; and / or,

[0020] The second pre-charge circuit includes a second pre-charge switch, the gate of which is coupled to the pre-charge control signal, the source of which is coupled to the first preset potential, and the drain of which is coupled to the second local input / output line node.

[0021] Optionally, the bit line sensing amplification circuit includes a latch circuit coupled to the memory array and the column gating circuit, for providing the first bit line node and the second bit line node, and for performing charge sharing between the first bit line node and the first local input / output line node, and between the second bit line node and the second local input / output line node, respectively, and amplifying the potential difference between the first bit line node and the second bit line node.

[0022] Optionally, the latching circuit includes a cross-coupled first inverter and a second inverter, wherein the input terminal of the first inverter is coupled to the first bit line node and the output terminal of the second inverter, and the input terminal of the second inverter is coupled to the second bit line node and the output terminal of the first inverter.

[0023] Optionally, the bit line sensing amplifier circuit further includes:

[0024] A third pre-charge circuit, coupled to the pre-charge control signal and the first bit line node, is used to pre-charge the potential of the first bit line node to a second preset potential under the control of the pre-charge control signal before the dual-ended transmission circuit is turned on for data transmission; and / or,

[0025] The fourth pre-charge circuit is coupled to the pre-charge control signal and the second bit line node, and is used to pre-charge the potential of the second bit line node to the second preset potential under the control of the pre-charge control signal before the dual-end transmission circuit is turned on for data transmission.

[0026] Optionally, the third pre-charge circuit includes a third pre-charge switch, the gate of which is coupled to the pre-charge control signal, the source of which is coupled to the second preset potential, and the drain of which is coupled to the first bit line node; and / or,

[0027] The fourth pre-charge circuit includes a fourth pre-charge switch, the gate of which is coupled to the pre-charge control signal, the source of which is coupled to the second preset potential, and the drain of which is coupled to the second bit line node.

[0028] Based on the same inventive concept, the present invention also provides a memory chip, which includes the data writing circuit as described in the present invention.

[0029] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0030] (1) Based on the existing data writing circuit architecture, the single-ended transmission circuit of the data input node IO of the coupled memory (e.g., DRAM / PSRAM) is replaced with a double-ended transmission circuit (which has a single data input terminal and two data output terminals). Thus, when the double-ended transmission circuit is turned on, the potential of the first local input / output line node (LIOT) or the second local input / output line node (LIOB) can be quickly pulled down, thereby quickly pulling down the potential of the first bit node bla or the second bit node blb. This allows the first bit node bla and the second bit node blb to quickly separate a larger voltage difference, thereby increasing the speed of writing "0" and "1" to the memory cell and greatly reducing the speed difference when writing "0" and "1" to the memory (making the speed of writing "0" and "1" approximately the same). This improves the performance of the memory and enables it to meet the requirements of higher performance products.

[0031] (2) The data writing circuit of the present invention also has a first to a fourth pre-charging circuit, so that before writing "0" or "1" to the storage array of the coupled memory, the first local input / output line node LIOT and the second local input / output line node LIOB can be pre-charged to a first preset potential through the first pre-charging circuit and the second pre-charging circuit, and the first bit line node bla and the second bit line node blb can be pre-charged to a second pre-charging bit through the third pre-charging circuit and the fourth pre-charging circuit. Thus, when the double-ended transmission circuit is turned on, the potential difference between the LIOT node and the LIOB node and the potential difference between the bla node and the blb node can be increased, so that the first bit line node bla and the second bit line node blb can quickly separate a larger voltage difference, thereby improving the speed of writing "0" and "1" to the storage cell of the memory, thereby improving the overall data writing speed of the memory.

[0032] (3) The dual-end transmission circuit and column selection circuit in the data writing circuit of the present invention are both constructed by n-type transistors (e.g., nmos), which can simplify the circuit, reduce costs, and take advantage of the fact that n-type transistors can transmit "0" faster, thereby increasing the speed of writing "0" and "1" to the memory cell, thus improving the overall data writing speed and performance of the memory. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the architecture of a data writing circuit inside a DRAM memory chip in the prior art.

[0034] Figure 2 yes Figure 1 The diagram shows the timing sequence of the data writing circuit.

[0035] Figure 3 This is a schematic diagram of the data read / write circuit architecture according to a specific embodiment of the present invention.

[0036] Figure 4A and Figure 4B These are schematic diagrams illustrating two example structures of the dual-ended transmission circuit in the data read / write circuit of a specific embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of the architecture of the bit line sensing amplifier circuit in the data read / write circuit of a specific embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of an example structure of a data read / write circuit according to a specific embodiment of the present invention.

[0039] Figure 7 yes Figure 6 The diagram shows a timing sequence of a data read / write circuit. Detailed Implementation

[0040] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0041] Please refer to Figure 1 In memory chips such as dynamic random access memory (DRAM) or pseudo static random access memory (PSRAM), the memory array typically consists of several memory cells (not shown) arranged in rows and columns. Data storage in each memory cell requires only a capacitor C0 and a transistor M0. When writing data, the corresponding data "0" or "1" is input from the outside through the memory's data input node IO. After passing through the write enable signal WREN, which controls the conduction of the switch N1 (a single-ended transmission circuit), the data is transmitted to the memory's first local input output line (LIOT) node. Then, after passing through the column select signal YST0, which controls the conduction of the switch N2 (coupled to the LIOT node), the data is transmitted to the latch circuit of the bit-line sense amplifier SA. Figure 1The latch circuit is labeled as a latch (e.g., a back-to-back inverter circuit). The bit line bla node is located within the latch circuit. Then, the data is written into the memory cell where M0 resides, via the transistor M0 (controlled by the row select signal vwlp) coupled to the bit line bla node of the latch circuit. (That is, the conduction of transistor M0 changes the amount of charge stored in capacitor C0, thus realizing the storage of binary bit data "1" or "0".) The timing sequence of this process is as follows: Figure 2 As shown, it specifically includes the following stages:

[0042] (1) Precharge phase: When the precharge control signal prec is 0, the switch P1 is turned on, the LIOT node is precharged to vcc, and the node bla / blb in the latch circuit is precharged to vcc / 2. Then, the precharge control signal prec is pulled high (i.e., prec = 1), and the LIOT node and the bla / blb node are in a short floating state.

[0043] (2) Data Transfer Stage (i.e., IO = 1): After the write enable signal WREN controls the switch N1 to turn on, the data input node IO and the LIOT node share charge. Since the LIOT node is pre-charged to the vcc potential, the potentials at the source and drain ends of the switch N1 are equal, so the LIOT node maintains its vcc potential unchanged. The column strobe signal YST0 controls the switch N2 to turn on, and the LIOT node and the bla node share charge. The potential of the bla node will be higher than vcc / 2. Under the action of the latch circuit, the bla node is further pulled high to vcc, and the blb node is pulled low to the ground vss of the memory (e.g., vss = 0). Finally, after the row strobe signal vwlp controls the transistor M0 to turn on, the blb node writes the data "0" (i.e., IO = 1, cell = 0) to the corresponding memory cell through the transistor M0.

[0044] (3) Transmitting "0" data stage (IO=0): After the write enable signal WREN controls the switch N1 to turn on, the IO node and the LIOT node share charge. Since the LIOT node is pre-charged to the vcc potential, the voltage difference between the source and drain of N1 is vcc, so the LIOT node is quickly pulled to VSS. The column strobe signal YST0 controls the switch N2 to turn on, and the LIOT node and the bla node share charge. The potential of the bla node will be lower than vcc / 2. Under the action of the latch circuit, the bla node is quickly pulled low to VSS, and the blb node is pulled high to vcc. Finally, after the row strobe signal vwlp controls the transistor M0 to turn on, the blb node writes the data "1" that is opposite to the data "0" received by the IO node into the cell through the transistor M0 (i.e., IO=0, cell=1).

[0045] As described above, in the existing scheme, when writing "1" data (i.e., IO=1), the voltage difference across N2 is only VCC / 2. This difference is even smaller when VCC is lower, resulting in a longer charge sharing time between the LIOT node and the bla node. Consequently, the speed of writing the opposite data "0" to the memory cell becomes very slow. Conversely, when writing "0" data (i.e., IO=0), since the voltage difference across the source and drain of the switching transistor N1 is VCC, the LIOT node is quickly pulled low due to the fast "0" transfer characteristic of N1 (which is an NMOS transistor). After N2 (also an NMOS transistor, which also has a fast "0" transfer characteristic) is turned on, the bla node is also pulled to VSS relatively quickly, resulting in a faster speed of writing the opposite data "1" to the memory cell. Therefore, the speed of writing "0" and "1" data in the memory cell will differ significantly, which will have a certain impact on the performance of the memory and make it difficult to meet the requirements of higher-performance products.

[0046] Based on this, the present invention provides a data writing circuit and a memory chip. While maintaining the original bit line sensing amplifier circuit (SA) architecture, the single-ended transmission circuit coupled to the SA is transformed into a double-ended transmission circuit. Thus, whether writing "0" data or "1" data to the memory array (e.g., DRAM / PSRAM), the potential of the bit line node bla or blb inside the SA can be quickly pulled down, allowing a larger voltage difference to be quickly separated between the bit line nodes bla and blb. This enables the data "0" or "1" to be written to the corresponding memory cell more quickly, greatly reducing the speed difference between writing "0" and writing "1" data to the memory cell (e.g., both are basically the same), thereby improving the performance of the memory chip (e.g., DRAM / PSRAM) and meeting the needs of higher performance products.

[0047] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0048] Please refer to Figure 3 An embodiment of the present invention provides a data writing circuit, which includes a dual-ended transmission circuit 10, a column gate circuit YST, and a bit line sensing amplifier circuit SA coupled in sequence, wherein the bit line sensing amplifier circuit SA is coupled to the memory array 20 of the memory.

[0049] Among them, the dual-ended transmission circuit 10 has a single data input terminal (not in Figure 3 (marked in the middle) and two data output terminals (not in the middle) Figure 3 (As marked in the image), the data input terminal of the dual-ended transmission circuit 10 is coupled to the data input node IO of the memory, one data output terminal of the dual-ended transmission circuit 10 is coupled to the first local input / output line node LIOT, and the other data output terminal of the dual-ended transmission circuit 10 is coupled to the second local input / output line node LIOB. The dual-ended transmission circuit 10 is used to be turned on under the control of the write enable signal WREN, and to transmit the data "0" or "1" received by the data input node IO to the first local input / output line node LIOT and the second local input / output line node LIOB in a complementary manner.

[0050] The column gating circuit YST can be coupled to a corresponding column address decoder (not shown), thereby transmitting the data of the first local input / output line node LIOT and the second local input / output line node LIOB to the complementary first bit node bla and the second bit node blb inside the bit sensing amplifier circuit SA according to the column gating signal YST0 output by the column address decoder.

[0051] The bit-line sensing amplifier circuit SA is used to write data externally input to the data input node IO, or data opposite to the data received by the data input node IO, into the corresponding storage cell in the storage array 20 through at least one of the first bit-line node blab and the second bit-line node blb. For example, when the data received by the IO node is "1" (i.e., IO = 1), "0" is written into the storage cell, and when the data received by the IO node is "0", "1" is written into the storage cell.

[0052] In this embodiment, the data writing circuit is integrated with the memory array 20 within the memory chip. This memory can be any suitable memory, such as dynamic random access memory (DRAM) or pseudo static random access memory (PSRAM). The memory array 20 is used to store data and typically has several memory cells arranged in rows and columns. Memory cells in the same row are coupled to the same word line (WL), and memory cells in the same column are coupled to the same bit line (BL). Data storage in each memory cell requires only one capacitor C0 and one transistor M0. In one example, please refer to... Figure 3 The bit line sensing amplifier circuit SA is coupled to the drain of transistor M0 through the second bit line node blb. In other examples, the bit line sensing amplifier circuit SA may also be coupled to the drain or source of transistor M0 through the first bit line node bla, or the bit line sensing amplifier circuit SA may also be coupled to transistor M0 through the first bit line node bla and the second bit line node blb.

[0053] It is worth noting that the first local input / output line node LIOT and the second local input / output line node LIOB are a pair of nodes with positive and inverted voltage levels respectively (in other words, they are paired and complementary). The LIOB and LIOT nodes provide a voltage difference that allows the column gating circuit YST to sense during memory write operations, thereby transferring data from the LIOB and LIOT nodes to the first bit node blab and the second bit node blb inside the bit sensing amplifier circuit SA. The first bit node blab and the second bit node blb are also paired and complementary.

[0054] Optionally, the data writing circuit of this embodiment may further include a first pre-charging circuit 11 and a second pre-charging circuit 12.

[0055] The first precharge circuit 11 is coupled to the precharge control signal prec and the first local input / output line node LIOT, and is used to precharge the potential of the first local input / output line node LIOT to a first preset potential (e.g., VCC) under the control of the precharge control signal prec before the two-end transmission circuit 10 is turned on for data transmission.

[0056] The second precharge circuit 12 is coupled to the precharge control signal prec and the second local input / output line node LIOB, and is used to precharge the potential of the second local input / output line node LIOB to a first preset potential (e.g., VCC) under the control of the precharge control signal prec before the two-ended transmission circuit 10 is turned on for data transmission.

[0057] It should be understood that the dual-ended transmission circuit 10, the column gating circuit YST, the bit line sensing amplifier circuit SA, the first pre-charge circuit 11, and the second pre-charge circuit 12 can be implemented using any suitable circuit design, and the present invention does not impose any specific limitations on them.

[0058] In one example, please refer to Figure 4A The dual-ended transmission circuit 10 includes a first switch N11, a second switch N12, and a third switch N13. The gates of both the first switch N11 and the third switch N13 are coupled to a write enable signal WREN. The source of the first switch N11 is coupled to the first local input / output line node LIOT. The drains of the first switch N11 and the gates of the second switch N12 are coupled to the data input node IO. The drain of the second switch N12 is coupled to the second local input / output line node LIOB. The source of the second switch N12 is coupled to the drain of the third switch N13. The source of the third switch N13 is grounded to VSS. Optionally, the first switch N11, the second switch N12, and the third switch N13 are all n-type transistors (e.g., NMOS transistors or NPN transistors). Therefore, constructing the dual-ended transmission circuit 10 using n-type transistors (e.g., NMOS transistors) simplifies the circuit and reduces costs.

[0059] In this example, please combine Figure 3 and Figure 4AWhen IO = 1, ION = 0, LIOB = 0, and the potential of the LIOT node remains constant at VCC. After the column gate circuit YST is enabled, the LIOB node and the blb node share charge, and the potential of the blb node is quickly pulled to VSS, ultimately writing "0" into the memory cell. When IO = 0, ION = 1, and the LIOT node and the IO node share charge. The potential of the LIOT node is quickly pulled to VSS, and after the column gate circuit YST is enabled, the LIOT node and the bla node share charge, and the potential of the bla node is quickly pulled to VSS, while the potential of the blb node is pulled to VCC, ultimately writing "1" into the memory cell. Clearly, in this example, the faster transmission of "0" by n-type transistors can be utilized to increase the speed of writing "0" and "1" into the memory cell, thereby ultimately improving the overall data write speed of the memory. In this case, the LIOT node side uses the source-drain method of N11 (i.e., nmos) to write the data of the IO node, while the LIOB node side uses the gate-drain method of N12 (i.e., nmos) to write the data of the IO node.

[0060] In another example, please refer to Figure 4B The dual-ended transmission circuit includes a first switch N11, a second switch N12, a third switch N13, and an inverting circuit inv. The gate of the first switch N11 and the input of the inverting circuit inv are both coupled to the data input node IO. The drain of the first switch N11 is coupled to the second local input / output line node LIOB. The gate of the second switch N12 is coupled to the output of the inverting circuit inv to receive data ION, which is opposite to that of the data input node IO (e.g., when IO=1, ION=0). The drain of the second switch N12 is coupled to the first local input / output line node LIOT. The sources of the first switch N11 and the second switch N12 are both coupled to the drain of the third switch N13. The gate of the third switch N13 is coupled to the write enable signal WREN. The inverting circuit inv can be any suitable inverting logic circuit, such as a NOT gate or an inverter. Optionally, the first switch N11, the second switch N12, and the third switch N13 are all n-type transistors (such as NMOS transistors or NPN transistors). By constructing the two-terminal transmission circuit 10 using n-type transistors (such as NMOS transistors), the circuit can be simplified and the cost reduced.

[0061] In this example, please combine Figure 3 and Figure 4BWhen IO = 1, ION = 0, LIOB = 0, and the potential of the LIOT node remains constant at vcc. After the column select circuit YST is turned on, the LIOB node and the blb node share charge, and the potential of the blb node is quickly pulled to VSS, ultimately writing "0" into the memory cell. When IO = 0, ION = 1, LIOT = 0, and the potential of the LIOB node remains constant at vcc. After the column select circuit YST is turned on, the LIOT node and the bla node share charge, and the potential of the bla node is quickly pulled to VSS, while the potential of the blb node is pulled to vcc, ultimately writing "1" into the memory cell. Obviously, in this example, the faster transmission of "0" by n-type transistors can also be utilized to increase the speed of writing "0" and "1" to the memory cells, thereby ultimately improving the overall data write speed of the memory. In this case, the LIOT node side uses the gate-drain of N11 (i.e., nmos) to write the data of the IO node, while the LIOB side uses the gate-drain of N12 (i.e., nmos) to write the data of the IO node.

[0062] In one example, please refer to Figure 6 The column selection circuit YST includes a first selection switch N21 and a second selection switch N22. The gate of the first selection switch N21 is coupled to the column selection signal YST0, the source of the first selection switch N21 is coupled to the first local input / output line node LIOT, and the drain of the first selection switch N21 is coupled to the first bit line node blab. The gate of the second selection switch N22 is coupled to the column selection signal YST0, the source of the second selection switch N22 is coupled to the second local input / output line node LIOB, and the drain of the second selection switch N22 is coupled to the second bit line node blb. Optionally, both the first gating switch N21 and the second gating switch N22 are n-type transistors (e.g., NMOS transistors or NPN transistors). By constructing the column gating circuit YST using n-type transistors (e.g., NMOS), the circuit can be simplified, the cost can be reduced, and the faster transmission of "0" by n-type transistors can be utilized to improve the speed of writing "0" and "1" to the memory cell, thereby ultimately improving the overall data write speed of the memory.

[0063] In one example, please refer to Figure 6 The first pre-charge circuit 11 includes a first pre-charge switch P1. The gate of the first pre-charge switch P1 is coupled to a pre-charge control signal prec, the source of the first pre-charge switch P1 is coupled to a first preset potential vcc, and the drain of the first pre-charge switch P1 is coupled to a first local input / output line node LIOT. Optionally, the first pre-charge switch P1 is a p-type transistor (e.g., a PMOS transistor or a PNP transistor).

[0064] In one example, please refer to Figure 6The second pre-charge circuit 12 includes a second pre-charge switch P2. The gate of the second pre-charge switch P2 is coupled to the pre-charge control signal prec, the source of the second pre-charge switch P2 is coupled to the first preset potential vcc, and the drain of the second pre-charge switch P2 is coupled to the second local input / output line node LIOB. Optionally, the second pre-charge switch P2 is a p-type transistor (e.g., a PMOS transistor or a PNP transistor).

[0065] In one example, please refer to Figure 3 The bit-line sensing amplifier circuit SA includes a latch circuit, coupled to the memory array 20 and the column gate circuit YST, for providing charge sharing between the first bit-line node bla and the second bit-line node blb, and between the bla node and the LIOT node, and between the blb node and the LOTB node, and amplifying the potential difference between the first bit-line node bla and the second bit-line node blb. The latch circuit can employ any suitable circuit design. Optionally, please refer to... Figure 6 The latch circuit includes a cross-coupled first inverter inv1 and a second inverter inv2. The input of the first inverter inv1 is coupled to the first bit line node blab and the output of the second inverter inv2. The input of the second inverter inv2 is coupled to the second bit line node blab and the output of the first inverter inv1.

[0066] The first inverter inv1 and the second inverter inv2 can be designed using any suitable circuit. For example, the first inverter inv1 includes a PMOS transistor P5 and an NMOS transistor N3, and the second inverter inv1 includes a PMOS transistor P6 and an NMOS transistor N4. The sources of PMOS transistors P5 and P6 are both coupled to a first preset potential Vcc. The sources of NMOS transistors N3 and N4 are both coupled to the memory ground VSS. The drains of PMOS transistors P5 and N3 are coupled to form the output terminal of the first inverter inv1, and are also coupled to the gates of PMOS transistors P6 and N4. The gates of PMOS transistors P5 and N3 are coupled to form the input terminal of the first inverter inv1, and are also coupled to the drains of PMOS transistors P6 and N4. The drain of PMOS transistor P6 and the drain of NMOS transistor N4 are coupled together to form the output terminal of the second inverter inv2, and the gate of PMOS transistor P6 and the gate of NMOS transistor N4 are coupled together to form the input terminal of the second inverter inv2.

[0067] Alternatively, please refer to Figure 5The bit-line sensing amplifier circuit SA also includes a third pre-charge circuit 13 and a fourth pre-charge circuit 14. The third pre-charge circuit 13 is coupled to a pre-charge control signal prec and the first bit-line node blab, and is used to pre-charge the potential of the first bit-line node blab to a second preset potential (e.g., VCC / 2) under the control of the pre-charge control signal prec before the dual-ended transmission circuit 10 is turned on for data transmission. The fourth pre-charge circuit 14 is coupled to the pre-charge control signal prec and the second bit-line node blab, and is used to pre-charge the potential of the second bit-line node blab to a second preset potential (e.g., VCC / 2) under the control of the pre-charge control signal prec before the dual-ended transmission circuit 10 is turned on for data transmission. Furthermore, the second preset potential can be half of the first preset potential or other values. The third pre-charge circuit 13 and the fourth pre-charge circuit 14 can employ any suitable circuit design.

[0068] In one example, please refer to Figure 6 The third pre-charge circuit 13 includes a third pre-charge switch P3. The gate of the third pre-charge switch P3 is coupled to the pre-charge control signal prec, the source of the third pre-charge switch P3 is coupled to the second preset potential vcc / 2, and the drain of the third pre-charge switch P3 is coupled to the first line node bla. Optionally, the third pre-charge switch P2 is a p-type transistor (e.g., a PMOS transistor or a PNP transistor).

[0069] In one example, please refer to Figure 6 The fourth pre-charge circuit 14 includes a fourth pre-charge switch P4. The gate of the fourth pre-charge switch P4 is coupled to a pre-charge control signal prec, the source of the fourth pre-charge switch P4 is coupled to a second preset potential vcc / 2, and the drain of the fourth pre-charge switch P4 is coupled to a second bit line node blb. Optionally, the fourth pre-charge switch P4 is a p-type transistor (e.g., a PMOS transistor or a PNP transistor).

[0070] It is worth noting that since the source and drain are fabricated identically in a MOSFET, the source can be used as the drain, and vice versa. The lower voltage end of an NMOS transistor can be used as the source, and the higher voltage end of a PMOS transistor can be used as the source. The naming of the source and drain has no impact on the circuit. Different actual voltages of the MOSFETs lead to different circuit analyses. Therefore, in the above example description, the drains of N11-N13, N21-N22, N3-N4, and P1-P4 can be replaced with sources, and vice versa. Furthermore, in other embodiments, at least one of N11-N13, N21-N22, N3-N4, and P1-P4 can be replaced with a MOSFET of the opposite type to the one described above, and the source-drain connection can be adaptively varied according to the conductivity type of the MOSFET.

[0071] In this embodiment, when writing data to the storage array, the corresponding data "0" or "1" is input from the outside through the data input node IO of the memory, and after passing through the double-ended transmission circuit 10 controlled by the write enable signal WREN, it is transmitted to the first local input / output line node LIOT and the second local input / output line node LIOB. After passing through the column selection circuit YST controlled by the column selection signal YST0, it is transmitted to the first bit node b1a and the second bit node b1b in the latch circuit of the bit line sensing amplifier circuit SA. Then, it is written into the storage cell cell where M0 is located by the transistor M0 coupled to the second bit node b1b of the latch circuit (which is controlled by the row selection control signal vwlp). (That is, the conduction of transistor M0 will change the amount of charge stored in capacitor C0, thereby realizing the storage of binary bit data "1" or "0".)

[0072] The following is based on Figure 4A and Figure 6 Taking the example circuit as an example (where the first preset potential is VCC and the second preset potential is VCC / 2), and combining it with... Figure 7 The signal timing diagram shown illustrates the operation of the data writing circuit in this embodiment.

[0073] Please refer to Figure 6 and Figure 7 The data writing circuit in this example operates through the following stages:

[0074] (1) Precharge phase: When the precharge control signal prec is low (i.e., prec=0), P1, P2, P3, and P4 are all turned on, and the LIOT node and LIOB node are precharged to the first preset potential vcc. The bit line nodes bla and blb inside the latch circuit are precharged to vcc / 2. Then, prec is pulled high (i.e., prec=1), and the LIOT node, LIOB node, bla node, and blb node are all in a short floating state.

[0075] (2) Transmitting "1" data stage: IO = 1, the write enable signal WREN controls the two-ended transmission circuit 10 to turn on (i.e. Figure 4A and Figure 4B (N11 to N13 in the circuit are all turned on). Since the LIOT node is pre-charged to the first preset potential vcc, and the IO node has the same potential as the LIOT node, the LIOT node maintains the first preset potential vcc unchanged. The IO node can discharge to ground through a discharge path in the two-ended transmission circuit 10 (e.g., ...). Figure 4AThe pull-down of the path formed by the conduction of N12 and N13 discharges the LIOB node, quickly discharging it from VCC to VSS. The column strobe signal YST0 controls the column strobe circuit YST to conduct (i.e., N21 and N22 are turned on), allowing the LIOB node and the blb node to share charge, and the blb node's potential is quickly brought to VSS. Under the action of the latch circuit, the bla node and the blb node will quickly create a larger voltage difference, further pulling the bla node up to VCC. Finally, the row strobe control signal vwlp controls the transistor M0 to turn on (i.e., the word line WL coupled to the memory cell is turned on), and the blb node writes "0" to the memory cell where M0 is located through this transistor M0.

[0076] (3) During the "0" data transmission phase, IO = 0, and the write enable signal WREN controls the two-ended transmission circuit 10 to turn on (i.e., Figure 4A and Figure 4B (N11 to N13 in the circuit are all turned on), the discharge path from the IO node to the LIOB node is turned off, and the IO node and the LIOT node share charge. Since the LIOT node is pre-charged to the VCC potential, the switching transistors (e.g., N11 to N13 in the circuit) coupled to the LIOT node in the two-terminal transmission circuit 10 are turned off. Figure 4A The voltage difference across N11 is vcc, so the LIOT node is quickly pulled to VSS by the IO node. The column strobe signal YST0 controls the column strobe circuit YST to conduct (i.e., N21 and N22 are turned on), and the LIOT node and the bla node share charge. The potential of the bla node will be lower than the second preset potential vcc / 2. Under the action of the latch circuit, the bla node is quickly pulled low to VSS, and the blb node is pulled high to vcc. Finally, after the row strobe control signal vwlp controls the transistor M0 to turn on, the blb node writes "1" to the memory cell where M0 is located through the transistor M0.

[0077] In the above embodiments, since the transistor M0 of the memory cell is coupled to the blb node, the data written to the memory cell will be opposite to the data received by the IO node. In other embodiments, when the transistor M0 of the memory cell is coupled to the blb node, the data written to the memory cell will be the same as the data received by the IO node. It should be understood that when writing data to the entire memory array, the data written from both the blb node and the bla node is generally stored simultaneously. The data written to the corresponding memory cell through the blb node will be positive (i.e., the data written to the memory cell is the same as the data received by the IO node), and the data written to the corresponding memory cell through the blb node will be negative (i.e., the data written to the memory cell is opposite to the data received by the IO node). For example, the memory array (which may be DRAM or PSRAM, etc.) is divided into multiple sections in the row direction (word line WL direction), which can be data segments or code segments, etc., the smallest logical units that can be placed in the memory. In two adjacent sections, one is written through the blb and the other is written through the blb.

[0078] In summary, the data writing circuit of the present invention, based on the existing data writing circuit architecture, replaces the single-ended transmission circuit of the data input node IO of the coupled memory (e.g., DRAM, PSRAM, etc.) with a double-ended transmission circuit (which has a single data input terminal and two data output terminals). Thus, when the double-ended transmission circuit is turned on, the potential of the first bit node b1 or the second bit node b1 can be quickly pulled down by rapidly pulling down the potential of the LIOT node or LIOB node of the memory. This allows the first bit node b1 and the second bit node b1 to quickly separate a larger voltage difference, thereby increasing the speed of writing "0" and "1" to the memory cells and greatly reducing the speed difference between writing "0" and "1" (making the speed of writing "0" and "1" approximately the same). This improves the performance of the memory, enabling it to meet the requirements of higher performance products. Furthermore, the data writing circuit of the present invention also has a first to a fourth pre-charge path, thereby enabling the first local input / output line node LIOT and the second local input / output line node LIOB to be pre-charged to a first preset potential through the first and second pre-charge paths, and the first bit line node bla and the second bit line node blb to be pre-charged to a second pre-charge potential through the third and fourth pre-charge paths. In this way, when the dual-ended transmission circuit is turned on, the potential difference between the LIOT node and the LIOB node and the potential difference between the bla node and the blb node can be increased, so that the first bit line node bla and the second bit line node blb can quickly separate a larger voltage difference, thereby improving the speed of writing "0" and "1" to the memory cell of the memory, and thus improving the overall data writing speed of the memory. Furthermore, the dual-ended transmission circuit and column gating circuit in the data writing circuit of the present invention are both constructed using n-type transistors (e.g., NMOS), which can simplify the circuit, reduce costs, and utilize the characteristic of n-type transistors to transmit "0" faster, thereby increasing the speed of writing "0" and "1" to the memory cells of the memory, and ultimately improving the overall data writing speed and performance of the memory.

[0079] This embodiment also provides a memory chip, which includes a data writing circuit as described in any embodiment of the present invention. The memory chip can be any suitable memory chip such as DRAM or PSRAM.

[0080] The memory chip in this embodiment, due to the use of the data writing circuit of the present invention, has a smaller difference in speed between writing "0" and writing "1", thus improving its performance.

[0081] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.

Claims

1. A data writing circuit, characterized in that, It includes a dual-ended transmission circuit, a column gating circuit, and a bit line sensing amplification circuit coupled in sequence, wherein the bit line sensing amplification circuit is coupled to the memory array of the memory; wherein: The dual-ended transmission circuit has a single data input terminal and two data output terminals. Its data input terminal is coupled to the data input node of the memory, and one of the data output terminals is coupled to a first local input / output line node, and the other data output terminal is coupled to a second local input / output line node. The dual-ended transmission circuit is used to be turned on under the control of a write enable signal and to transmit the data received by the data input node to the first local input / output line node and the second local input / output line node in a complementary manner. The column gating circuit is used to transmit the data of the first local input / output line node and the second local input / output line node to the complementary first bit line node and second bit line node inside the bit line sensing amplifier circuit. The bit line sensing amplifier circuit is used to write the data or data opposite to the data into the corresponding storage cell in the storage array through at least one of the first bit line node and the second bit line node; The dual-ended transmission circuit includes a first switch, a second switch, and a third switch. The gates of the first switch and the third switch are both coupled to the write enable signal. The source of the first switch is coupled to the first local input / output line node. The drain of the first switch and the gate of the second switch are both coupled to the data input node. The drain of the second switch is coupled to the second local input / output line node. The source of the second switch is coupled to the drain of the third switch. Alternatively, the dual-ended transmission circuit includes a first switch, a second switch, a third switch, and an inverting circuit. The gate of the first switch and the input of the inverting circuit are both coupled to the data input node. The drain of the first switch is coupled to the second local input / output line node. The gate of the second switch is coupled to the output of the inverting circuit. The drain of the second switch is coupled to the first local input / output line node. The sources of the first and second switches are both coupled to the drain of the third switch. The gate of the third switch is coupled to the write enable signal.

2. The data writing circuit as described in claim 1, characterized in that, The first switch, the second switch, and the third switch are all n-type transistors.

3. The data writing circuit as described in claim 1, characterized in that, The column gating circuit includes: The first gating switch has its gate coupled to the column gating signal, its source coupled to the first local input / output line node, and its drain coupled to the first bit line node. The second strobe switch has its gate coupled to the column strobe signal, its source coupled to the second local input / output line node, and its drain coupled to the second bit line node.

4. The data writing circuit as described in claim 3, characterized in that, Both the first and second gating switches are n-type transistors.

5. The data writing circuit as described in any one of claims 1-4, characterized in that, Also includes: The first pre-charge circuit is coupled to the pre-charge control signal and the first local input / output line node, and is used to pre-charge the potential of the first local input / output line node to a first preset potential under the control of the pre-charge control signal before the dual-ended transmission circuit is turned on for data transmission. And / or, The second pre-charge circuit is coupled to the pre-charge control signal and the second local input / output line node, and is used to pre-charge the potential of the second local input / output line node to the first preset potential under the control of the pre-charge control signal before the dual-ended transmission circuit is turned on for data transmission.

6. The data writing circuit as described in claim 5, characterized in that, The first pre-charge circuit includes a first pre-charge switch, the gate of the first pre-charge switch is coupled to the pre-charge control signal, the source of the first pre-charge switch is coupled to the first preset potential, and the drain of the first pre-charge switch is coupled to the first local input / output line node. And / or, The second pre-charge circuit includes a second pre-charge switch, the gate of which is coupled to the pre-charge control signal, the source of which is coupled to the first preset potential, and the drain of which is coupled to the second local input / output line node.

7. The data writing circuit as described in any one of claims 1-4 or 6, characterized in that, The bit line sensing amplification circuit includes a latch circuit coupled to the memory array and the column gating circuit, for providing the first bit line node and the second bit line node, and for performing charge sharing between the first bit line node and the first local input / output line node, and between the second bit line node and the second local input / output line node, respectively, and amplifying the voltage difference between the first bit line node and the second bit line node.

8. The data writing circuit as described in claim 7, characterized in that, The latching circuit includes a cross-coupled first inverter and a second inverter. The input terminal of the first inverter is coupled to the first bit line node and the output terminal of the second inverter, and the input terminal of the second inverter is coupled to the second bit line node and the output terminal of the first inverter.

9. The data writing circuit as described in claim 7, characterized in that, The bit line sensing amplifier circuit further includes: A third pre-charge circuit, coupled to the pre-charge control signal and the first bit line node, is used to pre-charge the potential of the first bit line node to a second preset potential under the control of the pre-charge control signal before the dual-ended transmission circuit is turned on for data transmission; and / or, The fourth pre-charge circuit is coupled to the pre-charge control signal and the second bit line node, and is used to pre-charge the potential of the second bit line node to the second preset potential under the control of the pre-charge control signal before the dual-end transmission circuit is turned on for data transmission.

10. The data writing circuit as described in claim 9, characterized in that, The third pre-charge circuit includes a third pre-charge switch, the gate of which is coupled to the pre-charge control signal, the source of which is coupled to the second preset potential, and the drain of which is coupled to the first bit line node. And / or, The fourth pre-charge circuit includes a fourth pre-charge switch, the gate of which is coupled to the pre-charge control signal, the source of which is coupled to the second preset potential, and the drain of which is coupled to the second bit line node.

11. A memory chip, characterized in that, Includes the data writing circuit as described in any one of claims 1-10.

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