Mainboard assembly for memory component testing and method of using same

Abstract

A mainboard assembly for testing memory components is described. The motherboard assembly has at least one CPU communicatively coupled with the at least one memory channel, and a memory controller or BIOS programmed to continue booting in the presence of a memory component failure. When a fault is detected, the memory controller or BIOS skips the read / write training program and uses the preset value of the PHY register in the previous successful boot program to continue the current boot without interrupting power. The memory controller or BIOS is also programmed to provide adjustable data retention time settings and adjustable speed settings without reboot or power down.

Description

Technical Field

[0001] The field of the invention is memory testing systems. Background Art

[0002] The background description includes information that may be helpful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, nor is it an admission that any publication specifically or implicitly referenced is prior art.

[0003] DRAM and flash memory technologies have been known to the public for many years. While the basic underlying technology has remained largely unchanged over time, interfaces such as Fast Page Mode (FPM), Extended Data Output (EDO), Synchronous DRAM (SDRAM), and Double Data Rates 1-4 (DDR1, DDR2, DDR3, DDR4) have evolved over time. In some applications, DRAM components are soldered to a PCB substrate to form a module, such as a DIMM module that plugs into a computer system's motherboard.

[0004] Traditionally, testing packaged memory components is accomplished through several steps and multiple insertions. Typically, packaged DRAM components first undergo burn-in ("BI") testing. This testing is performed with high parallelism in expensive BI systems. For example, current BI systems can cost between $500,000 and $1 million per test system. Due to the large number of components being tested and contacted, such systems operate at low frequencies of around 5-20 MHz, far from the normal operating frequency of 1 GHz for such semiconductors. To reduce signal requirements, most approaches use internal on-chip test circuitry to compress all data signals onto a single external data pin (for example, reducing 16 DQs to a single DQ) and employ other test modes to modify internal voltages to more effectively stress the memory components. BI testing aims to age the semiconductor under stress for several hours to avoid premature failures at the customer level. The associated stress testing is typically performed at temperatures up to 125 degrees Celsius and elevated voltages. Typically, thousands of components are tested in parallel in a single BI test system.

[0005] After a successful BI test, the components undergo weak cell or core testing. These tests are designed to identify weak DRAM memory cells that could fail at the customer level due to poor memory cell retention or other weaknesses. Testing is performed on expensive automated test equipment, typically costing $1 million to $3 million, operating at 200-500 MHz and testing 200-1000 components in parallel. Due to the large number of signals provided, some signals (e.g., address / command) are shared across multiple components, and chip vendor-provided data compression test patterns reduce the number of DQs that need to be contacted (e.g., through data compression (read) and copy (write) methods, only four data signals are required instead of all 16). This type of testing can be performed at different temperatures. For example, a group of components can be tested at a high temperature (e.g., 95 degrees Celsius), removed from the system, and later tested on another test system at a much lower temperature (e.g., -40 degrees Celsius). Removal is necessary because the test handler cannot change temperature very quickly without other adverse effects. The handling device is attached to the test system to feed the DRAM components to be tested onto the test head and provide the expected test temperature.

[0006] As is known in the art, after successful completion of the weak cell test, the component is subjected to a speed test performed by a DRAM speed tester. During this test, all electrical signals of the component need to be connected to the speed tester to ensure that all signals and circuits are fully functional. A DRAM with 16 DQs must be connected to 16 separate DQ signals in uncompressed mode. Therefore, the parallelism of such a test system is relatively low in the range of 50-200 components. In addition, the parts must run at full system speed in the range of 1GHz. Therefore, such a system is very expensive, typically costing between $3 million and $5 million. It may also be necessary to test at different temperatures (for example, 95°C and later again at -40°C) to ensure that customer specifications for a fully functional part are met.

[0007] As mentioned above, DRAM packaged components are submitted to a set of at least 3 different test systems for BI, weak cell and speed testing. Some test steps may have to be performed up to 5 times at different temperatures for the tests that need to be submitted. This means that if retesting is required, the component needs to be handled 5 times or more. This can cause the contacts (such as the contact balls of the FBGA component) to be damaged during operation, which is undesirable but unavoidable in today's test methods. In addition, very expensive tools are required to feed and handle the DRAM components within the test processing device and electrically connect them to the test head. For example, Hifix electrically connects the components to the tester signal channel. Such tools are used for specific products and must be provided for each individual DRAM. The tooling required for the 9×11mm FBGA 78 package is completely different from the tools and Hifix required for, for example, the 7×10mm FBGA 96 package. A set of tools for a product can easily cost more than $250,000.

[0008] Furthermore, conventional motherboards are designed to operate with fault-free memory modules and are not intended to be operated in a cluster to test memory components. In view of the above, readers can easily understand that there is still a need for a simpler and safer method to test memory components. Summary of the Invention

[0009] The present invention provides an apparatus, system, and method for a motherboard assembly to test memory components in the presence of a fault. The motherboard assembly includes at least one CPU or FPGA, at least one memory channel communicatively coupled to the CPU or FPGA, and a memory controller or BIOS. The memory controller or BIOS is programmed to: (a) skip write calibration, MPR mode write, and read / write center alignment in the presence of a memory component fault, and continue the current boot process without powering down using the preset values of the PHY registers from a previous successful boot process; (b) provide adjustable retention time settings without requiring a reboot or power down; and (c) provide adjustable speed settings without requiring a reboot or power down.

[0010] From a method perspective, a motherboard assembly can be configured to test a first plurality of memory components using a first plurality of memory channels to determine preset values for PHY registers to use in the event of a memory component failure. The first plurality of memory components have been previously tested and verified as non-defective, and therefore, the preset values for the PHY registers are not required during the first set of tests. Once the preset values for the PHY registers have been determined, a second plurality of memory components can be tested using the first plurality of memory channels. The second plurality of memory components can include at least one defective memory component that causes a failure during the boot process, in which case read / write centering is skipped and the preset values for the PHY registers are used to prevent the memory controller or BIOS from powering down and to continue booting and testing.

[0011] In other aspects, a method of using a motherboard assembly may include the following steps: (i) connecting a first memory component to a first memory channel; (ii) connecting a second memory component to a second memory channel, wherein the first memory channel and the second memory channel are communicatively coupled to a first CPU; and (iii) during testing of the first memory component and the second memory component, testing the first memory component and then testing the second memory component without powering off a memory controller or BIOS, even if the first memory component is defective and fails.

[0012] In other aspects, a method of using a motherboard assembly may include the following steps: (i) connecting a first memory component to a first memory channel; (ii) connecting a second memory component to a second memory channel, wherein the first memory channel and the second memory channel are communicatively coupled to a first CPU; and (iii) testing the first memory component at a first frequency without powering off a memory controller or BIOS during testing of the first memory component and the second memory component, and subsequently testing the second memory component at a second frequency different from the first frequency. It is contemplated that the first frequency and the second frequency differ by at least 100 Hz. It is also contemplated that, during testing of the first memory component and the second memory component, the first memory component and the second memory component are tested with different CAS latency, RAS-to-CAS latency settings, and / or RAS precharge latency settings without powering off a memory controller or BIOS, wherein the first CAS latency and the second CAS latency are different. In some instances, write calibration, MPR mode writes, and read / write center alignment are performed during testing of the first memory component and skipped during testing of the second memory component.

[0013] Various objects, features, aspects, and advantages of the present subject matter will become more apparent from the following detailed description of preferred embodiments and the accompanying drawings, wherein like numerals represent like components.

[0014] All publications mentioned herein are incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference. If a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.

[0015] The following description includes information that may be helpful in understanding the present invention. It is not intended to be an admission that any of the information provided herein is prior art or relevant to the present invention, nor is it intended that any publication specifically or implicitly referenced is prior art.

[0016] In some embodiments, the numerals representing the properties such as the amount of ingredients, concentrations, reaction conditions, etc., used to describe and claim certain embodiments of the present invention should be understood to be modified by the word "about" in some cases. Therefore, in some embodiments, the numerical parameters proposed in the written description and the appended claims are approximate values and can vary according to the desired properties sought to be obtained in a particular embodiment. In some embodiments, numerical parameters should be interpreted according to the number of reported significant figures and by applying ordinary rounding techniques. Although the numerical ranges and parameters setting forth the wide range of some embodiments of the present invention are approximate values, the numerical values set forth in the specific examples are reported as accurately as possible. The numerical values presented in some embodiments of the present invention may contain certain errors, which are necessarily caused by the standard deviations found in their respective test measurements.

[0017] Unless the context dictates otherwise, all ranges described herein should be interpreted as inclusive of their endpoints, and open-ended ranges should be understood to include only commercially practical values. Likewise, unless the context dictates otherwise, all lists of values should be interpreted as including intermediate values.

[0018] As used in the description herein and throughout the claims that follow, the meanings of “a,” “an,” and “the” include plural references unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

[0019] The description of the range of values herein is only intended to be a shorthand method for quoting each individual value falling within the range as a separate reference. Unless otherwise specified herein, each individual value is incorporated into the specification as if it were quoted separately in this article. Unless otherwise specified herein or clearly contradictory to the context, all methods described herein can be performed in any suitable order. The use of any and all examples or exemplary language (such as "such as") provided herein for certain embodiments is only intended to better illustrate the present invention and does not limit the scope of the present invention otherwise claimed. Any language in the description should not be interpreted as indicating any non-claim elements that are crucial to the practice of the present invention.

[0020] The grouping of the alternative elements or embodiments of the present invention disclosed herein should not be construed as limiting. Each group member can be quoted and advocated individually, or can be quoted and advocated in any combination with other members of the group or other elements herein. For convenience and / or patentability, one or more members of a group can be included in the group or deleted from the group. When any such inclusion or deletion occurs, this specification is deemed to include the modified group at this time, thereby meeting the written description of all Markush groups used in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A and Figure 1B Shown are top views of assembled test board systems according to two variations of embodiments of the present inventive subject matter, the test board systems including a frame and a plurality of main boards disposed thereon.

[0022] Figure 1C Shown Figure 1A or Figure 1B Bottom view of the multiple motherboards attached to the frame.

[0023] Figure 2 A separate frame view is provided.

[0024] Figure 3A and Figure 3B The embodiment of the subject matter of the present invention is shown Figure 1A ( Figure 3A )and Figure 1B ( Figure 3B )'s isolated front view of the motherboard.

[0025] Figure 3C A bottom view of a motherboard and its components according to an embodiment of the inventive subject matter is provided.

[0026] Figure 3D Shown according to Figure 3B A cross-sectional view of a motherboard according to an embodiment.

[0027] Figure 4A-4B A front view and a perspective view, respectively, are shown of a mainboard according to another embodiment of the inventive subject matter.

[0028] Figure 5A-5B Shown respectively Figure 4A-4B An embodiment of inserting a memory module into a memory module slot.

[0029] Figure 6 Shown is the assembled tester system with the microclimate chamber on top.

[0030] Figure 7A-7B Side and top views of a multi-layer motherboard assembly according to an embodiment of the inventive subject matter are shown.

[0031] Figure 8 Shown are top and side perspective views of multiple motherboard assemblies inserted into a frame to form an assembled test system with memory component receptacles, in accordance with an embodiment of the inventive subject matter.

[0032] Figure 9 Shown are top and side perspective views of multiple motherboard assemblies inserted into a frame to form an assembled test system with memory module slots, in accordance with an embodiment of the inventive subject matter.

[0033] Figure 10 Shows the .cvs file for speed grading using an FPGA board. DETAILED DESCRIPTION

[0034] In the following discussion, a large number of references will be made to servers, services, interfaces, engines, modules, clients, peers, portals, platforms, or other systems formed by computing devices. It should be understood that the use of these terms is considered to mean one or more computing devices having at least one processor (e.g., ASIC, FPGA, DSP, x86, ARM, ColdFire, GPU, multi-core processor, etc.) that is programmed to execute software instructions stored on a computer-readable tangible, non-transitory medium (e.g., hard drive, solid-state drive, RAM, flash memory, ROM, etc.). For example, a server may include one or more computers that operate as a network server, database server, or other type of computer server in a manner that performs the described role, duty, or function. It should be further understood that the disclosed computer-based algorithms, processes, methods, or other types of instruction sets may be embodied as a computer program product that includes a non-transitory tangible computer-readable medium storing instructions that cause the processor to perform the disclosed steps. Various servers, systems, databases, or interfaces may exchange data using standardized protocols or algorithms based on HTTP, HTTPS, AES, public-private key exchange, web service APIs, known financial transaction protocols, or other electronic information exchange methods. Data exchange may occur over a packet-switched network, the Internet, a local area network (LAN), a wide area network (WAN), a VPN, or other types of packet-switched networks.

[0035] The following discussion provides a number of example embodiments of the present subject matter. Although each embodiment represents a single combination of the present invention's elements, the present subject matter is considered to include all possible combinations of the disclosed elements. Thus, if one embodiment includes elements A, B, and C, and a second embodiment includes elements B and D, the present subject matter is also considered to include other remaining combinations of A, B, C, or D, even if not explicitly disclosed.

[0036] As used herein, unless the context dictates otherwise, the term "coupled to" is intended to include both direct coupling (where two elements being coupled to each other are in contact with each other) and indirect coupling (where at least one additional element is located between the two elements). Thus, the terms "coupled to" and "coupled with..." are synonymous.

[0037] Figure 1A and Figure 1BA top view (also referred to as a front view) of an assembly test board system 100 is shown, which includes a frame 110 and a plurality of main boards 120 disposed thereon according to an embodiment of the present subject matter. Figure 1A The embodiment of FIG. 1 shows a memory channel 123 in the form of a memory component receptacle 123A that is configured to receive a memory module for testing. Figure 1B The embodiment of FIG. 1 shows a memory channel 123 in the form of a memory module slot 123B that receives a memory module for testing. Figure 1A 、 Figure 1B Each embodiment of Figure 1A-1B In each of the figures, the CPU 121 arranged on the lower side of the main board 120 is shown by a dotted line.

[0038] Figure 1C Shown Figure 1A or Figure 1B A bottom view (also referred to as a rear view) of a plurality of motherboards 120 attached to a frame 110. For clarity and simplicity of illustration, memory channels 123 ( Figure 1A Memory component jack 123A, Figure 1B The memory module slot 123B) is not shown by a dotted line. Figure 1A The memory component jack 123A and Figure 1B The memory module socket 123B may be soldered to the mainboard 120 .

[0039] The mainboard 120 can be attached to and removed from the frame 110. In a preferred embodiment, the mainboard 120 can be attached to the frame 110 using plastic screws to minimize temperature transfer between the top and bottom sides of the mainboard 120. Other types of screws made of low heat transfer materials are also suitable. Other types of suitable attachment methods are also contemplated.

[0040] Without limiting the general applicability of our approach, we further describe the invention by way of an example of a DRAM (Dynamic Random Access Memory) test flow.

[0041] Figure 2 A separate frame 110 is shown. Frame 110 is made of a sturdy material. Suitable materials may include, but are not limited to, metal (e.g., aluminum) or other materials (e.g., carbon composite, fiberglass composite, or other rigid non-metallic materials). Frame 110 includes a space or cavity 111. When motherboard 120 is arranged (e.g., mounted) on the frame, cavity 111 allows access to the underside components of motherboard 120 from the underside. When motherboard 120 is mounted on frame 110, components on the underside of motherboard 120 (e.g., CPU 121) will extend into cavity 111.

[0042] Figure 1A-Figure 2The frame 110 is shown with six motherboards 120 mounted thereto, but it is contemplated that the frame 110 may mount more or fewer motherboards 120. For example, other configurations are contemplated that may accommodate four to ten motherboards 120.

[0043] Figure 1A-Figure 2 The dimensions of the illustrated embodiment are those of a standard BI board. The reader will appreciate that the system and method of the present invention eliminate the need for existing large, expensive BI testing systems. However, using standard BI dimensions allows for the use of other aspects of the standard BI process, such as automatic loaders and unloaders for loading and unloading memory components. Furthermore, software and socket performance analysis can be performed in a manner similar to existing BI systems.

[0044] exist Figure 1A and Figure 1B In the example shown, the tops of the motherboards 120 are aligned on the frame 110 so that they touch each other, and the frame 110 is not visible between the boards. The motherboards 120 are aligned so that the edges touch to form a continuous surface that serves to separate and thermally isolate the top side of the motherboard 120 with the memory channels 123 from the underside of the board with the CPU 121 and other sensitive electronic components.

[0045] The frame 110 includes an electrical connector 124A that is aligned to couple with the electrical connector 124B of the motherboard 120 to provide power to the CPU 121 and other components of the motherboard 120. Figure 1A As shown, the frame 110 may include an electrical connector 124A that connects the electrical connectors 124B of all installed motherboards 120 .

[0046] Figure 3A and Figure 3B An embodiment according to the subject matter of the present invention is shown Figure 1A ( Figure 3A )and Figure 1B ( Figure 3B ) is an independent front view of the main board 120. Figure 3C Shown Figure 3A 、 Figure 3B A rear view (bottom view) of the main board 120.

[0047] Figure 3A and Figure 3B The motherboard 120 shown includes a CPU 121 (shown in dotted lines) which is electrically connected to a memory component jack 123A ( Figure 3A ) and memory module slot 123B ( Figure 3B). The memory component receptacle 123A is configured to receive a corresponding memory component for testing, and the memory module slot 123B is configured to receive a corresponding memory module, which in turn contains one or more memory components for testing. Figure 1A-1B and Figure 3A-Figure 3B , the CPU 121 is shown in dotted lines to illustrate that it is located on the other side of the motherboard 120.

[0048] like Figure 3A and Figure 3B As shown, the CPU 121 is depicted by dashed lines as being disposed on the bottom side (also referred to as the back side) of the motherboard 120, while the memory channels 123 (memory component receptacles 123A and / or memory module slots 123B) are located at or near the top side (also referred to as the front side) of the motherboard 120.

[0049] This arrangement protects the CPU 121 from the temperature variations provided by the microclimate chamber when test memory units or memory components are inserted into the memory component receptacles 123A and / or the memory module slots 123B, respectively. For example, during testing, the temperature surrounding the CPU 121 can differ by at least 5 degrees Celsius from the temperature surrounding the memory channels 123 (and the memory modules or memory components connected thereto).

[0050] and Figure 1A-1B Same, in Figure 3A and Figure 3B The CPU 121 is shown by dotted lines to indicate that they are located on the motherboard 120 and the memory component socket 123A ( Figure 3A ) and memory module slot 123B ( Figure 3B ) on the opposite side. To keep the drawings clear, these memory channels 123 are Figure 3C Not shown by dotted lines.

[0051] In an embodiment of the present subject matter, the motherboard 120 also includes a wireless communication component that includes a wireless antenna that is communicatively coupled to the CPU 121 to enable the CPU 121 to send data to and receive data from an external computing device. The wireless antenna can be integrated into the CPU 121, such as in the embodiment shown here, or can be a separate antenna component. To protect the antenna and other communication components from the temperatures experienced in the test environment, the antenna and other communication components (when separated from the CPU 121) are also located on the underside of the motherboard 120, opposite the memory channel 123. Examples of contemplated wireless data transmission methods include WiFi, Bluetooth, NFC, etc. In an embodiment of the present subject matter, some or all of the communication functions and / or command functions can be handled by a separate board (e.g., a Raspberry Pi board) that can issue commands to components on the motherboard 120.

[0052] Figure 3D A cross section of the motherboard 120 is shown showing the connector 122 extending across the width of the motherboard 120 to connect the CPU 121 on the underside of the board with the memory channel 123 (memory module slots 123B in this example) on the top side of the motherboard 120. Figure 3D The embodiment shown in FIG. 1 shows only the memory module socket 123B, but an embodiment having a memory component receptacle 123A would be the same except that the memory component receptacle 123A replaces the memory module socket 123B.

[0053] exist Figure 1A-1B In each of the illustrated embodiments, the motherboard 120 attached to each frame 110 is shown as being identical. In other embodiments, the motherboard 120 may be different to accommodate a different number of memory cells to be tested, or to allow different types of memory cells to be tested simultaneously.

[0054] Figure 1A-Figure 1C The test panel system 100 shown in FIG. 1 shows a main panel 120 arranged along a single horizontal plane. In these embodiments, the dimensions of the test panel system 100 (including the main panel 120) are between 30 cm x 30 cm and 2 m x 2 m (including the frame 110). In a preferred embodiment, the dimensions are 40 cm x 60 cm, including the frame.

[0055] Figure 4A-4B A top view and a perspective view, respectively, of an embodiment of the inventive subject matter are shown in which the memory channels 123 (memory module slots 123B in this example) are arranged so that when a memory module is inserted, it is vertically aligned with the motherboard 120 (e.g., it is oriented perpendicular to the motherboard 120).

[0056] Figure 5A-5BMemory module 510 is shown inserted into memory module slot 123B. Figure 4A-4B Examples of Figure 4A-4B As shown, the memory modules 510 extend vertically from the mainboard 120 (e.g., no more than 15 degrees from vertical). Each memory module 510 may include a memory component capable of receiving a memory component for testing (e.g., a memory component configured as a memory module). Figure 5B One or more memory component sockets (represented by the blocks on each memory module 510 visible in FIG. 5 ).

[0057] Figure 6 A microclimate chamber 200 is shown having a microclimate chamber 200 disposed on the upper side or top side of the assembled test panel system 100. Figure 1A The microclimate chamber 200 can provide a heated and / or cooled environment to test memory components attached to the main board 120. The microclimate chamber 200 can have a heating source and / or a cooling source (not shown for clarity) to provide a heated and / or cooled environment for component testing.

[0058] As described above, when the main boards 120 are attached to the frame 110, the edges of the main boards 120 contact each other, forming a continuous or nearly continuous surface with no gaps between the main boards 120. This helps to isolate the underside of the main boards 120 from the climate generated by the microclimate chamber 200.

[0059] In the illustrated embodiment, the microclimate chamber 200 is sized to accommodate all of the motherboards 120 attached to the frame 110. In other embodiments, it is contemplated that the microclimate chamber 200 may be smaller so that it accommodates some, but not all, of the motherboards 120. The astute reader will readily appreciate that the microclimate chamber 200 eliminates the need for large, conventional, and expensive BI testing equipment.

[0060] The above-described embodiments are used to provide a temperature differential between a memory component being tested on a motherboard and a CPU on the same board. However, PCBs can be relatively thin and have multiple layers of metal traces. Therefore, if the memory components on the front side are exposed to very high or very low temperatures for an extended period of time, these temperatures can eventually transfer to the back side, causing damage or excessive thermomechanical stress or condensation. Therefore, it may be desirable to further isolate the CPU and other sensitive electronic components from the excessive temperatures required for testing semiconductor memory components. Therefore, in an embodiment of the present invention, the motherboard further separates the CPU from the memory components being tested by vertically spacing the components from the CPU.

[0061] Figure 7A-7B A side view and a top view, respectively, of a motherboard assembly 710 are shown, in accordance with an embodiment of the inventive subject matter.

[0062] like Figure 7AAs shown, the mainboard assembly 710 includes an upper mainboard 711 and a lower mainboard 712 .

[0063] The upper main board 711 includes one or more memory channels 723 . Figure 7A-7B The embodiment includes a memory component jack 723A (which is configured to receive a memory component for testing). However, as Figure 9 As shown in the portion of the assembled system in the illustrated embodiment, the general structure of the motherboard assembly 710 is suitable for embodiments having a memory module socket 723B (which is configured to receive a memory module for testing). Therefore, for embodiments using the memory module socket 723B, its structure will be the same as Figure 7A-7B The structure shown is the same, except that the motherboard assembly 710 will have a memory module socket 723B instead of a memory component receptacle 723A.

[0064] Figure 7A-7B The memory component jack 723A can be used with Figure 1A and Figure 3A The same as the memory component jack 123A, Figure 9 The memory module socket 723B can be used with Figure 1B and Figure 3B The same as the memory module slot 123B.

[0065] The lower mainboard 712 includes a CPU 721 on its underside. The lower mainboard 712 can be coupled to the upper mainboard 711 via a support connector 713. The upper and lower mainboards 711, 712 are arranged so that the two boards are parallel. In an embodiment, the angle difference between the upper and lower mainboards 711, 712 does not exceed 15 degrees.

[0066] In the embodiment of the inventive subject matter illustrated herein, a gap 715 is present between the upper mainboard 711 and the lower mainboard 712. The gap 715 between the upper mainboard 711 and the lower mainboard 712 helps to isolate the CPU 721 from the temperature applied to the memory modules and / or memory components being tested. In an embodiment, the width of the gap 715 can be between 1 mm and 100 mm.

[0067] The CPU 721 is connected to the memory component jack 723A and the memory module slot 723B (in Figure 9 In the embodiment) communication coupling. Figure 7A As shown, the connector 722 connects the components of the upper main board 711 and the lower main board 712 through the connection column 714. Therefore, the connector passes through the lower main board 712, the connection column 714 and the upper main board 711 to connect the CPU 721 to the memory component socket 723A.

[0068] In an embodiment of the present subject matter, motherboard assembly 710 includes more than one connection post 714. For example, motherboard assembly 710 may have 2-4 connection posts 714.

[0069] Each connecting post 714 can transmit multiple signals through the connector 722. It is contemplated that each connecting post 714 can transmit 100 to 1000 signals through the connector 722.

[0070] In embodiments of the present subject matter, upper main board 711 and lower main board 712 may be connected solely by connection posts 714, without requiring support connectors 713. In other embodiments, upper main board 711 and lower main board 712 are connected by support connectors 713, without requiring connection posts 714. In these embodiments, connector 722 is routed through one or more support connectors 713.

[0071] In the embodiment of the inventive subject matter illustrated herein, gap 715 includes an insulating layer 716 between upper main plate 711 and lower main plate 712 .

[0072] The insulating layer 716 can be air (e.g., ambient air or an enclosure containing air), a vacuum (e.g., an enclosure with a vacuum inside), Styrofoam, rubber, etc. The insulating layer can be a layer of material with air or vacuum bubbles (e.g., Styrofoam). In an embodiment such as that shown herein, the insulating layer 716 fills at least 70% of the gap 715.

[0073] The motherboard assembly 710 can be used with Figures 1A-6 The motherboard 120 is similar to Figure 2 A plurality of motherboard assemblies 710 can be attached to the frame 110 to test memory modules or memory components.

[0074] When mounted on a frame such as frame 110, the lower main board 712 can be mounted directly on the frame 110. The insulating layer 716 can be a rigid material with air pockets and spacers made of plastic. All of this can then be screwed together with the upper main board 711 on top.

[0075] Figure 8 Shown are top and side perspective views of a plurality of motherboard assemblies 710 inserted into the frame 110 to form the assembled tester system 800. In this example, the motherboard assembly 710 shown includes only the memory component receptacle 723A. As described above, Figure 9 Shows top and side perspective views of multiple motherboard assemblies 710 inserted into frame 110, with only Figure 9 The motherboard assembly has memory module slot 723B instead of Figure 8 Memory component jack 723A.

[0076] Figure 8 The assembly tester system 800 includes six motherboard assemblies 710 inserted into the frame 110 .

[0077] exist Figure 8 In the illustrated embodiment, each motherboard assembly 710 has a CPU 721 connected to two rows of memory component sockets 723A via connection posts 714. In other embodiments, each motherboard assembly 710 may have more than two rows of memory component sockets 723A for each CPU and may have multiple connection posts 714.

[0078] For simplicity, Figure 8 and Figure 9 The illustration of FIG. 7 does not show the insulating layer 716 , but it is contemplated that the assembly may include embodiments as described herein that include the insulating layer 716 .

[0079] and Figures 1A-6 The same embodiment as FIG7- Figure 9 Embodiments may include communication hardware, which may include other communication components and an antenna that enable the CPU 721 to exchange data with external computing devices. The antenna may be integrated into the CPU 721 or separate from the CPU 721. In embodiments where the antenna is separate from the CPU 721, the antenna is also provided on the lower motherboard 712 to protect it from the test environment.

[0080] and Figures 1A-6 As in the embodiment of the present invention, the motherboard assembly 710 may include a connector configured to be connected to a corresponding connector of the frame 110 so that power can be supplied to the motherboard assembly 710 .

[0081] In an embodiment of the present subject matter, the upper main plate 711 and the lower main plate 712 have the same or substantially the same area (within 10% of the surface area). In other embodiments of the present subject matter, the area of the upper main plate 711 is less than the area of the lower main plate 712, where the difference is greater than 10% of the surface area. In these embodiments, the differential area is protected by the insulating material described herein. Protected by the insulating material means that at least 80% of the differential area is protected by the insulating material.

[0082] Testing in the presence of faults

[0083] Unlike conventional motherboards that are designed to operate only with non-faulty memory modules and are not intended to operate as a cluster, motherboard 120 and motherboard assembly 710 have a memory controller or BIOS that is programmed to test memory components in the event of a failure.

[0084] For DRAM memory modules, the clock, command, and address lines (A, CK, CKE, WE, CSn) are connected using a fly-by routing topology. This is done because all DRAMs on a DIMM share the same address lines, and fly-by routing is required to achieve better signal integrity and high speed. From the ASIC / processor perspective, each DRAM memory on a DIMM is located at a different distance. From the DIMM perspective, the skew between the clock and data is different for each DRAM on the DIMM. For read / write training, the controller / PHYIP typically provides multiple algorithms. The most common are: (1) write calibration; (2) multi-purpose register (MPR) mode write; (3) read center alignment; and (4) write center alignment.

[0085] These algorithms, called read / write training routines, are executed by the memory controller or BIOS. Traditional motherboards typically require each algorithm to be enabled / disabled via registers. When a failure is detected, the program is halted, the memory channel and motherboard become inoperable, and action must be taken to restart the test.

[0086] The memory controller or BIOS of the motherboard 120 and motherboard assembly 710 is programmed to test the memory components by skipping the read / write training procedures in the event of a fault. This is achieved by using preset values for the relevant PHY registers, which are determined from a previous successful boot procedure. In this way, even if a fault occurs, the memory controller or BIOS will not disable or shut down the motherboard between different memory loads.

[0087] The memory controller or BIOS of motherboard 120 and motherboard assembly 710 is also programmed to allow adjustment and modification of retention time settings without powering down or rebooting. Conventional motherboard memory controller and BIOS settings typically only allow for 3.9us or 7.8us refresh settings. For an 8k refresh, a 3.9us setting corresponds to an 8k x 3.9us = 32ms DRAM refresh, while a 7.8us setting corresponds to a 64ms refresh setting for computer applications running with standard DRAM. However, memory testing requires different settings, as DRAMs are often tested with guard bands to protect customers from marginal retention failures or DRAM cell degradation. Standard 64ms-specified DRAMs are typically tested with a 100ms retention setting during manufacturing testing. Because the memory controller or BIOS can set refresh settings between 3.9us and 7.8us, adjustable retention time settings are required for memory testing. The memory controller or BIOS of motherboard 120 and motherboard assembly 710 is configured to allow adjustment of retention time settings within a range of 3.9us to 15.6us, or even greater, for effective DRAM testing. These adjustments preferably allow selection of flexible hold time settings with a step size of approximately 1.21875 us, which corresponds to a hold time setting step size of 10 ms.

[0088] The memory controller or BIOS of the motherboard 120 and motherboard assembly 710 is also programmed to allow speed settings to be adjusted and modified across power outages and reboots. Adjusting speed settings allows for speed grading. DRAM can have different speeds based on manufacturing variations (wider versus narrower transistor devices). For example, DDR-3 DRAM has speed grades of -1333, -1600, -1866, and -2133. To categorize the test equipment into the appropriate speed grade, it must be tested during the speed test step. The memory controller or BIOS of the motherboard 120 and motherboard assembly 710 is programmed to test the DRAM at different frequencies to determine the maximum speed grade achieved, without requiring power to be removed between different speed test runs. Therefore, write calibration and data eye centering calibration results remain valid and active between different test runs. Furthermore, BIOS settings for frequency and key speed parameter settings (such as CAS latency, RAS-to-CAS delay settings, and RAS precharge timing) can also be adjusted without powering down.

[0089] For CPUs without BIOS (e.g. FPGAs), speed settings are adjusted by changing the clock frequency on the fly. If the memory controller / PHY is modified appropriately so that the PHY registers used to write calibration and data eye centering results can be set externally, a reboot can be performed. Figure 10As shown, if the FPGA is to be used for testing, key DRAM operating parameters are provided to the memory controller (called MIG for Xilinx FPGAs) in the form of a .csv file. This is typically done only once to set the operating conditions of the DRAM channels used by the FPGA. However, the memory controllers of the motherboard 120 and motherboard assembly 710 are programmed to continuously update key DRAM operating parameters to achieve DRAM speed grading when the FPGA is used. To this end, multiple test runs are performed on the same DRAM at different clock frequencies and different .csv settings. Other file formats equivalent to .csv are also contemplated for use in completing FPGA motherboard speed grading.

[0090] It will be understood by those skilled in the art that more modifications may be made in addition to those already described without departing from the inventive concepts herein. Therefore, the subject matter of the present invention is not limited except in the spirit of the appended claims. In addition, when interpreting the specification and claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms "comprises" and "comprising" should be interpreted as referring to elements, parts or steps in a non-exclusive manner, indicating that the referenced elements, parts or steps may exist, be used or be combined with other elements, parts or steps that are not explicitly referenced. Where the specification claims relate to at least one selected from the group consisting of A, B, C... and N, the text should be interpreted as requiring only one element in the group, rather than A plus N or B plus N, etc.

Claims

1. A motherboard assembly for memory component testing, comprising: At least one CPU; at least one memory channel; at least one electrical connection communicatively coupling the CPU and the memory channel; The memory controller, or BIOS, is programmed to: (a) Skip write calibration, MPR mode write, read / write center alignment in the presence of a memory component failure and continue the current boot process using the preset values of the PHY registers from the previous successful boot process without powering down; (b) provide adjustable hold time settings without requiring a restart or power outage; as well as (c) Provides adjustable speed settings without requiring a restart or power outage.

2. The motherboard assembly according to claim 1, wherein: The memory channel is a slot or a receptacle. 3 . The motherboard assembly of claim 1 , further comprising a memory component configured to be coupled to the memory channel.

4. The motherboard assembly according to claim 3, wherein: The memory components include DRAM components.

5. The motherboard assembly according to claim 3, wherein: The memory component is not soldered to the memory module board, nor is it connected to the clamshell chip holder or PCB.

6. The motherboard assembly according to claim 1, wherein: The adjustable hold time settings include hold time settings other than 3.9 us and 7.8 us.

7. The motherboard assembly according to claim 1, wherein: The adjustable hold time setting includes a range of 3.9 us to 15.6 us.

8. The motherboard assembly according to claim 1, wherein: The adjustable hold time setting allows for incremental adjustments within a range of 0µs to 3.9µs.

9. A method of using the motherboard assembly of claim 1, comprising: testing a first plurality of memory components using a first plurality of memory channels to determine preset values of PHY registers to use in the presence of a memory component failure, wherein the first plurality of memory components have been previously tested and verified as non-defective; and A second plurality of memory components is tested using the first plurality of memory channels, wherein the second plurality of memory components includes at least one defective memory component, wherein the at least one defective memory component uses a preset value of a PHY register to prevent the memory controller or BIOS from powering off.

10. A method of using the motherboard assembly of claim 1, comprising: connecting a first memory component to a first memory channel; as well as During testing, the first memory component is tested at a first frequency and then tested at a second frequency without powering off a memory controller or BIOS.

11. The method according to claim 10, wherein: The first memory component fails during testing at the first frequency.

12. A method of using the motherboard assembly of claim 1, comprising: connecting a first memory component to a first memory channel; connecting a second memory component to a second memory channel; wherein the first memory channel and the second memory channel are communicatively coupled to the first CPU; During the testing at the first frequency and the second frequency, without powering off a memory controller or BIOS, testing the first memory component and the second memory component at the first frequency and subsequently testing the first memory component and the second memory component at the second frequency; and The first frequency and the second frequency differ by at least 100 Hz.

13. The method according to claim 12, wherein: During testing the first CAS latency and the second CAS latency, the first memory component and the second memory component are tested at the first CAS latency and then tested at the second CAS latency without powering off the memory controller or the BIOS, wherein the first CAS latency and the second CAS latency are different.

14. The method according to claim 12, wherein: During testing of a first RAS-to-CAS latency setting and a second RAS-to-CAS latency setting, the first memory component and the second memory component are tested at the first RAS-to-CAS latency setting without powering off the memory controller or the BIOS, and then the first memory component and the second memory component are tested at the second RAS-to-CAS latency setting, wherein the first RAS-to-CAS latency setting and the second RAS-to-CAS latency setting are different.

15. The method according to claim 12, wherein: During testing of a first RAS precharge delay setting and a second RAS precharge delay setting, the first memory component and the second memory component are tested with the first RAS precharge delay setting and subsequently tested with the second RAS precharge delay setting without powering off the memory controller or BIOS, wherein the first RAS precharge delay setting and the second RAS precharge delay setting are different.

16. The method according to claim 12, wherein During testing the first memory component at the first frequency, write calibration, MPR mode writing, and read / write center alignment are performed, and during testing the second memory component at the first frequency, the write calibration, MPR mode writing, and read / write center alignment are skipped.

17. A motherboard assembly for testing memory components, comprising: At least one FPGA; at least one memory channel; at least one electrical connection communicatively coupling the CPU and the memory channel; The memory controller, or BIOS, is programmed to: (a) Skip write calibration, MPR mode write, read / write center alignment in the presence of a memory component failure and continue the current boot process using the preset values of the PHY registers from the previous successful boot process without powering down; as well as (b) provide adjustable hold time settings without requiring a restart or power outage; as well as (c) Provides adjustable speed settings without requiring a restart or power outage.

18. A method of using the motherboard assembly of claim 17, comprising: connecting a first memory component to a first memory channel, wherein the first memory channel is communicatively coupled to a first FPGA; During the first test and the second test, without powering off the memory controller or BIOS, testing the first memory component at a first frequency defined by a first .cvs file in the first test and then testing the first memory component at a second frequency defined by a second .cvs file in the second test; and The first frequency differs from the second frequency by at least 100 Hz.

19. The method according to claim 18, wherein At least one other test parameter other than frequency is different during the first test and the second test, wherein the at least one other test parameter is defined in the first .cvs file and the second .cvs file as one or more of: Minperiod, tCKE, tFAW, tMRD, tRAS, tRCD, tREFI, tRP, tRRD, tRTP, tWR, tWTR, tXPR, tZYCS, tZQINIT, CAS latency, and CAS write latency.

20. A motherboard assembly for memory component testing, comprising: a frame sized to receive the upper and lower main panels; at least one memory channel, the at least one memory channel being disposed on the upper mainboard; a gap vertically separating the upper main board from the lower main board; at least one CPU or FPGA, wherein the at least one CPU or FPGA is disposed on the lower mainboard; at least one electronic connector communicatively coupling the at least one CPU or FPGA to the at least one memory channel; as well as The memory controller, or BIOS, is programmed to: (a) Skip write calibration, MPR mode write, read / write center alignment in the presence of a memory component failure and continue the current boot process using the preset values of the PHY registers from the previous successful boot process without powering down; as well as (b) provide adjustable hold time settings without requiring a restart or power outage; as well as (c) Provides adjustable speed settings without requiring a restart or power outage.

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