Digital primary and secondary fused pole-mounted circuit breaker and traveling wave distance measurement method

Abstract

The application discloses a kind of digital primary-secondary fusion pole-mounted circuit breaker and its travelling wave ranging time method. The circuit breaker includes feeder terminal and transformer digitizing unit, the feeder terminal is connected with satellite synchronous clock, and the feeder terminal and transformer digitizing unit are connected by cable to realize the uplink communication connection from the feeder terminal to the transformer digitizing unit. In the application, the feeder terminal periodically and uniformly sends data frame to the transformer digitizing unit based on second pulse signal, the transformer digitizing unit obtains time stamp synchronized with second pulse signal based on the received data frame, and obtains travelling wave data with time stamp, thereby improving the accuracy of ranging.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of power grid fault detection, and particularly relates to a digital primary and secondary fusion pole circuit breaker and a traveling wave distance measurement and time synchronization method of the digital primary and secondary fusion pole circuit breaker. BACKGROUND

[0002] Traveling wave distance measurement is a technology for fault positioning by using the propagation characteristics of traveling wave signals generated when a fault occurs. Double-end distance measurement is one of common traveling wave distance measurement methods, and the principle is to install traveling wave collection devices at both ends of a transmission line to record the arrival time of fault traveling waves respectively. Since the propagation speed of traveling wave signals on the transmission line is constant, the fault distance can be calculated by using the time difference and the traveling wave propagation speed. The accuracy of double-end distance measurement depends on the time synchronization accuracy of the traveling wave collection devices at both ends, and therefore time synchronization is one of the key technologies for double-end distance measurement.

[0003] At present, digital primary and secondary fusion pole circuit breakers are widely used in distribution networks, and have the ability of traveling wave collection and can be used for double-end distance measurement. The digital primary and secondary fusion pole circuit breaker usually includes an instrument transformer digitalization unit (ADMU) and a feeder terminal unit (FTU). The instrument transformer digitalization unit is connected with an electronic instrument transformer, is responsible for converting power frequency signals and traveling wave signals into digital signals, and transmits the collected power frequency data and traveling wave data downward to the feeder terminal unit through a cable (usually about 10 meters). The feeder terminal unit is connected with a satellite synchronous clock and can obtain high-precision second pulse signals, which can be used for time synchronization. However, since the instrument transformer digitalization unit is designed in a pluggable form to support live replacement, it cannot directly obtain the satellite synchronous clock signal through a coaxial cable. Therefore, in actual work, the instrument transformer digitalization unit can only rely on its internal clock to mark the time stamp of the collected traveling wave data, and then transmit the data downward to the feeder terminal unit. The feeder terminal unit then uploads the traveling wave data with the time stamp to the master station through GPRS communication for fault judgment. Since the internal clock of the instrument transformer digitalization unit is not synchronized with the satellite synchronous clock, the two sets of traveling wave data received by the master station are not based on the unified satellite synchronous clock reference, so that the time difference cannot be accurately calculated, and finally the accuracy and reliability of double-end distance measurement are affected. SUMMARY

[0004] The application provides a digital primary and secondary fusion pole circuit breaker and a traveling wave distance measurement and time synchronization method thereof, and has the advantages that the problem that the traveling wave data obtained by the pole circuit breaker cannot be synchronized with the satellite synchronous clock to cause inaccurate distance measurement is solved.

[0005] The technical scheme of the application is as follows.

[0006] A digital primary and secondary integrated pole-mounted circuit breaker includes a feeder terminal and a current transformer digitization unit. The feeder terminal and the current transformer digitization unit are connected by a cable to establish a downlink communication connection from the current transformer digitization unit to the feeder terminal. The feeder terminal is connected to a satellite synchronization clock, which is used to provide a second pulse signal.

[0007] The feeder terminal and the instrument transformer digital unit are also connected by a cable for uplink communication from the feeder terminal to the instrument transformer digital unit.

[0008] The feeder terminal periodically and uniformly sends data frames to the current transformer digitization unit based on the second pulse signal. The current transformer digitization unit obtains the timestamp synchronized with the second pulse signal based on the received data frames and obtains traveling wave data with the timestamp.

[0009] As a further improvement to the aforementioned digital primary and secondary integrated pole-mounted circuit breaker: the feeder terminal includes a frame protocol encoder and a frame timing logic control module;

[0010] The frame protocol encoder is used to encode and transmit uplink communication data;

[0011] The frame timing logic control module is used to control the frame protocol encoder to encode based on the second pulse signal and trigger the transmission of each data frame.

[0012] As a further improvement to the aforementioned digital primary and secondary fusion pole-mounted circuit breaker, the feeder terminal also includes a crystal oscillator error elimination module, which obtains correction data D3 based on the second pulse signal and sends the correction data D3 to the frame timing logic control module to adjust the frame timing and eliminate the error caused by the internal crystal oscillator of the feeder terminal.

[0013] As a further improvement to the aforementioned digital primary and secondary fusion pole-mounted circuit breaker, the feeder terminal also includes an encoding phase adjustment module, which is used to adjust the encoding period to achieve phase synchronization between the encoding period and the second pulse signal.

[0014] As a further improvement to the aforementioned digital primary and secondary integrated pole-mounted circuit breaker, it also includes a second pulse synthesis circuit and a timekeeping module;

[0015] The satellite synchronization clock sends the raw second pulse signal (PPS) to the second pulse synthesis circuit and the timekeeping module;

[0016] The timing module performs statistics on the original second pulse signal PPS, obtains the second shift signal PPS_B based on the statistics, and sends the second shift signal PPS_B to the second pulse synthesis circuit.

[0017] The second pulse synthesis circuit obtains the second pulse signal PPS1 based on the original second pulse signal PPS and the second shift signal PPS_B. When the original second pulse signal PPS is valid, the second pulse signal PPS1 is synchronized with the original second pulse signal PPS; otherwise, the second pulse signal PPS1 is synchronized with the second shift signal PPS_B.

[0018] The second pulse signal PPS1 serves as the reference for encoding and transmission by the feeder terminal.

[0019] This invention also discloses a traveling wave ranging and time synchronization method for a digital primary and secondary integrated pole-mounted circuit breaker. Specifically, in the feeder terminal of the digital primary and secondary integrated pole-mounted circuit breaker:

[0020] The frame timing logic control module performs an inter-frame crystal oscillator cycle countdown. After each crystal oscillator cycle, the count value is decremented by 1. When the count value of the inter-frame crystal oscillator cycle countdown becomes 0, control signal S3 is sent to the frame counter and control signal S4 is sent to the frame protocol encoder. The initial value of the inter-frame crystal oscillator cycle countdown is reset, and the next countdown begins. The frame timing logic control module also controls the initial value of the inter-frame crystal oscillator cycle countdown based on the received second pulse signal PPS1.

[0021] The frame counter counts the data frames between adjacent second pulse signals, starting from 0. Each time a control signal S3 is received, the count value is incremented by 1, and the current frame count D4 is sent to the frame protocol encoder. The maximum frame count is N. f -1, reset to 0 after reaching the maximum value, N f The preset number of data frames between adjacent second pulse signals;

[0022] The frame protocol encoder completes the encoding of the data frame according to the frame count D4, and triggers the transmission of the data frame according to the control signal S4.

[0023] As a further improvement to the traveling wave ranging and timing method of the aforementioned digital primary and secondary fusion pole-mounted circuit breaker: the frame counter also sends frame count D4 to the frame timing logic control module;

[0024] When the frame timing logic control module receives the second pulse signal PPS1, it adjusts the initial value of the inter-frame crystal oscillator period countdown based on the current frame count and the count value of the inter-frame crystal oscillator period countdown, thereby changing the data frame transmission rhythm so that the transmission time of the 0th frame is close to the arrival time of the second pulse signal PPS1, ensuring that the frame timing is synchronized with the second pulse signal PPS1.

[0025] As a further improvement to the traveling wave ranging and time synchronization method of the aforementioned digital primary and secondary fusion pole-mounted circuit breaker: a crystal oscillator error elimination module is also provided in the feeder terminal;

[0026] The crystal oscillator error elimination module receives the second pulse signal PPS1 and counts the number of local clock crystal oscillator cycles between adjacent second pulse signals PPS1 to obtain the statistical value of the number of crystal oscillator cycles per second. Then, it calculates the number of crystal oscillator error cycles a = the statistical value of the number of crystal oscillator cycles per second - the theoretical value of the number of crystal oscillator cycles per second, and sends the number of crystal oscillator error cycles a as correction data D3 to the frame timing logic control module. The theoretical value of the number of crystal oscillator cycles per second refers to the number of crystal oscillator cycles corresponding to 1 second calculated based on the theoretical value of the local crystal oscillator cycle of the feeder terminal.

[0027] The frame timing logic control module adjusts the initial value of the inter-frame crystal oscillator period countdown based on the number of crystal oscillator error cycles 'a': select 'a' data frames from other data frames besides frame 0 to adjust the initial value of the inter-frame crystal oscillator period countdown; if 'a' is greater than zero, the initial value of the inter-frame crystal oscillator period countdown corresponding to each selected data frame is increased by 1 based on the original initial value, otherwise it is decreased by 1.

[0028] As a further improvement to the traveling wave ranging and time synchronization method of the aforementioned digital primary and secondary fusion pole-mounted circuit breaker: the frame protocol encoder is also equipped with an encoding phase adjustment module;

[0029] After receiving the second pulse signal PPS1, the encoding phase adjustment module waits for a fixed period of time before controlling the frame protocol encoder to send the 0th frame. At the same time, within this fixed period of time, the encoding phase adjustment module adjusts the encoding period according to the phase relationship between the encoding period and the second pulse signal, thereby completing the phase synchronization between the encoding period and the second pulse signal without changing the number of encoding periods within this fixed period of time.

[0030] In the frame protocol encoder, when the control signal S4 is received, it is determined whether the current frame count is 0. If it is 0, the current 0th frame is sent again at the end of the fixed duration. Otherwise, the current data frame is sent directly under the trigger of the control signal S4.

[0031] As a further improvement to the traveling wave ranging and time synchronization method of the aforementioned digital primary and secondary fusion pole-mounted circuit breaker, the encoding phase adjustment module adjusts the encoding period within a fixed duration in the following manner:

[0032] Define the fixed waiting time as M crystal oscillator cycles, which correspond to P encoding cycles. After the second pulse signal PPS1 arrives, obtain the number of crystal oscillator cycles N between the falling edge of the second pulse signal PPS1 and the next rising edge of the encoding pulse. Then, select PN encoding cycles from the P-1 encoding cycles from the rising edge to the end of the fixed waiting time, and increment the number of crystal oscillator cycles corresponding to each selected encoding cycle by 1.

[0033] Compared with the prior art, the present invention has the following advantages:

[0034] 1. This invention establishes an uplink communication connection between the feeder terminal unit (FTU) and the digital transformer unit (ADMU). The feeder terminal periodically and uniformly sends data frames to the digital transformer unit based on the second pulse signal of the satellite synchronous clock, so that the digital transformer unit obtains a precise timestamp synchronized with the second pulse signal and adds the timestamp to the traveling wave data, thereby improving the accuracy of ranging.

[0035] 2. In the feeder terminal, the present invention performs timekeeping based on the second pulse of the satellite synchronization clock and synthesizes the second pulse signal PPS1. When the satellite synchronization clock signal is lost, the timekeeping module can be used to ensure the normal transmission of data frames and avoid communication interruption.

[0036] 3. This invention eliminates the influence of accumulated crystal oscillator error by statistically analyzing the actual number of crystal oscillator cycles between adjacent second pulse signals, calculating the difference between the statistical value and the theoretical value, and selecting some data frames to adjust the initial value of the inter-frame crystal oscillator cycle countdown. This enables the feeder terminal to accurately complete the transmission of a specified number of data frames between two second pulse signals.

[0037] 4. When the frame timing and the second pulse signal are out of sync, the present invention can dynamically adjust the initial value of the inter-frame crystal oscillator period countdown, adaptively change the transmission rhythm of the data frame, and realize the synchronization between the frame timing and the second pulse signal.

[0038] 5. When the transmission of frame 0 is triggered based on the second pulse signal, this invention employs a method of waiting for a fixed duration to delay the transmission of frame 0. During this fixed waiting period, the encoding period is adjusted according to the phase difference between the encoding period and the second pulse signal. This ensures that the phase of the encoding period is determined at the end of the waiting period without changing the number of encoding periods within that fixed duration, thus achieving phase synchronization between the encoding period and the second pulse signal. This method not only solves the problem of frame loss caused by phase difference but also, because it requires both ends to delay for an equal fixed duration, avoids ranging errors introduced by the delay. Attached Figure Description

[0039] Figure 1 A schematic diagram of the architecture of a digital primary and secondary integrated pole-mounted circuit breaker;

[0040] Figure 2 This describes the correspondence between the second pulse, the encoded pulse, and the clock crystal pulse when the second pulse signal arrives.

[0041] Figure 3 This is a schematic diagram of the downlink data encoding structure. Detailed Implementation

[0042] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0043] Example 1

[0044] This embodiment discloses a digital primary and secondary integrated pole-mounted circuit breaker and its traveling wave ranging and time synchronization method.

[0045] like Figure 1 The digital primary and secondary integrated pole-mounted circuit breaker in this embodiment includes a feeder terminal and a digital transformer unit.

[0046] The feeder terminal is connected to a satellite synchronization clock, which provides a second pulse signal.

[0047] Downlink communication between the feeder terminal and the instrument transformer digitization unit is achieved via a cable, with the cable connecting the feeder terminal to the feeder terminal. Uplink communication between the feeder terminal and the instrument transformer digitization unit is also achieved via a cable, with the cable connecting the feeder terminal to the instrument transformer digitization unit.

[0048] The feeder terminal periodically and uniformly transmits data frames to the current transformer digitization unit based on the second pulse signal. The current transformer digitization unit obtains a timestamp synchronized with the second pulse signal based on the received data frames, and transmits the timestamped traveling wave data to the feeder terminal through the downlink communication connection.

[0049] For the digital primary and secondary integrated circuit breakers in the State Grid's standardized materials, only the digital unit of the instrument transformer with traveling wave fault location function needs to be directly replaced; other hardware remains unchanged. This is because the original digital solution standardization document had 2 reserved wires in the 10-core cable, which can be used to achieve uplink communication from the feeder terminal to the digital unit of the instrument transformer.

[0050] The uplink communication adopts a serial communication method, and the link layer adopts (but is not limited to) the FT3 format and uses Manchester encoding (or other encoding methods).

[0051] The feeder terminal includes a second pulse synthesis circuit and a timing module. Upon receiving the second pulse signal, the feeder terminal first performs filtering and debouncing to prevent multiple triggers within one second. The resulting raw second pulse signal PPS is sent to the second pulse synthesis circuit and the timing module. The timing module performs statistical analysis on the raw second pulse signal PPS, and based on the statistics, obtains a second shift signal PPS_B, which is then sent to the second pulse synthesis circuit. The second pulse synthesis circuit obtains a second pulse signal PPS1 based on the raw second pulse signal PPS and the second shift signal PPS_B: when the raw second pulse signal PPS is valid, the second pulse signal PPS1 is synchronized with the raw second pulse signal PPS; otherwise, the second pulse signal PPS1 is synchronized with the second shift signal PPS_B. This mechanism ensures that the second pulse signal PPS1 can still be transmitted even if the raw second pulse signal PPS is lost, providing a time reference for encoding and transmission by the feeder terminal.

[0052] Furthermore, the feeder terminal includes a frame protocol encoder and a frame timing logic control module. The frame protocol encoder is used to encode and transmit uplink communication data. The frame timing logic control module is used to control the frame protocol encoder to encode data and trigger the transmission of each data frame based on a second pulse signal.

[0053] Specifically, the frame timing logic control module performs an inter-frame crystal oscillator cycle countdown. After each crystal oscillator cycle, the count value is decremented by 1. When the count value of the inter-frame crystal oscillator cycle countdown becomes 0, control signal S3 is sent to the frame counter, control signal S4 is sent to the frame protocol encoder, and the initial value of the inter-frame crystal oscillator cycle countdown is reset to start the next countdown.

[0054] The default initial value for the inter-frame crystal oscillator period countdown is the theoretical value of the inter-frame crystal oscillator period count, cyclecnt_0. The theoretical value of the inter-frame crystal oscillator period count refers to the number of crystal oscillator periods corresponding to the time interval between adjacent data frames, i.e., cyclecnt_0 = T / N. f T is the theoretical value of the number of crystal oscillator cycles per second, and N is... f This represents the preset number of data frames between adjacent second pulse signals. In this embodiment, the FTU's local crystal oscillator frequency is 160MHz, so the crystal oscillator period is 6.25ns, and the theoretical value of the number of crystal oscillator periods per second is T = 1.6 * 10^8. The number of data frames N between every two second pulses is... f =8000, therefore the theoretical value of the inter-frame crystal oscillator cycle count is cyclecnt_0 = 2 * 10^4, which means the theoretical interval between two data frames is 20,000 crystal oscillator cycles, with a duration of 125us. The initial value of the inter-frame crystal oscillator cycle countdown is adjustable, and the initial value corresponding to each frame can be adjusted independently.

[0055] The frame counter counts data frames between adjacent second pulse signals, starting from 0. Each time control signal S3 is received, the count value is incremented by 1, and the current frame count D4 is sent to the frame protocol encoder. The maximum frame count is N. f -1, reset to 0 after reaching the maximum value.

[0056] The frame protocol encoder encodes the data frame according to frame count D4, and simultaneously obtains a checksum D2 from the checksum generator, adding it to the data frame. The transmission of the data frame is then triggered according to control signal S4. The serially transmitted data frame constitutes... Figure 1 Signal S1 in the middle.

[0057] Furthermore, when the satellite synchronization clock is first connected, or when the satellite synchronization clock signal is restored after being lost, the frame count may not be synchronized with the second pulse signal of the satellite synchronization clock, meaning that the Nth frame may not have been sent exactly at the current time. f -1 data frame. If forced synchronization is attempted, frame loss will occur. To address this issue, the frame timing logic control module in this embodiment also controls the initial value of the inter-frame crystal oscillator period countdown based on the received second pulse signal PPS1, thereby changing the data frame transmission rhythm and ensuring that the frame timing is always synchronized with the second pulse signal PPS1.

[0058] Specifically, the frame counter also sends the frame count D4 to the frame timing logic control module. Upon receiving the second pulse signal PPS1, the frame timing logic control module reads the current frame count SmpCnt (i.e., D4) and the count value cyclecnt of the inter-frame crystal oscillator period countdown, and then performs the following processing:

[0059] (1) If the current frame count SmpCnt equals N f If the count value is -1 and the count value cyclecnt is less than the first threshold, then it is determined that the frame timing and the second pulse signal PPS1 have been synchronized.

[0060] In this embodiment, the first threshold is 8000.

[0061] (2) If the current frame count SmpCnt equals N f If the count value cyclecnt is greater than or equal to the first threshold and less than the second threshold, then the initial value of the countdown of all inter-frame crystal oscillator periods is adjusted to last_init-1, where last_init is the initial value of the countdown of inter-frame crystal oscillator periods before adjustment.

[0062] In this embodiment, the second threshold is 16000.

[0063] (3) If the current frame count SmpCnt equals N fIf the count value is -1 and the count value cyclecnt is greater than or equal to the second threshold, then the initial value of the countdown of all inter-frame crystal oscillator periods is adjusted to last_init - cyclecnt / N. f .

[0064] (4) If the current frame count SmpCnt is not equal to N f When the value is -1, the initial value of the inter-frame crystal oscillator period countdown is adjusted in different ways according to the numerical range of the frame count SmpCnt:

[0065] In this embodiment, N f =8000, the theoretical value of the inter-frame crystal oscillator cycle number is cyclecnt_0=20000, then the division of the numerical range and the corresponding adjustment method are as follows:

[0066] (4.1) If SmpCnt is greater than or equal to 1 and less than 2400, then the initial value of the countdown of all inter-frame crystal oscillator periods is adjusted to last_init+SmpCnt*20000 / 8000.

[0067] (4.2) If SmpCnt is greater than or equal to 2400 and less than 4000, then the initial value of the countdown of all inter-frame crystal oscillator periods is adjusted to last_init+6000.

[0068] (4.3) If SmpCnt is greater than or equal to 4000 and less than 5600, then adjust the initial value of the countdown of all inter-frame crystal oscillator periods to last_init-6000.

[0069] (4.4) If SmpCnt is greater than or equal to 5600 and less than 7998, then the initial value of the countdown of all inter-frame crystal oscillator periods is adjusted to last_init-SmpCnt*20000 / 8000.

[0070] (4.5) If SmpCnt equals 0 and cyclecnt is less than or equal to 12000, then adjust the initial value of the countdown of all inter-frame crystal oscillator cycles to last_init+(19999-cyclecnt) / 8000.

[0071] (4.6) If SmpCnt equals 0 and cyclecnt is greater than 12000 and less than or equal to 18000, then the initial value of the countdown of all inter-frame crystal oscillator periods is adjusted to last_init+1.

[0072] (4.7) If SmpCnt equals 0 and cyclecnt is greater than 18000, then only the last data frame (the Nth) is processed. fThe initial value of the inter-frame crystal oscillator cycle countdown (-1 frame) is adjusted to 19999-cyclecnt.

[0073] By using the above adjustment method, the initial value of the inter-frame crystal oscillator period countdown can be dynamically adjusted when the frame timing and the second pulse signal PPS1 are out of sync. Although the initial value of the inter-frame crystal oscillator period countdown will fluctuate during this process, the transmission rhythm of the data frames will also change accordingly. Ultimately, through the adaptive capability of the adjustment algorithm, the initial value of the inter-frame crystal oscillator period countdown will gradually approach and equal the theoretical value of the inter-frame crystal oscillator period count, and keep the frame timing synchronized with the second pulse signal.

[0074] Furthermore, feeder terminals typically use ordinary temperature-compensated crystal oscillators (TCCs). Unlike expensive temperature-controlled crystal oscillators and other complex clock circuits, TCCs have a certain clock error. This causes the N-times interval between two second pulse signals to not be accurately completed when the data frame is triggered by counting down according to the inter-frame crystal period. f Each data frame is transmitted. Therefore, it is necessary to correct for errors caused by the crystal oscillator.

[0075] The correction method is as follows: The feeder terminal is also equipped with a crystal oscillator error elimination module, which obtains correction data D3 based on the second pulse signal and sends the correction data D3 to the frame timing logic control module to adjust the frame timing and eliminate the error caused by the internal crystal oscillator of the feeder terminal.

[0076] The specific process is as follows:

[0077] The crystal oscillator error elimination module receives the second pulse signal PPS1 and counts the number of local clock crystal oscillator cycles between adjacent second pulse signals PPS1, obtaining a statistical value of the number of crystal oscillator cycles per second. Then, it calculates the number of crystal oscillator error cycles a = statistical value of the number of crystal oscillator cycles per second - theoretical value of the number of crystal oscillator cycles per second, and sends the number of crystal oscillator error cycles a as correction data D3 to the frame timing logic control module. The theoretical value of the number of crystal oscillator cycles per second refers to the number of crystal oscillator cycles corresponding to 1 second, calculated based on the theoretical value of the local crystal oscillator cycle of the feeder terminal.

[0078] The frame timing logic control module adjusts the initial value of the inter-frame crystal oscillator period countdown based on the number of crystal oscillator error cycles 'a': select 'a' data frames from other data frames besides frame 0 to adjust the initial value of the inter-frame crystal oscillator period countdown; if 'a' is greater than zero, the initial value of the inter-frame crystal oscillator period countdown corresponding to each selected data frame is increased by 1 based on the original initial value, otherwise it is decreased by 1.

[0079] In this embodiment, the method for selecting the a data frames is as follows: calculate N f / a is rounded down to get b, and then N is taken outside the 0th frame between second pulse signals. f-1 data frames are selected to make adjustments, specifically the 1*bth, 2*bth, ..., a*bth data frames.

[0080] It should be noted that, through theoretical calculations and derivations, it has been found that the number of crystal oscillator error cycles, 'a', is always less than N. f Because if a=N f =8000, then the deviation between the crystal oscillator and the second pulse is 8000 * 6.25 ns = 50 μS, which is much larger than the error range of the crystal oscillator.

[0081] The above correction method enables dynamic adjustment of the initial value of the inter-frame crystal oscillator period countdown, allowing the feeder terminal to accurately complete N between two second pulse signals. f Sending one data frame.

[0082] Furthermore, the arrival time of the second pulse has a certain degree of randomness, while the encoding period of the data frame corresponds to multiple crystal oscillator cycles of the feeder terminal. In this embodiment, the encoding rate is 10MHz and the encoding period is 100ns, corresponding to 16 crystal oscillator cycles of 6.25ns each. For ease of description, the number of crystal oscillator cycles corresponding to one encoding period is set as Z. Therefore, there are Z phase relationships between the second pulse signal PPS1 and the encoding period, with a maximum phase difference of Z-1 crystal oscillator cycles. In the case of synchronization, since the arrival of the second pulse needs to immediately trigger the frame protocol encoder to send the 0th frame, an excessively large phase difference means that the previous encoding period has not yet ended. Forcing an end will lead to an increased frame loss rate and may even cause decoding errors in subsequent stages. If the 0th frame is sent after the current encoding period ends, a random error will occur between the second pulse and the 0th frame, resulting in the subsequent digitization unit being unable to obtain a synchronized clock signal.

[0083] Therefore, the feeder terminal in this embodiment also includes an encoding phase adjustment module, which is used to adjust the encoding period to achieve phase synchronization between the encoding period and the second pulse signal.

[0084] After receiving the second pulse signal PPS1, the encoding phase adjustment module waits for a fixed duration before controlling the frame protocol encoder to send frame 0. Simultaneously, within this fixed duration, the encoding phase adjustment module adjusts the encoding period based on the phase relationship between the encoding period and the second pulse signal, thereby achieving phase synchronization between the encoding period and the second pulse signal without changing the number of encoding periods within this fixed duration.

[0085] like Figure 2The fixed waiting time is defined as M crystal oscillator cycles, corresponding to P coding cycles. Since the end of the data frame is an idle bit, all coding cycles corresponding to the second pulse signal are rising edges. After the second pulse signal arrives, the number of crystal oscillator cycles N between the falling edge of the second pulse signal and the next rising edge of the coding pulse is obtained, with one coding cycle corresponding to one coding pulse. Then, PN coding cycles are selected from the P-1 coding cycles from the rising edge to the end of the fixed waiting time, and the number of crystal oscillator cycles corresponding to each selected coding cycle is incremented by 1.

[0086] In this embodiment, the fixed waiting time is 1600ns, so M=256. This fixed waiting time corresponds to 16 encoding cycles (encoding pulses), and one encoding cycle of 100ns corresponds to 16 crystal oscillator cycles. After the second pulse signal arrives, the number of crystal oscillator cycles N between the falling edge of the second pulse signal and the next rising edge of the encoding pulse is obtained. Then, among the 15 encoding cycles from the rising edge to the end of the fixed waiting time (that is, 1600ns after the falling edge of the second pulse signal), the first 15-N encoding cycles are selected, and the number of crystal oscillator cycles corresponding to each selected encoding cycle is incremented by 1. After adjustment, the duration between the falling edge of the second pulse signal and the rising edge of the first subsequent encoding pulse is N*6.25ns. The duration occupied by the subsequent 15 encoding cycles is 15*16*6.25ns + (15-N)*6.25ns. Therefore, regardless of the value of N, the total fixed duration is necessarily 16*16*6.25ns = 1600ns. That is, the frame protocol encoder shifts the encoding pulse by adding N crystal oscillator cycles, thereby compensating for the phase difference of N crystal oscillator cycles between the second pulse and the encoding cycle. This adjusts the phase of the encoding cycle and achieves phase synchronization between the second pulse signal and the encoding cycle, ensuring that the 0th frame and the second pulse signal are strictly synchronized each time, so that the serial data sequence S1 contains synchronization clock information.

[0087] Correspondingly, in the frame protocol encoder, when the control signal S4 is received, it determines whether the current frame count is 0. If it is 0, the current 0th frame is sent again at the end of the fixed duration; otherwise, the current data frame is sent directly under the trigger of the control signal S4.

[0088] It should be noted that since both devices in the dual-end ranging system will have equal fixed delays, this delay will not introduce ranging errors. Furthermore, when the current transformer's digitization unit adds a timestamp, it will compensate for the 0th frame according to this preset fixed duration, ensuring that the timestamp is synchronized with the arrival time of the second pulse signal.

[0089] In addition, the communication data processor can also add the data D1 sent from the maintenance interface to the uplink communication data to perform upgrade and maintenance operations.

[0090] like Figure 1 After receiving signal S1, the current transformer digitization unit decodes signal S1 to obtain synchronization signal S10, which is then sent to the programmable logic device, frame protocol encoder, and frame protocol decoding simulator. If the frame protocol decoding simulator does not receive synchronization signal S10 within a certain time, it automatically generates pseudo-synchronization signal S20 and sends it to the frame decoding circuit, thereby forcibly triggering the generation of synchronization signal S10 and preventing disruption to the normal operation of the current transformer digitization unit.

[0091] The current and voltage signals acquired by the current and voltage transformers are simultaneously sent to the analog-to-digital converter (ADC). The ADC sends the converted current and voltage digital signals (D5) to the frame protocol encoder, while the status acquisition circuit sends the acquired status data (D7) to the frame protocol encoder. Simultaneously, the frame protocol encoder obtains the power frequency voltage data (D13) from the current and voltage digital signals (D5) and sends it to the programmable logic device (PLC).

[0092] The current and voltage signals collected by the current and voltage transformers are simultaneously sent to a high-speed analog-to-digital converter (ADC). The ADC converts the current and voltage signals into high-speed digital signals D11 and sends them to a programmable logic device (PLD). The PLD generates data D10 based on the high-speed digital signals D11 and the power frequency voltage data D13, and sends it to a microprocessor. The PLD also generates a second pulse signal PPS4 based on the synchronization signal S10 and sends it to the microprocessor of the transformer digitization unit (or PPS3 generated by a frame protocol decoder).

[0093] The microprocessor of the current transformer digitization unit uses a grounding algorithm based on data D10 to determine whether a grounding fault has occurred. This algorithm is existing technology and will not be described in detail here. If a grounding fault occurs, the fault occurrence timestamp D21 is obtained based on the second pulse signal PPS4 and sent to the programmable logic device.

[0094] The programmable logic device extracts the high-speed current and voltage data corresponding to the fault occurrence timestamp D21 from the high-speed data cache, then encapsulates the timestamp and the corresponding high-speed current and voltage data into data D6, and sends data D6 to the frame protocol encoder.

[0095] When the programmable logic device is working, it interacts with the high-speed data buffer by sending and receiving data D14 to improve the processing speed.

[0096] The frame protocol encoder uses the current and voltage digital signals D5 as power frequency data, and D6 as traveling wave data, along with the status data D7, to send to the feeder terminal in the downlink communication data signal S2.

[0097] like Figure 3 In this embodiment, based on FT3 format encoding, the traveling wave data is placed after the power frequency data in the form of extended frames, and the frame format of the traveling wave data is the same as that of the power frequency data. Based on relevant specifications and data length calculations, it can be seen that, with 20 spare bits reserved, four more sets of effective data can be added to the original four sets of power frequency data for transmitting traveling wave data, and the transmission rate is significantly improved compared to using other protocols.

[0098] The microprocessor of the instrument transformer digitization unit can also send the relevant fault judgment data D20 to the master station through the communication module of the instrument transformer digitization unit.

[0099] After receiving signal S2, the feeder terminal obtains power frequency data D5, traveling wave data D6, status data D7, and synchronization signal PPS2 from it, and then sends them to the feeder terminal's microprocessor. The feeder terminal's microprocessor encapsulates the relevant data into data D8 and sends it to the master station through the feeder terminal's communication module.

[0100] Meanwhile, during maintenance operations, the microprocessor of the feeder terminal can also encapsulate the relevant maintenance data into data D30 and send it to the maintenance interface through the communication data processor.

[0101] Example 2

[0102] The difference between this embodiment and Embodiment 1 is that, after receiving the second pulse signal PPS1, the frame timing logic controller calculates the time difference between the second pulse and the current frame header, and corrects the time difference within the next second to ensure that the feeder terminal is sending an idle bit when the second pulse arrives in the next second. At this time, the feeder terminal can directly send the 0th frame to achieve synchronization with the current transformer digitization unit. This method can also achieve synchronization between the second pulse signal and the 0th frame, but there will be a frame loss problem. To solve this problem, a flag bit needs to be added to the synchronized 0th frame, so as to notify the current transformer digitization unit that the frame count change at this position is a normal phenomenon.

[0103] Example 3

[0104] The difference between this embodiment and Embodiment 1 is that the feeder terminal does not have a crystal oscillator error elimination module, and it does not correct for errors generated by the crystal oscillator. The current transformer digitization unit obtains the second pulse signal through the 0th frame of signal S1, and then, based on the same crystal oscillator error elimination principle as in Embodiment 1, eliminates the error generated by its local clock to obtain a more accurate synchronization signal, and uses this to determine the timestamp.

[0105] Other implementation methods

[0106] After receiving signal S1, the current transformer digitization unit can obtain the corresponding synchronization signal based on each data frame, and thus obtain a timestamp synchronized with the second pulse signal PPS1 based on the synchronization signal. Obviously, the use of this timestamp is not limited to the above embodiment. Those skilled in the art can also use other methods to make the synchronization signal participate in fault judgment and downlink data transmission to ensure that the relevant data is accompanied by synchronized time information.

[0107] It should be noted that, for those skilled in the art, the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The scope of the present invention is defined by the claims rather than the foregoing description.

Claims

1. A digital primary and secondary integrated pole-mounted circuit breaker, comprising a feeder terminal and a current transformer digitization unit, wherein a downlink communication connection from the current transformer digitization unit to the feeder terminal is realized via a cable, characterized in that: The feeder terminal is connected to a satellite synchronization clock, which provides a second pulse signal; The feeder terminal and the instrument transformer digital unit are also connected by a cable for uplink communication from the feeder terminal to the instrument transformer digital unit. The feeder terminal periodically and uniformly sends data frames to the current transformer digitization unit based on the second pulse signal. The current transformer digitization unit obtains the timestamp synchronized with the second pulse signal based on the received data frames and obtains traveling wave data with the timestamp.

2. The digital primary and secondary integrated pole-mounted circuit breaker as described in claim 1, characterized in that: The feeder terminal includes a frame protocol encoder and a frame timing logic control module; The frame protocol encoder is used to encode and transmit uplink communication data; The frame timing logic control module is used to control the frame protocol encoder to encode based on the second pulse signal and trigger the transmission of each data frame.

3. The digital primary and secondary integrated pole-mounted circuit breaker as described in claim 2, characterized in that: The feeder terminal also includes a crystal oscillator error elimination module, which obtains correction data D3 based on the second pulse signal and sends the correction data D3 to the frame timing logic control module to adjust the frame timing and eliminate the error caused by the internal crystal oscillator of the feeder terminal.

4. The digital primary and secondary integrated pole-mounted circuit breaker as described in claim 2, characterized in that: The feeder terminal also includes an encoding phase adjustment module, which is used to adjust the encoding period to achieve phase synchronization between the encoding period and the second pulse signal.

5. The digital primary and secondary integrated pole-mounted circuit breaker as described in claim 2, characterized in that: It also includes a second pulse synthesis circuit and a timekeeping module; The satellite synchronization clock sends the raw second pulse signal (PPS) to the second pulse synthesis circuit and the timekeeping module; The timing module performs statistics on the original second pulse signal PPS, obtains the second shift signal PPS_B based on the statistics, and sends the second shift signal PPS_B to the second pulse synthesis circuit. The second pulse synthesis circuit obtains the second pulse signal PPS1 based on the original second pulse signal PPS and the second shift signal PPS_B. When the original second pulse signal PPS is valid, the second pulse signal PPS1 is synchronized with the original second pulse signal PPS; otherwise, the second pulse signal PPS1 is synchronized with the second shift signal PPS_B. The second pulse signal PPS1 serves as the reference for encoding and transmission by the feeder terminal.

6. A traveling wave ranging and time synchronization method for a digital primary and secondary integrated pole-mounted circuit breaker, characterized in that, In the feeder terminal of the digital primary and secondary integrated pole-mounted circuit breaker as described in claim 1: The frame timing logic control module performs an inter-frame crystal oscillator cycle countdown. After each crystal oscillator cycle, the count value is decremented by 1. When the count value of the inter-frame crystal oscillator cycle countdown becomes 0, control signal S3 is sent to the frame counter and control signal S4 is sent to the frame protocol encoder. The initial value of the inter-frame crystal oscillator cycle countdown is reset, and the next countdown begins. The frame timing logic control module also controls the initial value of the inter-frame crystal oscillator cycle countdown based on the received second pulse signal PPS1. The frame counter counts the data frames between adjacent second pulse signals, starting from 0. Each time a control signal S3 is received, the count value is incremented by 1, and the current frame count D4 is sent to the frame protocol encoder. The maximum frame count is N. f -1, reset to 0 after reaching the maximum value, N f The preset number of data frames between adjacent second pulse signals; The frame protocol encoder completes the encoding of the data frame according to the frame count D4, and triggers the transmission of the data frame according to the control signal S4.

7. The traveling wave ranging and time synchronization method based on the digital primary and secondary fusion pole-mounted circuit breaker as described in claim 6, characterized in that: The frame counter also sends frame count D4 to the frame timing logic control module; When the frame timing logic control module receives the second pulse signal PPS1, it adjusts the initial value of the inter-frame crystal oscillator period countdown based on the current frame count and the count value of the inter-frame crystal oscillator period countdown, thereby changing the data frame transmission rhythm so that the transmission time of the 0th frame is close to the arrival time of the second pulse signal PPS1, ensuring that the frame timing is synchronized with the second pulse signal PPS1.

8. The traveling wave ranging and time synchronization method based on the digital primary and secondary fusion pole-mounted circuit breaker as described in claim 6, characterized in that: The feeder terminal is also equipped with a crystal oscillator error elimination module; The crystal oscillator error elimination module receives the second pulse signal PPS1 and counts the number of local clock crystal oscillator cycles between adjacent second pulse signals PPS1 to obtain the statistical value of the number of crystal oscillator cycles per second. Then, it calculates the number of crystal oscillator error cycles a = the statistical value of the number of crystal oscillator cycles per second - the theoretical value of the number of crystal oscillator cycles per second, and sends the number of crystal oscillator error cycles a as correction data D3 to the frame timing logic control module. The theoretical value of the number of crystal oscillator cycles per second refers to the number of crystal oscillator cycles corresponding to 1 second calculated based on the theoretical value of the local crystal oscillator cycle of the feeder terminal. The frame timing logic control module adjusts the initial value of the inter-frame crystal oscillator period countdown based on the number of crystal oscillator error cycles 'a': select 'a' data frames from other data frames besides frame 0 to adjust the initial value of the inter-frame crystal oscillator period countdown. If a is greater than zero, the initial value of the inter-frame crystal oscillator period countdown corresponding to each selected data frame is increased by 1 based on the original initial value; otherwise, it is decreased by 1.

9. The traveling wave ranging and time synchronization method based on the digital primary and secondary fusion pole-mounted circuit breaker as described in claim 6, characterized in that: The frame protocol encoder also includes an encoding phase adjustment module; After receiving the second pulse signal PPS1, the encoding phase adjustment module waits for a fixed period of time before controlling the frame protocol encoder to send the 0th frame. At the same time, within this fixed period of time, the encoding phase adjustment module adjusts the encoding period according to the phase relationship between the encoding period and the second pulse signal, thereby completing the phase synchronization between the encoding period and the second pulse signal without changing the number of encoding periods within this fixed period of time. In the frame protocol encoder, when the control signal S4 is received, it is determined whether the current frame count is 0. If it is 0, the current 0th frame is sent again at the end of the fixed duration. Otherwise, the current data frame is sent directly under the trigger of the control signal S4.

10. The traveling wave ranging and time synchronization method based on the digital primary and secondary fusion pole-mounted circuit breaker as described in claim 9, characterized in that, The encoding phase adjustment module adjusts the encoding period within a fixed time interval as follows: Define the fixed waiting time as M crystal oscillator cycles, which correspond to P encoding cycles. After the second pulse signal PPS1 arrives, obtain the number of crystal oscillator cycles N between the falling edge of the second pulse signal PPS1 and the next rising edge of the encoding pulse. Then, select PN encoding cycles from the P-1 encoding cycles from the rising edge to the end of the fixed waiting time, and increment the number of crystal oscillator cycles corresponding to each selected encoding cycle by 1.

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