Semiconductor device

Abstract

A semiconductor device includes a substrate, an outer detection line, and an inner detection line. The substrate has a peripheral side. The outer side detection line is arranged on the substrate and is close to the peripheral side surface. The inner side detection line is arranged on the substrate, is close to the peripheral side surface and is isolated from the outer side detection line; the outer side detection line is closer to the peripheral side surface than the inner side detection line.

Description

Technical field

[0001] The present invention relates to a device, and more particularly, to a semiconductor device. [Background Technology]

[0002] Traditional semiconductor devices can develop cracks due to factors such as temperature and external forces. If a crack continues to grow, it will damage at least one component of the semiconductor device (conductive traces, conductive vias, circuits, active chips, passive components, layer structures, molding compounds, etc.). Therefore, detecting cracks in semiconductor devices has become a prominent task in the industry. [Summary of the invention]

[0003] In one embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a substrate, an outer detection line, and an inner detection line. The substrate has a peripheral side surface. The outer detection line is disposed on the substrate and adjacent to the peripheral side surface. The inner detection line is disposed on the substrate, adjacent to the peripheral side surface, and isolated from the outer detection line. The outer detection line is closer to the peripheral side surface than the inner detection line.

[0004] The numerous objects, features and advantages of the present invention will become clear when reading the following detailed description of the embodiments of the present invention and taking into account the accompanying drawings. However, the drawings used herein are for illustration purposes only and should not be considered as limiting.

Brief Description of the Drawings

[0005] The above objects and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings, in which:

[0006] Figure 1A A schematic top view of a semiconductor device according to an embodiment of the present invention is shown;

[0007] Figure 1B Shows the direction along 1B-1B' Figure 1A A cross-sectional view of the semiconductor device 100 in FIG.

[0008] Figure 1C Shows the direction along 1C-1C' Figure 1A A cross-sectional view of a semiconductor device in FIG.

[0009] Figure 2A A schematic top view of a semiconductor device according to another embodiment of the present invention is shown;

[0010] Figure 2B Shows the direction along 2B-2B' Figure 2A A cross-sectional view of a semiconductor device in FIG.

[0011] Figure 2CShows the direction along 2C-2C' Figure 2A A cross-sectional view of a semiconductor device in FIG.

[0012] Figure 3 A schematic top view of a semiconductor device according to another embodiment of the present invention is shown;

[0013] Figure 4 A schematic top view of a semiconductor device according to another embodiment of the present invention is shown; and

[0014] Figure 5 A schematic top view of a semiconductor device according to another embodiment of the present invention is shown. [Specific implementation method]

[0015] refer to Figures 1A to 1B , Figure 1A 1 is a top view diagram of a semiconductor device 100 according to an embodiment of the present invention. Figure 1B shows a cross-sectional view of the semiconductor device 100 along the 1B-1B' direction, Figure 1C The cross-sectional view of the semiconductor device 100 along the line 1C-1C′ is shown. The semiconductor device 100 is, for example, a semiconductor chip, a semiconductor module, a semiconductor package, etc.

[0016] like Figures 1A to 1C As shown, semiconductor device 100 includes a substrate 110, an outer test line 120, an inner test line 130, a first pad 140A, a second pad 140B, a third pad 150A, a fourth pad 150B, a first outer connecting line 160A, a second outer connecting line 160B, a first inner connecting line 170A, and a second inner connecting line 170B. Substrate 110 has a peripheral side surface 110s. Outer test line 120 is disposed on substrate 110 and adjacent to peripheral side surface 110s. Inner test line 130 is disposed on substrate 110 and adjacent to peripheral side surface 110s, isolated from outer test line 120. Outer test line 120 is closer to peripheral side surface 110s than inner test line 130. Therefore, if a crack (if any) occurs in semiconductor device 100, it can be detected by outer test line 120 and / or inner test line 130. Because cracks can be detected early, users can address the crack issue as quickly as possible.

[0017] like Figure 1AAs shown, the peripheral side surface 110s has four sub-peripheral side surfaces, for example, a first sub-peripheral side surface 110s1, a second sub-peripheral side surface 110s2, a third sub-peripheral side surface 110s3, and a fourth sub-peripheral side surface 110s4. The first sub-peripheral side surface 110s1, the second sub-peripheral side surface 110s2, the third sub-peripheral side surface 110s3, and the fourth sub-peripheral side surface 110s4 define the entire outer boundary of the substrate 110 or the semiconductor device 100. The outer detection line 120 and the inner detection line 130 extend along the four sub-peripheral side surfaces 110s1 to 110s4.

[0018] like Figure 1A As shown, first pad 140A is disposed on and exposed from substrate 110. First outer connection line 160A connects first pad 140A to first end 121 of outer detection line 120. Second pad 140B is disposed on and exposed from substrate 110. Second outer connection line 160B connects second pad 140B to second end 122 of outer detection line 120. First outer connection line 160A and / or second outer connection line 160B may include the same or similar features as outer detection line 120.

[0019] like Figure 1A As shown, third pad 150A is disposed on and exposed from substrate 110. First inner connecting line 170A connects third pad 150A to first end 131 of inner detection line 130. Fourth pad 150B is disposed on and exposed from substrate 110. Second inner connecting line 170B connects fourth pad 150B to second end 132 of inner detection line 130. First inner connecting line 170A and / or second inner connecting line 170B may include the same or similar features as inner detection line 130.

[0020] A detector (not shown) may detect first pad 140A and second pad 140B. If a crack disconnects outer detection line 120, the detector and outer detection line 120 cannot form a circuit loop, and thus the crack may be detected by the detector. Similarly, the detector may detect third pad 150A and fourth pad 150B. If a crack disconnects inner detection line 130, the detector and inner detection line 130 cannot form a circuit loop, and thus the crack may be detected by the detector.

[0021] Furthermore, if a crack occurs in semiconductor device 100, the crack may damage outer detection line 120, causing it to break. The broken outer detection line 120 may be detected by a probe that detects first pad 140A and second pad 140B. Similarly, if a crack occurs in semiconductor device 100, the crack may damage inner detection line 130, causing it to break. The broken inner detection line 130 may be detected by a probe that detects third pad 150A and fourth pad 150B.

[0022] like Figure 1B As shown, substrate 110 includes a base 111 and a plurality of dielectric layers 112 disposed on and stacked on base 111. Base 111 is, for example, a portion of a silicon wafer. Outer detection lines 120 include a plurality of outer conductive traces 123 and a plurality of conductive vias 124. Each outer conductive trace 123 is disposed on a corresponding dielectric layer 112, and one conductive via 124 connects two adjacent outer conductive traces 123.

[0023] like Figure 1B As shown, in one embodiment, the outer detection line 120 may extend in a wavy manner. In addition, the outer detection line 120 may include at least one outer rising section 120A' and at least one outer descending section 120D, wherein adjacent outer rising sections 120A' and outer descending sections 120D are connected to each other. Each outer rising section 120A' rises on a first extension path that is substantially parallel to the peripheral side surface 110s (e.g., the first sub-peripheral side surface 110s1, the second sub-peripheral side surface 110s2, the third sub-peripheral side surface 110s3, and the fourth sub-peripheral side surface 110s4), and each outer descending section 120D descends on the first extension path that is substantially parallel to the peripheral side surface 110s.

[0024] like Figure 1B As shown, the two adjacent segments that are directly connected are the outer rising segment 120A' and the outer descending segment 120D. Furthermore, in the adjacent outer descending segment 120D and the outer rising segment 120A', the outer descending segment 120D is connected to the outer rising segment 120A' at the bottom layer of the dielectric layer 112. In the adjacent outer rising segment 120A' and the outer descending segment 120D', the outer rising segment 120A' is connected to the outer descending segment 120D' at the top layer of the dielectric layer 112.

[0025] like Figure 1B As shown, each outer rising section 120A' can pass through all dielectric layers 112, and each outer descending section 120D can also pass through all dielectric layers 112. Therefore, any crack occurring in any dielectric layer 112 can be detected.

[0026] like Figure 1C As shown, the inner detection line 130 includes a plurality of inner conductive traces 133 and a plurality of conductive through-holes 134 . Each inner conductive trace 133 is disposed on a corresponding dielectric layer 112 , and one conductive through-hole 134 connects two adjacent inner conductive traces 133 .

[0027] like Figure 1CAs shown, in one embodiment, the inner detection line 130 may extend in a wavy manner. Furthermore, the inner detection line 130 may include at least one inner ascending section 130A and at least one inner descending section 130D, wherein adjacent inner ascending sections 130A and outer inner descending sections 130D are connected to each other. Each inner ascending section 130A ascends along a first extension path that is substantially parallel to the outer side surface 110s, and each inner descending section 130D descends along the first extension path that is substantially parallel to the outer side surface 110s.

[0028] like Figure 1C As shown, the two adjacent segments that are directly connected are the inner rising segment 130A and the inner descending segment 130D. Furthermore, in the case of adjacent inner descending segments 130D′ and inner rising segment 130A, the inner descending segment 130D′ is connected to the inner rising segment 130A at the topmost layer of the dielectric layer 112. In the case of adjacent inner rising segment 130A′ and inner descending segment 130D′, the inner rising segment 130A′ is connected to the inner descending segment 130D′ at the bottommost layer of the dielectric layer 112.

[0029] like Figure 1C As shown, each inner rising section 130A can pass through all dielectric layers 112, and each inner descending section 130D can also pass through all dielectric layers 112. Therefore, cracks occurring in any dielectric layer 112 can be detected.

[0030] like Figure 1B and 1C As shown, the rising section of the outer detection line corresponds to the falling section of the inner detection line. In addition, in the same area from the reference line L1 to the reference line L2, the outer rising section 120A' corresponds to the inner falling section 130D', and the outer falling section 120D' corresponds to the inner rising section 130A'. Therefore, although Figure 1B The lower dielectric layer 112 (or referred to as the “blank area BA”) lacks the segments of the outer detection lines 120, but Figure 1C The inner descending section 130D and the inner ascending section 130A in the embodiment can supplement the blank area BA because Figure 1C The inner descending section 130D and the inner ascending section 130A in the Figure 1B Corresponding to the blank area BA in .

[0031] In another embodiment, the rising section of the outer detection line 120 may correspond to the rising section of the inner detection line 130. In other embodiments, the rising section of the outer detection line 120 may correspond to a portion of the rising section and a portion of the falling section of the inner detection line 130.

[0032] refer to Figures 2A to 2C , Figure 2AFIG. 2 shows a top view schematic diagram of a semiconductor device 200 according to another embodiment of the present invention. Figure 2B Shown Figure 2A A cross-sectional view of the semiconductor device 200 along the direction 2B-2B', Figure 2C Shown Figure 2A FIG. 2 is a cross-sectional view of the semiconductor device 200 along the 2C-2C′ direction.

[0033] like Figures 2A to 2C As shown, the semiconductor device 200 includes a substrate 110, an outer detection line 220, an inner detection line 230, a first pad 140A, a second pad 140B, a third pad 150A, a fourth pad 150B, a first outer connecting line 160A, a second outer connecting line 160B, a first inner connecting line 170A and a second inner connecting line 170B.

[0034] like Figure 2B and 2C As shown, outer test lines 220 are disposed on substrate 110 and adjacent to outer side surface 110s. Inner test lines 230 are disposed on substrate 110 and adjacent to outer side surface 110s, and are isolated from outer test lines 220. Outer test lines 220 are closer to outer side surface 110s than inner test lines 230. Therefore, cracks (if any) occurring in semiconductor device 200 can be detected via outer test lines 220 and / or inner test lines 230.

[0035] like Figure 2A As shown, a first solder pad 140A is disposed on and exposed from the substrate 110. A first outer connecting line 160A connects the first solder pad 140A to a first end 221 of an outer detection line 220. A second solder pad 140B is disposed on and exposed from the substrate 110. A second solder pad 140B is disposed on and exposed from the substrate 110. A second outer connecting line 160B connects the second solder pad 140B to a second end 222 of an outer detection line 220. The first outer connecting line 160A and / or the second outer connecting line 160B may include the same or similar features as the outer detection line 220.

[0036] like Figure 2A As shown, third pad 150A is disposed on and exposed from substrate 110. First inner connecting line 170A connects third pad 150A to first end 231 of inner detection line 230. Fourth pad 150B is disposed on and exposed from substrate 110. Second inner connecting line 170B connects fourth pad 150B to second end 232 of inner detection line 230. First inner connecting line 170A and / or second inner connecting line 170B may include the same or similar features as inner detection line 230.

[0037] A detector (not shown) can detect first pad 140A and second pad 140B. If a crack disconnects outer detection line 220, the detector and outer detection line 220 cannot form a circuit loop, so the crack can be detected by the detector. Similarly, the detector can detect third pad 150A and fourth pad 150B. If a crack disconnects inner detection line 230, the detector and inner detection line 230 cannot form a circuit loop, so the crack can be detected by the detector.

[0038] Furthermore, if a crack occurs in the semiconductor device 200, the crack may damage the outer detection line 220, causing the outer detection line 220 to break. The broken outer detection line 220 can be detected by a detector (not shown) that detects the first and second pads 140A and 140B. Similarly, if a crack occurs in the semiconductor device 200, the crack may damage the inner detection line 230, causing the inner detection line 230 to break. The broken inner detection line 230 can be detected by a detector that detects the third and fourth pads 150A and 150B.

[0039] like Figure 2B As shown, the substrate 110 includes a base 111 and a plurality of dielectric layers ( 112 ′ and 112 ″) disposed on the base 111 and stacked on each other.

[0040] Semiconductor device 200 includes features that are the same as or similar to semiconductor device 100, with at least one difference being that outer test lines 220 and / or inner test lines 230 do not pass through all dielectric layers. Instead, outer test lines 220 and inner test lines 230 pass through all dielectric layers. For example, outer test lines 220 may pass through upper dielectric layer 112', while inner test lines 230 may pass through lower dielectric layer 112".

[0041] like Figure 2B As shown, in one embodiment, the outer detection line 220 may extend in a wavy manner. Furthermore, the outer detection line 220 may include at least one outer ascending segment 220A and at least one outer descending segment 220D, wherein adjacent outer ascending segments 220A and outer descending segments 220D are connected to each other. Each outer ascending segment 220A' ascends along a first extension path that is substantially parallel to the outer side surface 110s, and each outer descending segment 220D descends along a first extension path that is substantially parallel to the outer side surface 110s.

[0042] like Figure 2BAs shown, the two adjacent segments that are directly connected are the outer rising segment 220A and the outer descending segment 220D. Furthermore, among the adjacent outer rising segment 220A and the outer descending segment 220D', the outer rising segment 220A is connected to the outer descending segment 220D' at the topmost layer of the upper dielectric layer 112'. Among the adjacent outer descending segment 220D' and the outer rising segment 220A', the outer descending segment 220D' is connected to the outer rising segment 220A' at the bottommost layer of the upper dielectric layer 112'.

[0043] like Figure 2C As shown, in one embodiment, the inner detection line 230 may extend in a wavy manner. Furthermore, the inner detection line 230 may include at least one inner ascending segment 230A and at least one inner descending segment 230D, wherein adjacent inner ascending segments 230A and inner descending segments 230D are connected to each other. Each inner ascending segment 230A ascends along a first extension path that is substantially parallel to the outer side surface 110s, and each inner descending segment 230D descends along the first extension path that is substantially parallel to the outer side surface 110s.

[0044] like Figure 2C As shown, the two adjacent segments that are directly connected are the inner rising segment 230A and the inner descending segment 230D. In addition, in the adjacent inner rising segment 230A and the inner descending segment 230D', the inner rising segment 230A is connected to the inner descending segment 230D' at the top layer of the lower dielectric layer 112". In the adjacent inner descending segment 230D' and the inner rising segment 230A', the inner descending segment 230D' and the inner rising segment 230A' are connected to the bottom layer of the lower dielectric layer 112".

[0045] like Figure 2B and 2C As shown, the rising section of the outer detection line corresponds to the rising section of the inner detection line. Furthermore, within the same region from reference line L1 to reference line L2, the outer descending section 220D' corresponds to the inner descending section 230D', and the outer ascending section 220A' corresponds to the inner ascending section 230A'. In another embodiment, within the same region from reference line L1 to reference line L2, the outer descending section 220D' corresponds to the inner ascending section 230A', and the outer ascending section 220A' corresponds to the inner descending section 230D'.

[0046] refer to Figure 3 , Figure 3According to another embodiment of the present invention, a top view schematic diagram of a semiconductor device 300 is shown. The semiconductor device 300 includes a substrate 110, a first inspection group DS31, a second inspection group DS32, a first pad 140A, a second pad 140B, a third pad 150A, and a fourth pad 150B. The first inspection group DS31 and the second inspection group DS32 each include an outer inspection line 320 and an inner inspection line 330. The outer inspection line 320 may include features that are the same as or similar to those of the outer inspection line 120 or the outer inspection line 220. The inner inspection line 330 may include features that are the same as or similar to those of the outer inspection line 130 or the inner inspection line 230.

[0047] like Figure 3 As shown, the first detection group DS31 includes outer detection lines 320, inner detection lines 330, a first inner connecting line 370A, a second inner connecting line 370B, a first inner-outer connecting line 335A, and a second inner-outer connecting line 335B. The inner detection lines 330 include a first sub-inner detection line 330A and a second sub-inner detection line 330B. The first inner connecting line 370A connects the first solder pad 140A to the first end 331 of the first sub-inner detection line 330A of the inner detection lines 330. The second inner connecting line 370B connects the second solder pad 140B to the second end 332 of the second sub-inner detection line 330B of the inner detection lines 330. The first inner-outer connecting line 335A connects the outer detection lines 320 to the first sub-inner detection line 330A of the inner detection lines 330. The second inner-outer connection line 335B connects the outer detection line 320 with the second sub-inner detection line 330B of the inner detection line 330 .

[0048] In this embodiment, the first inner connecting line 370A, the second inner connecting line 370B, and / or the second inner-outer connecting line 335B may include the same or similar features as the inner detection line 130 or the inner detection line 230. The first inner-outer connecting line 335A may include the same or similar features as the detection line (the outer detection line or the inner detection line).

[0049] like Figure 3As shown, in the first inspection group DS31, the outer inspection line 320 is adjacent to the first peripheral side surface 110s1, the second peripheral side surface 110s2, and the fourth peripheral side surface 110s4, the first sub-inner inspection line 330A is adjacent to the first peripheral side surface 110s1 and the second peripheral side surface 110s2, and the second sub-inner inspection line 330B is adjacent to the first peripheral side surface 110s1 and the fourth peripheral side surface 110s4. In the first inspection group DS31, the outer inspection line 320, the first sub-inner inspection line 330A, and the second sub-inner inspection line 330B may extend along a first extension path that is substantially parallel to the first peripheral side surface 110s1, the second peripheral side surface 110s2, and the fourth peripheral side surface 110s4. In the first inspection group DS31, the first inner-outer connecting line 335A may extend along a second extension path that is substantially perpendicular to the second peripheral side surface 110s2, and the second inner-outer connecting line 335B may extend along a fourth extension path that is substantially perpendicular to the fourth peripheral side surface 110s4.

[0050] like Figure 3 As shown, the second inspection group DS32 includes outer inspection lines 320, inner inspection lines 330, a first inner connecting line 370A, a second inner connecting line 370B, a first inner-outer connecting line 335A, and a second inner-outer connecting line 335B. The inner inspection lines 330 include a first sub-inner inspection line 330A and a second sub-inner inspection line 330B. The first inner connecting line 370A connects the third solder pad 150A to the first end 331 of the first sub-inner inspection line 330A of the inner inspection lines 330. The second inner connecting line 370B connects the fourth solder pad 150B to the second end 332 of the second sub-inner inspection line 330B of the inner inspection lines 330. The first inner-outer connecting line 335A connects the outer inspection lines 320 to the first sub-inner inspection line 330A of the inner inspection lines 330. The second inner-outer connecting line 335B connects the outer inspection lines 320 to the second sub-inner inspection line 330B of the inner inspection lines 330.

[0051] like Figure 3As shown, in the second inspection group DS32, the outer inspection line 320 is adjacent to the second peripheral side surface 110s2, the third peripheral side surface 110s3, and the fourth peripheral side surface 110s4, the first sub-inner inspection line 330A is adjacent to the second peripheral side surface 110s2 and the third peripheral side surface 110s3, and the second sub-inner inspection line 330B is adjacent to the third peripheral side surface 110s3 and the fourth peripheral side surface 110s4. In the second inspection group DS32, the outer inspection line 320, the first sub-inner inspection line 330A, and the second sub-inner inspection line 330B may extend along the second peripheral side surface 110s2, the third peripheral side surface 110s3, and the fourth peripheral side surface 110s4. In the second inspection group DS32, the first inner-outer connecting line 335A may extend along a second extension path that is substantially perpendicular to the second peripheral side surface 110s2, and the second inner-outer connecting line 335B may extend along a fourth extension path that is substantially perpendicular to the fourth peripheral side surface 110s4.

[0052] A detector (not shown) may detect the first pad 140A and the second pad 140B. If a crack disconnects the outer detection line 320 and / or the inner detection line 330 in the first detection group DS31, the detector and the first detection group DS31 cannot form a circuit loop, and thus the detector may detect the crack. Similarly, the detector may detect the third pad 150A and the fourth pad 150B. If a crack disconnects the inner detection line 330 and / or the inner detection line 330 in the second detection group DS32, the detector and the second detection group DS32 cannot form a circuit loop, and thus the detector may detect the crack.

[0053] refer to Figure 4 , Figure 4 FIG4 is a schematic top view of a semiconductor device 400 according to another embodiment of the present invention. The semiconductor device 400 includes a substrate 110, a first detection group DS41, a second detection group DS42, a third detection group DS43, a fourth detection group DS44, and a switch 490. The first detection group DS41, the second detection group DS42, the third detection group DS43, and the fourth detection group DS44 each include an outer detection line 420 and an inner detection line 430. The outer detection line 420 may include features that are the same as or similar to those of the outer detection line 120 or the outer detection line 220. The inner detection line 430 may include features that are the same as or similar to those of the outer detection line 130 or the outer detection line 230.

[0054] In this embodiment, at least one first detection group DS41, second detection group DS42, third detection group DS43, fourth detection group DS44, and switch 490 may be formed within (or completely embedded in) substrate 110, for example, substrate 111 (not shown) and / or dielectric layer 112 (not shown) of substrate 110. In other words, at least one first detection group DS41, second detection group DS42, third detection group DS43, fourth detection group DS44, and switch 490 are not exposed from semiconductor device 100.

[0055] like Figure 4 As shown, the first detection group DS41 includes an outer detection line 420, an inner detection line 430, a first outer connecting line 460A, a first inner connecting line 470A, and a first inner-outer connecting line 435A. The first outer connecting line 460A connects the switch 490 to the first end 421 of the outer detection line 420. The first inner connecting line 470A connects the switch unit 491 of the switch 490 to the second end 431 of the inner detection line 430. The first inner-outer connecting line 435A connects the outer detection line 420 with the inner detection line 430.

[0056] like Figure 4 As shown, in the first detection group DS41, the outer detection lines 420 are adjacent to the first peripheral side surface 110s1 and the second peripheral side surface 110s2, and the inner detection lines 430 are adjacent to the first peripheral side surface 110s1 and the second peripheral side surface 110s2. In the first detection group DS41, the outer detection lines 420 and the inner detection lines 430 may extend along a first extension path that is substantially parallel to the first peripheral side surface 110s1 and the second peripheral side surface 110s2. In the first detection group DS41, the first inner-outer connecting line 435A may extend along a second extension path that is substantially perpendicular to the second peripheral side surface 110s2.

[0057] like Figure 4 As shown, the second detection group DS42 includes an outer detection line 420, an inner detection line 430, a first outer connection line 460A, a first inner connection line 470A, and a first inner-outer connection line 435A. The first outer connection line 460A connects the switch 490 to the first end 421 of the outer detection line 420. The first inner connection line 470A connects the switch unit 492 of the switch 490 to the second end 431 of the inner detection line 430. The first inner-outer connection line 435A connects the outer detection line 420 with the inner detection line 430.

[0058] like Figure 4As shown, in the second detection group DS42, the outer detection line 420 is adjacent to the second peripheral side surface 110s2 and the third peripheral side surface 110s3, and the inner detection line 430 is adjacent to the second peripheral side surface 110s2 and the third peripheral side surface 110s3. In the second detection group DS42, the outer detection line 420 and the inner detection line 430 may extend along a first extension path that is substantially parallel to the second peripheral side surface 110s2 and the third peripheral side surface 110s3. In the second detection group DS42, the first inner-outer connection line 435A may extend along a second extension path that is substantially perpendicular to the second peripheral side surface 110s2.

[0059] like Figure 4 As shown, the third detection group DS43 includes an outer detection line 420, an inner detection line 430, a first outer connection line 460A, a first inner connection line 470A, and a first inner-outer connection line 435A. The first outer connection line 460A connects the switch 490 to the first end 421 of the outer detection line 420. The first inner connection line 470A connects the switch unit 493 of the switch 490 to the second end 431 of the inner detection line 430. The first inner-outer connection line 435A connects the outer detection line 420 with the inner detection line 430.

[0060] like Figure 4 As shown, in the third inspection group DS43, the outer inspection lines 420 are adjacent to the third peripheral side surface 110s3 and the fourth peripheral side surface 110s4, and the inner inspection lines 430 are adjacent to the third peripheral side surface 110s3 and the fourth peripheral side surface 110s4. In the third inspection group DS43, the outer inspection lines 420 and the inner inspection lines 430 may extend along a first extension path that is substantially parallel to the third peripheral side surface 110s3 and the fourth peripheral side surface 110s4. In the third inspection group DS43, the first inner-outer connecting line 435A may extend along a third extension path that is substantially perpendicular to the third peripheral side surface 110s3.

[0061] like Figure 4 As shown, the fourth detection group DS44 includes an outer detection line 420, an inner detection line 430, a first outer connecting line 460A, a first inner connecting line 470A, and a first inner-outer connecting line 435A. The first outer connecting line 460A connects the switch 490 to the first end 421 of the outer detection line 420. The first inner connecting line 470A connects the switch unit 494 of the switch 490 to the second end 431 of the inner detection line 430. The first inner-outer connecting line 435A connects the outer detection line 420 with the inner detection line 430.

[0062] like Figure 4As shown, in the fourth inspection group DS44, the outer inspection lines 420 are adjacent to the first peripheral side surface 110s1 and the fourth peripheral side surface 110s4, and the inner inspection lines 430 are adjacent to the first peripheral side surface 110s1 and the fourth peripheral side surface 110s4. In the fourth inspection group DS44, the outer inspection lines 420 and the inner inspection lines 430 may extend along a first extension path that is substantially parallel to the first peripheral side surface 110s1 and the fourth peripheral side surface 110s4. In the fourth inspection group DS44, the first inner-outer connecting line 435A may extend along a fourth extension path that is substantially perpendicular to the fourth peripheral side surface 110s4.

[0063] The switch 490 may be disposed on or on the substrate 110. In some embodiments, the switch 490 may be part of a circuit substrate (not shown), such as a printed circuit board or the like. The circuit substrate is electrically connected to the semiconductor device 400. The switch 490 may control one of the switch units 491, 492, 493, and 494 to open to detect whether the corresponding detection line is broken.

[0064] refer to Figure 5 , Figure 5 A schematic top view of a semiconductor device 500 according to another embodiment of the present invention is shown. Semiconductor device 500 includes a substrate 110, outer test lines 520, a first test group DS51, a second test group DS52, a third test group DS53, a fourth test group DS54, and a switch 590. Each of the first test group DS51, the second test group DS52, the third test group DS53, and the fourth test group DS54 includes an inner test line 530. The inner test line 530 may include features that are the same as or similar to those of the outer test line 130 or the outer test line 230.

[0065] like Figure 5 As shown, the outer detection line 520 is adjacent to the first peripheral side 110s1, the second peripheral side 110s2, the third peripheral side 110s3, and the fourth peripheral side 110s4. The outer detection line 520 may extend along a first extension path that is substantially parallel to the first peripheral side 110s1, the second peripheral side 110s2, the third peripheral side 110s3, and the fourth peripheral side 110s4.

[0066] In this embodiment, at least one of the first detection group DS51, the second detection group DS52, the third detection group DS53, the fourth detection group DS54, and the switch 590 may be formed within (or completely embedded in) the substrate 110, for example, the substrate 111 (not shown) and / or the dielectric layer 112 (not shown). In other words, at least one of the first detection group DS51, the second detection group DS52, the third detection group DS53, the fourth detection group DS54, and the switch 590 is not exposed from the semiconductor device 500.

[0067] like Figure 5 As shown, the first detection group DS51 includes an inner detection line 530, a first inner connection line 570A, and a second inner connection line 570B. The first inner connection line 570A connects the switch 590 to the first end 531 of the inner detection line 530. The second inner connection line 570B connects the switch unit 591 of the switch 590 to the second end 532 of the inner detection line 530.

[0068] In this embodiment, the first inner connecting line 570A and / or the second inner connecting line 570B may include features that are the same as or similar to those of the inner detection line 130 or the inner detection line 230 .

[0069] like Figure 5 As shown, in the first detection group DS51, the inner detection line 530 extends adjacent to the first peripheral side surface 110s1 and the second peripheral side surface 110s2. In the first detection group DS51, the inner detection line 530 may extend along a first extension path that is substantially parallel to the first peripheral side surface 110s1 and the second peripheral side surface 110s2.

[0070] like Figure 5 As shown, the second detection group DS52 includes an inner detection line 530, a first inner connection line 570A, and a second inner connection line 570B. The first inner connection line 570A connects the switch 590 to the first end 531 of the inner detection line 530. The second inner connection line 570B connects the switch unit 592 of the switch 590 to the second end 532 of the inner detection line 530.

[0071] like Figure 5 As shown, in the second detection group DS52, the inner detection line 530 extends adjacent to the second peripheral side surface 110s2 and the third peripheral side surface 110s3. In the second detection group DS52, the inner detection line 530 may extend along a first extension path that is substantially parallel to the second peripheral side surface 110s2 and the third peripheral side surface 110s3.

[0072] like Figure 5 As shown, the third detection group DS53 includes an inner detection line 530, a first inner connection line 570A, and a second inner connection line 570B. The first inner connection line 570A connects the switch 590 to the first end 531 of the inner detection line 530. The second inner connection line 570B connects the switch unit 593 of the switch 590 to the second end 532 of the inner detection line 530.

[0073] like Figure 5As shown, in the third detection group DS53, the inner detection line 530 extends adjacent to the third peripheral side surface 110s3 and the fourth peripheral side surface 110s4. In the third detection group DS53, the inner detection line 530 may extend along a first extension path that is substantially parallel to the third peripheral side surface 110s3 and the fourth peripheral side surface 110s4.

[0074] like Figure 5 As shown, the fourth detection group DS54 includes an inner detection line 530, a first inner connection line 570A, and a second inner connection line 570B. The first inner connection line 570A connects the switch 590 to the first end 531 of the inner detection line 530. The second inner connection line 570B connects the switch unit 594 of the switch 590 to the second end 532 of the inner detection line 530.

[0075] like Figure 5 As shown, in the fourth detection group DS54, the inner detection line 530 extends adjacent to the first peripheral side surface 110s1 and the fourth peripheral side surface 110s4. In the fourth detection group DS54, the inner detection line 530 may extend along a first extension path substantially parallel to the first peripheral side surface 110s1 and the fourth peripheral side surface 110s4.

[0076] like Figure 5 In some embodiments shown, the semiconductor device 500 may further include a fifth detection group DS55, which includes an outer detection line 520, a first outer connection line 560A, and a second outer connection line 560B. The first outer connection line 560A connects the switch 590 to the first end 521 of the outer detection line 520. The second outer connection line 560B connects the switch unit 595 of the switch 590 to the second end 522 of the outer detection line 520.

[0077] The switch 590 may control one of the switch units 591 , 592 , 593 , 594 and 595 to be opened to detect whether the corresponding detection line is broken.

[0078] While the present invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it should be understood that the present invention is not necessarily limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which should be interpreted in the broadest possible manner to cover all such modifications and similar structures.

Claims

1. A semiconductor device comprising: a base having peripheral sides; an outer detection line disposed on the substrate and adjacent to the outer side surface; as well as an inner detection line disposed on the substrate, adjacent to the outer side surface, and isolated from the outer detection line; The outer detection line is closer to the outer side surface than the inner detection line.

2. The semiconductor device according to claim 1, wherein The outer detection line extends along a first extension path substantially parallel to the outer side surface.

3. The semiconductor device according to claim 1 , further comprising: a first pad disposed on and exposed from the substrate; a first outer connecting line connecting the first pad and the first end of the outer detection line; a second pad disposed on and exposed from the substrate; and A second outer connecting line is connected to the second pad and the second end of the outer detection line.

4. The semiconductor device according to claim 3, wherein The peripheral side surface has a first peripheral side surface, a second peripheral side surface, a third peripheral side surface opposite to the first peripheral side surface, and a fourth peripheral side surface opposite to the second peripheral side surface; the first outer connecting line and the second outer connecting line extend along a second extension path substantially perpendicular to the second peripheral side surface.

5. The semiconductor device according to claim 1 , further comprising: a third pad disposed on and exposed from the substrate; a first inner connecting line connecting the third pad and the first end of the inner detection line; a fourth pad disposed on and exposed from the substrate; and A second inner connecting line is connected to the fourth pad and the second end of the inner detection line.

6. The semiconductor device according to claim 1, wherein The substrate comprises: a plurality of dielectric layers stacked on top of each other; The outer detection line includes a plurality of conductive tracks and a plurality of conductive through-holes, each conductive track is arranged on a corresponding dielectric layer, and one conductive through-hole connects two adjacent conductive tracks.

7. The semiconductor device according to claim 1, wherein The outer detection line includes an outer ascending section and an outer descending section connected to the outer ascending section, and the inner detection line includes an inner ascending section and an inner descending section connected to the inner ascending section; The outer rising section corresponds to the inner descending section, and the outer descending section corresponds to the inner rising section.

8. The semiconductor device according to claim 1, wherein The outer detection line includes an outer ascending section and an outer descending section connected to the outer ascending section, and the inner detection line includes an inner ascending section and an inner descending section connected to the inner ascending section; The outer rising section corresponds to the inner rising section, and the outer descending section corresponds to the inner descending section.

9. The semiconductor device according to claim 1, further comprising: a first detection group and a second detection group, wherein each of the first detection group and the second detection group includes the outer detection line and the inner detection line; Wherein, the peripheral side surface has a first peripheral side surface, a second peripheral side surface, a third peripheral side surface opposite to the first peripheral side surface, and a fourth peripheral side surface opposite to the second peripheral side surface; the first detection group extends adjacent to the first peripheral side surface, the second peripheral side surface and the fourth peripheral side surface, and the second detection group extends adjacent to the second peripheral side surface, the third peripheral side surface and the fourth peripheral side surface.

10. The semiconductor device according to claim 9, wherein each of the first inspection group and the second inspection group comprises: the outer detection line; The inner detection line includes a first sub-inner detection line and a second sub-inner detection line; a first inner connecting line connecting a first end of the first sub-inner detection line and the inner detection line; a second inner connecting line connecting the second end of the second sub-inner detection line and the inner detection line; a first inner-outer connecting line connecting the outer detection line and the first sub-inner detection line; and A second inner-outer connecting line connects the outer detection line and the second sub-inner detection line.

11. The semiconductor device as claimed in claim 1, further comprising: a first detection group, a second detection group, a third detection group, and a fourth detection group, wherein each of the first detection group, the second detection group, the third detection group, and the fourth detection group includes an outer detection line and an inner detection line; The peripheral side surfaces include a first peripheral side surface, a second peripheral side surface, a third peripheral side surface opposite to the first peripheral side surface, and a fourth peripheral side surface opposite to the second peripheral side surface; the first detection group extends adjacent to the first peripheral side surface and the second peripheral side surface, the second detection group extends adjacent to the second peripheral side surface and the third peripheral side surface, the third detection group extends adjacent to the third peripheral side surface and the fourth peripheral side surface, and the fourth detection group extends adjacent to the fourth peripheral side surface and the first peripheral side surface.

12. The semiconductor device according to claim 11, further comprising: A switch is provided on the substrate and is electrically connected to the first detection group, the second detection group, the third detection group and the fourth detection group.

13. The semiconductor device as claimed in claim 11, wherein the first detection group, the second detection group, the third detection group and the fourth detection group are completely embedded in the substrate.

14. The semiconductor device according to claim 11, wherein each of the first test group, the second test group, the third test group, and the fourth test group comprises: External test line; Internal test line; a first external connection line connected to a first end of the external detection line; a first internal connecting line connected to the second end of the internal detection line; as well as A first internal-external connecting line connects the external detection line and the internal detection line.

15. The semiconductor device according to claim 12, wherein each of the first test group, the second test group, the third test group, and the fourth test group comprises: External test line; Internal test line; a first external connection line connecting the switch and a first end of the external detection line; a first internal connection line connecting the switch unit of the switch and the second end of the internal detection line; as well as A first internal-external connecting line connects the external detection line and the internal detection line.

16. The semiconductor device as claimed in claim 1, further comprising: an external detection line; as well as a first detection group, a second detection group, a third detection group, and a fourth detection group, wherein each of the first detection group, the second detection group, the third detection group, and the fourth detection group includes an internal detection line; The outer side surfaces include a first outer side surface, a second outer side surface, a third outer side surface opposite to the first outer side surface, and a fourth outer side surface opposite to the second outer side surface; the outer detection line extends adjacent to the first outer side surface, the second outer side surface, the third outer side surface, and the fourth outer side surface; The first detection group extends adjacent to the first and second peripheral sides, the second detection group extends adjacent to the second and third peripheral sides, the third detection group extends adjacent to the third and fourth peripheral sides, and the fourth detection group extends adjacent to the fourth and first peripheral sides.

17. The semiconductor device according to claim 16, further comprising: A switch is provided on the substrate and is electrically connected to the first detection group, the second detection group, the third detection group and the fourth detection group.

18. The semiconductor device as claimed in claim 16, wherein the first detection group, the second detection group, the third detection group and the fourth detection group are completely embedded in the substrate.

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