Grain crack detection system and semiconductor device

Abstract

The invention relates to a grain crack detection system and a semiconductor device. A grain crack detection system includes a semiconductor device. The device includes: a semiconductor body in or on which at least one component is integrated, and which includes a conductive region; an electrically insulating layer disposed on the conductive region; a first conductive trace disposed on the electrically insulating layer; a first contact electrically connected to the first conductive trace; and a second contact electrically connected to the conductive region. The system also includes a measurement unit. The first conductive trace, the electrically insulating layer, and the conductive region form a capacitor. The grain crack detection system is operable in a first mode in which the measurement unit is configured to output a first electrical signal to the first contact and / or the second contact and to determine whether at least one grain crack is present in the semiconductor body based on an I-V characteristic corresponding to the output first electrical signal.

Description

Technical Field

[0001] The present invention relates to a crystal grain crack detection system and a semiconductor device suitable for the crystal grain crack detection system. Background Art

[0002] Semiconductor products are typically produced using semiconductor wafers. Multiple identical components or circuits are implemented on these wafers. By dicing the semiconductor wafer, multiple substantially identical semiconductor dies are obtained, each containing a corresponding component or circuit.

[0003] Typically, multiple processing steps, including cutting, are required to produce semiconductor dies. These steps can damage the semiconductor dies. One example of such damage is the formation of cracks within the semiconductor dies. These cracks can cause undesirable electrical behavior in components or circuits formed on these dies.

[0004] Several solutions are known for detecting cracks in semiconductor dies. A first example (disclosed in US Pat. No. 10,241,151 B2) involves using metal traces separated by a thin dielectric layer. In the presence of a die crack, the dielectric layer will be damaged and the capacitance measured between the metal traces will show signs of leakage.

[0005] Detecting cracks can be performed at the semiconductor wafer level or at the semiconductor die level. Hereinafter, both semiconductor wafers and semiconductor dies are referred to as semiconductor bodies.

[0006] Some electrical components benefit from having a relatively thin semiconductor substrate. One example of such a component is a power amplifier, where substrate thickness is associated with parasitic inductance and / or thermal resistance.

[0007] Relatively thin semiconductor substrates are more susceptible to cracks. Furthermore, some of these cracks may be smaller in size compared to thicker substrates. Some of these cracks are referred to as microcracks and can range in width from 1 to 10 nanometers, in length from a few micrometers to 1000 micrometers, and in depth from a few micrometers to the full thickness of the grain.

[0008] Applicants have discovered that microcracks cannot be detected with sufficient accuracy and / or convenience using existing grain crack detection methods. Summary of the Invention

[0009] An object of the present invention is to provide a grain crack detection system capable of easily detecting microcracks.

[0010] According to the present invention, this object is achieved using a die crack detection system comprising a semiconductor device having a semiconductor body, in which at least one component is integrated or on which the semiconductor body comprises an electrically conductive region. The electrically conductive region can be formed during growth of the semiconductor body or can be formed using ion implantation.

[0011] The semiconductor device further includes: an electrically insulating layer disposed on the conductive region; a first conductive trace disposed on the electrically insulating layer; a first contact electrically connected to the first conductive trace; and a second contact electrically connected to the conductive region.

[0012] The die crack detection system further includes a measurement unit. The first conductive trace, the electrically insulating layer, and the conductive region form a capacitor. Furthermore, the die crack detection system is capable of operating in a first mode, wherein the measurement unit is configured to output a first electrical signal to the first contact and / or the second contact, and to determine whether at least one die crack is present in the semiconductor body based on an IV characteristic corresponding to the output first electrical signal.

[0013] According to the present invention, a capacitor is formed between the conductive region and the first conductive trace. Because the conductive region, which is part of the semiconductor body, serves as one of the plates / terminals of the capacitor, the capacitor is more sensitive to cracks in the semiconductor body and is therefore suitable for detecting microcracks in the semiconductor body.

[0014] The second contact may be configured to be electrically grounded when operating in the first mode. In this case, the first electrical signal may be a current passing through the first contact or a voltage applied to the first contact. In other embodiments, the first electrical signal is a differential signal. For example, the first electrical signal may include a voltage v1 applied to the first contact and a voltage -v1 applied to the second contact.

[0015] The first electrical signal may be a voltage signal, and the measurement unit may be configured to determine the presence of at least one grain crack when a current passing through the first contact and / or the second contact exceeds a first threshold. In the presence of a grain crack, the electrically insulating layer may be damaged, and a leakage path may be formed between the conductive region and the first conductive trace. It should be noted that the present invention is not limited to a single electrically insulating layer disposed between the conductive region and the first conductive region. Rather, multiple electrically insulating layers may be used, optionally separated by electrically floating plates.

[0016] The measurement unit can be configured to measure the current through the first contact and / or the second contact within a predetermined amount of time after applying the voltage signal to avoid or limit the measurement of the current associated with charging the capacitance formed between the first conductive trace and the conductive region. A leakage capacitor can be represented by a parallel connection of an ideal capacitor and a non-zero resistance. When the voltage signal is applied, a relatively large current will flow through the ideal capacitor. After a period of time, assuming that the voltage signal is a slowly varying signal or a step signal, the voltage across the ideal capacitor will be the same as the voltage signal. Measuring the current after the voltage across the capacitor stabilizes can provide more accurate information regarding the presence of a grain crack. More specifically, a relatively high current is associated with the presence of a grain crack, while a relatively low current is associated with the absence of a grain crack.

[0017] The at least one component may be a metal-oxide-semiconductor field effect transistor (MOSFET), a metal-insulator-semiconductor field effect transistor (MISFET), or a metal-insulator-metal capacitor. The semiconductor body may include a silicon substrate, and the at least one component may include a laterally diffused metal-oxide-semiconductor (LDMOS) field effect transistor.

[0018] The electrically insulating layer may be formed by an electrically insulating layer which is also arranged between the gate and the semiconductor body of a MOSFET or MISFET, or may be formed by the insulator of a metal-insulator-metal capacitor.

[0019] The thickness of the electrically insulating layer may be in the range of 2 nanometers to 200 nanometers. The electrically insulating layer may be made of silicon oxide, silicon dioxide, silicon nitride, or silicon oxynitride. Furthermore, the width of the first conductive trace may be in the range of 0.1 micrometer to 50 micrometers, more preferably in the range of 1 micrometer to 10 micrometers, and the first conductive trace may be made of polysilicon and / or metal.

[0020] The die crack detection system may further include a second conductive trace having a third contact and a fourth contact disposed at opposite ends of the second conductive trace. In this case, the die crack detection system may further operate in a second mode. The measurement unit may be configured to: output a second electrical signal to the third contact and / or the fourth contact when the die crack detection system operates in the second mode; and determine whether at least one die crack is present in the semiconductor body based on an IV characteristic corresponding to the output second electrical signal.

[0021] Similar to the first electrical signal, the fourth contact can be configured to be electrically grounded when operating in the second mode. In this case, the second electrical signal can be a current passing through the third contact or a voltage applied to the third contact. In other embodiments, the second electrical signal is a differential signal. For example, the second electrical signal can include a voltage v2 applied to the third contact and a voltage -v2 applied to the fourth contact.

[0022] The second electrical signal may be a voltage signal, and the measuring unit may be configured to determine the presence of at least one die crack when the current through the third contact and / or the fourth contact is below a second threshold when the die crack detection system operates in the second mode.

[0023] The measurement unit can be configured to measure the current through the third and / or fourth contacts within a predetermined amount of time after applying the voltage signal to avoid or limit measurement of the current associated with charging the capacitance formed between the second conductive trace and the conductive region. The second conductive trace can be represented by a ladder network including a shunt capacitor and a series resistor. The presence of a grain crack at the location of the second conductive trace will result in a very high series resistance. Consequently, a relatively high current is associated with the absence of a grain crack, while a relatively low current is associated with the presence of a grain crack.

[0024] The grain crack detection system can also operate in a third mode, wherein the measuring unit is configured to, when the grain crack detection system operates in the third mode: output a third electrical signal to the first contact and / or the second contact, and output a fourth electrical signal to the third contact and / or the fourth contact; and determine whether there is at least one grain crack in the semiconductor body based on the IV characteristics corresponding to the output third electrical signal and associated with the first contact and the second contact, and based on the IV characteristics corresponding to the output fourth electrical signal and associated with the third contact and the fourth contact.

[0025] The second conductive trace can form an elongated resistor, such as a thin film resistor, wherein the second conductive trace is preferably made of metal, such as one or more materials selected from Ti, TiN, and W. The sheet resistance of the second conductive trace can be in the range of 0.1 ohm / square to 50 ohm / square, more preferably between 1 ohm / square and 10 ohm / square, and even more preferably between 1 ohm / square and 5 ohm / square, and the width of the second conductive trace can be in the range of 0.1 micrometer to 50 micrometers, more preferably between 1 micrometer and 10 micrometers. The second conductive trace can be arranged directly above the first conductive trace. The lengths of the first and second traces are adapted to the configuration of the circuit.

[0026] The first contact may be arranged at one end of the first conductive trace. The first conductive trace may further include a fifth contact arranged at an opposite end of the first conductive trace. The first contact and the fifth contact may be configured to be contacted by a measurement probe or other electrical connector of the measurement unit.

[0027] The shape of the second conductive trace can be the same as the shape of the first conductive trace. This allows the first and second conductive traces to be formed into a combined path. This is advantageous when designing semiconductor devices, circuits, or components. For example, a user can draw a single path on a CAD system, allowing the first and second conductive traces to be drawn simultaneously. In addition, the first and third contacts can form a first unit, and the fourth and fifth contacts can form a second unit. These units can be inserted after the path is drawn. In other embodiments, the first unit can be automatically drawn when the path is drawn, and the second unit can be automatically drawn after the path is completed. In addition, the first unit can be the same as the second unit.

[0028] The first unit and the second unit may each include: a contact pad; a first trace contact portion, the first trace contact portion being electrically connected to the first conductive trace; a second trace contact portion, the second trace contact portion being electrically connected to the second conductive trace; and at least one of the following features: a) one or more first through-holes, the first through-holes connecting the first trace contact portion to the contact pad; b) one or more second through-holes, the second through-holes connecting the second trace contact portion to the contact pad; and c) one or more ground through-holes, the ground through-holes connecting the contact pad to ground at least during operation.

[0029] During the design phase, the user can draw a path and then connect its ends to the first unit or the second unit. It should be noted here that the first unit and the second unit can be different embodiments of a common unit or the same embodiment. The user can adjust the common unit to form the first unit and the second unit by selecting the vias to be used. For example, when designing the first unit, the user may be given the option of implementing any one or more of the above-mentioned vias. When only the first via is selected, the contact pad is only connected to the first conductive trace. When only the second via is selected, the contact pad is only connected to the second conductive trace. If one or more ground vias are used, the contact pad can be grounded during operation. In these cases, if the first via and / or the second via are used, the corresponding first trace and / or second trace is grounded.

[0030] The semiconductor body may include a substrate having an epitaxial layer disposed thereon, wherein the conductive region is formed within the epitaxial layer. The epitaxial layer may include one or more sublayers. The conductive region may be formed in one or more of these sublayers by ion implantation. Alternatively, the conductive region may be formed during the growth of the epitaxial layer or one or more sublayers of the epitaxial layer. The second contact may be formed on and / or from the backside of the substrate.

[0031] Grounding the conductive region can be achieved in various ways. For example, one or more vias can be used to connect the conductive region to the backside of the semiconductor substrate and, in turn, to the second contact. In other embodiments, the substrate can be a conductive substrate, and the epitaxial layer can be electrically connected to the conductive substrate. In this case, when the die crack detection system operates in the first mode, the conductive region can be electrically grounded through the conductive substrate.

[0032] The thickness of the semiconductor body may be in the range of 25 micrometers to 1000 micrometers, more preferably between 50 micrometers and 500 micrometers.

[0033] In some embodiments, the measurement unit is disposed externally to the semiconductor body. For example, the measurement unit may be a separate device having a measurement probe configured to contact the first, second, third, fourth, and / or fifth contacts. Alternatively, for some embodiments, the measurement unit may be integrated into the semiconductor body. In this case, the measurement unit may have an input terminal configured to receive a control signal to enable the die crack detection system to operate in the first mode, the second mode, or the third mode, and an output terminal configured to output a signal indicating whether the measurement unit has determined the presence of at least one die crack in the semiconductor body.

[0034] According to a second aspect, the present invention provides a semiconductor device configured as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Next, the present invention will be described with reference to the accompanying drawings, in which:

[0036] Figure 1 An example of a silicon LDMOS transistor including a p-type silicon substrate is shown at the top, an example of a gallium nitride MISFET including a GaN substrate is shown in the middle, and a cross-section of a semiconductor device suitable for use in a grain crack detection system according to the present invention is shown at the bottom.

[0037] Figure 2 A top view of a semiconductor device that can be used as a die crack detection system according to the present invention is schematically shown.

[0038] Figure 3 A top view of a semiconductor device is shown.

[0039] Figure 4 A schematic diagram showing units of a grain crack detection system according to the present invention is shown.

[0040] Figure 5 Other different examples of the first unit according to the present invention are shown.

[0041] Figure 6 A semiconductor die is shown, wherein the die crack detection system of the present invention is implemented on the semiconductor die. DETAILED DESCRIPTION

[0042] Figure 1 At the top, an example of a silicon LDMOS transistor 100 is shown, comprising a p-type silicon substrate 101, on which has been grown a p-type epitaxial layer 102. An n-type drift region 103 is formed inside layer 102. Contact can be made to this layer using a drain contact 104, which is arranged above a highly doped n-type drain contact region 105 formed inside drift region 103.

[0043] A p-type body 106 is formed in layer 102 extending below a polysilicon gate contact 107. An n-type source region 108 and a p-type region 109 are formed in body 106. Optionally, a source contact 110 is provided which is arranged above the source regions 108, 109.

[0044] There is a gate oxide layer 111 between the gate contact 107 and the epitaxial layer 102. The oxide layer 111 can also be used to form a capacitor of the die crack detection system according to the present invention.

[0045] Figure 1 In the center, an example of a gallium nitride MISFET 200 is shown, including a GaN substrate 201, which itself can be arranged on a sapphire or SiC substrate. An n-type AlGaN layer 202 is arranged on the GaN substrate 201. A two-dimensional electron gas (2DEG) forms at the heterojunction between layers 201 and 202. A gate contact 203 can be used to control the electron concentration within the 2DEG. An insulating layer 204 (such as a silicon nitride layer) is arranged between the gate contact 203 and the AlGaN layer 202.

[0046] Inside the AlGaN layer, highly doped n-type contact regions 205 , 206 are provided to achieve low ohmic contact resistance with the source contact 207 and the drain contact 208 , respectively.

[0047] Similar to the gate oxide 111 , the insulating layer 204 may also be used to form a capacitor of the die crack detection system according to the present invention.

[0048] Figure 1At the bottom, a cross-section of a semiconductor device 300 suitable for use in a die crack detection system according to the present invention is shown. The semiconductor device comprises a semiconductor body 301 on which an insulating layer 302 is disposed. Conductive traces 303 are disposed on top of insulating layer 302. Furthermore, one or more dielectric layers 304 are disposed above conductive traces 303. These dielectric layers are part of a metal layer stack in which additional conductive traces are formed, but are thicker than traces 303. A thin layer 305 of resistive material is deposited on the one or more dielectric layers to form a thin film resistor.

[0049] Semiconductor device 300 may relate to MISFET 200 or LDMOS transistor 100. For example, trace 303 may be formed using the same layers and simultaneously with gate contact 203 or gate contact 107. In addition, semiconductor body 301 may correspond to a combination of substrate 101 and epitaxial layer 102, or to a combination of GaN substrate 201 and AlGaN layer 202. Insulating layer 302 may be formed using the same layers and simultaneously with gate oxide 111 and insulating layer 204.

[0050] Figure 2 A top view of a semiconductor device 300 that can be used as a grain crack detection system according to the present invention is schematically shown, wherein the dashed line II corresponds to the cross section shown at the bottom. In addition, in the device 300, a separate contact 306 is provided at the back side of the semiconductor body 301. Figure 2 , the first contact C1 and the fifth contact C5 are electrically connected to the trace 303, and the third contact C3 and the fourth contact C4 are connected to the trace 305. The second contact C2 corresponds to the contact 306.

[0051] Figure 2 A measuring unit 500 is further schematically shown that can provide an electrical signal (such as current or voltage) to any one or more of the contacts C1-C5. In addition, the measuring unit 500 can also measure the voltage at any one or more of the contacts C1-C5 and / or the current through any one or more of the contacts C1-C5.

[0052] Figure 2 The die crack detection system can operate in three modes. In the first mode, only trace 303 is used to detect cracks. This measurement is based on the IV characteristic of a parallel capacitor between C2 and either C1 or C5. The table below provides an example of this mode. Here, #n represents the signal applied to contact Cn, V1 represents voltage V1, GND represents ground reference voltage, and NC indicates that the corresponding contact is not connected. Furthermore, I(n) represents the measured value of the current through contact n.

[0053] model #1 #2 #3 #4 #5 Measurements 1 V1 GND NC NC NC I(1) or I(2) 1 NC V1 NC NC GND I(2) or I(5) 1 V1 GND NC NC V1 I(1) and I(5), or I(2)

[0054] In the second mode, only trace 305 is used to detect cracks. This measurement is based on the IV characteristics of a series resistor between the third and fourth contacts. An example of this mode is provided in the table below.

[0055] model #1 #2 #3 #4 #5 Measurements 2 NC NC V1 GND NC I(3) or I(4) 2 NC NC +V1 -V1 NC I(3) or I(4)

[0056] In the third mode, both trace 303 and trace 305 are used to detect cracks. In the table below, an example of this mode is provided.

[0057] model #1 #2 #3 #4 #5 Measurements 3 V1 GND V2 GND NC (I(3) or I(4)) and (I(1) or I(2)) 3 V1 GND +V2 -V2 V1 (I(3) or I(4)) and (I(1), I(2), I(5))

[0058] The above list of examples of various modes is not exhaustive. Furthermore, in the above examples, the first and third contacts and the fourth and fifth contacts are different contacts. This enables, for example, different signals to be applied simultaneously to the first and third contacts. In this way, the traces 303, 305 can be used simultaneously to detect die cracks. In other embodiments, these measurements will be performed sequentially. In this case, the first and third contacts may be electrically connected, and the fourth and fifth contacts may be electrically connected. For example, these contacts may form or be connected to a single conductive pad. In Figure 3 and Figure 4 An example of such an embodiment is shown in .

[0059] Figure 3 A top view of the semiconductor device 300 is shown, wherein the dashed line II corresponds to Figure 1 The semiconductor device 300 includes traces 303 and 305. Figure 3 303 are combined into path 310. More specifically, trace 305 is located above trace 303. When designing a circuit that includes a die crack detection system, path 310 can be drawn as a component using a CAD system. After drawing path 310, contacts must be provided to the path. To this end, first unit 320 and second unit 330 are provided on opposite sides of path 310. In some embodiments, one of units 320 and 330 is omitted.

[0060] Each of first unit 320 and second unit 330 includes an element 303p for trace 303 and an element 305p for trace 305. Element 303p is used to connect to trace 303 of path 310, and element 305p is used to connect to trace 305 of path 310. Furthermore, each of units 320 and 330 includes one or more vias 311 for connecting element 303p to pads 312 formed in a relatively thick metal layer, and one or more vias 313 for connecting element 305p to pads 314 also formed in a relatively thick metal layer. Pads 312 and 314 enable electrical contact to be made with traces 303 and 305, respectively, to apply an electrical signal for die crack detection.

[0061] exist Figure 3 In the illustrated embodiment of a die crack detection system, pads 312, 314 of a first unit 320 are interconnected to form pad 315. No such interconnection exists for a second unit 330 of the semiconductor device. Furthermore, pad 315 is connected to ground via one or more additional vias 316. For example, grounding can be achieved using vias extending into the semiconductor body to a layer that is electrically grounded during operation. Alternatively, grounding can be achieved in a different manner, such as by providing a dedicated contact in the form of a lead or other terminal that is electrically grounded during operation.

[0062] Figure 4 Schematic diagrams of units 320, 330 of a die crack detection system according to the present invention are shown, wherein pads 312, 314 are interconnected to form pads 315L, 315R, respectively. Furthermore, a separate contact 318 is provided at the back side of the semiconductor body.

[0063] Dashed lines 303L and 305L respectively illustrate electrical connections between traces 303 and 305 and pad 315L, dashed lines 303R and 305R respectively illustrate electrical connections between traces 303 and 305 and pad 315R, and dashed lines 317L and 317R illustrate electrical connections between pads 315L and 315R and center ground pad 318.

[0064] Dashed lines 303L, 305L, 303R, 305R, 317L, and 317R indicate that the corresponding connections are optional.

[0065] Figure 5 Other different examples of first cells according to the present invention are shown. In the first cell on the left side of the figure, only trace 303 is connected to pad 315. In the first cell in the middle of the figure, both traces 303 and 305 are connected to pad 315, while in the first cell on the right side of the figure, only trace 305 is connected to pad 315.

[0066] Figure 6FIG. 4 shows a semiconductor die 400 in which the die crack detection system of the present invention is implemented. The semiconductor die 400 includes circuits 401A, 401B and a plurality of paths 402, each of which is configured as Figure 3 Path 310 in FIG. Two or more paths meet at intersection 404. At intersection 404, trace 303 and trace 305 of each path are physically connected to each other. Units 450 are provided at each end to enable application of electrical signals. These units are configured similarly to units 320 and 330 discussed above.

[0067] By using a relatively narrow path, it is possible to detect whether the interior of the semiconductor die 400 indicated by the dotted circle has a die crack.

[0068] In the above, the present invention has been explained using detailed embodiments of the present invention. However, the present invention is not limited to these embodiments. On the contrary, there are many possible modifications, as long as they do not depart from the scope of protection of the present invention.

Claims

1. A grain crack detection system comprising: A semiconductor device, comprising: a semiconductor body in which or on which at least one component is integrated, and which includes an electrically conductive region; an electrically insulating layer disposed on the conductive region; a first conductive trace disposed on the electrically insulating layer; a first contact electrically connected to the first conductive trace; and a second contact electrically connected to the conductive region; and Measuring unit; wherein the first conductive trace, the electrically insulating layer, and the conductive region form a capacitor; and The die crack detection system is capable of operating in a first mode, wherein the measurement unit is configured to output a first electrical signal to the first contact and / or the second contact, and determine whether at least one die crack exists in the semiconductor body based on an IV characteristic corresponding to the output first electrical signal; Wherein, the first contact is arranged at one end of the first conductive trace, wherein the first conductive trace includes a fifth contact arranged at an opposite end of the first conductive trace.

2. The grain crack detection system according to claim 1, wherein: The second contact is configured to be electrically grounded when operating in the first mode.

3. The grain crack detection system according to claim 1 or 2, wherein: The first electrical signal is a voltage signal, and wherein the measuring unit is configured to determine the presence of at least one die crack when a current through the first contact and / or the second contact exceeds a first threshold value.

4. The grain crack detection system according to claim 3, wherein: The measurement unit is configured to measure current through the first and / or second contacts within a predetermined amount of time after applying a voltage signal to avoid or limit measurement of current associated with charging of a capacitance formed between the first conductive trace and the conductive region.

5. The grain crack detection system according to claim 1 or 2, wherein: The at least one component is a metal-oxide-semiconductor field-effect transistor, a metal-insulator-semiconductor field-effect transistor, or a metal-insulator-metal capacitor.

6. The die crack detection system according to claim 1 or 2, further comprising a second conductive trace having a third contact point and a fourth contact point disposed on opposite ends of the second conductive trace; in, The grain crack detection system is also capable of operating in a second mode; Wherein, the measuring unit is configured to, when the grain crack detection system operates in the second mode: outputting a second electrical signal to the third contact and / or the fourth contact; and Whether at least one grain crack exists in the semiconductor body is determined based on an IV characteristic corresponding to the output second electrical signal.

7. The grain crack detection system according to claim 6, wherein: The die crack detection system is further capable of operating in a third mode, wherein the measurement unit is configured to: outputting a third electrical signal to the first contact and / or the second contact, and outputting a fourth electrical signal to the third contact and / or the fourth contact; and Whether at least one grain crack exists in the semiconductor body is determined based on the IV characteristics corresponding to the output third electrical signal and associated with the first contact and the second contact, and based on the IV characteristics corresponding to the output fourth electrical signal and associated with the third contact and the fourth contact.

8. The grain crack detection system according to claim 1 or 2, wherein: The semiconductor body comprises a substrate having an epitaxial layer arranged thereon, wherein the electrically conductive region is formed within the epitaxial layer, and wherein the second contact is formed on and / or by a back side of the substrate.

9. The grain crack detection system according to claim 1 or 2, wherein: The measuring unit is integrated in the semiconductor body, and the measuring unit has an input terminal and an output terminal, the input terminal is used to receive a control signal to enable the grain crack detection system to operate in a first mode, a second mode or a third mode, and the output terminal is used to output a signal indicating whether the measuring unit has determined that at least one grain crack exists in the semiconductor body. 10 . A semiconductor device configured as a semiconductor device of the die crack detection system according to claim 1 .

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