Embedded hybrid parallel power module packaging structure, packaging method and main drive inverter

Abstract

The invention belongs to the technical field of semiconductor packaging, and discloses an embedded hybrid parallel power module packaging structure, a packaging method and a main drive inverter. The packaging structure comprises a substrate; the multi-layer PCB is arranged on the surface of the substrate; the first power chip set is embedded in the groove of the multi-layer PCB; the second power chip set is embedded in the groove of the multi-layer PCB; the first driving chip group is used for driving the first power chip; the second driving chip group is used for driving the second power chip; the transformer array is arranged on the surface of the multi-layer PCB, and the output end of the transformer array is connected with the input end of the first driving chip set and the input end of the second driving chip set; the copper layer is arranged on the surface, far away from the substrate, of the multi-layer PCB and is used as a power access point of input current; and the decoupling network is bridged between the adjacent copper layers through a branch circuit. The packaging structure can effectively reduce the voltage spike and improve the device performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to an embedded hybrid parallel power module packaging structure, a packaging method, and a main drive inverter. Background Art

[0002] A power module is an electronic component that integrates power semiconductor devices and auxiliary circuits. It efficiently controls and converts electrical energy and is primarily used in industrial drives, new energy vehicles, rail transit, and renewable energy. Power modules currently used in the main drive inverters of high-performance new energy vehicles are categorized into two types: potting and plastic encapsulation, depending on the sealing material. Hybrid power drive (HPD) packaging using potting is more commonly used in new energy vehicles due to its excellent heat dissipation and mechanical stability.

[0003] Existing power modules, due to the inclusion of power terminals and bonding wires, typically introduce parasitic inductance in the range of 6-10nH. Under high-frequency switching, the interaction between parasitic inductance and the high switching current change rate (di / dt) can produce significant voltage spikes, which not only reduces the control accuracy of the system but may even cause damage to the chip. Secondly, the structural characteristics of the bonding wires make it easy for the power module to fall off during use, resulting in power cycle failure, which to a certain extent weakens the reliability of the power module. The above defects limit the reliability and power density improvement needs of the main drive inverter of new energy vehicles, and urgently need to be improved through optimization of the packaging structure. Summary of the Invention

[0004] To this end, the embodiments of the present application provide an embedded hybrid parallel power module packaging structure, packaging method and main drive inverter. The packaging structure of the present application effectively shortens the path of the commutation loop, reduces the parasitic inductance of the entire packaging structure, and improves the reliability of the packaging structure.

[0005] In a first aspect, the present application provides an embedded hybrid parallel power module packaging structure.

[0006] This application is achieved through the following technical solutions:

[0007] An embedded hybrid parallel power module packaging structure, comprising:

[0008] substrate;

[0009] A multi-layer PCB board is arranged on the surface of the substrate, and a groove is formed in the multi-layer PCB board;

[0010] A first power chipset, comprising eight first power chips, embedded in the grooves of the multi-layer PCB;

[0011] A second power chipset, comprising four second power chips, is topologically connected in parallel with the first power chipset and is distributed in a groove of the multi-layer PCB;

[0012] A first driver chipset, comprising two first driver chips, mounted on a surface of the multi-layer PCB away from the substrate, for driving the first power chipset;

[0013] A second driver chipset, comprising two second driver chips, mounted on a surface of the multi-layer PCB away from the substrate, for driving the second power chipset;

[0014] a transformer array comprising four transformers, disposed on a surface of the multilayer PCB away from the substrate, wherein output ends of two of the transformers are electrically connected to input ends of the first driver chip, and output ends of the other two transformers are electrically connected to input ends of the second driver chip;

[0015] A copper layer is provided on a surface of the multi-layer PCB away from the substrate and is used as a power access point for input current;

[0016] The decoupling network, including multiple distributed capacitance elements, is connected across adjacent copper layers through branch circuits.

[0017] In a preferred example of the present application, it can be further configured to further include an insulating substrate;

[0018] The insulating substrate is arranged between the base plate and the multilayer PCB board, one surface of the insulating substrate is connected to the bottom of the multilayer PCB board through metal paste, and the other surface of the insulating substrate is connected to the surface of the base plate through metal paste.

[0019] In a preferred example of the present application, it can be further configured that the multilayer PCB board includes a first layer, a second layer, a third layer, a core layer, and a fourth layer stacked from top to bottom, wherein the first layer, the second layer, the third layer, and the fourth layer are all composite layers consisting of a copper layer and a PP layer;

[0020] The first layer and the second layer are connected through copper vias, the second layer and the third layer are connected through copper vias, the third layer is connected to the first power chip and the second power chip through copper vias, and the core layer is connected to the fourth layer through copper vias.

[0021] In a preferred example of the present application, it can be further configured that the gates of the eight first power chips of the first power chipset are gathered on the third layer of the multi-layer PCB board through copper vias.

[0022] In a preferred example of the present application, it can be further configured that the gates of the four second power chips of the second power chipset are gathered on the third layer of the multi-layer PCB board through copper vias.

[0023] In a preferred example of the present application, it can be further configured that the first power chip is a SiC MOSFET power chip, and the second power chip is a Si IGBT power chip.

[0024] In a preferred example of the present application, it can be further configured that the first driver chip is a SiC MOSFET driver chip, and the second driver chip is a Si IGBT driver chip.

[0025] In a second aspect, the present application provides an embedded hybrid parallel power module packaging method.

[0026] This application is achieved through the following technical solutions:

[0027] A method for packaging an embedded hybrid parallel power module, for producing the packaging structure as described in the first aspect, comprising:

[0028] A layer of sintering material is applied to the groove of the base through a silver paste printing process and pre-baked under a preset temperature condition;

[0029] Mounting a plurality of first power chips and a plurality of second power chips on the sintered material by a patch process, wherein the first power chips and the second power chips are arranged in a parallel topology;

[0030] Place the assembled base and power chip together into the sintering equipment for sintering process;

[0031] Place the sintered base onto the core layer, and inject the PP material into the groove on the base surface for lamination and curing;

[0032] The third layer, the second layer, and the first layer are sequentially stacked on the upper surface of the core layer, and the fourth layer is stacked on the lower surface of the core layer to obtain a multi-layer PCB board;

[0033] Sintering the multi-layer PCB board and the substrate using a mixed slurry to interconnect;

[0034] The decoupling network, the transformer array, the first driver chipset and the second driver chipset are fixed on the upper surface of the multi-layer PCB board through a surface mounting process.

[0035] In a preferred example of this application, it can be further set as follows:

[0036] The third layer, the second layer, and the first layer are sequentially stacked on the upper surface of the core layer, and the fourth layer is stacked on the lower surface of the core layer to obtain a multi-layer PCB board, including:

[0037] A PP layer and a copper layer are placed on the upper surface of the core layer, and laminated and cured to form a third layer;

[0038] A PP layer and a copper layer are placed on the surface of the third layer, and laminated and cured to form the second layer;

[0039] A PP layer and a copper layer are placed on the surface of the second layer, and laminated and cured to form a first layer;

[0040] A PP layer and a copper layer are placed under the core layer, laminated and cured to form the fourth layer, and a multi-layer PCB board is obtained.

[0041] In a third aspect, the present application provides a main drive inverter.

[0042] This application is achieved through the following technical solutions:

[0043] A main drive inverter comprises the embedded hybrid parallel power module packaging structure described in the first aspect.

[0044] In summary, compared with the prior art, the technical solutions provided by the embodiments of the present application have at least the following beneficial effects:

[0045] The embedded hybrid parallel power module packaging structure proposed in the present application includes a substrate; a multi-layer PCB board, arranged on the surface of the substrate, and having a groove formed in the multi-layer PCB board; a first power chipset, comprising eight first power chips, embedded in the groove of the multi-layer PCB board; a second power chipset, comprising four second power chips, distributed in the groove of the multi-layer PCB board in a parallel topology with the first power chipset; a first driver chipset, comprising two first driver chips, mounted on the surface of the multi-layer PCB board away from the substrate, for driving the first power chipset; a second driver chipset, comprising two second driver chips, mounted on the surface of the multi-layer PCB board away from the substrate, for driving the second power chipset; a transformer array, comprising four transformers, arranged on the surface of the multi-layer PCB board away from the substrate, wherein the output ends of two transformers are electrically connected to the input ends of the first driver chips, and the output ends of the other two transformers are electrically connected to the input ends of the second driver chips; a copper layer, arranged on the surface of the multi-layer PCB board away from the substrate, for serving as a power access point for the input current; and a decoupling network, comprising multiple distributed capacitor elements, connected across adjacent copper layers through branch circuits. Compared to traditional packaging methods, the package structure proposed in this application utilizes copper charging terminals on the surface of a multi-layer PCB board, eliminating the need for additional power terminal structures. The current transmission method is optimized from bond wires to copper-plated connections, and the current transmission direction is adjusted from horizontal transmission to vertical transmission, effectively reducing the parasitic inductance of the package structure and thus suppressing the generation of voltage spikes.

[0046] By connecting different power chips in parallel and controlling the power chips through integrated driving elements on the surface of the packaging structure, different conduction and switching moments can be adjusted to achieve transient current sharing and minimize the overload of each power chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic cross-sectional view of an embedded hybrid parallel power module packaging structure provided in one embodiment of the present application;

[0048] Figure 2 A schematic diagram of the layout of a power chip provided in one embodiment of the present application;

[0049] Figure 3 A schematic top view of an embedded hybrid parallel power module packaging structure provided in one embodiment of the present application;

[0050] Figure 4 A schematic cross-sectional view of an embedded hybrid parallel power module packaging structure provided in another embodiment of the present application;

[0051] Figure 5 A schematic cross-sectional view of a multi-layer PCB board provided in yet another embodiment of the present application;

[0052] Figure 6 A circuit connection diagram of a power chip provided in another embodiment of the present application. DETAILED DESCRIPTION

[0053] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed, but as long as they are within the scope of the claims of the present application, they are protected by the patent law.

[0054] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0055] In the description of this application, it should be understood that the technical terms or scientific terms used in this application should be understood by a technician with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. When the number of a component or element is not specifically stated below in the embodiments disclosed in this application, it means that the component or element can be one or more, or can be understood as at least one. "At least one" refers to one or more, and "a plurality" refers to at least two.

[0056] In addition, the term "and / or" in this application is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this application, unless otherwise specified, generally indicates that the related objects are in an "or" relationship.

[0057] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on the quantity and execution order.

[0058] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0059] The embodiments of the present application are described in further detail below with reference to the accompanying drawings.

[0060] substrate;

[0061] A multi-layer PCB board is arranged on the surface of the substrate, and a groove is formed in the multi-layer PCB board;

[0062] A first power chipset, comprising eight first power chips, embedded in a groove of the multi-layer PCB board;

[0063] A second power chipset, comprising four second power chips, is topologically distributed in parallel with the first power chipset in a groove of the multi-layer PCB;

[0064] A first driver chipset, comprising two first driver chips, mounted on a surface of the multi-layer PCB away from the substrate, for driving the first power chipset;

[0065] A second driver chipset, comprising two second driver chips, mounted on a surface of the multi-layer PCB away from the substrate, for driving the second power chipset;

[0066] A transformer array, comprising four transformers, is disposed on a surface of the multilayer PCB away from the substrate, wherein the output ends of two of the transformers are electrically connected to the input ends of the first driver chip, and the output ends of the other two transformers are electrically connected to the input ends of the second driver chip;

[0067] The copper layer is located on the surface of the multi-layer PCB away from the substrate and is used as the power input point for the input current.

[0068] The decoupling network, including multiple distributed capacitance elements, is connected across adjacent copper layers through branch circuits.

[0069] Reference Figures 1 to 3 As shown, Figure 1 A cross-sectional schematic diagram of an embedded hybrid parallel power module packaging structure provided in one embodiment of the present application is shown. Figure 2 A schematic diagram of the layout of the power chip provided in this application; Figure 3 A top view schematic diagram of the embedded hybrid parallel power module packaging structure.

[0070] The bottom layer of the packaging structure is a substrate 10 , which has two relatively parallel surfaces along the x1 axis, namely, surface M1 (main surface) and surface M2 . A multi-layer PCB board 20 is provided on the surface M1 of the substrate 10 .

[0071] A groove C is provided on the multi-layer PCB 20 for mounting power chips. In this embodiment, the groove C of the multi-layer PCB 20 is provided with a first power chipset group 30 and a second power chipset group 40. The number of power chips included in the first power chipset group 30 is twice the number of power chips included in the second power chipset group 40. Specifically, the first power chipset group 30 includes eight first power chips 30a ( Figure 1 The second power chipset 40 includes four second power chips 40a ( Figure 1(One is shown in FIG. 1 ), the second power chip 40a and the first power chip 30a are arranged in parallel topology within the groove C of the multi-layer PCB 20. The upper ends of the second power chip 40a and the first power chip 30a can be flush with the upper end of the groove C of the multi-layer PCB 20, or lower than the upper end of the groove C of the multi-layer PCB 20.

[0072] In some embodiments, a plurality of bases are embedded in the groove C of the multilayer PCB board 20, and the first power chip 30a and the second power chip 40a are connected to the bases via a sintered material. Each first power chip 30a is connected to a base, and each second power chip 40a is connected to a base. The sintered material connecting the power chips and the bases can be nano silver paste or nano copper paste. The bases are made of a material with good heat dissipation properties, such as a copper plate or an aluminum alloy heat dissipation base.

[0073] Reference Figure 2 As shown, twelve pedestals 201 are disposed in groove C of a multilayer PCB 20. Eight of the pedestals 201 are connected to first power chips 30a, and four of the pedestals 201 are connected to second power chips 40a. The eight first power chips 30a and four second power chips 40a are connected in parallel, with the first power chips 30a located on both sides of the second power chips 40a.

[0074] The first power chip 30 a and the second power chip 40 a are two different types of power chips.

[0075] Reference Figure 3 As shown, a first driver chipset 50 is disposed on the surface of the multilayer PCB 20. The first driver chipset 50 includes two first driver chips 50a. The output of the first driver chipset 50 is connected to the input of the first power chips 30a to drive the first power chips 30a. Specifically, the two first driver chips 50a are divided into an upper bridge chip and a lower bridge chip. The output of the upper bridge chip is connected to the four first power chips 30a, and the output of the lower bridge chip is connected to the four first power chips 30a.

[0076] A second driver chipset 60 is also provided on the surface of the multilayer PCB 20. The second driver chipset 60 includes two second driver chips 60a. The output of the second driver chipset 60 is connected to the input of the second power chip 40a, thereby driving the second power chip 40a. Specifically, the two second driver chips 60a are divided into an upper bridge chip and a lower bridge chip. The output of the upper bridge chip is connected to the two second driver chips 60a, and the output of the lower bridge chip is connected to the two second driver chips 60a.

[0077] A transformer array 70 is also provided on the surface of the multilayer PCB 20. The output of the transformer array 70 is connected to the input of the first driver chipset 50 and the input of the second driver chipset 60. The number of transformers 70a included in the transformer array 70 is the same as the total number of first driver chips 50a and second driver chips 60a. That is, one transformer 70a is connected to each first driver chip 50a, and one transformer 70a is connected to each second driver chip 60a.

[0078] The transformer array 70 includes four transformers 70 a , wherein the output ends of two transformers 70 a are electrically connected to the input ends of the first driver chip 50 a , and the input ends of the other two transformers 70 a are electrically connected to the input ends of the second driver chip 60 a .

[0079] A copper layer 80 is also provided on the surface of the multi-layer PCB board 20, and the copper layer 80 serves as a power access point for the input current. Figure 3 As shown, the copper layer 80 is provided at both ends of the surface of the multi-layer PCB board 20, one end is an AC alternating current end, and the other end is a DC direct current end, including two DC- and one DC+.

[0080] A decoupling network 90 is also provided on the surface of the multilayer PCB 20, comprising a plurality of distributed capacitor elements connected across adjacent copper layers 80 via branch circuits. In this embodiment, the package structure includes two decoupling capacitors connected across the copper layers 80.

[0081] It should be noted that the first driver chipset 50 , the second driver chipset 60 , the transformer array 70 and the decoupling network 90 are all interconnected with the surface M1 of the multi-layer PCB board 20 through an SMT process (surface mount technology).

[0082] Compared to traditional power modules, the packaging structure of this application significantly reduces module size while significantly increasing power density. Furthermore, placing the decoupling capacitors between the copper layers of the current loop effectively reduces parasitic inductance, further optimizing the switching characteristics of the power module and significantly improving its performance.

[0083] In some embodiments, the packaging structure also includes an insulating substrate: specifically, the insulating substrate is arranged between the substrate and the multi-layer PCB board, one surface of the insulating substrate is connected to the bottom of the multi-layer PCB board through metal paste, and the other surface of the insulating substrate is connected to the surface of the substrate through metal paste.

[0084] See Figure 4 As shown, an insulating substrate 11 is connected to a surface M1 of the base plate, and the other surface of the insulating substrate 11 is connected to the bottom of the multi-layer PCB board 20 through metal paste.

[0085] Specifically, the insulating substrate 11 is at least one of aluminum oxide Al2O3, silicon nitride Si3N4, aluminum nitride AlN, and zirconium oxide ZTA.

[0086] In some embodiments, the multilayer PCB board includes a first layer, a second layer, a third layer, a core layer, and a fourth layer stacked from top to bottom, wherein the first layer, the second layer, the third layer, and the fourth layer are all composite layers consisting of a copper layer and a PP layer;

[0087] The first layer and the second layer are connected through copper vias, the second layer and the third layer are connected through copper vias, the third layer is connected to the first power chip and the second power chip through copper vias, and the core layer is connected to the fourth layer through copper vias.

[0088] See attached Figure 5 As shown, the multi-layer PCB board 20 is a multi-layer structure, including a first layer 21, a second layer 22, a third layer 23, a core layer 2a and a fourth layer 24 from top to bottom. The groove C of the multi-layer PCB board 20 passes through the first layer 21, the second layer 22 and partially passes through the third layer 23.

[0089] Specifically, first layer 21 includes a first copper layer 21a and a first adhesive layer 21b; second layer 22 includes a second copper layer 22a and a second adhesive layer 22b; third layer 23 includes a third copper layer 23a and a third adhesive layer 23b; and fourth layer 24 includes a fourth copper layer 24a and a fourth adhesive layer 24b. The first adhesive layer 21b is connected to the second copper layer 22a, the second adhesive layer 22b is connected to the third copper layer 23a, the third adhesive layer 23b is connected to one surface of the core layer 2a, and the other surface of the core layer 2a is connected to the fourth copper layer 24a. The first layer 21 and the second layer 22 are connected via a first copper via 1. Specifically, the first copper via 1 electrically connects the first copper layer 21a of the first layer 21 and the second copper layer 22a of the second layer 22. The second layer 22 and the third layer 23 are connected via a second copper via 2. Specifically, the second copper layer 22a of the second layer 22 and the third copper layer 23a of the third layer 23 are electrically connected via the second copper via 2. The third layer 23 and the core layer 2a are connected via a third copper via 3. Specifically, the third copper via 3 connects the third copper layer 23a of the third layer 23 and the core layer 2a. The third layer 23, the core layer 2a, and the fourth layer 24 are connected via a fourth copper via 4. The first copper via 1, the second copper via 2, and the third copper via 3 can be used for current signal transmission, while the fourth copper via 4 serves as a bottom heat sink. The adhesive layer is the PP layer.

[0090] It should be noted that the numbers of the first copper holes 1 , the second copper holes 2 , the third copper holes 3 and the fourth copper holes 4 shown in the figure are for illustration only and do not limit the number of the copper holes.

[0091] In some embodiments, the gate of the first power chip 30 a is connected to the third layer of the multi-layer PCB through a copper via.

[0092] In some embodiments, the gate of the second power chip 40 a is connected to the third layer of the multi-layer PCB through a copper via.

[0093] The embedded hybrid parallel power module packaging method in the present application inputs current to the drain of the upper bridge chip through the copper layer located on the surface of the multi-layer PCB board, and then the current is conducted to the drain of the lower bridge chip through the copper hole via the source of the upper bridge chip, and then flows back to the copper layer on the surface of the multi-layer PCB board through the copper hole via the source of the lower bridge chip. Compared with the power module of the traditional packaging form, the packaging structure of the present application eliminates the additional power terminal structure, optimizes the current transmission method from bonding wires to copper column connection, and adjusts the current transmission direction from horizontal to vertical. This structure significantly shortens the path of the commutation circuit, effectively reduces the parasitic inductance of the entire power module, thereby suppressing the generation of voltage spikes, and further improving the control accuracy and operation stability of the system.

[0094] In some embodiments, the first power chip is a SiC MOSFET power chip, the second power chip is a Si IGBT power chip, and the number of first power chips is twice the number of second power chips. This 2:1 SiC-IGBT hybrid achieves complementary characteristics of the different devices, achieving a balance between efficiency, cost, and reliability. It can leverage the high-frequency advantages of SiC to dominate dynamic losses, while using IGBTs to reduce costs in the low-frequency range.

[0095] In some embodiments, the first driver chip is a SiC MOSFET driver chip, and the second driver chip is a Si IGBT driver chip.

[0096] In some embodiments, reference Figure 6 The figure shows the circuit connection diagram between the power chip and the driver chip. MOSFET is the first power chip, i.e. Figure 6 P1, P3, P4, P6, P7, P9, P10 and P12 in the figure; IGBT is the second power chip, that is, Figure 6 P2, P5, P8, and P11 are shown in Figure 1. HG1, HG2, LG1, and LG2 are the output terminals of the driver chip, HS is the source signal, HG1 is connected to the gate of the IGBT, HG2 is connected to the gate of the MOSFET, LG1 is connected to the gate of the IGBT, and LG2 is connected to the gate of the MOS.

[0097] The embedded hybrid parallel power module packaging structure proposed in this application was subjected to parasitic inductance simulation testing, and the inductance between the positive terminal DC+ and the negative terminal DC- of the power supply was found to be 1.7nH. Compared with the 10nH inductance of the traditional HPD packaging format, the parasitic inductance was reduced by about 83%, effectively suppressing voltage spikes and improving high-frequency switching stability. Through double-pulse simulation testing, it was found that dv / dt and di / dt were improved by 98% and 105% respectively compared with the traditional HPD packaging format, and the switching loss was reduced by 70%. Through the integrated design of the embedded packaging, the power density of the power module was increased by 70%. At the same time, due to the use of a hybrid parallel strategy of SiC MOSFET and Si IGBT, the driving range can be improved by 2.83% compared with traditional IGBT modules in the WLTP operating condition simulation. In reliability simulation, the power cycle life of the embedded package power module using copper plating for electrical interconnection is 3.5 times that of the traditional bond wire packaging.

[0098] Another embodiment of the present application further provides an embedded hybrid parallel power module packaging method for manufacturing the above-mentioned packaging structure, comprising:

[0099] S1: A layer of sintering material is applied to the groove of the base through a silver paste printing process and pre-baked at a preset temperature.

[0100] S2: mounting a plurality of first power chips and a plurality of second power chips on the sintered material through a patch process, wherein the first power chips and the second power chips are arranged in a parallel topology;

[0101] S3: Place the assembled base and power chip into the sintering equipment for sintering process;

[0102] S4: Place the sintered base onto the core layer, and inject the PP material into the groove on the base surface for lamination and curing;

[0103] S5: constructing the third layer, the second layer, and the first layer on the upper surface of the core layer in sequence, and constructing the fourth layer on the lower surface of the core layer, thereby obtaining a multi-layer PCB board;

[0104] S6: Sintering the multi-layer PCB board and the substrate using the mixed slurry to interconnect;

[0105] S7: Fixing the decoupling network, the transformer array, the first driver chipset and the second driver chipset on the upper surface of the multi-layer PCB board by a surface mounting process.

[0106] In some embodiments, S5: sequentially stacking and constructing a third layer, a second layer, and a first layer on the upper surface of the core layer, and stacking and constructing a fourth layer on the lower surface of the core layer to obtain a multilayer PCB board, specifically comprising: placing a PP layer and a copper layer on the upper surface of the core layer, laminating and curing to form a third layer;

[0107] A PP layer and a copper layer are placed on the surface of the third layer, and laminated and cured to form the second layer;

[0108] A PP layer and a copper layer are placed on the surface of the second layer, and laminated and cured to form a first layer;

[0109] A PP layer and a copper layer are placed under the core layer, laminated and cured to form the fourth layer, and a multi-layer PCB board is obtained.

[0110] Embodiments of the present application also provide a main drive inverter, comprising the aforementioned embedded hybrid parallel power module packaging structure and a product produced by the aforementioned embedded hybrid parallel power module packaging method. Using the embedded hybrid parallel power module packaging structure proposed in this application in a main drive inverter can effectively improve the control accuracy and operational stability of the system.

[0111] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, the division of the above-mentioned functional units and modules is only used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the system described in this application is divided into different functional units or modules to complete all or part of the functions described above.

Claims

1. An embedded hybrid parallel power module packaging structure, characterized in that: include: substrate; A multi-layer PCB board is arranged on the surface of the substrate, and a groove is formed in the multi-layer PCB board; A first power chipset, comprising eight first power chips, embedded in the grooves of the multi-layer PCB; A second power chipset, comprising four second power chips, is topologically connected in parallel with the first power chipset and is distributed in a groove of the multi-layer PCB; A first driver chipset, comprising two first driver chips, mounted on a surface of the multi-layer PCB away from the substrate, for driving the first power chipset; A second driver chipset, comprising two second driver chips, mounted on a surface of the multi-layer PCB away from the substrate, for driving the second power chipset; a transformer array comprising four transformers, disposed on a surface of the multilayer PCB away from the substrate, wherein output ends of two of the transformers are electrically connected to input ends of the first driver chip, and output ends of the other two transformers are electrically connected to input ends of the second driver chip; A copper layer is provided on a surface of the multi-layer PCB away from the substrate and is used as a power access point for input current; The decoupling network, including multiple distributed capacitance elements, is connected across adjacent copper layers through branch circuits.

2. The embedded hybrid parallel power module packaging structure according to claim 1, characterized in that: Also included is an insulating substrate; The insulating substrate is arranged between the base plate and the multilayer PCB board, one surface of the insulating substrate is connected to the bottom of the multilayer PCB board through metal paste, and the other surface of the insulating substrate is connected to the surface of the base plate through metal paste.

3. The embedded hybrid parallel power module packaging structure according to claim 1, characterized in that: The multi-layer PCB board includes a first layer, a second layer, a third layer, a core layer and a fourth layer stacked from top to bottom, wherein the first layer, the second layer, the third layer and the fourth layer are all composite layers composed of a copper layer and a PP layer; The first layer and the second layer are connected through copper vias, the second layer and the third layer are connected through copper vias, the third layer is connected to the first power chip and the second power chip through copper vias, and the core layer is connected to the fourth layer through copper vias.

4. The embedded hybrid parallel power module packaging structure according to claim 3, characterized in that: The gates of the eight first power chips of the first power chipset are gathered on the third layer of the multi-layer PCB through copper vias.

5. The embedded hybrid parallel power module packaging structure according to claim 3, characterized in that: The gates of the four second power chips of the second power chipset are gathered together on the third layer of the multi-layer PCB through copper vias.

6. The embedded hybrid parallel power module packaging structure according to claim 1, characterized in that: The first power chip is a SiC MOSFET power chip, and the second power chip is a Si IGBT power chip.

7. The embedded hybrid parallel power module packaging structure according to claim 6, characterized in that: The first driver chip is a SiC MOSFET driver chip, and the second driver chip is a Si IGBT driver chip.

8. A method for packaging an embedded hybrid parallel power module, characterized in that: Used to manufacture the packaging structure according to any one of claims 1 to 7, comprising: A layer of sintering material is applied to the groove of the base through a silver paste printing process and pre-baked under a preset temperature condition; Mounting a plurality of first power chips and a plurality of second power chips on the sintered material by a patch process, wherein the first power chips and the second power chips are arranged in a parallel topology; Place the assembled base and power chip together into the sintering equipment for sintering process; Place the sintered base onto the core layer, and inject the PP material into the groove on the base surface for lamination and curing; The third layer, the second layer, and the first layer are sequentially stacked on the upper surface of the core layer, and the fourth layer is stacked on the lower surface of the core layer to obtain a multi-layer PCB board; Sintering the multi-layer PCB board and the substrate using a mixed slurry to interconnect; The decoupling network, the transformer array, the first driver chipset and the second driver chipset are fixed on the upper surface of the multi-layer PCB board through a surface mounting process.

9. The embedded hybrid parallel power module packaging method according to claim 8, characterized in that: The third layer, the second layer, and the first layer are sequentially stacked on the upper surface of the core layer, and the fourth layer is stacked on the lower surface of the core layer to obtain a multi-layer PCB board, including: A PP layer and a copper layer are placed on the upper surface of the core layer, and laminated and cured to form a third layer; A PP layer and a copper layer are placed on the surface of the third layer, and laminated and cured to form the second layer; A PP layer and a copper layer are placed on the surface of the second layer, and laminated and cured to form a first layer; A PP layer and a copper layer are placed under the core layer, laminated and cured to form the fourth layer, and a multi-layer PCB board is obtained.

10. A main drive inverter, characterized in that: It comprises the embedded hybrid parallel power module packaging structure as described in any one of claims 1 to 7.

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