Driving circuit, controller and vehicle

Abstract

The invention discloses a driving circuit, a controller and a vehicle, and relates to the technical field of electronic circuits. The driving circuit comprises a current sampling module, a latch module and a first control module. A first output end of the current sampling module is connected with a first input end of the latch module. The output end of the latch module is connected with the first input end of the first control module; the output end of the first control module is connected with the enabling end of the driving module; the current sampling module is used for collecting a current value of an input current of a driving object of the driving module, and outputting a first overcurrent notification signal through a first output end of the current sampling module when it is determined that the input current is overcurrent; the latch module is used for outputting a second overcurrent notification signal to the first control module under the condition that the first overcurrent notification signal is received, and the second overcurrent notification signal is a latch signal aiming at the first overcurrent notification signal; and the first control module is used for controlling the driving module to stop enabling under the condition that the second overcurrent notification signal is received.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and more specifically, to a drive circuit, a controller, and a vehicle. Background Art

[0002] In electronic devices, driver chips are core components and are widely used in power management, motor control, LED lighting and other fields.

[0003] For example, a driver chip can be used in a motor controller. The motor controller also includes power management components, a control board, and a current sampling module. The power management components are used to form at least a three-phase bridge arm, and the current sampling module is used to sample the input current of the three-phase bridge arm.

[0004] If an overcurrent condition occurs in the input current of the power transistors in the motor controller, the performance of the power transistors driven by the driver chip will degrade and become damaged, potentially leading to more serious safety issues such as explosion and burnout of the motor controller. Therefore, how to protect the input current of the power transistors from overcurrent conditions has become a pressing technical issue. Summary of the Invention

[0005] One purpose of this application is to provide a new technical solution for a driving circuit.

[0006] According to a first aspect of the present application, a driving circuit is provided, comprising: a current sampling module, a latch module, and a first control module, wherein:

[0007] The first output terminal of the current sampling module is connected to the first input terminal of the latch module;

[0008] The output end of the latch module is connected to the first input end of the first control module;

[0009] The output terminal of the first control module is connected to the enable terminal of the driving module;

[0010] The current sampling module is used to collect the current value of the input current of the driving object of the driving module, and output a first overcurrent notification signal through the first output terminal of the current sampling module when it is determined that the input current is overcurrent;

[0011] The latch module is configured to output a second overcurrent notification signal to the first control module upon receiving the first overcurrent notification signal, wherein the second overcurrent notification signal is a latch signal for the first overcurrent notification signal;

[0012] The first control module is configured to control the driving module to stop being enabled when the second overcurrent notification signal is received.

[0013] Optionally, the driving circuit further includes: a second control module, wherein:

[0014] The first output terminal of the current sampling module is connected to the first input terminal of the second control module;

[0015] The first output terminal of the second control module is connected to the second input terminal of the first control module;

[0016] The second control module is configured to output a third overcurrent notification signal to the first control module when receiving the first overcurrent notification signal;

[0017] The first control module is configured to control the driving module to stop being enabled when at least one of the third overcurrent notification signal and the second overcurrent notification signal is received.

[0018] Optionally, the latch module outputs the second overcurrent notification signal to the first control module at a first moment;

[0019] The second control module outputs the third overcurrent notification signal to the first control module at a second time; the second time is later than the first time;

[0020] The first control module is configured to control the driving module to stop being enabled when receiving the second overcurrent notification signal;

[0021] The first control module is configured to control the driving module to stop being enabled again when the third overcurrent notification signal is received.

[0022] Optionally, the second output end of the current sampling module is connected to the second input end of the second control module, and the current sampling module is further used to convert the input current into a voltage signal, and transmit the voltage signal to the second control module through the second output end of the current sampling module;

[0023] The second control module is configured to output a third overcurrent notification signal to the first control module when it is determined at least according to the voltage signal that the input current is overcurrent.

[0024] Optionally, the second output terminal of the second control module is connected to the second input terminal of the latch module;

[0025] The current sampling module is further configured to output a first non-overcurrent notification signal through the first output terminal of the current sampling module when it is determined that the input current is not overcurrent;

[0026] The second control module is configured to output a reset signal to the latch module and a second non-overcurrent notification signal to the first control module when receiving the first non-overcurrent notification signal;

[0027] The latch module is configured to output a third non-overcurrent notification signal to the first control module when receiving the reset signal and the first non-overcurrent notification signal;

[0028] The first control module is configured to control the driving module to be enabled when receiving the third non-overcurrent notification signal and the second non-overcurrent notification signal.

[0029] Optionally, the second output terminal of the second control module is connected to the second input terminal of the latch module;

[0030] The current sampling module is further configured to output a first non-overcurrent notification signal through the first output terminal of the current sampling module when it is determined that the input current is not overcurrent;

[0031] The second control module is configured to output a reset signal to the latch module and a second non-overcurrent notification signal to the first control module when it is determined according to the voltage signal that the input current is not overcurrent;

[0032] The latch module is configured to output a third non-overcurrent notification signal to the first control module when receiving the reset signal and the first non-overcurrent notification signal;

[0033] The first control module is configured to control the driving module to be enabled when receiving the third non-overcurrent notification signal and the second non-overcurrent notification signal.

[0034] Optionally, the first control module includes: an AND gate circuit, a first pull-up resistor, and a first power supply, wherein:

[0035] The first input end of the AND gate circuit is connected to the first output end of the second control module and the first end of the first pull-up resistor respectively, the second input end of the AND gate circuit is connected to the output end of the latch module, and the output end of the AND gate circuit is connected to the enable end of the driving module;

[0036] The first power source is connected to the second end of the first pull-up resistor.

[0037] Optionally, the latch module includes: a first NAND gate circuit, a second NAND gate circuit, a second pull-up resistor, a second power supply, a third pull-up resistor and a third power supply, and a unidirectional conduction unit, wherein:

[0038] The first end of the one-way conducting unit is connected to the first output end of the current sampling module, the second end of the one-way conducting unit is connected to the first input end of the first NAND gate circuit, and the conducting direction of the one-way conducting unit is the direction in which the second end of the one-way conducting unit points to the first end of the one-way conducting unit;

[0039] The second input terminal of the first NAND gate circuit is connected to the output terminal of the second NAND gate circuit, and the output terminal of the first NAND gate circuit is connected to the first input terminal of the second NAND gate circuit;

[0040] A first end of the second pull-up resistor is connected to the second power supply, and a second end of the second pull-up resistor is connected to the first input end and the ground end of the first NAND gate circuit respectively;

[0041] The second input terminal of the second NAND gate circuit is connected to the second output terminal of the second control module, and the output terminal of the second NAND gate circuit is connected to the first input terminal of the first control module;

[0042] The third power supply is connected to the output end of the second NAND gate circuit through the third pull-up resistor.

[0043] Optionally, the driving circuit further includes: a filter capacitor, wherein:

[0044] The second pull-up resistor is grounded through the filter capacitor.

[0045] Optionally, the unidirectional conducting unit is a diode, wherein:

[0046] The anode of the diode is connected to the first input end of the first NAND gate circuit, and the cathode of the diode is connected to the first output end of the current sampling module.

[0047] Optionally, the second control module includes a first core and a second core, wherein:

[0048] The first core is connected to both the first output terminal of the current sampling module and the second output terminal of the current sampling module, and the first core is in communication connection with the second core;

[0049] The first core is configured to send an overcurrent check indication signal to the second core upon receiving the first overcurrent notification signal and / or determining that the driving current is overcurrent according to the voltage signal;

[0050] The second core is connected to both the first output terminal of the current sampling module and the second output terminal of the current sampling module, and the second core is connected to the first input terminal of the first control module;

[0051] When the second core receives the check indication signal, it determines whether the first overcurrent notification signal is received, and determines whether the driving current is overcurrent based on the voltage signal. When the second core receives the first overcurrent notification signal and determines that the driving current is overcurrent based on the voltage signal, the second core sends a third overcurrent notification signal to the first control module.

[0052] Optionally, the third output terminal of the second control module is connected to the driving signal input terminal of the driving module, wherein:

[0053] The second control module stops outputting the driving signal to the driving module when outputting the third over-current notification signal.

[0054] According to a second aspect of the present application, a controller is provided, comprising: a current sensor, a control chip, a driver chip, and a latch, wherein:

[0055] The first output terminal of the current sensor is connected to the first input terminal of the latch;

[0056] The output terminal of the latch is connected to the first input terminal of the control chip;

[0057] The output terminal of the control chip is connected to the enable terminal of the driver chip;

[0058] The current sensor collects the current value of the input current of the driving object of the driving chip, and outputs a first overcurrent notification signal through the first output terminal of the current sensor when it is determined that the input current is overcurrent;

[0059] The latch outputs a second overcurrent notification signal to the control chip when receiving the first overcurrent notification signal, wherein the second overcurrent notification signal is a latch signal for the first overcurrent notification signal;

[0060] When the control chip receives the second overcurrent notification signal, it controls the driving chip to stop being enabled.

[0061] According to a third aspect of the present application, there is provided a vehicle, comprising the drive circuit according to any one of the first aspects;

[0062] Alternatively, it includes the controller described in the second aspect.

[0063] The present application provides a driving circuit, comprising: a current sampling module, a latch module, and a second control module, wherein: a first output terminal of the current sampling module is connected to a first input terminal of the latch module; an output terminal of the latch module is connected to a second input terminal of the second control module; and an output terminal of the second control module is connected to an enable terminal of the driving module; wherein the current sampling module is used to collect the current value of the input current of the driving object of the driving module, and output a first overcurrent notification signal through the first output terminal of the current sampling module when determining that the input current is overcurrent; the latch module is used to output a second overcurrent notification signal to the second control module when receiving the first overcurrent notification signal, wherein the second overcurrent notification signal is a latch signal for the first overcurrent notification signal; and the second control module is used to control the driving module to stop enabling when receiving the second overcurrent notification signal. The driving circuit provided by the present application can stop enabling the driving module when the input current of the driving object of the driving module is overcurrent, thereby protecting the driving object of the driving module from current overcurrent. For example, when the driving object is a power device as a power module, protection of the input current of the power device from current overcurrent can be achieved. Furthermore, in the drive circuit provided herein, the current sampled by the current sampling module represents the input current of the drive module's driven object, i.e., the actual current. This eliminates the risk of false alarms and false triggering in the drive circuit provided herein. Furthermore, if the current sampling module lacks a latching function for the first overcurrent notification signal, the latching module can latch the first overcurrent notification signal. This prevents the drive module from constantly switching between enabling and disabling, potentially leading to overheating and explosion of power tubes in the drive module's driven object, for example.

[0064] Other features and advantages of the present application will become apparent from the following detailed description of exemplary embodiments of the present application with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the application and, together with the description, serve to explain the principles of the application.

[0066] Figure 1 This is a schematic diagram of the structure of a driving circuit provided by this application. Figure 1 ;

[0067] Figure 2 This is a schematic diagram of the drive circuit provided by the user. Figure 2 ;

[0068] Figure 3 This is a schematic diagram of the drive circuit provided by the user. Figure 3 ;

[0069] Reference numerals:

[0070] 100-driving module; 101-current sampling module; 102-first control module;

[0071] 1021 - first power supply; 1022 - first pull-up resistor; 1023 - AND gate circuit;

[0072] 103-latch module; 1031-unidirectional conduction unit; 1032-second power supply;

[0073] 1033 - second pull-up resistor; 1034 - first NAND gate circuit; 1035 - third pull-up resistor;

[0074] 1036 - a third power supply; 1037 - a second NAND gate circuit; 1038 - a filter capacitor;

[0075] 104 - second control module; 200 - drive module. DETAILED DESCRIPTION

[0076] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present application.

[0077] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0078] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0079] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0080] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0081] In motor controller technology, once an overcurrent occurs in a power transistor, the driver chip must be quickly deactivated to quickly shut down the transistor, as the device can withstand the overcurrent for a relatively short time. However, the driver chip is typically controlled by the control chip within the motor controller. After receiving the overcurrent signal from the current sampling module, the control chip (DSP) takes much longer to process than the device can withstand the overcurrent. Therefore, an additional path is needed to quickly deactivate the driver chip.

[0082] In the related art, there are also some solutions that can control the driver chip to quickly stop and enable, but new technical problems have arisen. Specifically, the current sampling module that samples the input current of the power tube does not have a latching function. As a result, when the power tube is overcurrent, when the output signal of the current sampling module frequently switches between indicating overcurrent and no overcurrent, the driver chip will also frequently switch between stopping and enabling, causing the power tube to frequently switch between on and off. In this way, the power tube may explode due to frequent switching, which may cause the motor controller to burn out.

[0083] To solve the above problems, the present application provides a driving circuit 100, such as Figure 1 As shown, it includes: a current sampling module 101, a latch module 103 and a first control module 102, wherein:

[0084] The first output terminal of the current sampling module 101 is connected to the first input terminal of the latch module 103;

[0085] The output terminal of the latch module 103 is connected to the first input terminal of the first control module 102;

[0086] The output terminal of the first control module 102 is connected to the enable terminal of the driving module 200;

[0087] The current sampling module 101 is used to collect the current value of the input current of the driving object of the driving module 200, and output a first overcurrent notification signal through the first output terminal of the current sampling module 101 when it is determined that the input current is overcurrent;

[0088] The latch module 103 is configured to output a second overcurrent notification signal to the first control module 102 upon receiving the first overcurrent notification signal, wherein the second overcurrent notification signal is a latch signal for the first overcurrent notification signal;

[0089] The first control module 102 is configured to control the driving module 200 to stop being enabled when receiving the second over-current notification signal.

[0090] In this embodiment, the current sampling module 101 is used to collect the current value of the input current of the drive object of the driver module 200. In one example, the driver module 200 is specifically a driver chip serving as the drive object, wherein the drive object can be a power module, which includes power transistors, and the power transistors can be IGBTs. The power module can be specifically a three-phase full-bridge inverter circuit. The current on the DC bus passes through the three-phase full-bridge inverter circuit to form a three-phase current. This three-phase current is input to the three-phase windings of the motor. The three-phase windings of the motor generate a three-phase magnetic field, which drives the motor. On this basis, the input end of the current sampling module 101 is connected to the DC bus current output end to collect the current value of the current on the DC bus. When the driver circuit provided in the application determines that the current on the DC bus is overcurrent, it controls the driver chip to stop enabling, thereby stopping the drive of the three-phase full-bridge inverter circuit, thereby preventing the overcurrent current on the DC bus from entering the three-phase full-bridge inverter circuit and causing damage to the three-phase full-bridge inverter circuit.

[0091] After collecting the input current value, the current sampling module 101 compares the collected current value with a pre-stored preset current value, where the preset current value is the maximum current value when the input current is not overcurrent. If the collected current value is less than or equal to the preset current value, the input current is determined to be undercurrent. Conversely, if the collected current value is greater than the preset current value, the input current is determined to be overcurrent. If the input current is determined to be overcurrent, a first overcurrent notification signal is output through the first output terminal of the current sampling module 101. Based on this, the latch module 103 receives the first overcurrent notification signal.

[0092] After receiving the first overcurrent notification signal, the latch module 103 determines that the input current is overcurrent. At this time, the first overcurrent notification signal is latched to obtain a second overcurrent notification signal. Thereafter, the second overcurrent notification signal is output to the first control module 102.

[0093] After receiving the third over-current notification signal, the first control module 102 controls the driving module 200 to stop being enabled.

[0094] Based on the above, it can be seen that the drive circuit provided by the present application can disable the driver module 200 when the input current of the drive object of the driver module 200 overcurrents, thereby protecting the drive object of the driver module from overcurrent. For example, when the drive object is a power device as a power module, the input current of the power tube device can be protected from overcurrent. In addition, on the one hand, in the drive circuit 100 provided by the present application, the current collected by the current sampling module 101 is the input current of the drive object of the driver module, that is, the actual current, which makes the drive circuit provided by the present application free from problems such as false alarms and false triggers. On the other hand, when the current sampling module 101 does not have a latching function for the first overcurrent notification signal, the latching module 103 can latch the first overcurrent notification signal. This can avoid the occurrence of problems such as overheating and bursting of power tubes in the drive object of the driver module 200 caused by the driver module 200 constantly switching between enabling and disabling.

[0095] The present application provides a driving circuit, comprising: a current sampling module, a latch module, and a second control module, wherein: a first output terminal of the current sampling module is connected to a first input terminal of the latch module; an output terminal of the latch module is connected to a second input terminal of the second control module; and an output terminal of the second control module is connected to an enable terminal of the driving module; wherein the current sampling module is used to collect the current value of the input current of the driving object of the driving module, and output a first overcurrent notification signal through the first output terminal of the current sampling module when determining that the input current is overcurrent; the latch module is used to output a second overcurrent notification signal to the second control module when receiving the first overcurrent notification signal, wherein the second overcurrent notification signal is a latch signal for the first overcurrent notification signal; and the second control module is used to control the driving module to stop enabling when receiving the second overcurrent notification signal. The driving circuit provided by the present application can stop enabling the driving module when the input current of the driving object of the driving module is overcurrent, thereby protecting the driving object of the driving module from current overcurrent. For example, when the driving object is a power device as a power module, protection of the input current of the power device from current overcurrent can be achieved. Furthermore, in the drive circuit provided herein, the current sampled by the current sampling module represents the input current of the drive module's driven object, i.e., the actual current. This eliminates the risk of false alarms and false triggering in the drive circuit provided herein. Furthermore, if the current sampling module lacks a latching function for the first overcurrent notification signal, the latching module can latch the first overcurrent notification signal. This prevents the drive module from constantly switching between enabling and disabling, potentially leading to overheating and explosion of power tubes in the drive module's driven object, for example.

[0096] In one embodiment of the present application, in the above Figure 1 Based on the embodiment shown, Figure 2 As shown, the driving circuit provided by this application also includes:

[0097] The second control module 104 includes:

[0098] The first output terminal of the current sampling module 101 is connected to the first input terminal of the second control module 104;

[0099] The first output terminal of the second control module 104 is connected to the second input terminal of the first control module 102;

[0100] The second control module 104 is configured to output a third overcurrent notification signal to the first control module 102 upon receiving the first overcurrent notification signal;

[0101] The first control module 102 is configured to control the driving module 200 to stop being enabled when receiving at least one of the third over-current notification signal and the second over-current notification signal.

[0102] In this embodiment, after collecting the current value of the input current, the current sampling module 101 compares the collected current value with a pre-stored preset current value, where the preset current value is the maximum current value when the input current is not overcurrent. If the collected current value is less than or equal to the preset current value, it is determined that the input current is not overcurrent. Conversely, if the collected current value is greater than the preset current value, it is determined that the input current is overcurrent. If it is determined that the input current is overcurrent, a first overcurrent notification signal is output through the first output terminal of the current sampling module 101. Based on this, both the first control module 101 and the latch module 103 receive the first overcurrent notification signal.

[0103] After receiving the first overcurrent notification signal, the latch module 103 determines that the input current is overcurrent. At this time, the first overcurrent notification signal is latched to obtain a second overcurrent notification signal. Thereafter, the second overcurrent notification signal is output to the first control module 102.

[0104] After receiving the third over-current notification signal, the first control module 102 controls the driving module 200 to stop being enabled.

[0105] Furthermore, after receiving the first overcurrent notification signal, the second control module 104 determines that the input current is overcurrent. At this time, the second control module 104 outputs a third overcurrent notification signal to the first control module 102.

[0106] When receiving the second over-current notification, the first control module 102 controls the driving module 200 to stop being enabled again.

[0107] Based on the above, it can be seen that the driver circuit provided by the present application can disable the driver module 200 when the input current of the driver module 200's driven object overcurrents, thereby protecting the driver module's driven object from current overcurrent conditions. Furthermore, in the driver circuit 100 provided by the present application, the current sampled by the current sampling module 101 is the input current of the driver module's driven object, i.e., the actual current. This eliminates the problems of false alarms and false triggers in the driver circuit provided by the present application. Furthermore, if the current sampling module 101 does not have a latching function for the first overcurrent notification signal, the latch module 103 can latch the first overcurrent notification signal. This can prevent the driver module 200 from constantly switching between enabling and disabling, which could lead to overheating and explosion of power transistors in the driver module's driven object. Furthermore, by adding the latch module, the driver module can be controlled to disable more quickly in the event of an input current overcurrent, compared to the second control module 104, thereby preventing explosion of transistors in the driver module 200's driven object due to excessive input current. On the other hand, the second control module combines the two signals output by the first control module and the latch module, and inputs the combined signals into an enable pin of the driving module, thereby achieving dual control of the driving module.

[0108] In one embodiment of the present application, the latch module 103 outputs a second overcurrent notification signal to the first control module 102 at a first moment;

[0109] The second control module 104 outputs a third overcurrent notification signal to the first control module 102 at a second time, where the second time is later than the first time;

[0110] The first control module 102 is configured to control the driving module 200 to stop being enabled when receiving the second overcurrent notification signal;

[0111] The first control module 102 is configured to control the driving module 200 to stop being enabled again when receiving the third over-current notification signal.

[0112] For a detailed description of this embodiment, please refer to the previous embodiment. Furthermore, in this embodiment, the duration from the moment the current sampling module 101 samples the input current to the first moment is shorter than the duration of overcurrent that the driver module's driven object can tolerate. Thus, upon receiving the first overcurrent notification signal, the latch module 103 outputs the second overcurrent notification signal to the first control module 102 at the first moment. This ensures that the driven object is protected from damage caused by prolonged overcurrent input current, such as preventing the explosion of power transistors in the driven object caused by prolonged overcurrent.

[0113] In one example, the time duration from the moment the current sampling module 101 samples the input current to the first moment may be, for example, 1.61 μs. When the driven object includes an IGBT power transistor, the overcurrent duration that the driven object of the driving module can tolerate may be, for example, 3 μs.

[0114] In one embodiment of the present application, Figure 2 As shown, the second output terminal of the current sampling module 101 is connected to the second input terminal of the second control module 104. The current sampling module 101 is also used to convert the input current into a voltage signal and transmit the voltage signal to the second control module 104 through the second output terminal of the current sampling module 101;

[0115] The second control module 104 is configured to output a third overcurrent notification signal to the first control module 102 when it is determined at least according to the voltage signal that the input current is overcurrent.

[0116] In this embodiment, the current sampling module 101 also has the function of converting the input current into a proportional voltage signal. After the current sampling module 101 converts the input current into a proportional voltage signal, it transmits the converted voltage signal to the second control module 104 via its own second output terminal and the second input terminal of the second control module 104.

[0117] Upon receiving the voltage signal, the second control module 104 detects the voltage value of the voltage signal and compares the detected voltage value with a pre-stored preset voltage value. The preset voltage value is the maximum voltage value of the voltage signal converted by the current sampling module 101 when the input current is not overcurrent. If the detected voltage value is less than or equal to the preset voltage value, the input current is determined to be not overcurrent. In this case, the second control module 104 does not output the third overcurrent notification signal to the first control module 102.

[0118] On the contrary, if the detected voltage value is greater than the preset voltage value, it is determined that the input current is overcurrent. At this time, the second control module 104 outputs a third overcurrent notification signal to the first control module 102. That is, in this embodiment, whether the input current is overcurrent is determined based on whether the detected voltage value is greater than the preset voltage value. This is because the voltage signal detected by the first control signal is an analog quantity and has a low possibility of being interfered with. However, the signal output by the current sampling module 101 through its first output terminal, such as the first overcurrent notification signal, is a digital quantity and has a high possibility of being interfered with. That is, the second control module 104 is more accurate in determining whether the input current is overcurrent based on the voltage signal.

[0119] In this embodiment, the problems of false alarm and false triggering of the driving circuit caused by interference provided by the present application can be avoided.

[0120] In one embodiment of the present application, Figure 2 As shown, the second output terminal of the second control module 104 is connected to the second input terminal of the latch module 103;

[0121] The current sampling module 101 is further configured to output a first non-overcurrent notification signal through the first output terminal of the current sampling module 101 when it is determined that the input current is not overcurrent;

[0122] The second control module 104 is configured to output a reset signal to the latch module 103 and a second non-overcurrent notification signal to the first control module 102 upon receiving the first non-overcurrent notification signal;

[0123] The latch module 103 is configured to output a third non-overcurrent notification signal to the first control module 102 upon receiving the reset signal and the first non-overcurrent notification signal;

[0124] The first control module 102 is configured to control the driving module 200 to be enabled when receiving the third non-overcurrent notification signal and the second non-overcurrent notification signal.

[0125] In this embodiment, the current sampling module 101 determines that the input current is not overcurrent in two situations: situation one is that the input current itself is not overcurrent, and situation two is that after the input current is overcurrent, after the fault is cleared, the input current is restored from overcurrent to non-overcurrent.

[0126] When the current sampling module 101 determines that the input current is not overcurrent, it outputs a first non-overcurrent notification signal through the first output terminal of the current sampling module 101. At this time, the second control module 104 and the latch module 103 both receive the first non-overcurrent notification signal.

[0127] Upon receiving the first non-overcurrent notification signal, the second control module 104 outputs a reset signal to the latch module 103 and a second non-overcurrent notification signal to the first control module 102. Consequently, the latch module 103 receives the reset signal and the first control module 102 receives the second non-overcurrent notification signal.

[0128] When the latch module 103 receives the reset signal and the first non-overcurrent notification signal, the latch module 103 exits the latch state and outputs the third non-overcurrent notification signal to the first control module 102. Based on this, the first control module 102 receives the third non-overcurrent notification signal.

[0129] When the first control module 102 receives the second non-overcurrent notification signal and the third non-overcurrent notification signal, it determines that the input current is not overcurrent and controls the driving module 200 to be enabled.

[0130] In this embodiment, the driving circuit provided in this application can also control the driving module 200 to be enabled when the input current is not overcurrent, or is overcurrent but no longer overcurrent after the fault is cleared.

[0131] In one embodiment of the present application, the second output terminal of the second control module 104 is connected to the second input terminal of the latch module 103;

[0132] The current sampling module 101 is further configured to output a first non-overcurrent notification signal through the first output terminal of the current sampling module 101 when it is determined that the input current is not overcurrent;

[0133] The second control module 104 is configured to output a reset signal to the latch module 103 and a second non-overcurrent notification signal to the first control module 102 when it is determined according to the voltage signal that the input current is not overcurrent;

[0134] The latch module 103 is configured to output a third non-overcurrent notification signal to the first control module 102 upon receiving the reset signal and the first non-overcurrent notification signal;

[0135] The first control module 102 is configured to control the driving module 200 to be enabled upon receiving the third non-overcurrent notification signal and the second non-overcurrent notification signal.

[0136] Compared to the previous embodiment, in which the second control module 104 outputs a reset signal to the latch module 103 and a second non-overcurrent notification signal to the first control module 102 upon receiving the first non-overcurrent notification signal, in this embodiment, the second control module 104 outputs a reset signal to the latch module 103 and a second non-overcurrent notification signal to the first control module 102 upon determining that the input current is not overcurrent based on the voltage signal. In this way, the second control module 104 can more accurately determine whether the input current is overcurrent based on the voltage signal. On this basis, it can more accurately output a reset signal to the latch module 103 and a second non-overcurrent notification signal to the first control module 102.

[0137] In one embodiment of the present application, Figure 3 As shown, the first control module 102 includes: an AND gate circuit 1023, a first pull-up resistor 1022 and a first power supply 1021, wherein:

[0138] A first input terminal of the AND gate circuit 1023 is connected to the first output terminal of the second control module 104 and the first terminal of the first pull-up resistor 1022 respectively, a second input terminal of the AND gate circuit 1023 is connected to the output terminal of the latch module 103, and an output terminal of the AND gate circuit 1023 is connected to the enable terminal of the driving module 200;

[0139] The first power source 1021 is connected to the second end of the first pull-up resistor 1022 .

[0140] In this embodiment, the first power supply 1021 is a power supply that can provide a 5V voltage signal. Furthermore, this embodiment implements the first control module through an AND gate circuit 1023, which can combine the two signals output by the second control module 104 and the latch module 103 and input them to an enable pin of the driver module 200, thereby achieving dual control of the driver module 200. The first control module 102 has a simple structure and is easy to implement.

[0141] In one embodiment of the present application, the latch module 103 includes: a first NAND gate circuit 1034, a second NAND gate circuit 1037, a second pull-up resistor 1033, a second power supply 1032, a third pull-up resistor 1035, a third power supply 1036, and a unidirectional conduction unit 1031, wherein:

[0142] A first end of the unidirectional conducting unit 1031 is connected to the first output end of the current sampling module 101, and a second end of the unidirectional conducting unit 1031 is connected to the first input end of the first NAND gate circuit 1034. The conducting direction of the unidirectional conducting unit 1031 is the direction from the second end of the unidirectional conducting unit 1031 to the first end of the unidirectional conducting unit 1031.

[0143] The second input terminal of the first NAND gate circuit 1034 is connected to the output terminal of the second NAND gate circuit 1037 , and the output terminal of the first NAND gate circuit 1034 is connected to the first input terminal of the second NAND gate circuit 1037 ;

[0144] A first end of the second pull-up resistor 1033 is connected to the output end of the second power supply 1032 , and a second end of the second pull-up resistor 1033 is connected to the first input end and the ground end of the first NAND gate circuit 1034 , respectively.

[0145] The second input terminal of the second NAND gate circuit 1037 is connected to the second output terminal of the second control module 104 , and the output terminal of the second NAND gate circuit 1037 is connected to the first input terminal of the first control module 102 ;

[0146] The output end of the third power supply 1036 is connected to the output end of the second NAND gate circuit 1037 through the third pull-up resistor 1035 .

[0147] In this embodiment, the second power supply 1032 and the third power supply 1036 are a power supply that can provide a 5V voltage signal. In addition, this embodiment provides a structure of a latch module 103 that is simple and easy to implement.

[0148] In one embodiment of the present application, Figure 3As shown, the driving circuit provided by the present application further includes a filter capacitor 1038, wherein:

[0149] The second pull-up resistor 1033 is grounded via the filter capacitor 1038 .

[0150] In this embodiment, the interference signal can be filtered out by the filter capacitor 1038 , which enables the latch module 103 to receive the accurate signal output by the current sampling module.

[0151] In one embodiment of the present application, Figure 3 As shown, the unidirectional conducting unit 1031 is a diode, wherein:

[0152] The anode of the diode is connected to the first input terminal of the first NAND gate circuit 1034 , and the cathode of the diode is connected to the first output terminal of the current sampling module 101 .

[0153] In this embodiment, the unidirectional conducting unit 1031 is implemented by a diode, which is simple and easy to implement.

[0154] In one embodiment of the present application, in the driving circuit provided by the present application, the second control module 104 includes a first core and a second core, wherein:

[0155] The first core is connected to both the first output terminal of the current sampling module 101 and the second output terminal of the current sampling module 101 , and the first core is in communication connection with the second core;

[0156] The first core is configured to send an overcurrent check indication signal to the second core upon receiving a first overcurrent notification signal and / or determining that the driving current is overcurrent according to the voltage signal;

[0157] The second core is connected to both the first output terminal of the current sampling module 101 and the second output terminal of the current sampling module 101 , and the second core is connected to the first input terminal of the first control module 102 ;

[0158] When the second core receives the backcheck indication signal, it determines whether the first overcurrent notification signal is received, and determines whether the driving current is overcurrent based on the voltage signal. When the first overcurrent notification signal is received and the driving current is determined to be overcurrent based on the voltage signal, the second core sends a third overcurrent notification signal to the first control module 102.

[0159] In this embodiment, the first control module is implemented using a dual-core approach consisting of a first core and a second core. If the first core determines that the input current is overcurrent, it sends a checkback indication to the second core. Upon receiving the checkback indication, the second core rechecks whether the input current is overcurrent. This reduces the likelihood of processing errors in the first control module.

[0160] In one embodiment of the present application, Figure 2 As shown, the third output terminal of the second control module 104 is connected to the driving signal input terminal of the driving module 200, wherein:

[0161] The second control module 104 is configured to stop outputting the driving signal to the driving module 200 when outputting the third over-current notification signal.

[0162] In this embodiment, when the second control module 104 outputs the third overcurrent notification signal, it indicates that the input current is overcurrent. In this case, the second control module 104 stops outputting the drive signal to the driver module 200, thereby protecting the components in the driver module 200. The components in the driver module 200 are typically power devices, and the drive signal is typically a PWM signal.

[0163] by Figure 3 Taking the driving circuit shown as an example, the working principle of the driving circuit provided by this application is explained as follows.

[0164] If the current sampling module 101 determines that the input current is not overcurrent, the first output terminal of the current sampling module 101 outputs a high-level signal, which serves as the first non-overcurrent notification signal. Simultaneously, the current sampling module 101 converts the input current into a voltage signal and inputs it to the second control module 104. Based on this, the first input terminal of the second control module 104 receives the high-level signal, which serves as the first non-overcurrent notification signal, and the second input terminal of the second control module 104 receives the voltage signal. Based on the voltage signal, the second control module 104 determines that the input current is not overcurrent. At this point, the second control module 104 outputs a high-level reset signal to the second input terminal of the second NAND gate 1037 and inputs a high-level second non-overcurrent notification signal to the first input terminal of the AND gate 1023. Because the first output terminal of the current sampling module 101 is a high-level signal and the diode serving as the unidirectional conduction unit 1031 is present, the first input terminal of the first NAND gate 1034 is a high-level signal. The second input terminal of the second NAND gate 1037 is a high-level signal. The output of the second NAND gate 1037 is pulled up by a 5V third power supply 1036, so the second input to the first NAND gate 1034 also receives a high-level signal. The two high-level signals input to the first NAND gate 1034 output a low-level signal after passing through the first NAND gate 1034. Consequently, the first input to the second NAND gate 1037 receives a low-level signal. After a high-level signal and a low-level signal are input to the second NAND gate 1037, the second NAND gate 1037 outputs a high-level signal. The feedback between the first NAND gate 1034 and the second NAND gate 1037 is further strengthened, ensuring that the latch module 103 inputs the third non-overcurrent notification signal, which is a high-level signal, to the second input of the AND gate 1023. Simultaneously, the first output of the second control module 104 outputs the second non-overcurrent notification signal, which is a high-level signal. Since both inputs of the AND gate 1023 are high-level signals, it outputs a high-level signal to the driver module 200. When the enable signal of the driving module 200 is a high-level signal, the driving module 200 is allowed to operate normally.

[0165] Correspondingly, when the current sampling module 101 determines that the input current is overcurrent, the first output terminal of the current sampling module 101 outputs a low-level first overcurrent notification signal. Simultaneously, the current sampling module 101 converts the input current into a voltage signal and inputs it to the second control module 104. Based on this, the first input terminal of the second control module 104 receives the low-level signal as the first overcurrent notification signal, and the second input terminal of the second control module 104 receives the voltage signal. The second control module 104 determines that the input current is overcurrent based on the voltage signal. At this point, the high-level signal input to the first input terminal of the first NAND gate 1034 becomes the low-level first overcurrent notification signal. After passing through the first NAND gate 1034, the high-level signal and the low-level signal are output as a high-level signal. At this point, two high-level signals are input to the second NAND gate 1037, which then become low-level signals after passing through the second NAND gate 1037. When the output of the second NAND gate 1037 is low, the external 5V pull-up signal from the third power supply 1036 ceases to function, and the second input terminal of the AND gate 1023 becomes a low-level signal, which serves as the second overcurrent notification signal. After the AND gate 1023 performs the calculation, the output is low. At this point, the enable pin of the driver module 200 becomes a low-level signal, and the driver module 200 ceases operation. Simultaneously, after receiving the low-level signal serving as the first overcurrent notification signal, the first core of the second control module 104 instructs the second core to recheck and determine whether the input current is overcurrent. If the second core determines that there is an overcurrent, the second control module 104 outputs a low-level third overcurrent notification signal. At this point, the first input terminal of the AND gate 1023 receives the low-level third overcurrent notification signal, causing the enable pin of the driver module 200 to remain low, and the driver module 200 ceases operation.

[0166] After the input current recovers from an overcurrent state, the first overcurrent notification signal output by the current sampling module 101 switches to a first non-overcurrent notification signal. At this point, the first input terminal of the first NAND gate 1034 returns to a high-level signal. However, the output signal of the second NAND gate 1037 remains a low-level signal, and the second input terminal fed back to the first NAND gate 1034 is a low-level signal. At this point, the first NAND gate 1034 outputs a high-level signal, and the first input terminal input to the second NAND gate 1037 is a high-level signal. The high-level reset signal output by the second control module 104 changes from a high-level signal to a low-level second non-overcurrent notification signal. The driver circuit 100 provided in the present application enters reset mode, and the output of the second NAND gate 1037 becomes a high-level signal.

[0167] It should be noted that Figure 3In the example, the voltage value of the first power source 1021, the second power source 1032, and the third power source 1036 is 5V. Of course, the voltage values of the first power source 1021, the second power source 1032, and the third power source 1036 are not limited to 5V. For example, they can also be any of 3.3V, 5V, and 12V. Furthermore, the voltage values of the first power source 1021, the second power source 1032, and the third power source 1036 can be different.

[0168] Furthermore, the low-level and high-level signals in the above examples are relative. That is, the high-level and low-level signals do not involve specific voltage ranges; the voltage value of the high-level signal is higher than the voltage value of the low-level signal. For example, the voltage value corresponding to the high-level signal, which serves as the first non-overcurrent notification signal, is greater than 50% of the voltage value of the second power supply 1032. Correspondingly, the voltage value corresponding to the low-level first overcurrent notification signal is less than 50% of the voltage value of the second power supply 1032. Similarly, the voltage value corresponding to the high-level reset signal is greater than 50% of the voltage value of the third power supply 1036. The voltage value corresponding to the high-level second non-overcurrent notification signal is greater than 50% of the voltage value of the first power supply 1021. The voltage value corresponding to the low-level second overcurrent notification signal is less than 50% of the voltage value of the third power supply 1036. The voltage value corresponding to the high-level third non-overcurrent notification signal is greater than 50% of the voltage value of the third power supply 1036. The voltage value corresponding to the low-level third overcurrent notification signal is less than 50% of the voltage value of the first power supply 1021.

[0169] The present application also provides an electronic device, which includes the driving circuit provided by any of the above embodiments.

[0170] The present application also provides a motor controller, comprising: a current sensor, a control chip, a driver chip, and a latch, wherein:

[0171] The first output terminal of the current sensor is connected to the first input terminal of the latch;

[0172] The output terminal of the latch is connected to the first input terminal of the control chip;

[0173] The output terminal of the control chip is connected to the enable terminal of the driver chip;

[0174] The current sensor collects the current value of the input current of the driving object of the driving chip, and outputs a first overcurrent notification signal through the first output terminal of the current sensor when it is determined that the input current is overcurrent;

[0175] When the latch receives the first overcurrent notification signal, it outputs a second overcurrent notification signal to the control chip, where the second overcurrent notification signal is a latch signal for the first overcurrent notification signal;

[0176] When the control chip receives the second over-current notification signal, it controls the driving chip to stop being enabled.

[0177] It should be noted that the specific implementation of the current sensor in this embodiment is the same as the specific implementation of the current sampling module in any of the above-mentioned drive circuit embodiments, the specific implementation of the control chip in this embodiment is the same as the specific implementation of the first control module in any of the above-mentioned drive circuit embodiments, the specific implementation of the latch in this embodiment is the same as the specific implementation of the latch module in any of the above-mentioned drive circuit embodiments, and the specific implementation of the drive chip in this embodiment is the same as the specific implementation of the drive module in any of the above-mentioned drive circuit embodiments, which will not be repeated here.

[0178] In one example, the controller may be specifically a motor controller. On this basis, the driving chip may be specifically a driving chip in the motor controller. The driving object may be a power module in the motor controller. The power module includes a power tube, which may be an IGBT.

[0179] The present application also provides a vehicle, which includes the controller provided by the above controller embodiment. Alternatively, the vehicle includes the drive circuit provided by any of the above drive circuit embodiments.

[0180] The embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein. The scope of this application is defined by the appended claims.

Claims

1. A driving circuit (100), characterized in that: include: A current sampling module (101), a latch module (103) and a first control module (102), wherein: The first output end of the current sampling module (101) is connected to the first input end of the latch module (103); The output end of the latch module (103) is connected to the first input end of the first control module (102); The output end of the first control module (102) is connected to the enable end of the driving module (200); The current sampling module (101) is used to collect the current value of the input current of the driving object of the driving module (200), and output a first overcurrent notification signal through the first output terminal of the current sampling module (101) when it is determined that the input current is overcurrent; The latch module (103) is used to output a second overcurrent notification signal to the first control module (102) when receiving the first overcurrent notification signal, wherein the second overcurrent notification signal is a latch signal for the first overcurrent notification signal; The first control module (102) is used for controlling the driving module (200) to stop being enabled when the second overcurrent notification signal is received.

2. The driving circuit according to claim 1, wherein: The driving circuit further comprises: a second control module (104), wherein: The first output end of the current sampling module (101) is connected to the first input end of the second control module (104); The first output end of the second control module (104) is connected to the second input end of the first control module (102); The second control module (104) is configured to output a third overcurrent notification signal to the first control module (102) upon receiving the first overcurrent notification signal; The first control module (102) is used for controlling the driving module (200) to stop being enabled when at least one of the third overcurrent notification signal and the second overcurrent notification signal is received.

3. The driving circuit according to claim 2, wherein: The latch module (103) outputs the second overcurrent notification signal to the first control module (102) at a first moment; The second control module (104) outputs the third overcurrent notification signal to the first control module (102) at a second moment; the second moment is later than the first moment; The first control module (102) is used to control the driving module (200) to stop being enabled when receiving the second overcurrent notification signal; The first control module (102) is used for controlling the driving module (200) to stop being enabled again when the third overcurrent notification signal is received.

4. The driving circuit according to claim 2, wherein: The second output end of the current sampling module (101) is connected to the second input end of the second control module (104); the current sampling module (101) is further used to convert the input current into a voltage signal, and transmit the voltage signal to the second control module (104) through the second output end of the current sampling module (101); The second control module (104) is configured to output a third overcurrent notification signal to the first control module (102) when it is determined at least based on the voltage signal that the input current is overcurrent.

5. The driving circuit according to claim 2, wherein: The second output end of the second control module (104) is connected to the second input end of the latch module (103); The current sampling module (101) is further configured to output a first non-overcurrent notification signal through a first output terminal of the current sampling module (101) when it is determined that the input current is not overcurrent; Upon receiving the first non-overcurrent notification signal, the second control module (104) outputs a reset signal to the latch module (103) and outputs a second non-overcurrent notification signal to the first control module (102); The latch module (103) is used to output a third non-overcurrent notification signal to the first control module (102) when receiving the reset signal and the first non-overcurrent notification signal; The first control module (102) is used to control the driving module (200) to be enabled when receiving the third non-overcurrent notification signal and the second non-overcurrent notification signal.

6. The driving circuit according to claim 4, wherein: The second output end of the second control module (104) is connected to the second input end of the latch module (103); The current sampling module (101) is further configured to output a first non-overcurrent notification signal through a first output terminal of the current sampling module (101) when it is determined that the input current is not overcurrent; The second control module (104) is configured to output a reset signal to the latch module (103) and a second non-overcurrent notification signal to the first control module (102) when it is determined based on the voltage signal that the input current is not overcurrent; The latch module (103) is used to output a third non-overcurrent notification signal to the first control module (102) when receiving the reset signal and the first non-overcurrent notification signal; The first control module (102) is used to control the driving module (200) to be enabled when receiving the third non-overcurrent notification signal and the second non-overcurrent notification signal.

7. The driving circuit according to claim 2, wherein: The first control module (102) comprises: an AND gate circuit (1023), a first pull-up resistor (1022) and a first power supply (1021), wherein: The first input end of the AND gate circuit (1023) is respectively connected to the first output end of the second control module (104) and the first end of the first pull-up resistor (1022); the second input end of the AND gate circuit (1023) is connected to the output end of the latch module (103); and the output end of the AND gate circuit (1023) is connected to the enable end of the driving module (200); The first power source (1022) is connected to the second end of the first pull-up resistor (1022).

8. The driving circuit according to claim 2, wherein: The latch module (103) comprises: a first NAND gate circuit (1034), a second NAND gate circuit (1037), a second pull-up resistor (1033), a second power supply (1032), a third pull-up resistor (1035), a third power supply (1036), and a unidirectional conduction unit (1031), wherein: The first end of the one-way conducting unit (1031) is connected to the first output end of the current sampling module (101), the second end of the one-way conducting unit (1031) is connected to the first input end of the first NAND gate circuit (1034), and the conducting direction of the one-way conducting unit (1031) is the direction in which the second end of the one-way conducting unit (1031) points to the first end of the one-way conducting unit (1031); The second input terminal of the first NAND gate circuit (1034) is connected to the output terminal of the second NAND gate circuit (1037), and the output terminal of the first NAND gate circuit (1034) is connected to the first input terminal of the second NAND gate circuit (1037); The first end of the second pull-up resistor (1033) is connected to the second power supply (1032), and the second end of the second pull-up resistor (1033) is respectively connected to the first input end and the ground end of the first NAND gate circuit (1034); The second input end of the second NAND gate circuit (1037) is connected to the second output end of the second control module (104), and the output end of the second NAND gate circuit (1037) is connected to the first input end of the first control module (102); The third power supply (1036) is connected to the output end of the second NAND gate circuit (1037) via the third pull-up resistor (1035).

9. The driving circuit according to claim 8, characterized in that: The driving circuit further comprises: a filter capacitor (1038), wherein: The second pull-up resistor (1033) is grounded via the filter capacitor (1038).

10. The driving circuit according to claim 8, wherein: The one-way conducting unit (1031) is a diode, wherein: The anode of the diode is connected to the first input end of the first NAND gate circuit (1034), and the cathode of the diode is connected to the first output end of the current sampling module (101).

11. The driving circuit according to claim 4, wherein: The second control module (104) comprises a first core and a second core, wherein: The first core is connected to both the first output end of the current sampling module (101) and the second output end of the current sampling module (101), and the first core is in communication connection with the second core; The first core is configured to send an overcurrent check indication signal to the second core upon receiving the first overcurrent notification signal and / or determining that the driving current is overcurrent according to the voltage signal; The second core is connected to both the first output end of the current sampling module (101) and the second output end of the current sampling module (101), and the second core is connected to the first input end of the first control module (102); When the second core receives the check indication signal, it determines whether the first overcurrent notification signal is received, and determines whether the driving current is overcurrent based on the voltage signal. When the second core receives the first overcurrent notification signal and determines that the driving current is overcurrent based on the voltage signal, the second core sends a third overcurrent notification signal to the first control module (102).

12. The driving circuit according to claim 2, wherein: The third output terminal of the second control module (104) is connected to the driving signal input terminal of the driving module (200), wherein: The second control module (104) stops outputting the driving signal to the driving module (200) when outputting the third overcurrent notification signal.

13. A controller, characterized in that: include: Current sensor, control chip, driver chip, latch, including: The first output terminal of the current sensor is connected to the first input terminal of the latch; The output terminal of the latch is connected to the first input terminal of the control chip; The output terminal of the control chip is connected to the enable terminal of the driver chip; The current sensor collects the current value of the input current of the driving object of the driving chip, and outputs a first overcurrent notification signal through the first output terminal of the current sensor when it is determined that the input current is overcurrent; The latch outputs a second overcurrent notification signal to the control chip when receiving the first overcurrent notification signal, wherein the second overcurrent notification signal is a latch signal for the first overcurrent notification signal; When the control chip receives the second overcurrent notification signal, it controls the driving chip to stop being enabled.

14. A vehicle, characterized in that: comprising a driving circuit as claimed in any one of claims 1 to 12; Alternatively, comprising the controller as claimed in claim 13.

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