High-speed cross-voltage domain level conversion method and circuit

Abstract

The invention discloses a high-speed cross-voltage-domain level conversion method and circuit, and belongs to the technical field of signal processing, and the level conversion method comprises the steps: obtaining an input signal; performing level shift on the input signal to obtain a first signal, and performing level shift on the input signal after phase inversion to obtain a second signal; the first signal is delayed by a first time compared with the input signal, and the second signal is delayed by the first time compared with the input signal; and determining an output signal according to the first signal and the second signal. When level shifting is carried out on a level signal, duty ratio adjustment does not need to be carried out on the signal, an output signal consistent with the duty ratio of the input signal can be generated by carrying out delay on the input signal, carrying out phase inversion and then carrying out delay, and combining the generated two groups of signals.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a high-speed cross-voltage domain level conversion method and circuit. Background Art

[0002] Level shifting circuits are widely used in communications equipment, computers, audio devices, and other fields. They can convert high-voltage signals into low-voltage signals, or vice versa. However, signal level conversion using level shifting circuits is susceptible to external factors such as voltage, process, and temperature, resulting in the inability to maintain the signal's duty cycle after level conversion.

[0003] The current solutions to this problem are mainly to add a duty cycle adjustment circuit to the level conversion circuit or to adjust the duty cycle of the output signal after the level conversion. However, the implementation of these two methods is relatively complex and requires the design of a corresponding duty cycle control circuit. Summary of the Invention

[0004] One of the objectives of the present invention is to provide a high-speed level conversion method across voltage domains to solve the technical problem that the level conversion method in the prior art requires direct adjustment of the duty cycle to maintain the consistency of the input and output duty cycles, resulting in high implementation difficulty and complex processing process.

[0005] One of the objectives of the present invention is to provide a high-speed cross-voltage domain level conversion circuit.

[0006] To achieve one of the above-mentioned objectives, an embodiment of the present invention provides a high-speed level conversion method across voltage domains. The high-speed level conversion method across voltage domains includes: Get input signal; Performing level shifting on the input signal to obtain a first signal, and inverting the input signal and then performing level shifting on the input signal to obtain a second signal; the first signal is delayed by a first time compared to the input signal, and the second signal is delayed by the first time compared to the input signal; An output signal is determined according to the first signal and the second signal.

[0007] As a further improvement of an embodiment of the present invention, determining an output signal according to the first signal and the second signal includes: The rising edge and the falling edge of the output signal are determined according to the first signal and the second signal.

[0008] As a further improvement of an embodiment of the present invention, determining an output signal according to the first signal and the second signal includes: The output signal is determined according to rising edges or falling edges of the first signal and the second signal.

[0009] As a further improvement of an embodiment of the present invention, determining an output signal according to the first signal and the second signal includes: triggering a rising edge of the output signal according to the rising edge of the first signal, and maintaining the output signal at a high level after the rising edge; The falling edge of the output signal is triggered according to the rising edge of the second signal, and the output signal is kept at a low level after the falling edge.

[0010] As a further improvement of an embodiment of the present invention, determining an output signal according to the first signal and the second signal further includes: Keeping the output signal at a high level after its rising edge, and keeping the high level segment potential of the output signal consistent with the high level segment potential of the first signal; The output signal is kept at a low level after its falling edge, and the low level segment potential of the output signal is kept consistent with the low level segment potential of the second signal.

[0011] To achieve one of the above-mentioned objectives, an embodiment of the present invention provides a high-speed cross-voltage domain level conversion circuit. The high-speed cross-voltage domain level conversion circuit includes: a level conversion module, configured to obtain an input signal, perform level shifting on the input signal to obtain a first signal, and invert the input signal and perform level shifting on the input signal to obtain a second signal; the first signal is delayed by a first time compared to the input signal, and the second signal is delayed by the first time compared to the input signal; An output module, wherein an input end of the output module is connected to an output end of the level conversion module, and is used to determine an output signal according to the first signal and the second signal.

[0012] As a further improvement of an embodiment of the present invention, the level conversion module includes: A first level conversion unit, configured to perform level conversion on the input signal to obtain a first signal; an inverter, configured to invert the input signal; A second level conversion unit, wherein the input end of the second level conversion unit is connected to the output end of the inverter; and is used to perform level shift on the output signal of the inverter to obtain a second signal.

[0013] As a further improvement of an embodiment of the present invention, the output module includes: a multiplexer, wherein an input end of the multiplexer is connected to an output end of the first level conversion unit and an output end of the second level conversion unit, and is configured to trigger generation of a rising edge or a falling edge of the output signal according to a rising edge or a falling edge of the first signal and the second signal; A latch, wherein the input end of the latch is connected to the output end of the multiplexer, and is used to keep the output signal at a high level after its rising edge and at a low level after its falling edge.

[0014] As a further improvement of an embodiment of the present invention, the multiplexer is further configured to: triggering the generation of a rising edge of the output signal according to the rising edge of the first signal; The falling edge of the output signal is generated according to the rising edge of the second signal.

[0015] As a further improvement of an embodiment of the present invention, the latch is further used for: Keeping the output signal at a high level after its rising edge, and keeping the high level segment potential of the output signal consistent with the high level segment potential of the first signal; The output signal is kept at a low level after its falling edge, and the low level segment potential of the output signal is kept consistent with the low level segment potential of the second signal.

[0016] Compared with the prior art, the present invention obtains two sets of opposite signals based on the input signal, which form a reference to each other, thereby retaining the original information of the input signal to the greatest extent; by delaying the two sets of opposite signals for the same time, the accompanying delay occurring in the level transfer stage can be utilized to achieve temporal comparison of the two sets of signals, and ultimately generate an output signal consistent with the duty cycle of the input signal based on the two sets of signals, effectively avoiding the design of directly adjusting the duty cycle, simplifying the steps in the method, and simplifying the structural configuration in the structural design corresponding to the method, thereby reducing costs and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the structure of a high-speed cross-voltage domain level conversion circuit according to an embodiment of the present invention; Figure 2 Schematic diagram of a high-speed cross-voltage domain level conversion circuit according to another embodiment of the present invention; Figure 3 A circuit diagram of a high-speed cross-voltage domain level conversion circuit according to an embodiment of the present invention; Figure 4 This is a flow chart of a high-speed cross-voltage domain level conversion method according to an embodiment of the present invention; Figure 5This is a flow chart of a high-speed cross-voltage domain level conversion method according to another embodiment of the present invention; Figure 6 A schematic diagram of input signal waveform changes according to an embodiment of the present invention; Figure 7 This is a flow chart of a high-speed cross-voltage domain level conversion method according to another embodiment of the present invention; Figure 8 FIG. 4 is a schematic diagram of an input signal waveform change according to another embodiment of the present invention. DETAILED DESCRIPTION

[0018] The present invention will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by those skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0019] It should be noted that the term "comprise" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements that are inherent to such process, method, article or apparatus.

[0020] Furthermore, the terms “first,” “second,” etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0021] like Figure 1 , an embodiment of the present invention provides a high-speed cross-voltage domain level conversion circuit.

[0022] The level conversion circuit can be implemented independently, for example, in the form of an integrated circuit in a control system, a communication system, or a power transmission system.

[0023] The level conversion circuit can also be prepared on a specific carrier and implemented in an integrated form.

[0024] In one embodiment, the carrier of the level conversion circuit may be a substrate, from which an independent integrated circuit chip may be manufactured.

[0025] In one embodiment, the carrier of the level conversion circuit may be a functional module, for example, may be integrated into a microcontroller unit (MCU).

[0026] When the level conversion circuit is integrated into the MCU, it usually exists in the form of an embedded module. These modules can be a series of specialized circuits inside the MCU, specifically including a level conversion module and an output module.

[0027] like Figure 1 As shown, the level conversion circuit includes a level conversion module 101.

[0028] The level conversion module 101 can be configured as a traditional level conversion circuit or a combination of an inverter and a traditional level conversion circuit. Traditional level conversion circuits include: diode level conversion circuits, transistor level conversion circuits, MOS tube level conversion circuits and level conversion chips.

[0029] The level conversion module 101 can be used to convert between voltage domains. For example, the level conversion module 101 is used to increase the input low-voltage domain signal to a high-voltage domain signal before outputting it; or for example, the level conversion module 101 is used to decrease the input high-voltage domain signal to a low-voltage domain signal before outputting it.

[0030] In the embodiment of the present invention, the level conversion module 101 is used to obtain an input signal; the level conversion module 101 is used to level-shift the input signal to obtain a first signal; and the level conversion module 101 is used to invert the input signal and then level-shift it to obtain a second signal.

[0031] The first signal is delayed by a first time compared to the input signal.

[0032] The second signal is delayed by a first time compared to the input signal.

[0033] In one embodiment, the input signal is a low voltage domain signal; in another embodiment, the input signal is a high voltage domain signal.

[0034] In one embodiment, inverting the input signal may be performing an inverting operation on the input signal; in another embodiment, inverting the input signal may be directly receiving a signal that is inverted to the input signal.

[0035] Level shifting is the process of converting signal levels between different voltage levels. Level shifting is used to ensure that circuits or components operating at different voltage standards can communicate correctly.

[0036] The first time is determined based on the configuration of the level conversion circuit or the level conversion module. In one embodiment, the first time is the time during which the level conversion circuit or the level conversion module actively delays the input signal. In another embodiment, the first time is a delay naturally occurring due to external factors, the configuration of the level conversion circuit itself, or the configuration of the level conversion module itself.

[0037] The level conversion circuit includes an output module 102 .

[0038] The input port of the output module 102 is connected to the output port of the level conversion module 101 .

[0039] The output module 102 can select an input signal as an output through a multiplexer and hold the output signal through a latch.

[0040] In the embodiment of the present invention, the output module 102 is configured to determine an output signal according to the first signal and the second signal.

[0041] In this way, the input signal is inverted to obtain two opposite signals, which are then level-shifted and delayed. The delayed signals are then recombined through the output module. In this way, the level conversion circuit can output a signal with the same duty cycle as the input signal, achieving the effect of keeping the signal duty cycle unchanged after level conversion.

[0042] In one embodiment, if Figure 1 As shown, the level conversion module 101 includes a first level conversion unit 1011 .

[0043] The first level conversion unit 1011 can be configured as a traditional level conversion circuit. Traditional level conversion circuits include: a diode level conversion circuit, a transistor level conversion circuit, a MOS transistor level conversion circuit, and a level conversion chip.

[0044] The input end of the first level conversion unit 1011 is coupled to the input signal, and the output end of the first level conversion unit 1011 is connected to the output module. The output of the first level conversion unit 1011 is used to form a group of inputs of the output module.

[0045] The first level conversion unit 1011 is configured to perform level conversion on an input signal to obtain a first signal.

[0046] The first signal is delayed by a first time compared to the input signal.

[0047] The level conversion module 101 includes a second level conversion unit 1013 .

[0048] The second level conversion unit 1013 can be configured as a traditional level conversion circuit. Traditional level conversion circuits include: a diode level conversion circuit, a transistor level conversion circuit, a MOS transistor level conversion circuit, and a level conversion chip.

[0049] In one embodiment, the first level conversion unit 1011 and the second level conversion unit 1013 have the same configuration to achieve the same delay (eg, the same first time delay).

[0050] In this embodiment, the first level conversion unit 1011 and the second level conversion unit 1013 are configured to be identical, thereby achieving a configuration in which the first signal is delayed by a first time compared to the input signal, and the second signal is delayed by the same first time compared to the input signal.

[0051] The input end of the second level conversion unit 1013 is coupled to the input signal, and the output end of the second level conversion unit 1013 is connected to the output module. The output of the second level conversion unit 1013 is used to form a group of inputs of the output module.

[0052] The second level conversion unit 1013 is used to invert the input signal and then perform level shift on the input signal to obtain a second signal.

[0053] The second signal is delayed by a first time compared to the input signal.

[0054] The level conversion module 101 includes an inverter 1012 .

[0055] An input terminal of the inverter 1012 is coupled to an input signal, and an output terminal of the inverter 1012 is connected to an input terminal of the second level conversion unit 1013 .

[0056] The inverter 1012 is used to invert the input signal.

[0057] The second level conversion unit 1013 is configured to perform level conversion on the output signal of the inverter 1012 to obtain a second signal.

[0058] The second signal is delayed by a first time compared to the input signal.

[0059] In one embodiment, Figure 2 As shown, the output end of the inverter 1012 is connected to the input end of the first level conversion unit 1011 .

[0060] If the input signals are two opposite signals, an inverter is not required, and the two opposite signals can be directly input into the first level conversion unit 1011 and the second level conversion unit 1013 respectively.

[0061] In this way, two opposite signals with the same delay can be obtained by processing the input signal through the inverter and the level conversion unit, which facilitates the subsequent output module to reorganize the signal.

[0062] In one embodiment, if Figure 1 As shown, the output module 102 includes a multiplexer 1021 .

[0063] The multiplexer 1021 may be configured as a two-to-one multiplexer.

[0064] An input end of the multiplexer 1021 is coupled to an output signal of the level conversion module, an output end of the multiplexer 1021 is connected to the latch 1022 , and the output of the multiplexer 1021 is used to form an input of the latch 1022 .

[0065] The multiplexer 1021 is configured to trigger the generation of a rising edge or a falling edge of an output signal according to the rising edge or the falling edge of the first signal and the second signal.

[0066] The output module 102 includes a latch 1022 .

[0067] Latch 1022 may be configured as an SR latch.

[0068] An input terminal of the latch 1022 is coupled to the output signal of the multiplexer 1021 , and an output terminal of the latch 1022 outputs a final output signal.

[0069] The latch 1022 is used to keep the output signal at a high level after the rising edge of the output signal.

[0070] The latch 1022 is used to keep the output signal at a low level after the falling edge of the output signal.

[0071] In a specific embodiment, the multiplexer 1021 is further configured to trigger the generation of a rising edge of the output signal according to the rising edge of the first signal.

[0072] In a specific embodiment, the multiplexer 1021 is further configured to trigger the generation of a falling edge of the output signal according to the rising edge of the second signal.

[0073] In a specific embodiment, the latch 1022 is further configured to: keep the output signal at a high level after its rising edge, and keep the high level segment potential of the output signal consistent with the high level segment potential of the first signal.

[0074] In a specific embodiment, the latch 1022 is further configured to: keep the output signal at a low level after its falling edge, and keep the low level segment potential of the output signal consistent with the low level segment potential of the second signal.

[0075] In this way, by reorganizing the output signal of the level conversion module, an output signal having a duty cycle consistent with the input signal can be obtained, and there is no need to add a duty cycle adjustment circuit, which is simple and convenient to implement.

[0076] In a specific embodiment, Figure 3 As shown, the configuration of the level conversion circuit specifically includes: an inverter, a first level conversion unit, a second level conversion unit, a multiplexer and a latch.

[0077] An input terminal of the first level conversion unit is coupled to an input signal, and an output terminal of the first level conversion unit is connected to the multiplexer.

[0078] An input terminal of the inverter is coupled to an input signal, and an output terminal of the inverter is connected to the second level conversion unit.

[0079] An input end of the second level conversion unit is coupled to an output signal of the inverter, and an output end of the second level conversion unit is connected to the multiplexer.

[0080] An input end of the multiplexer is coupled to an output signal of the first level conversion unit and an output signal of the second level conversion unit, and an output end of the multiplexer is connected to the latch.

[0081] The input end of the latch is coupled to the output signal of the multiplexer, and the output end of the latch outputs the final output signal.

[0082] The specific working principle of the circuit is as follows: The input signal is input into the level conversion circuit. In one embodiment, the input signal is divided into two paths. One input signal is inverted and then input into a level conversion unit for level conversion to obtain the second signal HV_SB; the other input signal is directly input into another level conversion unit for level conversion to obtain the first signal HV_SA.

[0083] In another embodiment, the input signal itself is two opposite signals, which are directly input into the first level conversion unit and the second level conversion unit respectively for level shifting to obtain the first signal HV_SA and the second signal HV_SB.

[0084] The first signal HV_SA and the second signal HV_SB are input into the multiplexer, and the multiplexer is connected to the high voltage domain power supply voltage VDDH and the high voltage domain reference ground VSSH to select and determine the signal output; then the frequency band of the multiplexer output signal is maintained by the latch to obtain the output signal. A multiplexer is a combinational logic circuit that selects and generates signal outputs based on multiple signal inputs. The multiplexer includes several switches that, under the influence of preset control signals, select specific signal inputs and couple them to output terminals. These switches then output high-level signals based on the high-voltage domain supply voltage VDDH and low-level signals based on the high-voltage domain reference ground VSSH.

[0085] The latch is configured as a bistable circuit with a memory function. It is used to temporarily store a signal to maintain a specific level state.

[0086] A latch can be constructed by cross-coupling two NOR gates to switch between two stable states: set (Q = 1) and reset (Q = 0).

[0087] It should be noted that the level conversion units used in the embodiment of the present invention may be of any type; the two groups of level conversion units may be of the same type or produce the same delay effect.

[0088] In some embodiments, the output module 102 is not limited to including a multiplexer and a latch that cooperate with each other. Other circuits having multiplexer and latch functions can also be alternatively implemented in the level conversion circuit provided by the present invention.

[0089] In the present invention, level shifting is performed by configuring two groups of level conversion units to implement the same delay on the input signal. Based on the fact that the two groups of level conversion units are in the same environment and are affected by the same external environment, no matter how the external influencing factors change, the performance of the overall circuit is not affected, thereby eliminating the influence of external factors on the circuit performance.

[0090] Since the level conversion unit generates the same delay for the two mutually inverted input signals, it is only necessary to reorganize the input signals after level shifting to keep the duty cycle of the output signal unchanged compared to the input signal, making circuit layout and practical application simpler and more convenient.

[0091] like Figure 4 , an embodiment of the present invention provides a high-speed level conversion method across voltage domains.

[0092] The level conversion method described in any of the following technical solutions can be implemented in the aforementioned level conversion circuit. The level conversion circuit described in any of the above technical solutions can serve as the basis for implementing the level conversion method described in the following technical solutions.

[0093] The level conversion method comprises: S101: Acquire an input signal.

[0094] In one embodiment, the acquired input signal may be a signal in the low-level domain to be converted to the high-level domain, or may be a signal in the high-level domain to be converted to the low-level domain.

[0095] S102 , performing level shifting on the input signal to obtain a first signal, and inverting the input signal and performing level shifting on the input signal to obtain a second signal.

[0096] The first signal is delayed by a first time compared to the input signal.

[0097] The second signal is delayed by the first time compared to the input signal.

[0098] In one embodiment, if Figure 1 and Figure 2 As shown, an inverter can be used to invert the input signal, and then the input signal and the inverted input signal are level-converted by two identical level conversion units, thereby achieving the same-directional level transfer and the same signal delay.

[0099] In another embodiment, two mutually opposite high-level signals may be obtained, or two mutually opposite low-level signals may be obtained. In this embodiment, the step of inverting the input signal and then performing level shifting in step S102 may be understood as performing level shifting on the inverted input signal.

[0100] The present invention does not limit the configuration of the level conversion units to be exactly the same. All level conversion units that can perform the same delay on the signal can be implemented in any technical solution provided by the present invention.

[0101] S103: Determine an output signal according to the first signal and the second signal.

[0102] In this way, through steps S101 - S103 , when the level signal is level-shifted, there is no need to adjust the duty cycle of the signal, and the output signal having the same duty cycle as the input signal can be generated by utilizing the delay of the two groups of signals.

[0103] In one embodiment, determining an output signal according to the first signal and the second signal includes: The rising edge and the falling edge of the output signal are determined according to the first signal and the second signal.

[0104] For example, the rising edge and falling edge of the output signal are determined according to information such as the rising edge, falling edge, duty cycle, duration of maintaining a high level or duration of maintaining a low level of the first signal and the second signal.

[0105] In one embodiment, determining an output signal according to the first signal and the second signal includes: The output signal is determined according to rising edges or falling edges of the first signal and the second signal.

[0106] For example, according to the rising edge or falling edge of the first signal and the second signal, information such as the rising edge, falling edge, duty cycle, duration of maintaining a high level, or duration of maintaining a low level of the output signal is determined.

[0107] In a specific embodiment, determining an output signal according to the first signal and the second signal includes: The rising edge and the falling edge of the output signal are determined according to the rising edge or the falling edge of the first signal and the second signal.

[0108] For example, the rising edge of the output signal is determined based on the rising edge of the first signal; for example, the rising edge of the output signal is determined based on the falling edge of the first signal; for example, the falling edge of the output signal is determined based on the rising edge of the first signal; for example, the falling edge of the output signal is determined based on the falling edge of the first signal.

[0109] For example, the rising edge of the output signal is determined based on the rising edge of the second signal; for example, the rising edge of the output signal is determined based on the falling edge of the second signal; for example, the falling edge of the output signal is determined based on the rising edge of the second signal; for example, the falling edge of the output signal is determined based on the falling edge of the second signal.

[0110] First embodiment like Figure 5 , an embodiment of the present invention provides a high-speed level conversion method across voltage domains.

[0111] The level conversion method comprises: S501, obtaining an input signal; S502, performing level shifting on the input signal to obtain a first signal, and inverting the input signal and performing level shifting on the input signal to obtain a second signal; S5031. Triggering a rising edge of the output signal according to the rising edge of the first signal, and maintaining the output signal at a high level after the rising edge; S5032. Trigger the generation of a falling edge of the output signal according to the rising edge of the second signal, and maintain the output signal at a low level after the falling edge.

[0112] In this way, the above steps S501-S5032 can ensure that the duty cycles of the input signal and the output signal are consistent, without the need to add a special step to adjust the duty cycle of the high voltage domain output signal. The operation is simple and convenient and is not affected by external factors.

[0113] In one embodiment, step S5031 includes: the high-level segment potential of the output signal is consistent with the high-level segment potential of the first signal. In this way, the level conversion of the high-level segment potential is achieved, and the conversion from the low voltage domain to the high voltage domain is achieved, or the conversion from the high voltage domain to the low voltage domain is achieved.

[0114] In one embodiment, step S5032 includes: the low-level segment potential of the output signal is consistent with the low-level segment potential of the second signal. In this way, the level conversion of the low-level segment potential is achieved, and the conversion from the low voltage domain to the high voltage domain is achieved, or the conversion from the high voltage domain to the low voltage domain is achieved.

[0115] Figure 6 The waveform change process of the input signal in the above steps S501-S5032 is shown, as well as the relationship between the rising edge and falling edge of the input signal and the rising edge and falling edge of the output signal.

[0116] The first signal HV_SA is a waveform of a signal obtained by level shifting the low-voltage domain input signal, and the second signal HV_SB is a waveform of a signal obtained by inverting the low-voltage domain input signal and level shifting it.

[0117] The rising edge of the low voltage domain input signal corresponds to the rising edge of the first signal, and the rising edge of the first signal corresponds to the rising edge of the high voltage domain output signal. The rising edge of the low voltage domain input signal corresponds to the rising edge of the high voltage domain output signal.

[0118] The falling edge of the low voltage domain input signal corresponds to the rising edge of the second signal, and the rising edge of the second signal corresponds to the falling edge of the high voltage domain output signal.

[0119] Based on the correspondence between the rising edge of the low voltage domain input signal and the rising edge of the high voltage domain output signal, and the correspondence between the falling edge of the low voltage domain input signal and the falling edge of the high voltage domain output signal, it is determined that the duty cycle of the low voltage domain input signal and the high voltage domain output signal are the same.

[0120] Second embodiment like Figure 7 , an embodiment of the present invention provides a high-speed level conversion method across voltage domains.

[0121] The level conversion method comprises: S701, obtaining an input signal; S702, performing level shifting on the input signal to obtain a first signal, and inverting the input signal and performing level shifting on the input signal to obtain a second signal; S7031. Triggering a falling edge of the output signal according to the falling edge of the first signal, and maintaining the output signal at a low level after the falling edge; S7032. Trigger a rising edge of the output signal according to the falling edge of the second signal, and keep the output signal at a high level after the rising edge.

[0122] In this way, the above steps S701-S7032 can ensure that the duty cycles of the input signal and the output signal are consistent, without the need to add a special step to adjust the duty cycle of the high voltage domain output signal. The operation is simple and convenient and is not affected by external factors.

[0123] In one embodiment, step S7031 includes: the low-level segment potential of the output signal is consistent with the low-level segment potential of the first signal.

[0124] In one embodiment, step S7032 includes: the high level segment potential of the output signal is consistent with the high level segment potential of the second signal.

[0125] Figure 8The waveform change process of the input signal in the above steps S701-S7032 and the relationship between the rising edge and falling edge of the input signal and the rising edge and falling edge of the output signal are shown.

[0126] The first signal HV_SA is a waveform of a signal obtained by level shifting the low-voltage domain input signal, and the second signal HV_SB is a waveform of a signal obtained by inverting the low-voltage domain input signal and level shifting it.

[0127] The falling edge of the low voltage domain input signal corresponds to the falling edge of the first signal, and the falling edge of the first signal corresponds to the falling edge of the high voltage domain output signal. The falling edge of the low voltage domain input signal corresponds to the falling edge of the high voltage domain output signal.

[0128] The rising edge of the low voltage domain input signal corresponds to the falling edge of the second signal, and the falling edge of the second signal corresponds to the rising edge of the high voltage domain output signal. The rising edge of the low voltage domain input signal corresponds to the rising edge of the high voltage domain output signal.

[0129] Based on the correspondence between the rising edge of the low voltage domain input signal and the rising edge of the high voltage domain output signal, and the correspondence between the falling edge of the low voltage domain input signal and the falling edge of the high voltage domain output signal, it is determined that the duty cycle of the low voltage domain input signal and the high voltage domain output signal are the same.

[0130] The high-speed cross-voltage domain level conversion method provided by the present invention does not require signal duty cycle adjustment when the level signal is level-shifted. By delaying the input signal and first inverting it and then delaying it, and combining the two sets of signals generated, an output signal with a duty cycle consistent with the input signal can be generated.

[0131] In a preferred embodiment of the present invention, a first signal is obtained by level-shifting the input signal while delaying it for a first time, and a second signal is obtained by inverting the input signal, then level-shifting it while delaying it for a first time; and a multiplexer output signal is determined based on the first and second signals. When the input signal is level-shifted, because the circuit delays are the same, or further, because the level-shifting units (or modules) used to delay and generate the first and second signals are the same, the present invention eliminates the need to adjust the signal's duty cycle. By combining the signals after passing through two level-shifting units with the same delay, an output signal with a duty cycle consistent with the input signal can be generated.

[0132] It should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation method can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0133] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A high-speed level conversion method across voltage domains, characterized in that: The high-speed cross-voltage domain level conversion method includes: Get input signal; Performing level shifting on the input signal to obtain a first signal, and inverting the input signal and then performing level shifting on the input signal to obtain a second signal; the first signal is delayed by a first time compared to the input signal, and the second signal is delayed by the first time compared to the input signal; determining an output signal according to the first signal and the second signal; The determining an output signal according to the first signal and the second signal includes: The rising edge of the output signal is generated according to the rising edge of the first signal, and the falling edge of the output signal is generated according to the rising edge of the second signal, or The falling edge of the output signal is triggered according to the falling edge of the first signal, and the rising edge of the output signal is triggered according to the falling edge of the second signal.

2. The high-speed cross-voltage domain level conversion method according to claim 1, characterized in that: The determining an output signal according to the first signal and the second signal includes: triggering a rising edge of the output signal according to the rising edge of the first signal, and maintaining the output signal at a high level after the rising edge; The falling edge of the output signal is triggered according to the rising edge of the second signal, and the output signal is kept at a low level after the falling edge.

3. The high-speed cross-voltage domain level conversion method according to claim 2, characterized in that: The determining an output signal according to the first signal and the second signal further includes: Keeping the output signal at a high level after its rising edge, and keeping the high level segment potential of the output signal consistent with the high level segment potential of the first signal; The output signal is kept at a low level after its falling edge, and the low level segment potential of the output signal is kept consistent with the low level segment potential of the second signal.

4. A high-speed cross-voltage domain level conversion circuit, characterized in that: The cross-voltage domain level conversion circuit includes: a level conversion module, configured to obtain an input signal, perform level shifting on the input signal to obtain a first signal, and invert the input signal and then perform level shifting on the input signal to obtain a second signal; the first signal is delayed by a first time compared to the input signal, and the second signal is delayed by the first time compared to the input signal; an output module, wherein the input end of the output module is connected to the output end of the level conversion module, and is configured to determine an output signal according to the first signal and the second signal; the output module comprises: A multiplexer, wherein the input end of the multiplexer is coupled to the output signal of the level conversion module, and is used to trigger the generation of a rising edge of the output signal according to the rising edge of the first signal, and to trigger the generation of a falling edge of the output signal according to the rising edge of the second signal, or to trigger the generation of a falling edge of the output signal according to the falling edge of the first signal, and to trigger the generation of a rising edge of the output signal according to the falling edge of the second signal.

5. The high-speed cross-voltage domain level conversion circuit according to claim 4, characterized in that: The level conversion module includes: A first level conversion unit, configured to perform level conversion on the input signal to obtain a first signal; an inverter, configured to invert the input signal; A second level conversion unit, wherein the input end of the second level conversion unit is connected to the output end of the inverter; and is used to perform level shift on the output signal of the inverter to obtain a second signal.

6. The high-speed cross-voltage domain level conversion circuit according to claim 5, characterized in that: The output module includes: A latch, wherein the input end of the latch is connected to the output end of the multiplexer, and is used to keep the output signal at a high level after its rising edge and at a low level after its falling edge.

7. The high-speed cross-voltage domain level conversion circuit according to claim 6, characterized in that: The latch is also used to: Keeping the output signal at a high level after its rising edge, and keeping the high level segment potential of the output signal consistent with the high level segment potential of the first signal; The output signal is kept at a low level after its falling edge, and the low level segment potential of the output signal is kept consistent with the low level segment potential of the second signal.

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