Charge compensation circuit, direct charge transfer circuit and digital-to-analog converter

Abstract

The application relates to a charge compensation circuit, a direct charge transfer circuit and a digital-to-analog converter. The charge compensation circuit comprises one or more compensation sub-circuits; the compensation sub-circuit comprises a first compensation switch and a charge buffer; a first end of the first compensation switch is used for accessing a first reference voltage or a second reference voltage of the direct charge transfer circuit; a second end of the first compensation switch is used for connecting a first differential output end of a full-differential operational amplifier of the direct charge transfer circuit; the first compensation switch is connected with the charge buffer, and the charge buffer is used for transmitting compensation charges obtained before and after the first compensation switch is closed to a second differential input end of the full-differential operational amplifier. The application can eliminate the charge injection effect of the direct charge transfer circuit, and effectively improve the SNDR performance of a Sigma-Delta digital-to-analog converter.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, and in particular to a charge compensation circuit, a direct charge transfer circuit, and a digital-to-analog converter. Background Technology

[0002] The basic structure of a multi-bit delta-sigma (Sigma-Delta) digital-to-analog converter (DAC) is a direct charge transfer stage (DCT), also known as a direct charge transfer circuit. If the operational amplifier (OPA) in the direct charge transfer circuit is an ideal amplifier, and all switches are ideal switches, then this DAC can achieve high SNDR (Signal-to-Noise and Distortion Ratio) performance. The high SNDR performance of multi-bit delta-sigma DACs is the main reason why this type of DAC is widely used in the audio field.

[0003] However, in practical DCT-DAC circuits, the limited bandwidth, slew rate, and low-frequency noise of the operational amplifier all degrade SNDR performance. The non-ideal factors of the switches in the circuit have a particularly significant impact on SNDR performance. Among the non-ideal factors of the switches, the most difficult to eliminate is channel charge injection, which originates from the absorption and release of channel charge at the instant the switch is turned on or off. How to eliminate charge injection in DCT-DAC circuits has become an urgent problem to be solved in the process of improving the performance of multi-bit ΔΣ digital-to-analog converters. Summary of the Invention

[0004] Therefore, it is necessary to provide a charge compensation circuit, a direct charge transfer circuit, and a digital-to-analog converter that can eliminate the charge injection effect of a direct charge transfer circuit.

[0005] In one embodiment, this application provides a charge compensation circuit applied to the direct charge transfer circuit of a Sigma-Delta digital-to-analog converter; the charge compensation circuit includes one or more compensation sub-circuits; the compensation sub-circuit includes a first compensation switch and a charge buffer;

[0006] The first terminal of the first compensation switch is used to connect to the first reference voltage or the second reference voltage of the direct charge transfer circuit; the second terminal of the first compensation switch is used to connect to the first differential output terminal of the fully differential operational amplifier of the direct charge transfer circuit.

[0007] The first compensation switch is connected to a charge buffer, which is used to transfer the compensation charge obtained before and after the first compensation switch is closed to the second differential input terminal of the fully differential operational amplifier; the compensation charge is used to cancel the injected charge generated by the switched capacitor subarray connected to the first differential input terminal in the direct charge transfer circuit; the number of compensation subcircuits is the same as the number of switched capacitor subarrays connected to the first differential input terminal.

[0008] In one embodiment, the compensation sub-circuit further includes a second compensation switch and a third compensation switch;

[0009] One end of the second compensation switch is used to connect to the second reference voltage, and the other end of the second compensation switch is connected to the first end of the first compensation switch.

[0010] One end of the third compensation switch is used to connect to the first reference voltage, and the other end of the third compensation switch is connected to the first end of the first compensation switch and the other end of the second compensation switch.

[0011] In one embodiment, the dimensions of both the second and third compensation switches are smaller than the dimensions of the first compensation switch.

[0012] In one embodiment, the charge buffer includes a first buffer switch; the charge compensation circuit further includes a fourth compensation switch;

[0013] One end of the fourth compensation switch is used to connect to the first differential output terminal, and the other end of the fourth compensation switch is connected to the second terminal of the first compensation switch;

[0014] One end of the first buffer switch is connected between the first end of the first compensation switch and the other end of the fourth compensation switch, and the other end of the first buffer switch is used to connect to the second differential input terminal.

[0015] In one embodiment, the size of both the first buffer switch and the fourth compensation switch is smaller than the size of the first compensation switch.

[0016] In one embodiment, the charge buffer includes a second buffer switch; the charge compensation circuit also includes a DC blocking capacitor;

[0017] One end of the second buffer switch is connected to the first end of the first compensation switch, and the other end of the second buffer switch is connected to one end of the DC blocking capacitor. The other end of the DC blocking capacitor is used to connect to the second differential input terminal.

[0018] In one embodiment, the size of the second buffer switch is smaller than the size of the first compensation switch.

[0019] Secondly, in one embodiment, this application provides a direct charge transfer circuit applied to a Sigma-Delta digital-to-analog converter; the direct charge transfer circuit includes: a first switched capacitor array, a second switched capacitor array, a fully differential operational amplifier, a first feedback capacitor, a second feedback capacitor, a first control switch, a second control switch, a third control switch, and a fourth control switch; the first switched capacitor array and the second switched capacitor array each include the same number of switched capacitor subarrays;

[0020] Each switched capacitor subarray in the first switched capacitor array is connected to the non-inverting input of the fully differential operational amplifier via a second control switch. One end of the first control switch is used to connect to the second reference voltage, and the other end of the first control switch is connected between each switched capacitor subarray in the first switched capacitor array and the second control switch. The first switched capacitor array is also connected to the inverting output of the fully differential operational amplifier, the first reference voltage, the second reference voltage, and the digital signal to be converted.

[0021] In the second switched capacitor array, each switched capacitor subarray is connected to the inverting input of the fully differential operational amplifier via a fourth control switch. One end of the third control switch is used to connect to the second reference voltage, and the other end of the third control switch is connected between each switched capacitor subarray in the second switched capacitor array and the fourth control switch. The second switched capacitor array is also connected to the non-inverting output of the fully differential operational amplifier, the first reference voltage, the second reference voltage, and the digital signal to be converted.

[0022] One end of the first feedback capacitor is connected to the non-inverting input terminal, and the other end of the first feedback capacitor is connected to the inverting output terminal; one end of the first feedback capacitor is connected to the inverting input terminal, and the other end of the first feedback capacitor is connected to the non-inverting output terminal.

[0023] The direct charge transfer circuit also includes two charge compensation circuits as described in any embodiment of the first aspect: one charge compensation circuit is connected to the non-inverting input terminal, and the other charge compensation circuit is connected to the inverting input terminal;

[0024] The charge compensation circuit connected to the inverting input terminal uses the non-inverting input terminal as the first differential input terminal and the inverting input terminal as the second differential input terminal; the charge compensation circuit connected to the non-inverting input terminal uses the inverting input terminal as the first differential input terminal and the non-inverting input terminal as the second differential input terminal.

[0025] In one embodiment, the switched capacitor subarray includes a first sampling switch, a second sampling switch, a third sampling switch, and an integrating capacitor;

[0026] One end of the first sampling switch is connected to the first reference voltage, and the other end of the first sampling switch is connected to one end of the integrating capacitor, the other end of the second sampling switch, and the other end of the third sampling switch, respectively.

[0027] One end of the second sampling switch is connected to the second reference voltage, and the other end of the second sampling switch is also connected to one end of the integrating capacitor and the other end of the third sampling switch;

[0028] When the switched capacitor subarray is connected to the non-inverting input terminal, one end of the third sampling switch is connected to the inverting output terminal, the other end of the third sampling switch is connected to one end of the integrating capacitor, and the other end of the integrating capacitor is connected to the non-inverting input terminal through the second control switch.

[0029] When the switched capacitor subarray is connected to the inverting input terminal, one end of the third sampling switch is connected to the non-inverting output terminal, the other end of the third sampling switch is connected to one end of the integrating capacitor, and the other end of the integrating capacitor is connected to the inverting input terminal through the fourth control switch.

[0030] Thirdly, in one embodiment, this application provides a digital-to-analog converter including a direct charge transfer circuit as described in any of the second aspect embodiments.

[0031] The aforementioned charge compensation circuit, direct charge transfer circuit, and digital-to-analog converter (DAC) all utilize a charge compensation circuit that obtains a compensation charge equal in magnitude to the injected charge generated by the switched capacitor subarray connected to the first differential input terminal in the direct charge transfer circuit via a first compensation switch in the compensation subcircuit. The compensation charge is then transferred to the second differential input terminal of the fully differential operational amplifier to cancel out the injected charge generated by the corresponding switched capacitor subarray, thereby effectively improving the SNDR performance of the Sigma-Delta DAC. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a conventional direct charge transfer circuit in one embodiment;

[0034] Figure 2 This is a schematic diagram of a charge compensation circuit in one embodiment;

[0035] Figure 3 This is the control timing of the first compensation switch of the P array in one embodiment;

[0036] Figure 4 This is the control timing sequence of the first compensation switch of the N array in one embodiment;

[0037] Figure 5 This is a schematic diagram of another charge compensation circuit in one embodiment;

[0038] Figure 6 This is a schematic diagram of another charge compensation circuit in one embodiment;

[0039] Figure 7 This is a schematic diagram of a direct charge transfer circuit in one embodiment;

[0040] Figure 8 This is a schematic diagram of another charge compensation circuit in one embodiment;

[0041] Figure 9 This is a schematic diagram of another direct charge transfer circuit in one embodiment;

[0042] Figure 10 This is a schematic diagram of another direct charge transfer circuit in one embodiment;

[0043] Figure 11 This is a schematic diagram of another direct charge transfer circuit in one embodiment. Detailed Implementation

[0044] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0046] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0047] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0048] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0049] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0050] For multi-bit Δ∑ digital-to-analog converters (i.e., multi-bit Sigma-Delta digital-to-analog converters), due to their small step size and low out-of-band noise power, their remaining power decreases exponentially with the number of bits N retained after truncation. Therefore, the switched capacitor filter circuit of this type of digital-to-analog converter can be implemented with a relatively simple structure.

[0051] Specifically, the basic structure of a multi-bit Sigma-Delta digital-to-analog converter (DAC) is a direct charge-transfer stage (or direct charge-transfer circuit). Understandably, if the operational amplifier (OPA) in the direct charge-transfer circuit is an ideal amplifier, and all switches are ideal switches, then the DAC can achieve a high signal-to-noise and distortion ratio (SNDR) performance. This is the main reason why Sigma-Delta DACs are widely used in the audio field.

[0052] However, in traditional DCT-DAC circuits, the limited bandwidth, slew rate, and low-frequency noise of the op-amp all reduce SNDR, and the non-ideal factors of the switches in the circuit have a particularly prominent impact on SNDR performance.

[0053] Non-ideal factors in switching include channel charge injection, harmonic distortion caused by clock feedthrough, and increased noise floor due to KT / C noise in the switching capacitor. Specifically, among these three non-ideal factors: KT / C noise is unavoidable and can only be reduced by increasing the area (i.e., increasing the capacitor plate size); although the clock feedthrough effect has a significant impact, it originates from the gate-drain and gate-source overlap capacitance of the MOS switch, which is fixed and independent of the bias voltage on both sides of the switch, resulting in a fixed offset error. This offset can be canceled out by PMOS and NMOS transmission gates (although there may be slight mismatch) or completely canceled out by a fully differential circuit; channel charge injection is the most difficult to eliminate, originating from the absorption and release of channel charge at the moment the switch is turned on or off. Current methods in the field to mitigate the above-mentioned charge injection effect include using dummy switches, CMOS complementary switches, parallel delay switches, or fully differential circuit structures.

[0054] However, in practical applications, none of the above methods can completely or significantly reduce the impact of charge injection. The main reason why the charge injection effect is difficult to eliminate is that channel charge is a function of parameters such as power supply voltage, signal voltage, and even the bulk effect coefficient. Even the impedance on both sides of the switch significantly affects the proportion of channel charge redistribution. Analyzing methods to mitigate the charge injection effect: dummy switches can only be used under the premise of equal channel charge distribution; CMOS complementary switches can only work with one input signal voltage (approximately half the power supply voltage); parallel delay switches can only reduce charge injection during switch-off, but not during switch-on; fully differential circuit structures can only eliminate fixed offsets, but cannot eliminate differential charge injection. Furthermore, while reducing the size of the MOS switch can reduce the injected charge, this also leads to a decrease in circuit speed.

[0055] To make the application scenarios, technical objectives, and advantages of the technical solutions of this application clearer, such as Figure 1 As shown, for Figure 1 The given traditional m-bit (2 m The direct charge transfer circuit 10 (=M) is analyzed. The specific analysis is as follows:

[0056] The operational amplifier OPA is a fully differential operational amplifier. The first feedback capacitor Cfbp and the second feedback capacitor Cfbn are the same feedback capacitor. The first switched capacitor array (i.e., P array) and the second switched capacitor array (i.e., N array) each include M switched capacitor subarrays.

[0057] Cpi and Cni represent the integrating capacitors in the i-th (i=1,2...M) switched capacitor subarray of the first and second switched capacitor arrays, respectively. All capacitors are of equal size and can be denoted as C0. S1pi, S2pi, and S3pi represent the three sampling switches in the i-th (i=1,2...M) switched capacitor subarray of array P: S1pi is the first sampling switch of array P, S2pi is the second sampling switch of array P, and S3pi is the third sampling switch of array P. Similarly, S1ni, S2ni, and S3ni represent the three switches in the i-th (i=1,2...M) switched capacitor subarray of array N: S1ni is the first sampling switch of array N, S2ni is the second sampling switch of array N, and S3ni is the third sampling switch of array N. It can be assumed that the signals on the left and right sides of the third sampling switch S3pi of array P are EPi and FPi, respectively, and the signals on the left and right sides of the third sampling switch S3ni of array N are ENi and FNi, respectively.

[0058] Furthermore, S4p and S5p are the first and second control switches of the P-terminal (i.e., the circuit on the non-inverting input side of the fully differential amplifier OPA, VINP), respectively, and are also the two master switches of the P-terminal circuit; S4n and S5n are the first and second control switches of the N-terminal (i.e., the circuit on the inverting input side of the fully differential amplifier OPA, VINN), respectively, and are also the two master switches of the N-terminal. The differential signals output by the fully differential operational amplifier OPA are VOUTP and VOUTN at the non-inverting and inverting output terminals, respectively.

[0059] like Figure 1 As shown, the node signals for capacitors Cpi and Cni in parallel are SUMP and SUMN, respectively, and the node signals for the OPA input are VINP and VINN, respectively. In the above DCT-DAC circuit, circuit control is mainly achieved using a clock signal divided into two phases; specifically, it uses a pair of differential clock signals with a phase difference of 180 degrees. and Perform DCT control. Furthermore, The slightly delayed signal is , The slightly delayed signal is The above and It is used to prevent S5p and S3pi, as well as S5n and S3ni, from being turned on and off simultaneously. In this way, the effect of charge injection of S5p and S5n can be eliminated. Figure 1 The VREFP and VREFN shown are the first reference voltage (i.e., the positive reference voltage) and the second reference voltage (i.e., the negative reference voltage), respectively. Figure 1DP1~DP shown M and DN1~DN M All are digital signals to be converted, DN1~DN M It is DP1~DP M The inverted signal. In practical applications, DP1~DP M It can represent the digital signal data output by the modulator.

[0060] The charge injection effects caused by multiple transfer gate switches in the above DCT are different: During the switching phase, the charge injection effect caused by S4p and S4n can be completely eliminated by the differential circuit structure of the DCT. Specifically, before and after the S4p and S4n switches are turned on and off, the voltages on their left and right sides remain VREFN, which actually manifests as common-mode interference that can be eliminated by the differential circuit. The charge injection effects caused by S1pi, S2pi, S1ni, and S2ni do not cause problems during the switching on process because these charges are directly absorbed by VREFP or VREFN. However, during the switching off process, since S4p and S4n have already been turned off in advance, the voltages on the right sides of Cpi and Cni will be reduced. The common points SUMP and SUMN are floating, causing most of the channel charge of the switch to be injected into the parasitic capacitance of the node to ground. Only a small portion of the charge can be injected into Cpi and Cni, causing a momentary jump in their differential voltage. This jump mainly depends on the ratio between the parasitic capacitance and the intrinsic capacitance, which is very small in practical applications. The charge injection effect caused by S5p and S5n can also be completely eliminated by the differential circuit. Before and after the S5p and S5n switches are turned on and off, the voltage on the left and right sides remains VREFN, so it also exhibits common-mode interference that can be eliminated by the differential circuit.

[0061] It is important to note that, in Figure 1 In the direct charge transfer circuit 10 shown, the switches that have the greatest impact on harmonic distortion due to charge injection are S3pi and S3ni, i.e., the third sampling switches. The specific analysis is as follows:

[0062] For the P array, S5p is already enabled before S3pi is enabled, at which point the voltage of SUMP is VREFN. Before the rising edge arrives, the node FPi to the left of Cpi has been charged to VREFP or VREFN, and the voltage of the node EPi to the left of the third sampling switch is VOUTP, which is a voltage that changes with the DAC output; At the rising edge, the S3pi switch opens, and the channels on both sides of the transmission gate switch need to absorb or release charge. Some charge is absorbed or released from VOUTP, and some is absorbed or released from the left plate of Cpi. Since VOUTP is the output of the operational amplifier and has very low impedance, its absorption or release of charge has little effect on VOUTP. However, the charge absorbed or released from the left plate of Cpi will cause a significant change in the charge on capacitor Cpi. Unfortunately, the charge absorbed or released from the left plate of Cpi is related to the voltage of the current node FPi to the left of Cpi (…). Before the arrival of the node, it is charged to either VREFP or VREFN, depending on the DP. i and DN i It is also related to the current VOUTP voltage (when S3pi is turned off to on, the voltages before and after are VREFP / VREFN and VOUTP, respectively, and the charge change is proportional to the voltage difference before and after).

[0063] For the N-array, S5n is already enabled before S3ni is enabled, at which point the voltage of SUMN is VREFN. Before the rising edge arrives, the left node FNi of Cni has been charged to VREFP or VREFN, and the voltage of the left node ENi of the third sampling switch is VOUTN, which is a voltage that changes with the DAC output; At the rising edge, the S3ni switch opens, and the channels on both sides of the transmission gate switch need to absorb or release charge. Some charge is absorbed or released from VOUTN, and some from the left plate of capacitor Cni. Since VOUTN is the output of the operational amplifier and has very low impedance, its absorption or release of charge has little effect on VOUTN; however, the charge absorbed or released from the left plate of capacitor Cni will cause a significant change in the charge on capacitor Cni. Unfortunately, the charge absorbed or released from the left plate of capacitor Cni is related to the voltage of the current node FNi to the left of Cni (…). Before the arrival of the node, it is charged to either VREFP or VREFN, depending on the DP. i and DN i It is also related to the current VOUTN voltage (when switch S3ni is turned off to on, the voltages before and after are VREFP / VREFN and VOUTN, respectively, and the charge change is proportional to the voltage difference before and after).

[0064] Since the charge injection effect of the third sampling switch is related not only to the current input DPi and DNi signals, but also to the current voltages of VOUTP and VOUTN, and the charge injection directions on the P side and the N side are opposite, the conventional direct charge transfer circuit 10 cannot eliminate the nonlinear charge injection effect of the switch through the differential circuit.

[0065] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. The specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0066] In one embodiment, such as Figure 2 As shown, this application provides a charge compensation circuit 20, which is applied to, for example... Figure 1 The Sigma-Delta digital-to-analog converter shown has a direct charge transfer circuit 10; the charge compensation circuit 10 includes one or more compensation sub-circuits 202; the compensation sub-circuit 202 includes a first compensation switch S3Ci and a charge buffer 204;

[0067] The first terminal APi of the first compensation switch S3Ci is used to connect to the second reference voltage VREFN or the second reference voltage of the direct charge transfer circuit 10; the second terminal BPi of the first compensation switch S3Ci is used to connect to the first differential output terminal VOUT1 of the fully differential operational amplifier OPA of the direct charge transfer circuit 10.

[0068] The first compensation switch S3Ci is connected to the charge buffer 204. The charge buffer 204 is used to transfer the compensation charge obtained before and after the first compensation switch S3Ci is closed to the second differential input terminal VIN2 of the fully differential operational amplifier OPA. The compensation charge is used to cancel the injected charge generated by the switched capacitor subarray connected to the first differential input terminal VIN1 in the direct charge transfer circuit 10. The number of compensation sub-circuits is the same as the number of switched capacitor subarrays connected to the first differential input terminal VIN1.

[0069] It is understandable that the compensation charge obtained before and after the first compensation switch S3Ci is closed is the charge absorbed or injected before and after the first compensation switch S3Ci is closed.

[0070] In some examples, the first compensation switch S3Ci can be the same as the third sampling switch ( Figure 1The transmission gate switches (S3pi and S3ni) are of the same size. In this embodiment, the switch size can be the width-to-length ratio of an NMOS or PMOS element. Furthermore, since the transmission gate switch does not distinguish between left and right polarities, the corresponding characteristic descriptions of the first terminal APi and the second terminal BPi of the first compensation switch S3Ci can actually be interchanged, and the interchanged situation has the same implementation principle as the original situation, which will not be repeated here.

[0071] In practical applications, when the first differential input terminal VIN1 is the non-inverting input terminal VINP of the fully differential operational amplifier OPA (i.e., the second terminal BPi of the first compensation switch S3Ci is connected to the non-inverting input terminal VINP), the first differential output terminal VOUT1 corresponds to the inverting output terminal VOUTP of the fully differential operational amplifier OPA; when the first differential input terminal VIN1 is the inverting input terminal VINN of the fully differential operational amplifier OPA (i.e., the second terminal BPi of the first compensation switch S3Ci is connected to the inverting input terminal VINN), the first differential output terminal VOUT1 corresponds to the non-inverting output terminal VOUTN of the fully differential operational amplifier OPA.

[0072] Specifically, the control timing of the charge compensation circuit in this application embodiment in practical applications is as follows: Figure 3 and Figure 4 As shown, the specific analysis is as follows:

[0073] For the circuit on the P-array side of the direct charge transfer circuit, the second terminal of the first compensation switch S3Cpi is connected to the non-inverting input terminal VINP of the fully differential operational amplifier OPA. The size of the first compensation switch S3Cpi is the same as that of the third sampling switch S3pi of the P-array.

[0074] During the charging phase of a direct charge transfer circuit, i.e. At this time, the third sampling switch S3pi of the P array is closed, causing the right-hand node FPi of the third sampling switch S3pi to be charged to VREFP or VREFN. The voltage of this right-hand node FPi actually depends on the input DP. i Signals and DN i Signal (DP i and DN i (Logical inversion), while the left node EPi of the third sampling switch S3pi of the P array is connected to the inverting output VOUTP of the fully differential operational amplifier.

[0075] Based on the operating status of the third sampling switch S3pi of the P array described above, such as Figure 3 As shown, Figure 3 The control timing for the first compensation switch S3Cpi of the P array. During the charging phase, the first compensation switch S3Cpi of the P array is opened, and the first terminal APi of the first compensation switch S3Cpi will be charged to the same voltage VREFP or VREFN as the right node FPi of the third sampling switch S3pi of the P array (depending on the input DP). i Signals and DN i (Signal); The second terminal BPi of the first compensation switch S3Cpi of the P array will be charged to the same voltage VOUTP as the left node EPi of the third sampling switch S3pi of the P array. In actual cases, the transmission gate switch does not distinguish between left and right polarities, and the left and right described above can be interchanged. Therefore, during the charging phase, the voltages of the two nodes of the first compensation switch S3Cpi of the P array and the voltages of the two nodes of the third sampling switch S3pi of the P array remain the same.

[0076] In the integration stage of a direct charge transfer circuit, i.e. When the third sampling switch S3pi of the P array is closed, the voltages at the right node FPi and the left node EPi of the third sampling switch S3pi are equal to the voltage VOUTP at the inverting output of the fully differential operational amplifier. At this time, the first compensation switch S3Cpi of the P array is also conducting. The voltages at the first terminal APi and the second terminal BPi of the first compensation switch S3Cpi are charged to VOUTP. Therefore, during the integration phase, the voltages at the nodes at the first and second terminals of the first compensation switch S3Cpi and the voltages at the left and right nodes of the third sampling switch S3pi remain the same. That is, before and after the third sampling switch of the P array is closed, the magnitudes of charge absorbed or injected by the first compensation switch S3Cpi and the third sampling switch S3pi are equal. The charge buffer 204 transfers the charge absorbed or injected before and after the first compensation switch S3Cpi is closed to the inverting input VINN of the fully differential operational amplifier OPA in a 1:1 ratio. Based on the foregoing analysis, it can be understood that the charge absorbed or injected before and after the third sampling switch S3pi of the P array is closed will be transferred to the SUMP node of the circuit, and will eventually be transferred to the non-inverting input terminal VINP of the fully differential operational amplifier (the two are short-circuited after S5p is closed). The first compensation switch S3Cpi of the P array will inject a charge of the same size into VINN. For the differential output VOUTP-VOUTN, the injected charge input from the non-inverting input terminal VINP and the compensation charge input from the inverting input terminal VINN are common-mode signals, which cannot affect the THD+N (Total Harmonic Distortion + Noise) and SNDR of the differential output signals VOUTP-VOUTN.

[0077] Based on the same principle described above, the compensation of injected charge in the N-array is analyzed. For the N-array side of the direct charge transfer circuit, the second terminal of the first compensation switch is connected to the inverting input of the fully differential operational amplifier. The size of the first compensation switch S3Cni of the N-array is the same as that of the third sampling switch S3Ni of the N-array. Furthermore, due to the symmetrical structure of the direct charge transfer circuit, the sizes of the first compensation switch S3Cni of the N-array, the first compensation switch S3Cpi of the P-array, the third sampling switch S3Ni of the N-array, and the third sampling switch S3Pi of the P-array are all the same.

[0078] During the charging phase of a direct charge transfer circuit, i.e. At this time, the third sampling switch S3ni of the N-array is closed, and the right-hand node FNi of the third sampling switch S3ni of the N-array is charged to VREFP or VREFN. The voltage of this right-hand node FNi actually depends on the current DP. i Signals and DN i The signals (both are logically inverted), and the left node ENi of the third sampling switch S3ni of the N array is connected to the non-inverting output VOUTN of the fully differential operational amplifier.

[0079] Based on the operating state of the third sampling switch S3ni of the above N array, as follows: Figure 4 As shown, Figure 4 The control timing is for the first compensation switch S3Cni of the N array. During the charging phase, the first compensation switch S3Cni of the N array is opened, and the first terminal ANi of the first compensation switch S3Cni of the N array will be charged to the same voltage VREFP or VREFN as the right node FNi of the third sampling switch S3ni of the N array (depending on the input DP). i Signals and DN i (Signal); The second terminal BNi of the first compensation switch S3Cni of the N array is charged to the same voltage VOUTN as the left node ENi of the third sampling switch S3ni of the N array. In practice, the transmission gate switch does not distinguish between left and right polarities, and the left and right described above can be interchanged. Therefore, during the charging phase, the voltages of the two nodes of the first compensation switch S3Cni of the N array and the voltages of the two nodes of the third sampling switch S3ni of the N array remain the same.

[0080] In the integration stage of a direct charge transfer circuit, i.e. When the third sampling switch S3ni of the N-array is closed, the voltages of the right node FNi and the left node ENi of the third sampling switch S3ni are both VOUTN. At this time, the first compensation switch S3Cni of the N-array is also conducting, and the voltages of the first terminal ANi and the second terminal BNi of the first compensation switch S3Cni are charged to VOUTN. Therefore, during the integration phase, the voltages of the two nodes of the first compensation switch S3Cni and the voltages of the left and right nodes of the third sampling switch S3ni remain the same. That is, before and after the third sampling switch of the N-array is closed, the magnitude of the charge absorbed or injected by the first compensation switch S3Cni and the third sampling switch S3ni is equal. The charge buffer will transfer the charge absorbed or injected by the first compensation switch S3Cni before and after it is closed to the non-inverting input VINP of the fully differential operational amplifier OPA in a 1:1 ratio. Based on the foregoing analysis, it can be understood that the charge absorbed or injected before and after the third sampling switch S3ni of the N array is closed will be transferred to the SUMP node of the circuit, and will eventually be transferred to the inverting input terminal VINN of the fully differential operational amplifier (the two are short-circuited after S5n is closed). The first compensation switch S3Cni of the N array will inject a charge of the same size into VINP. For the differential output VOUTP-VOUTN, the injected charge input from the inverting input terminal VINN and the compensation charge input from the non-inverting input terminal VINP are common-mode signals, which cannot affect the THD+N and SNDR of the differential output signals VOUTP-VOUTN.

[0081] The charge compensation circuit of this application obtains a compensation charge equal in magnitude to the injected charge generated by the switched capacitor subarray connected to the first differential input terminal in the direct charge transfer circuit through the first compensation switch in the compensation subcircuit. This compensation charge is then transferred to the second differential input terminal of the fully differential operational amplifier, thereby compensating for the injected charge generated by the switched capacitor subarray and effectively improving the SNDR performance of the Sigma-Delta digital-to-analog converter. Furthermore, simulation results show that the total harmonic distortion (THD) of a conventional direct charge transfer circuit without the charge compensation circuit of this application is -80 dB, while the THD of the direct charge transfer circuit can be reduced to -100 dB after incorporating the charge compensation circuit. Therefore, the charge compensation circuit of this application can significantly improve the THD of the digital-to-analog converter and enhance its SNDR performance.

[0082] In one embodiment, such as Figure 5 As shown, the compensation sub-circuit 202 also includes a second compensation switch Ss3i and a third compensation switch Ss4i;

[0083] One end of the second compensation switch Ss3i is used to connect to the second reference voltage VREFN, and the other end of the second compensation switch Ss3i is connected to the first end of the first compensation switch S3Ci.

[0084] One end of the third compensation switch Ss4i is used to connect to the first reference voltage VREFP, and the other end of the third compensation switch Ss4i is connected to the first end of the first compensation switch S3Ci and the other end of the second compensation switch Ss3i.

[0085] Understandable. Figure 5 The diagram only shows the second compensation switch Ss3i and the third compensation switch Ss4i of one of the compensation sub-circuits 202 in the charge compensation circuit. Other compensation sub-circuits 202 are provided with the second compensation switch Ss3i and the third compensation switch Ss4i with the same structural relationship.

[0086] Specifically, the embodiments of this application are applied to, for example, Figure 1 Taking the direct charge transfer circuit shown as an example, the control timing of the second compensation switch is the same as the control timing of the first sampling switch of the P array and N array (i.e., The control timing of the third compensation switch is the same as that of the second sampling switches S2pi and S2ni of the P array and N array (i.e., By controlling the on / off state of the second compensation switch Ss3i and the third compensation switch Ss4i, it is possible to select whether the first reference voltage or the second reference voltage is connected to the first terminal of the first compensation switch S3Ci.

[0087] In one embodiment, the dimensions of both the second and third compensation switches are smaller than the dimensions of the first compensation switch.

[0088] For example, the second and third compensation switches may employ switching elements with the smallest width-to-length ratio under current manufacturing processes.

[0089] Specifically, by reducing the size of the second and third compensation switches, it is possible to avoid the introduction of additional charge injection by the second and third compensation switches. Furthermore, since the parasitic capacitance of each node in the charge compensation circuit is very small, the reduction in the size of the switches will not affect the relatively low charge flow rate of the charge compensation circuit.

[0090] In one embodiment, such as Figure 6 As shown, the charge buffer includes a first buffer switch Ss2i; the charge compensation circuit also includes a fourth compensation switch Ss1i.

[0091] One end of the fourth compensation switch Ss1i is used to connect to the first differential output terminal VOUT1, and the other end of the fourth compensation switch Ss1i is connected to the second end of the first compensation switch S3Ci.

[0092] One end of the first buffer switch Ss2i is connected between the first end of the first compensation switch S3Ci and the other end of the fourth compensation switch Ss1i, and the other end of the first buffer switch Ss2i is used to connect to the second differential input terminal VIN2.

[0093] Specifically, when the second differential input terminal VIN2 is the non-inverting input terminal VINP of the fully differential operational amplifier (i.e., the second terminal of the first compensation switch S3Ci is connected to the non-inverting input terminal VINP), the second differential output terminal corresponds to the inverting output terminal of the fully differential operational amplifier; when the second differential input terminal VIN2 is the inverting input terminal VINN of the fully differential operational amplifier (i.e., the second terminal of the first compensation switch S3Ci is connected to the inverting input terminal VINN), the second differential output terminal corresponds to the non-inverting output terminal VOUTN of the fully differential operational amplifier OPA.

[0094] Specifically, the embodiments of this application are applied to Figure 1 The direct charge transfer circuit shown is illustrated in the example where the charge compensation circuit controls the input voltage at the first terminal of the first compensation switch via a second and a third compensation switch. Figure 7 As shown, Figure 7 The dashed boxes in the middle show the actual circuit structures of a compensation sub-circuit in the P-array and N-array, respectively. The specific implementation process is as follows:

[0095] For a switched capacitor subarray of a P array, in stage, The logic and The logic is consistent, only Compared to There will be a slight delay, but in the analysis, it can be considered as the same signal.

[0096] exist During this phase, the voltage at the first terminal APi of the first compensation switch of the P array is connected to either the first reference voltage VREFP or the second reference voltage VREFN (depending on the current DP) by one of the second compensation switch Ssp3i and the third compensation switch Ssp4i. i Signals and DN i The signal is the same as the FPi node voltage of the third sampling switch S3pi of the current P array; at the same time, the second terminal BPi of the first compensation switch of the P array is connected to the inverting output terminal VOUTP of the fully differential operational amplifier through the fourth compensation switch Ssp1i of the P array, while the first buffer switch Ssp2i (i.e., charge buffer) of the P array is open at this time, and the first compensation switch S3Cpi of the P array is also open. Optionally, the second compensation switch Ssp3i, the third compensation switch Ssp4i, the fourth compensation switch Ssp1i and the first buffer switch Ssp2i are all ultra-small size switches.

[0097] exist During this phase, the second compensation switch Ssp3i, the third compensation switch Ssp4i, and the fourth compensation switch Ssp1i of the P array are disconnected, while the first compensation switch S3Cpi and the first buffer switch Ssp2i of the P array are closed. The first terminal APi and the second terminal BPi of the first compensation switch of the P array are connected to the inverting input terminal VINN by the first buffer switch Ssp2i of the P array, and the compensation charge absorbed or injected by the first compensation switch is transferred to the inverting input terminal VINN.

[0098] Similarly, for a switched capacitor subarray of an N array, in stage, The logic and The logic is consistent, only Compared to There will be a slight delay, but in the analysis, it can be considered as the same signal.

[0099] exist During this phase, the voltage at the first terminal ANi of the first compensation switch of the P array is connected to either the first reference voltage VREFP or the second reference voltage VREFN (depending on the current DP) by one of the second compensation switch Ssn3i and the third compensation switch Ssn4i. i Signals and DN i The signal is the same as the FNi node voltage of the third sampling switch S3ni of the current N-array; at the same time, the second terminal BNi of the first compensation switch of the N-array is connected to the non-inverting output terminal VOUTN of the fully differential operational amplifier through the fourth compensation switch Ssn1i, while the first buffer switch Ssn2i (i.e., charge buffer) of the N-array is open at this time, and the first compensation switch S3Cni of the N-array is also open. Optionally, the second compensation switch Ssn3i, the third compensation switch Ssn4i, the fourth compensation switch Ssn1i and the first buffer switch Ssn2i are all ultra-small size switches.

[0100] exist During this phase, the second compensation switch Ssn3i, the third compensation switch Ssn4i, and the fourth compensation switch Ssn1i of the N array are disconnected, while the first compensation switch S3Cni and the first buffer switch Ssn2i of the N array are closed. The first terminal ANi and the second terminal BNi of the first compensation switch of the N array are connected to the non-inverting input terminal VINP by the first buffer switch Ssn2i of the N array, and the compensation charge absorbed or injected by the first compensation switch is transferred to the non-inverting input terminal VINP.

[0101] In one embodiment, the size of both the first buffer switch and the fourth compensation switch is smaller than the size of the first compensation switch.

[0102] Specifically, the second, third, and fourth compensation switches of the P and N arrays, as well as the first buffer switch, can be switches with the smallest aspect ratio of the current process, thereby minimizing the introduction of additional charge injection by the compensation switches.

[0103] In one embodiment, such as Figure 8 As shown, the charge buffer includes a second buffer switch Ss5i; the charge compensation circuit also includes a DC blocking capacitor Cci.

[0104] One end of the second buffer switch Ss5i is connected to the first end of the first compensation switch S3Ci, and the other end of the second buffer switch Ss5i is connected to one end of the DC blocking capacitor Cci. The other end of the DC blocking capacitor Cci is used to connect to the second differential input terminal VIN2.

[0105] Specifically, when the second differential input terminal VIN2 is the non-inverting input terminal VINP of the fully differential operational amplifier (i.e., the second terminal of the first compensation switch S3Ci is connected to the non-inverting input terminal VINP), the second differential output terminal corresponds to the inverting output terminal of the fully differential operational amplifier; when the second differential input terminal VIN2 is the inverting input terminal VINN of the fully differential operational amplifier (i.e., the second terminal of the first compensation switch S3Ci is connected to the inverting input terminal VINN), the second differential output terminal corresponds to the non-inverting output terminal VOUTN of the fully differential operational amplifier OPA.

[0106] Specifically, the embodiments of this application are applied to Figure 1 The direct charge transfer circuit shown is illustrated in the example where the charge compensation circuit controls the input voltage at the first terminal of the first compensation switch via a second and a third compensation switch. Figure 9 As shown, Figure 9 The dashed boxes in the middle show the actual circuit structures of a compensation sub-circuit in the P-array and N-array, respectively. The specific implementation process is as follows:

[0107] For a switched capacitor subarray of a P array, in stage, Logic and Same, only There is a slight delay, which can be considered and It is the same signal. During this stage, the voltage APi at the first terminal of the first compensation switch of the P array is connected to either the first reference voltage VREFP or the second reference voltage VREFN (depending on the current input DPi and DNi signals) by one of the second compensation switches Ssp3i and Ssp4i of the P array. That is, the voltage APi at the first terminal of the first compensation switch of the P array is the same as the FPi node voltage of the current third sampling switch S3pi of the P array. At the same time, the second terminal BPi of the first compensation switch of the P array is connected to the inverting output terminal VOUTP of the fully differential operational amplifier. In addition, the second buffer switch Ssp5i of the P array is open, and the first compensation switch S3Cpi of the P array is also open. Optionally, the second compensation switch Ssp3i, the third compensation switch Ssp4i, and the second buffer switch Ssp5i of the P array are all ultra-small size switches.

[0108] exist During this phase, the second compensation switch Ssp3i and the third compensation switch Ssp4i of the P array are open, while the first compensation switch S3Cpi and the second buffer switch Ssp5i of the P array are closed. The node voltage of the first terminal APi of the first compensation switch is short-circuited to the inverting output terminal VOUTP. At the same time, the compensation charge absorbed or injected by the APi node can be injected into the inverting input terminal VINN of the fully differential operational amplifier through the DC blocking capacitor Ccpi of the P array.

[0109] Similarly, for a switched capacitor subarray of an N array, in Phase, in which Logic and Same, only There is a slight delay, which can be considered and It is the same signal. During this stage, the voltage at the first terminal ANi of the first compensation switch of the N array is connected to either the first reference voltage VREFP or the second reference voltage VREFN (depending on the current input DPi and DNi signals) by one of the second compensation switches Ssn3i and Ssn4i of the N array. That is, the voltage at the first terminal ANi of the first compensation switch of the N array is the same as the voltage at the FNi node of the current third sampling switch S3ni of the N array. At the same time, the second terminal BNi of the first compensation switch of the N array is connected to the non-inverting output terminal VOUTN of the fully differential operational amplifier. In addition, the second buffer switch Ssn5i is open, and the first compensation switch S3Cni of the N array is also open. Optionally, the second compensation switch Ssn3i, the third compensation switch Ssn4i, and the second buffer switch Ssn5i are all ultra-small size switches.

[0110] exist During this phase, the second compensation switch Ssn3i and the third compensation switch Ssn4i of the N array are open, while the first compensation switch S3Cni and the second buffer switch Ssn5i of the N array are closed. The node voltage of the first terminal ANi of the first compensation switch is short-circuited to VOUTN. At the same time, the compensation charge absorbed or injected at node ANi is injected into the non-inverting input terminal VINP of the fully differential operational amplifier through the DC blocking capacitor Ccni of the N array.

[0111] In one embodiment, the size of the second buffer switch is smaller than the size of the first compensation switch.

[0112] For example, the second compensation switch, third compensation switch, fourth compensation switch and second buffer switch of the P array and N array described above can be switches with the smallest width-to-length ratio of the current process, thereby avoiding the introduction of additional charge injection by the compensation switches as much as possible.

[0113] In one embodiment, such as Figure 10 As shown, this application provides a direct charge transfer circuit 30, applied to a Sigma-Delta digital-to-analog converter; the direct charge transfer circuit 30 includes: a first switched capacitor array (an array composed of M switched capacitor subarrays 40 on the non-inverting input side of the fully differential operational amplifier OPA in the figure), a second switched capacitor array (an array composed of M switched capacitor subarrays 40 on the inverting input side of the fully differential operational amplifier OPA in the figure), a fully differential operational amplifier OPA, a first feedback capacitor Cfbp, a second feedback capacitor Cfbn, a first control switch S4p, a second control switch S5p, a third control switch S4n, and a fourth control switch S5n; the first switched capacitor array and the second switched capacitor array each include the same number of switched capacitor subarrays 40;

[0114] In the first switched capacitor array, each switched capacitor subarray 40 is connected to the non-inverting input terminal VINP of the fully differential operational amplifier OPA via a second control switch S5p. One end of the first control switch S4p is used to connect to the second reference voltage VREFN, and the other end of the first control switch S4p is connected between each switched capacitor subarray 40 in the first switched capacitor array and the second control switch S5p. The first switched capacitor array is also connected to the inverting output terminal VOUTP of the fully differential operational amplifier OPA, the first reference voltage VREFP, the second reference voltage VREFN, and the digital signal to be converted.

[0115] In the second switched capacitor array, each switched capacitor subarray 40 is connected to the inverting input terminal VINN of the fully differential operational amplifier OPA via the fourth control switch S5n. One end of the third control switch S4n is used to connect to the second reference voltage VREFN, and the other end of the third control switch S4n is connected between each switched capacitor subarray 40 in the second switched capacitor array and the fourth control switch S5n. The second switched capacitor array is also connected to the non-inverting output terminal VOUTN of the fully differential operational amplifier OPA, the first reference voltage VREFP, the second reference voltage VREFN, and the digital signal to be converted.

[0116] One end of the first feedback capacitor Cfbp is connected to the non-inverting input terminal VINP, and the other end of the first feedback capacitor Cfbp is connected to the inverting output terminal VOUTP; one end of the first feedback capacitor Cfbp is connected to the inverting input terminal VINN, and the other end of the first feedback capacitor Cfbp is connected to the non-inverting output terminal VOUTN.

[0117] The direct charge transfer circuit also includes two charge compensation circuits as described in any of the above embodiments: one charge compensation circuit is connected to the non-inverting input terminal VINP, and the other charge compensation circuit is connected to the inverting input terminal VINN;

[0118] The charge compensation circuit connected to the inverting input terminal VINN uses the non-inverting input terminal VINP as the first differential input terminal and the inverting input terminal VINN as the second differential input terminal; the charge compensation circuit connected to the non-inverting input terminal VINP uses the inverting input terminal VINN as the first differential input terminal and the non-inverting input terminal VINP as the second differential input terminal.

[0119] In one embodiment, such as Figure 11 As shown, the switched capacitor subarray 40 includes a first sampling switch S1i, a second sampling switch S2i, a third sampling switch S3i, and an integrating capacitor Ci.

[0120] One end of the first sampling switch S1i is connected to the first reference voltage VREFP, and the other end of the first sampling switch S1i is connected to one end of the integrating capacitor Ci, the other end of the second sampling switch S2i, and the other end of the third sampling switch S3i, respectively.

[0121] One end of the second sampling switch S2i is connected to the second reference voltage VREFN, and the other end of the second sampling switch S2i is also connected to one end of the integrating capacitor Ci and the other end of the third sampling switch S3i.

[0122] When the switched capacitor subarray 40 is connected to the non-inverting input terminal VINP, one end of the third sampling switch S3i is connected to the inverting output terminal VOUTP, and the other end of the third sampling switch S3i is connected to one end of the integrating capacitor Ci. The other end of the integrating capacitor Ci is connected to the non-inverting input terminal VINP through the second control switch S5p.

[0123] With the switched capacitor subarray 40 connected to the inverting input terminal VINN, one end of the third sampling switch S3i is connected to the non-inverting output terminal VOUTN, and the other end of the third sampling switch S3i is connected to one end of the integrating capacitor Ci. The other end of the integrating capacitor Ci is connected to the inverting input terminal VINN through the fourth control switch S5n.

[0124] It should be noted that the specific limitations of the direct charge transfer circuit in the embodiments of this application can be found in the specific limitations of the charge compensation circuit in the above embodiments, such as the control timing of each switch in each direct charge transfer circuit and... Figure 1 The switch control timing shown is the same, so it will not be repeated here.

[0125] In one embodiment, this application provides a digital-to-analog converter (DAC) including a direct charge transfer circuit as described in any of the above embodiments. Specifically, the DAC is a Sigma-Delta DAC.

[0126] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0127] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A charge compensation circuit, characterized in that, A direct charge transfer circuit for use in a Sigma-Delta digital-to-analog converter; the charge compensation circuit includes one or more compensation sub-circuits; the compensation sub-circuit includes a first compensation switch and a charge buffer; The first terminal of the first compensation switch is used to connect to the first reference voltage or the second reference voltage of the direct charge transfer circuit; the second terminal of the first compensation switch is used to connect to the first differential output terminal of the fully differential operational amplifier of the direct charge transfer circuit. The first compensation switch is connected to the charge buffer, which is used to transfer the compensation charge obtained before and after the first compensation switch is closed to the second differential input terminal of the fully differential operational amplifier; the compensation charge is used to cancel the injected charge generated by the switched capacitor subarray connected to the first differential input terminal of the fully differential operational amplifier in the direct charge transfer circuit; The number of the compensation sub-circuits is the same as the number of the switched capacitor sub-arrays connected to the first differential input terminal.

2. The charge compensation circuit according to claim 1, characterized in that, The compensation sub-circuit also includes a second compensation switch and a third compensation switch; One end of the second compensation switch is used to connect to the second reference voltage, and the other end of the second compensation switch is connected to the first end of the first compensation switch; One end of the third compensation switch is used to connect to the first reference voltage, and the other end of the third compensation switch is connected to the first end of the first compensation switch and the other end of the second compensation switch.

3. The charge compensation circuit according to claim 2, characterized in that, The dimensions of the second compensation switch and the third compensation switch are both smaller than the dimensions of the first compensation switch.

4. The charge compensation circuit according to claim 1 or 2, characterized in that, The charge buffer includes a first buffer switch; the charge compensation circuit further includes a fourth compensation switch. One end of the fourth compensation switch is used to connect to the first differential output terminal, and the other end of the fourth compensation switch is connected to the second terminal of the first compensation switch. One end of the first buffer switch is connected between the first end of the first compensation switch and the other end of the fourth compensation switch, and the other end of the first buffer switch is used to connect to the second differential input terminal.

5. The charge compensation circuit according to claim 4, characterized in that, The size of the first buffer switch and the size of the fourth compensation switch are both smaller than the size of the first compensation switch.

6. The charge compensation circuit according to claim 1 or 2, characterized in that, The charge buffer includes a second buffer switch; the charge compensation circuit also includes a DC blocking capacitor. One end of the second buffer switch is connected to the first end of the first compensation switch, and the other end of the second buffer switch is connected to one end of the DC blocking capacitor. The other end of the DC blocking capacitor is used to connect to the second differential input terminal.

7. The charge compensation circuit according to claim 6, characterized in that, The size of the second buffer switch is smaller than the size of the first compensation switch.

8. A direct charge transfer circuit, characterized in that, Applied to Sigma-Delta digital-to-analog converters; The direct charge transfer circuit includes: a first switched capacitor array, a second switched capacitor array, a fully differential operational amplifier, a first feedback capacitor, a second feedback capacitor, a first control switch, a second control switch, a third control switch, and a fourth control switch; the first switched capacitor array and the second switched capacitor array each include the same number of switched capacitor subarrays; Each switched capacitor subarray in the first switched capacitor array is connected to the non-inverting input of the fully differential operational amplifier via the second control switch. One end of the first control switch is used to connect to the second reference voltage, and the other end of the first control switch is connected between each switched capacitor subarray in the first switched capacitor array and the second control switch. The first switched capacitor array is also connected to the inverting output of the fully differential operational amplifier, the first reference voltage, the second reference voltage, and the digital signal to be converted. Each switched capacitor subarray in the second switched capacitor array is connected to the inverting input of the fully differential operational amplifier via the fourth control switch. One end of the third control switch is used to connect to the second reference voltage, and the other end of the third control switch is connected between each switched capacitor subarray in the second switched capacitor array and the fourth control switch. The second switched capacitor array is also connected to the non-inverting output of the fully differential operational amplifier, the first reference voltage, the second reference voltage, and the digital signal to be converted. One end of the first feedback capacitor is connected to the non-inverting input terminal, and the other end of the first feedback capacitor is connected to the inverting output terminal; one end of the second feedback capacitor is connected to the inverting input terminal, and the other end of the second feedback capacitor is connected to the non-inverting output terminal. The direct charge transfer circuit further includes two charge compensation circuits as described in any one of claims 1 to 7: one of the charge compensation circuits is connected to the non-inverting input terminal, and the other charge compensation circuit is connected to the inverting input terminal; The charge compensation circuit connected to the inverting input terminal uses the non-inverting input terminal as the first differential input terminal and the inverting input terminal as the second differential input terminal; the charge compensation circuit connected to the non-inverting input terminal uses the inverting input terminal as the first differential input terminal and the non-inverting input terminal as the second differential input terminal.

9. The direct charge transfer circuit according to claim 8, characterized in that, The switched capacitor subarray includes a first sampling switch, a second sampling switch, a third sampling switch, and an integrating capacitor; One end of the first sampling switch is connected to the first reference voltage, and the other end of the first sampling switch is connected to one end of the integrating capacitor, the other end of the second sampling switch, and the other end of the third sampling switch, respectively. One end of the second sampling switch is connected to the second reference voltage, and the other end of the second sampling switch is also connected to one end of the integrating capacitor and the other end of the third sampling switch; When the switched capacitor subarray is connected to the non-inverting input terminal, one end of the third sampling switch is connected to the inverting output terminal, the other end of the third sampling switch is connected to one end of the integrating capacitor, and the other end of the integrating capacitor is connected to the non-inverting input terminal through the second control switch; When the switched capacitor subarray is connected to the inverting input terminal, one end of the third sampling switch is connected to the non-inverting output terminal, the other end of the third sampling switch is connected to one end of the integrating capacitor, and the other end of the integrating capacitor is connected to the inverting input terminal through the fourth control switch.

10. A digital-to-analog converter, characterized in that, Includes the direct charge transfer circuit as described in claim 8 or 9.

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