Interconnection structure layer, manufacturing method of interconnection structure layer and circuit board

Abstract

The invention discloses an interconnection structure layer, a manufacturing method of the interconnection structure layer and a circuit board, the interconnection structure layer can be overlaid between two circuit layers with interconnection requirements, and the interconnection structure layer comprises an insulating layer and a conductive column; the conductive columns are embedded in the whole insulating layer at a preset hole density. According to the invention, the distribution density and the diameter of the conductive columns embedded in the insulating layer are limited, so that the bonding pads needing to be interconnected with the outside in the circuit layer can be at least in contact with one conductive column used for interlayer conduction, and the region between any two bonding pads in the same circuit layer is not only in contact with the conductive column. In this way, any interconnection between layers can be achieved, and meanwhile it is guaranteed that short circuit of a single circuit layer cannot be caused. High-precision alignment is not needed, random interconnection between the circuit layers is achieved, the number of pressing times accumulated on one board is reduced, and therefore the machining difficulty is reduced, and the yield is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board manufacturing, and in particular to an interconnection structure layer, a manufacturing method of the interconnection structure layer, and a circuit board. Background Art

[0002] With the development of miniaturization and multi-functionality in products, the demand for product integration is becoming increasingly higher. To provide hardware support for various functions, the number of conductive circuit layers in circuit boards is increasing, and the requirements for inter-layer interconnection are also becoming increasingly stringent. For example, high-density interconnect (HDI) boards require multiple lamination processes to stack multiple circuit layers. As the number of layers increases, the number of laminations accumulated on the same board increases, resulting in a lengthy processing process. In addition, to meet the high-density interconnection between HDI board layers, precise alignment is required before lamination of the circuit layers. The high-precision alignment requirements and the increasing number of laminations increase the difficulty of HDI board processing and reduce the board processing yield. Summary of the Invention

[0003] Based on this, it is necessary to provide an interconnection structure layer, a method for manufacturing the interconnection structure layer, and a circuit board to address the above technical problems, so as to solve the problem of low processing yield of high-density interconnection circuit boards.

[0004] In a first aspect, an interconnection structure layer is provided, comprising: a conductive pillar; an insulating layer; through holes distributed in the insulating layer at a preset hole density throughout the insulating layer, the through holes being used to embed the conductive pillars; the interconnection structure layer is used to be superimposed between two circuit layers with interconnection requirements, and at least one of the conductive pillars is in contact with a surface pad of the circuit layer, and the diameter of any of the conductive pillars is smaller than the minimum spacing between adjacent pads in any of the circuit layers.

[0005] In an embodiment of the present application, the through holes are evenly distributed in the insulating layer; and the distance between any two of the through holes is smaller than the diameter of the smallest pad in any of the circuit layers.

[0006] In the embodiment of the present application, the thickness of the insulating layer is 20-50 μm.

[0007] In the embodiment of the present application, the diameter of the conductive pillars is 15-20 μm; and the spacing between the conductive pillars is 10 μm.

[0008] In a second aspect, a method for manufacturing an interconnection structure layer is provided, which comprises: providing a separable core board; the separable core board comprises a surface seed layer that can be peeled off from the separable core board; pressing an insulating layer on the outer surface of the surface seed layer; laser drilling the insulating layer according to a preset hole density to form a blind hole penetrating the insulating layer; and exposing the area on the surface seed layer involved in electroplating conduction by laser ablation; electroplating and filling the blind hole to form a conductive column to form an interconnection structure layer on the surface seed layer; peeling the surface seed layer from the separable core board to separate the interconnection structure layer with the surface seed layer; pasting a protective film on the side of the interconnection structure layer away from the surface seed layer, then flash etching away the material of the surface seed layer, and then removing the protective film.

[0009] In an embodiment of the present application, laminating the insulating layer on the outer surface of the surface seed layer includes: stacking the insulating layer and the conductive layer in sequence on the outer surface of the surface seed layer, and then laminating the conductive layer; laser drilling the insulating layer according to a preset hole density to form a blind hole passing through the insulating layer includes: laser drilling on the conductive layer according to the preset hole density to form a blind hole passing through the conductive layer and the insulating layer; performing black shadow treatment on the blind hole, and flash etching away the material of the conductive layer after the black shadow treatment.

[0010] In an embodiment of the present application, before laser drilling is performed on the conductive layer according to the preset hole density, the method further includes: micro-etching a side of the conductive layer facing away from the insulating layer.

[0011] In the embodiment of the present application, the diameter of the blind hole is 15-20 μm; and the spacing between adjacent blind holes is 10 μm.

[0012] In the embodiment of the present application, the thickness of the conductive layer after micro-etching is 1-2 μm.

[0013] In a third aspect, a circuit board is provided, which includes at least two circuit layers with interconnection requirements and at least one interconnection structure layer described in the above embodiment; the interconnection structure layer is superimposed between any two of the circuit layers.

[0014] In any of the above-mentioned solutions, the interconnection structure layer can be superimposed between two circuit layers that require interconnection, and the insulating adhesive material in the interconnection structure layer can serve as the adhesive material required for lamination of the circuit layers; conductive pillars distributed at a preset density are embedded in the entire insulating layer formed by the insulating adhesive material, and the distribution of the conductive pillars in the interconnection structure layer can ensure that when the interconnection structure layer is superimposed between the two circuit layers, at least one conductive pillar is in contact with the surface pads of any upper or lower circuit layer, thereby ensuring that there is a conductive medium between the pads that need to be connected in the two circuit layers, thereby realizing inter-layer interconnection; in addition, the diameter of any conductive pillar in the interconnection structure layer is smaller than the minimum spacing between adjacent pads in any circuit layer. In this way, even if the area between two adjacent pads of a circuit layer contacts a conductive pillar, the end face of the conductive pillar cannot contact the two adjacent pads at the same time, thereby avoiding connecting two pads of the same circuit layer and causing a short circuit.

[0015] The interconnection structure layer proposed in the present application does not need to be precisely aligned when it is superimposed between two circuit layers, because by limiting the distribution density and diameter size of the conductive columns embedded in the insulating layer, the pads in the circuit layer that need to be interconnected with the outside can contact at least one conductive column for interlayer conduction, so that the area between any two pads in the same circuit layer will not only contact the conductive column, but also contact the insulating layer material around the conductive column, so that arbitrary interconnection between layers can be achieved while ensuring that no short circuit occurs in the single-layer circuit layer. In addition, when a high-density interconnection board is made based on the interconnection structure layer, it is allowed to split the high-density interconnection board into multiple multi-layer boards for separate processing, and then use the interconnection structure layer to achieve the bonding of the multi-layer boards and arbitrary interconnection between boards, so that the number of cumulative pressings on a board can be reduced. The present application uses the interconnection structure layer to reduce the number of cumulative pressings on a board and reduce the requirements for the alignment accuracy of the circuit layer while ensuring high-density arbitrary interconnection between board layers, thereby reducing processing difficulty and improving yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A cross-sectional view of an interconnect structure layer shown in an exemplary embodiment of the present application; Figure 2 A cross-sectional view of a circuit board shown as an exemplary embodiment of the present application; Figure 3This is a flow chart of a method for manufacturing an interconnect structure layer according to an exemplary embodiment of the present application; Figure 4 A cross-sectional view of a separable core panel according to an exemplary embodiment of the present application is shown; Figure 5 A cross-sectional view of a laminated plate according to an exemplary embodiment of the present application; Figure 6 A cross-sectional view of a plate after drilling according to an exemplary embodiment of the present application; Figure 7 A cross-sectional view of a black shadow rear plate according to an exemplary embodiment of the present application; Figure 8 A cross-sectional view of a plate after flash corrosion according to an exemplary embodiment of the present application; Figure 9 A cross-sectional view of a plate after electroplating according to an exemplary embodiment of the present application; Figure 10 A cross-sectional view of an interconnect structure layer with a surface seed layer according to an exemplary embodiment of the present application; Figure 11 This is a cross-sectional view of an interconnect structure layer according to another exemplary embodiment of the present application.

[0018] The reference numerals in the specification are as follows: 1. Interconnection structure layer; 11. Insulation layer in the interconnection structure layer; 12. Conductive column; 2. First-order board; 21. Solder pad on the first-order board; 3. Second-order board; 31. Solder pad on the second-order board; 4. Fourth-order board; 5. Separable core board; 51. Dielectric layer; 52. First copper foil layer; 53. Surface seed layer; 6. Insulation layer on the surface seed layer; 7. Blind hole; 8. Conductive layer. DETAILED DESCRIPTION

[0019] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0020] It should be understood that the embodiments set forth below represent the necessary information to enable those skilled in the art to implement the embodiments and to illustrate the best mode of implementing the embodiments. After reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0021] It should also be understood that the terms "upper", "lower", "left", "right", "front", "back", "bottom", "middle", "top", etc. may be used in this document to describe various elements, and the indicated orientation or position relationship is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, so these elements should not be restricted by these terms.

[0022] It is further understood that the terms “comprises” and “includes” when used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0024] The interconnection structure layer proposed in the embodiment of the present application can be applied to the technical field of multi-layer circuit board processing and manufacturing. When manufacturing a multi-layer board, the interconnection structure layer is used to achieve interconnection between the internal layers. The interconnection structure layer embeds a densely distributed thin conductive pillar in the insulating layer to ensure that the pads of the circuit layers arranged on the upper and lower surfaces of the interconnection structure layer can contact at least one thin conductive pillar, thereby achieving interconnection between the two circuit layers. At the same time, it ensures that no two pads on the same circuit layer can contact the end face of a thin conductive pillar at the same time, thereby avoiding short circuiting of a single circuit layer. The interconnection structure layer realizes arbitrary interconnection between circuit layers without precise alignment by constraining the distribution density and diameter of the conductive pillars, facilitating the bonding of any two circuit layers in the HDI board. In this way, the interconnection structure layer can be superimposed between the circuit layers when manufacturing the HDI board, and then pressed in one go, thereby reducing the number of pressings accumulated on a single board during circuit board manufacturing and reducing the requirements for alignment accuracy of high-density interconnected boards. Overall, the processing process is shortened, the processing difficulty is reduced, and the yield rate is easily improved.

[0025] Example 1 Figure 1 This is a cross-sectional view of an interconnection structure layer 1 according to an exemplary embodiment of the present application.

[0026] like Figure 1 As shown, the interconnection structure layer 11 provided in the present application may include an insulating layer 11 and a conductive column 12 formed of an insulating adhesive material.

[0027] The insulating layer 11 has through holes distributed on the entire insulating layer 11 at a preset hole density, and each through hole is used to embed a conductive pillar 12. Therefore, the conductive pillars 12 embedded in the insulating layer 11 are also distributed on the insulating layer 11 at the preset hole density.

[0028] Interconnection structure layer 1 can be stacked between two circuit layers requiring interconnection. When interconnection structure layer 1 is stacked between two circuit layers, at least one conductive pillar 12 is in contact with a surface pad on a circuit layer, and the diameter of any conductive pillar 12 is smaller than the minimum spacing between adjacent pads in any circuit layer.

[0029] For example, the insulating layer 11 is made of a prepreg, and holes are opened in the insulating layer 11 at a certain hole density. The hole density can be determined by determining the number of through holes required to be opened per unit area based on the distribution of pads on the circuit layer to be interconnected using the interconnection structure layer 1.

[0030] For example, the pad diameter and the spacing between pads commonly used in the HDI board processing process are determined, and the minimum value of these two parameters is determined. The opening diameter of the insulating layer 11 is determined to be a value smaller than the minimum value, and the ratio between the opening diameter and the minimum value is calculated, and the ratio is used as the hole density on the insulating layer 11.

[0031] For example, Figure 2 As shown, when making a fourth-order board, a first-order board 2 and a second-order board 3 are first processed separately. When making the first-order board 2, two circuit layers need to be pressed once, and when making the second-order board 3, three circuit layers need to be pressed twice.

[0032] The interconnection structure layer 1 is stacked between the processed first-order plate 2 and the second-order plate 3, as shown in FIG. Figure 2 As shown, each blind hole pad on the first-order plate 2 and the second-order plate 3 can contact multiple conductive pillars 12, and as long as there is a conductive pillar 12 between the upper and lower pads 21 and pads 31 that need to be connected, the upper and lower pads 21 and pads 31 can be connected. Therefore, the interconnection structure layer 1 can meet any interconnection requirements between circuit layers; in addition, as Figure 2 As shown, the area between the two blind via pads 21 in the first-order board 2 is in contact not only with the conductive pillars 12 of the interconnect structure layer 1 but also with the insulating adhesive material surrounding the conductive pillars 12. Furthermore, the area between the two blind via pads 31 in the second-order board 3 is also in contact with both the conductive pillars 12 of the interconnect structure layer 1 and the insulating adhesive material surrounding the conductive pillars 12. Therefore, two adjacent pads on the same circuit layer cannot be connected, and a short circuit will not occur.

[0033] When stacking the first-order board 2, the interconnection structure layer 1 and the second-order board 3 together, there is no need to precisely align the layers. The high-density distribution of conductive pillars 12 can ensure that there must be at least one conductive pillar 12 between the upper and lower pads 21 and pads 31 that need to be connected.

[0034] Finally, the first-order board 2 and the second-order board 3 are pressed together through the interconnection structure layer 1 to obtain a fourth-order board 4. The fourth-order board 4 produced in this way only requires three pressings. Compared with pressing once to make a first-order board, then pressing a circuit layer on the first-order board to make a second-order board, then pressing a circuit layer on the second-order board to make a third-order board, and then pressing a circuit layer on the third-order board to make a fourth-order board, and so on, a cumulative pressing four times to make a fourth-order board, the interconnection structure layer 1 can shorten the cumulative pressing times on a board layer, shortening the processing process.

[0035] In summary, the interconnection structure layer proposed in the embodiment of the present application can be superimposed between two circuit layers that need to be interconnected, and the insulating adhesive material in the interconnection structure layer can be used as the adhesive material required for lamination of the circuit layers; conductive columns distributed at a preset density are embedded on the entire insulating layer formed by the insulating adhesive material, and the distribution of the conductive columns in the interconnection structure layer can ensure that when the interconnection structure layer is superimposed between the two circuit layers, there is at least one conductive column in contact with the surface pads of any upper or lower circuit layer, thereby ensuring that there is a conductive medium between the pads that need to be connected up and down in the two circuit layers, thereby realizing inter-layer interconnection; in addition, the diameter of any conductive column in the interconnection structure layer is smaller than the minimum spacing between adjacent pads in any circuit layer, so that even if the area between two adjacent pads of a circuit layer contacts a conductive column, the end face of the conductive column cannot contact the two adjacent pads at the same time, thereby avoiding connecting two pads of the same circuit layer to cause a short circuit. The interconnection structure layer proposed in the present application does not need to be precisely aligned when it is superimposed between two circuit layers, because by limiting the distribution density and diameter size of the conductive columns embedded in the insulating layer, the pads in the circuit layer that need to be interconnected with the outside can contact at least one conductive column for interlayer conduction, so that the gap between any two pads densely distributed in the circuit layer will not only contact the conductive column but also the insulating layer material around the conductive column; while achieving arbitrary interconnection between layers, it is ensured that no short circuit will occur in the single-layer circuit layer. In addition, when making a high-density interconnection board based on the interconnection structure layer, it is allowed to split the high-density interconnection board into multiple multi-layer boards for separate processing, and then use the interconnection structure layer to achieve the bonding of the multi-layer boards and arbitrary interconnection between boards, which can reduce the number of press-fits accumulated on a board. The present application uses the interconnection structure layer to reduce the number of press-fits accumulated on a board and reduce the requirements for the alignment accuracy of the circuit layer while ensuring high-density arbitrary interconnection between board layers, thereby reducing processing difficulty and improving yield.

[0036] In some embodiments, the through holes on the insulating layer 11 are evenly distributed, that is, at a preset hole density, the spacing between each hole is the same.

[0037] The spacing between each two adjacent through-holes is smaller than the diameter of the smallest pad in any circuit layer to be interconnected using the interconnection structure layer 1. This ensures that no matter how the interconnection structure layer 1 is placed between two circuit layers, the smallest pad on the circuit layer will not only contact the insulating adhesive material of the insulating layer 11, but will inevitably contact at least one conductive pillar 12.

[0038] In this way, when interconnecting two circuit layers using the interconnection structure layer 1, arbitrary interconnection without alignment can be achieved, which reduces the difficulty of processing high-density interconnection boards and further improves the yield rate.

[0039] Furthermore, in some embodiments, when the pads are in shapes other than circular, the distance between any two through holes is smaller than the maximum width of the smallest pad in any circuit layer.

[0040] In some embodiments, the thickness of the insulating layer 11 may be 20-50 μm.

[0041] In some embodiments, the conductive pillars 12 may be copper pillars; the diameter of the conductive pillars 12 is 15-20 μm; and the spacing between the conductive pillars 12 is 10 μm. By limiting the diameter and spacing of the conductive pillars 12 to a relatively small range, a high-density distribution of fine copper wires is achieved on the interconnect structure layer 1, enabling a wide range of interconnect structure layers with different specifications.

[0042] Example 2 In order to obtain the interconnection structure layer 1 in the above embodiment, the present application proposes a method for manufacturing the interconnection structure layer 1, such as Figure 3 As shown, the method for manufacturing the interconnection structure layer 1 may include the following steps: S301, providing a separable core plate; the separable core plate includes a surface seed layer that can be peeled off from the separable core plate.

[0043] For example, a detachable plate (Detach Core) is selected as the material, and the material is cut to obtain a detachable core plate as a processing substrate.

[0044] like Figure 4 As shown, the separable core board 5 may include a dielectric layer 51 and a first copper foil layer 52 and a second copper foil layer sequentially stacked on both sides of the dielectric layer 51 .

[0045] The thickness of the first copper foil layer 52 may be 18 μm, and the thickness of the second copper foil layer may be 3 μm.

[0046] The second copper foil layer serves as a surface seed layer 53 of the separable core board 5 .

[0047] The first copper foil layer 52 and the second copper foil layer can be separated from the separable core board 5 in their entirety by external force.

[0048] S302, pressing an insulating layer onto the outer surface of the surface seed layer.

[0049] Exemplarily, the insulating layer 6 is pressed onto the outer surfaces of the surface seed layer 53 on the upper and lower surfaces of the separable core plate 5 , respectively.

[0050] Since the insulating layer 6 is an insulating adhesive material, such as a prepreg, the lamination can be achieved through the following process: The insulating layer 6 can be stacked on the outer surface of the surface seed layer, and release paper can be pasted on the side of the insulating layer 6 facing away from the outer surface of the surface seed layer, and then the insulating layer 6 can be pressed onto the separable core board 5.

[0051] Since the adhesion between the circuit layers needs to be achieved by further relying on the viscosity of the insulating layer after the interconnection structure layer is formed, the lamination process in this step can use low-temperature lamination, so that the insulating layer can still be in a semi-cured state after lamination. For example, low-temperature lamination at 110 degrees can be used. When using this interconnection structure layer to interconnect two circuit layers, high-temperature lamination can be used to press the two circuit layers onto both sides of the interconnection structure layer, so that the insulating adhesive material of the interconnection structure layer can be in a cured state after lamination.

[0052] S303, laser drilling is performed on the insulating layer according to a preset hole density to form blind holes penetrating the insulating layer; and the area on the surface seed layer involved in electroplating conduction is exposed by laser ablation.

[0053] For example, laser drilling is performed on the laminated insulating layer 6 according to a predetermined hole density, and the drilling depth can penetrate the insulating layer 6, thereby forming blind holes 7 in the insulating layer. The drilled insulating layer 6 is equivalent to the insulating layer 11 in the interconnect structure layer 1 described in the first embodiment.

[0054] The preset hole density and hole diameter used in laser drilling can refer to the description of the conductive pillars 12 of the interconnection structure layer 1 and the through holes on the insulating layer 11 in the above embodiment, and will not be repeated here.

[0055] Before the electroplating process, it is also necessary to use a laser to burn the edge of the board, thereby ablating an area for electroplating and conducting on the surface seed layer 53 of the separable core board 5. The size and position of the ablated area can be set as needed and are not limited in this application.

[0056] S304 , filling the blind holes with electroplating to form conductive pillars, thereby forming an interconnection structure layer on the surface seed layer.

[0057] The blind holes 7 obtained by laser drilling in step S303 are filled with electroplating to form conductive pillars 12 in the blind holes. The insulating layer 6 embedded with the conductive pillars 12 can serve as the interconnection structure layer 1.

[0058] In some embodiments, the blind hole 7 can be shadowed before electroplating to form a conductive thin layer with graphite as the main component on the hole wall, providing good conductive flux for subsequent electroplating, ensuring that the metal ions in the electroplating solution can be evenly deposited on the hole wall, so that the resulting conductive column 12 can have good conductivity.

[0059] In other embodiments, the hole walls can be directly carbonized during the laser drilling process, forming a conductive carbon layer on the hole wall surface. For example, a laser beam can be used to carbonize the insulating layer inside a blind hole, causing the insulating layer to be carbonized by the laser beam and leaving conductive carbon particles on the hole wall for subsequent direct electroplating.

[0060] S305 , peeling the surface seed layer from the separable core board to separate the interconnect structure insulation layer with the surface seed layer.

[0061] For example, after the electroplating and hole filling process, the surface seed layer 53 is completely peeled off from the separable core board 5. Simultaneously, the interconnect structure layer 1, which is laminated to the surface seed layer 53, is also peeled off from the separable core board along with the surface seed layer 53. This results in the interconnect structure layer 1 with the surface seed layer 53.

[0062] S306 , a protective film is adhered to the side of the interconnect structure layer facing away from the surface seed layer, and then the material of the surface seed layer is flash-etched away, and then the protective film is removed.

[0063] Illustratively, after the interconnection structure layer 1 is separated from the separable core board 5 , a protective film is adhered to the side of the interconnection structure layer 1 facing away from the surface seed layer 53 , such as a protective tape is attached to the surface of the interconnection structure layer away from the surface seed layer 53 .

[0064] After the protective tape is applied, the material of the surface seed layer 53 is flash-etched away, and then the protective tape is torn off, thereby obtaining an insulating layer embedded with conductive pillars as the interconnection structure layer 1 .

[0065] In summary, the method for manufacturing the interconnection structure layer proposed in the embodiment of the present application is to laminate an insulating layer onto the outer surface of the surface seed layer of the separable core board, then laser drill and fill the insulating layer with electroplating, embed conductive pillars in the insulating layer at a high density, and then separate the insulating layer with embedded conductive pillars from the separable board to obtain the interconnection structure layer. In this way, an interconnection structure layer is obtained that maintains insulating bonding properties while being densely embedded with multiple conductive pillars. This interconnection structure layer can be used to bond together circuit layers that need to be interconnected, and the conductive pillars can be used to meet the interconnection requirements between the two circuit layers.

[0066] In some embodiments, an insulating layer 6 and a conductive layer 8 are sequentially stacked on the outer surface of each surface seed layer 53 of the provided separable core board 5. For example, a prepreg and a copper foil are sequentially stacked. Then, after stacking, the insulating layer 6 and the conductive layer 8 are pressed onto the separable core board 5. Figure 5 This is a cross-sectional view of the sheet after pressing.

[0067] Then, in the laser drilling process, laser drilling is performed on the conductive layer 8 according to a preset hole density to form blind holes 7 that penetrate the two adjacent conductive layers and the insulating layer. A portion of the surface seed layer 53 adjacent to the insulating layer 6 is laser ablated to form an area for electroplating conduction. For example, after laminating the prepreg and copper foil on the separable core board, laser drilling is performed on the copper foil. Figure 6 This is a cross-sectional view of the plate after drilling.

[0068] Furthermore, after the drilling is completed, the blind hole 7 can be further subjected to a black shadow treatment so as to form a graphite conductive thin layer on the hole wall. Figure 7 The figure shows the cross section of the plate after the black shadow.

[0069] Furthermore, after the blind hole shadow is completed, the material of the conductive layer 8 is flash-etched. For example, if the semi-cured sheet and copper foil are pressed together on the separable core board, the outermost copper layer can be flash-etched after drilling and shadow processing. Figure 8 The figure shows the cross section of the plate after flash corrosion.

[0070] Then, the electroplating process is performed to fill the blind holes 7 opened in the insulating layer 6 with electroplating. Figure 9 The figure shows the cross-section of the plate after electroplating.

[0071] Then, the surface seed layer 53 is separated from the separable core plate 5. Figure 10 FIG. 1 is a cross-sectional view of an interconnect structure layer with a surface seed layer peeled off from a separable core board.

[0072] Then, tape is applied to the surface of the interconnection structure layer 1 away from the surface seed layer 53, and then the surface seed layer 53 is flash-etched away to obtain the interconnection structure layer 1 that can be used for any interconnection between circuit layers. Figure 11 , which is a cross-sectional view of the interconnection structure layer finally obtained.

[0073] In this embodiment, when the insulating layer 6 is pressed onto the separable core board 5, the conductive layer 8 is also pressed onto the surface of the insulating layer 6, and then the conductive layer 8 is removed after the black shadow treatment. The conductive layer 8 can prevent the conductive graphite from adhering to the surface of the insulating layer 6 during the black shadow treatment, thereby ensuring the insulation of other areas in the insulating layer 6 except for the through holes.

[0074] In some embodiments, before laser drilling holes in the conductive layer 8 at a predetermined hole density, the side of the conductive layer 8 facing away from the insulating layer 6 can be micro-etched. This allows the conductive layer 8 to protect the areas of the insulating layer 6 that require insulation during the shading process and reduces the difficulty of flash etching the conductive layer after the shading process. Micro-etching is a process that finely treats the metal surface, creating a microscopically rough surface structure through slight corrosion.

[0075] In some embodiments, the thickness of the conductive layer 8 after micro-etching is 1-2 μm.

[0076] In some embodiments, the diameter of the blind holes 7 in the insulating layer 6 is 15-20 μm; and the spacing between adjacent blind holes 7 is 10 μm.

[0077] The present invention uses ultra-small laser hole electroplating to create an interconnection structure layer with high-density embedded copper pillars. This interconnection structure layer can be used for arbitrary connections between different stacked structures. During the processing of high-density interconnected boards, arbitrary connections between multiple multilayer boards can be achieved, reducing the number of press-fits and eliminating the need for special alignment. For example, an interconnection structure layer with copper pillars of 15-20μm diameter and 10μm spacing can achieve high-density arbitrary interconnection of boards with dense blind vias, such as boards with BGA holes with a center-to-center spacing of 40μm.

[0078] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. An interconnection structure layer, characterized in that: The interconnect structure layer includes: Conductive column; Insulating layer; the insulating layer has through holes distributed on the entire insulating layer at a preset hole density, the through holes being used to embed the conductive pillars; The interconnection structure layer is used to be superimposed between two circuit layers with interconnection requirements, and at least one of the conductive pillars is in contact with the surface pad of the circuit layer, and the diameter of any of the conductive pillars is smaller than the minimum spacing between adjacent pads in any of the circuit layers.

2. The interconnection structure layer according to claim 1, characterized in that: The through holes are evenly distributed in the insulating layer; The distance between any two of the through holes is smaller than the diameter of the smallest pad in any of the circuit layers.

3. The interconnection structure layer according to claim 1, characterized in that: The thickness of the insulating layer is 20-50 μm.

4. The interconnection structure layer according to claim 1, characterized in that: The diameter of the conductive column is 15-20 μm; The distance between the conductive pillars is 10 μm.

5. A method for manufacturing an interconnection structure layer, characterized in that: The production method comprises: Providing a separable core panel; the separable core panel comprising a surface seed layer capable of being peeled off from the separable core panel; Laminating an insulating layer on the outer surface of the surface seed layer; Laser drilling the insulating layer according to a preset hole density to form blind holes penetrating the insulating layer; and exposing the electroplating conductive area on the surface seed layer by laser ablation; Filling the blind holes with electroplating to form conductive pillars, thereby forming an interconnection structure layer on the surface seed layer; peeling the surface seed layer from the separable core plate to separate the interconnected structure layer with the surface seed layer; A protective film is attached to a side of the interconnect structure layer facing away from the surface seed layer, and then the material of the surface seed layer is flash-etched away, and then the protective film is removed.

6. The manufacturing method according to claim 5, characterized in that: The step of laminating the insulating layer on the outer surface of the surface seed layer comprises: stacking the insulating layer and the conductive layer in sequence on the outer surface of the surface seed layer, and then pressing the conductive layer; The step of laser drilling the insulating layer according to a preset hole density to form blind holes penetrating the insulating layer comprises: Performing laser drilling on the conductive layer according to the preset hole density to form blind holes penetrating the conductive layer and the insulating layer; The blind hole is subjected to black shadow processing, and the material of the conductive layer is flash-etched away after the black shadow processing.

7. The production method according to claim 6, characterized in that: Before laser drilling holes on the conductive layer according to the preset hole density, the method further includes: Micro-etching is performed on a side of the conductive layer facing away from the insulating layer.

8. The manufacturing method according to claim 5, characterized in that: The diameter of the blind holes is 15-20 μm; the spacing between adjacent blind holes is 10 μm.

9. The production method according to claim 7, characterized in that: The thickness of the conductive layer after micro-etching is 1~2μm.

10. A circuit board, characterized in that: The circuit board comprises at least two circuit layers with interconnection requirements and at least one interconnection structure layer according to any one of claims 1 to 4; The interconnection structure layer is stacked between any two of the circuit layers.

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