Power semiconductor device

Abstract

There is provided a power semiconductor device including: a first trench recessed into a semiconductor layer in a first direction from a surface of the semiconductor layer and extending in a second direction different from the first direction; a source contact region in contact with a surface of the semiconductor layer and spaced apart from the first trench in the second direction; a source region in contact with the source contact region and one side of the first trench and having a first conductivity type impurity; a well region in contact with a bottom surface and one side of the source region, and in contact with both sides and the bottom surface of the first trench, and having a second conductivity type impurity; a drift region in contact with a bottom surface of the well region and having a first conductivity type impurity; and a junction resistance reduction cell disposed in the well region and in contact with the drift region and a bottom surface of the first trench, and having a first conductivity type impurity.

Description

[0001] This application is a divisional application with application number 202110580877.2 filed on May 26, 2021, and the invention name is Power Semiconductor Device and Manufacturing Method Thereof.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of Korean Patent Application No. 10-2020-0063131 filed in the Korean Intellectual Property Office on May 26, 2020, Korean Patent Application No. 10-2020-0064148 filed in the Korean Intellectual Property Office on May 28, 2020, Korean Patent Application No. 10-2020-0066309 filed in the Korean Intellectual Property Office on June 2, 2020, Korean Patent Application No. 10-2020-0068205 filed in the Korean Intellectual Property Office on June 5, 2020, The present invention claims priority from Korean Patent Application No. 10-2020-0069417 filed in the Korean Intellectual Property Office on June 9, 2020, Korean Patent Application No. 10-2020-0070701 filed in the Korean Intellectual Property Office on June 11, 2020, Korean Patent Application No. 10-2020-0071310 filed in the Korean Intellectual Property Office on June 12, 2020, and Korean Patent Application No. 10-2020-0144559 filed in the Korean Intellectual Property Office on November 2, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The present disclosure relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a method of manufacturing the same. Background Art

[0005] Power semiconductor devices are semiconductor devices that operate in high-voltage and high-current environments. They are used in fields requiring high-power switching, such as power conversion, power converters, and inverters. For example, power semiconductor devices may include insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field-effect transistors (MOSFETs). Power semiconductor devices generally require high withstand voltage characteristics, and now also require high-speed switching operations.

[0006] Thus, power semiconductor devices using silicon carbide (SiC) are being developed as a replacement for silicon (Si). Compared to silicon, silicon carbide (SiC), a wide-gap semiconductor material with a larger bandgap than silicon, can maintain stability even at high temperatures. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, silicon carbide makes stable operation at high temperatures possible through the following characteristics: a higher breakdown voltage than silicon and excellent heat release.

[0007] To increase the channel density of power semiconductor devices using silicon carbide, trench gate structures with vertical channel structures are being developed. However, because the electric field concentrates at the trench edges, there are limitations in reducing channel density by using structures that protect the lower portion of the trench. Furthermore, since the source contact structure is located between the gate electrodes, it is difficult to reduce the distance between the gate electrodes. This limits the reduction in channel density.

[0008] Prior art references

[0009] Patent References

[0010] Patent Document 1: Korean Patent Application Publication No. 2011-0049249 (May 12, 2011). Summary of the Invention

[0011] The present disclosure has been made to solve the above-mentioned problems occurring in the prior art while intactly maintaining the advantages achieved by the prior art.

[0012] One aspect of the present disclosure provides a silicon carbide-based power semiconductor device capable of alleviating electric field concentration and increasing channel density and a method for manufacturing the same. However, the above purpose is an example, and the scope of the present invention is not limited thereto.

[0013] The technical problems to be solved by the present disclosure are not limited to the above-mentioned problems, and any other technical problems not mentioned herein will be clearly understood by those skilled in the art to which the present disclosure belongs from the following description.

[0014] According to one aspect of the present disclosure, a power semiconductor device includes: a semiconductor layer of silicon carbide (SiC); at least one trench extending in one direction and formed to be recessed from the surface of the semiconductor layer into the semiconductor layer to a given depth; a gate insulating layer formed on at least the inner wall of the at least one trench; at least one gate electrode layer formed on the gate insulating layer to bury the at least one trench; a drift region having a first conductivity type formed in the semiconductor layer on at least one side of the at least one gate electrode layer; a well region formed in the semiconductor layer, the well region being formed deeper in the semiconductor layer than the at least one gate electrode layer to contact at least a portion of the drift region and surrounding the bottom surface of the at least one gate electrode layer at least at one end of the at least one gate electrode layer, the well region having a second conductivity type; a source region formed in the well region and having the first conductivity type; and at least one channel region having the second conductivity type formed in the semiconductor layer between the drift region and the source region and on one side of the at least one gate electrode layer, an inversion channel being formed in the at least one channel region along the one direction.

[0015] The source region includes a source contact region connected to the source electrode layer outside one end of the at least one gate electrode layer.

[0016] The power semiconductor device may include: a well contact region in the source contact region extending from the well region, through the source region and connected to the source electrode layer, the well contact region having the second conductivity type, wherein the doping concentration of the well contact region is higher than the doping concentration of the well region.

[0017] The drift region may include a vertical portion vertically extending in the semiconductor layer at one side of the at least one gate electrode layer, wherein the at least one channel region is formed in the semiconductor layer between the vertical portion of the drift region and the source region.

[0018] The well region, the source region, and the channel region are formed in the semiconductor layer to be located on opposite sides of a vertical portion of the drift region.

[0019] The drift region may include a vertical portion extending vertically in the semiconductor layer on opposite sides of the at least one gate electrode layer, wherein the at least one channel region includes a channel region formed in the semiconductor layer between the vertical portion of the drift region and the source region.

[0020] The at least one channel region may be a portion of the well region.

[0021] The at least one trench may include a plurality of trenches formed in the semiconductor layer in parallel along the one direction, wherein the at least one gate electrode layer includes a plurality of gate electrode layers formed by burying the plurality of trenches, wherein the well region and the source region extend across the plurality of gate electrode layers, and wherein the at least one channel region includes a plurality of channel regions formed in the semiconductor layer on one side of the plurality of gate electrode layers.

[0022] The source region may include a source contact region connected to a source electrode layer at an outer side of one end of the plurality of gate electrode layers.

[0023] The drift region may include a vertical portion vertically extending in the semiconductor layer between the plurality of gate electrode layers, wherein the channel region is formed in the semiconductor layer between the vertical portion of the drift region and the source region.

[0024] The at least one trench may include a plurality of trenches arranged to be spaced apart from each other in a straight line along the one direction, wherein the at least one gate electrode layer includes a plurality of gate electrode layers formed by burying the plurality of trenches, and wherein the well region and the source region are formed at least in the semiconductor layer between the plurality of trenches.

[0025] The power semiconductor device may further include a drain region formed in the semiconductor layer below the drift region and having the first conductivity type, wherein a doping concentration of the drain region is higher than a doping concentration of the drift region.

[0026] According to another aspect of the present disclosure, a power semiconductor device includes: a semiconductor layer of silicon carbide (SiC); a plurality of trenches extending in parallel in one direction and formed to be recessed from the surface of the semiconductor layer into the semiconductor layer to a given depth; a gate insulating layer formed on at least the inner walls of the trenches; a plurality of gate electrode layers formed on the gate insulating layer to bury the plurality of trenches; a drift region comprising a plurality of vertical portions formed in the semiconductor layer between the plurality of gate electrode layers; the drift region having a first conductivity type; a well region formed in the semiconductor layer, the well region being formed deeper in the semiconductor layer than the plurality of gate electrode layers to contact the plurality of vertical portions of the drift region and surrounding the bottom surfaces of the plurality of gate electrode layers at opposite ends of the plurality of gate electrode layers, the well region having a second conductivity type; a source region formed in the well region and having the first conductivity type; and a plurality of channel regions formed in the semiconductor layer between the plurality of vertical portions of the drift region and the source region and on opposite sides of the plurality of gate electrode layers, inversion channels being respectively formed in the plurality of channel regions along the one direction, the plurality of channel regions having the second conductivity type.

[0027] According to another aspect of the present disclosure, a method for manufacturing a power semiconductor device includes: forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC); forming a well region having a second conductivity type in the semiconductor layer and contacting at least a portion of the drift region; forming a source region having the first conductivity type in the well region; forming at least one channel region having the second conductivity type in the semiconductor layer between the drift region and the source region, forming an inversion channel in one direction in the channel region; forming at least one trench shallower than the well region to be recessed from the surface of the semiconductor layer into the semiconductor layer to a given depth and extending across the drift region in the one direction; forming a gate insulating layer on at least an inner wall of the at least one trench; and forming at least one gate electrode layer on the gate insulating layer to bury the at least one trench, wherein the well region is formed in the semiconductor layer deeper than the at least one gate electrode layer to surround the bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer; wherein the channel region is formed in the semiconductor layer between the drift region and the source region and on one side of the at least one gate electrode layer.

[0028] The forming of the source region may include forming a source contact region connected to the source electrode layer outside one end of the at least one gate electrode layer.

[0029] The method may further include: forming a well contact region in the source contact region, the well contact region extending from the well region through the source region and connected to the source electrode layer, the well contact region having the second conductivity type, wherein the doping concentration of the well contact region is higher than the doping concentration of the well region.

[0030] The forming of the well region may be performed by implanting impurities of the second conductivity type into the semiconductor layer, wherein the forming of the source region may be performed by implanting impurities having the first conductivity type into the well region.

[0031] The drift region may be formed on the drain region having the first conductivity type, wherein a doping concentration of the drain region is higher than a doping concentration of the drift region.

[0032] The drain region may be formed of a substrate of the first conductivity type, wherein the drift region is formed of an epitaxial layer on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings:

[0034] Figure 1is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0035] Figure 2 is shown along Figure 1 A plan view of the power semiconductor device taken along line II-II;

[0036] Figure 3 is shown along Figure 1 A cross-sectional view of the power semiconductor device taken along line III-III;

[0037] Figure 4 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0038] Figure 5 It is shown along Figure 4 A cross-sectional view of the power semiconductor device taken along line VV;

[0039] Figure 6 It is shown along Figure 4 A cross-sectional view of the power semiconductor device taken along line VI-VI;

[0040] Figures 7 to 9 is a schematic perspective view illustrating a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0041] Figure 10 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0042] Figure 11 It is shown along Figure 10 A plan view of the power semiconductor device taken along line II-II;

[0043] Figure 12 It is shown along Figure 11 A cross-sectional view of the power semiconductor device taken along line III-III;

[0044] Figure 13 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0045] Figure 14 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0046] Figure 15 It is shown along Figure 14 A plan view of the power semiconductor device taken along line VI-VI;

[0047] Figure 16 It is shown along Figure 15A cross-sectional view of the power semiconductor device taken along line VII-VII;

[0048] Figure 17 It is shown along Figure 15 A cross-sectional view of the power semiconductor device taken along line VIII-VIII;

[0049] Figure 18 and Figure 19 is a cross-sectional view illustrating a power semiconductor device according to another embodiment of the present disclosure;

[0050] Figures 20 to 22 is a schematic perspective view illustrating a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0051] Figure 23 is a graph showing a change in electric field according to a depth of a power semiconductor device according to an embodiment of the present disclosure;

[0052] Figure 24 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0053] Figure 25 It is shown along Figure 24 A plan view of the power semiconductor device taken along line II-II;

[0054] Figure 26 It is shown along Figure 25 A cross-sectional view of the power semiconductor device taken along line III-III;

[0055] Figure 27 It shows that along Figure 25 A cross-sectional view of the power semiconductor device taken along line IV-IV;

[0056] Figure 28 and Figure 29 is a cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure;

[0057] Figure 30 is a cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure;

[0058] Figure 31 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0059] Figure 32 It is shown along Figure 31 A plan view of the power semiconductor device taken along line IX-IX;

[0060] Figure 33 is shown along Figure 32A cross-sectional view of the power semiconductor device taken along line XX;

[0061] Figure 34 is a cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure;

[0062] Figures 35 to 37 is a schematic perspective view illustrating a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0063] Figure 38 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0064] Figure 39 It is shown along Figure 38 A plan view of the power semiconductor device taken along line II-II;

[0065] Figure 40 It is shown along Figure 39 A cross-sectional view of the power semiconductor device taken along line III-III;

[0066] Figure 41 is shown along Figure 39 A cross-sectional view of the power semiconductor device taken along line IV-IV;

[0067] Figure 42 and Figure 43 is a cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure;

[0068] Figure 44 is a schematic cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure;

[0069] Figures 45 to 47 is a schematic perspective view illustrating a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0070] Figure 48 is a graph showing characteristics of a diode of a power semiconductor device according to an embodiment of the present disclosure;

[0071] Figure 49 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0072] Figure 50 It is shown along Figure 49 A plan view of the power semiconductor device taken along line II-II;

[0073] Figure 51 It is shown along Figure 50 A cross-sectional view of the power semiconductor device taken along line III-III;

[0074] Figure 52 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0075] Figure 53 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0076] Figure 54 It is shown along Figure 53 A plan view of the power semiconductor device taken along line VI-VI;

[0077] Figure 55 It is shown along Figure 54 A cross-sectional view of the power semiconductor device taken along line VII-VII;

[0078] Figure 56 It is shown along Figure 54 A cross-sectional view of the power semiconductor device taken along line VIII-VIII;

[0079] Figure 57 and Figure 58 is a cross-sectional view illustrating a power semiconductor device according to another embodiment of the present disclosure;

[0080] Figures 59 to 61 is a schematic perspective view illustrating a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0081] Figure 62 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0082] Figure 63 It is shown along Figure 62 A plan view of the power semiconductor device taken along line II-II;

[0083] Figure 64 is shown along Figure 63 A cross-sectional view of the power semiconductor device taken along line III-III;

[0084] Figure 65 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0085] Figure 66 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0086] Figure 67 It is shown along Figure 66 A plan view of the power semiconductor device taken along line VI-VI;

[0087] Figure 68 It is shown along Figure 67 A cross-sectional view of the power semiconductor device taken along line VII-VII;

[0088] Figure 69 is shown along Figure 67 A cross-sectional view of the power semiconductor device taken along line VIII-VIII;

[0089] Figure 70 and Figure 71 is a cross-sectional view illustrating a power semiconductor device according to another embodiment of the present disclosure;

[0090] Figures 72 to 74 is a schematic perspective view illustrating a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0091] Figure 75 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0092] Figure 76 It is shown along Figure 75 A plan view of the power semiconductor device taken along line II-II;

[0093] Figure 77 It is shown along Figure 76 A cross-sectional view of the power semiconductor device taken along line III-III;

[0094] Figure 78 It is shown along Figure 76 A cross-sectional view of the power semiconductor device taken along line IV-IV;

[0095] Figure 79 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0096] Figure 80 It is shown along Figure 79 A plan view of the power semiconductor device taken along line VI-VI;

[0097] Figure 81 is shown along Figure 80 A cross-sectional view of the power semiconductor device taken along line VII-VII;

[0098] Figure 82 It is shown along Figure 80 A cross-sectional view of the power semiconductor device taken along line VIII-VIII;

[0099] Figures 83 to 86 is a cross-sectional view illustrating a power semiconductor device according to another embodiment of the present disclosure;

[0100] Figures 87 to 89is a schematic perspective view illustrating a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0101] Figure 90 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0102] Figure 91 It is shown along Figure 90 A plan view of the power semiconductor device taken along line II-II;

[0103] Figure 92 is shown along Figure 91 A cross-sectional view of the power semiconductor device taken along line III-III;

[0104] Figure 93 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0105] Figure 94 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0106] Figure 95 is shown along Figure 94 A plan view of the power semiconductor device taken along line VI-VI;

[0107] Figure 96 It is shown along Figure 95 A cross-sectional view of the power semiconductor device taken along line VII-VII;

[0108] Figure 97 It is shown along Figure 95 A cross-sectional view of the power semiconductor device taken along line VIII-VIII;

[0109] Figure 98 is a cross-sectional view illustrating a power semiconductor device according to another embodiment of the present disclosure; and

[0110] Figure 99 is a perspective view illustrating a power semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0111] Below, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure can be implemented in various different forms and should not be construed as being limited to the embodiments disclosed below. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete and the scope of the present invention will be fully conveyed to those skilled in the art. In addition, for ease of description, the sizes of at least some components or elements shown in the accompanying drawings may be enlarged or reduced. In the accompanying drawings, the same reference numerals refer to the same elements.

[0112] Unless otherwise defined, all terms used herein should be interpreted as commonly understood by those skilled in the art. In the drawings, the sizes of layers and regions are exaggerated for description, and thus are provided to describe the normal structure of the present disclosure.

[0113] Like reference numerals denote like components. When a first component, such as a layer, region, or substrate, is described as being "on" a second component, it can be understood that the first component is directly on the second component or that a third component is interposed therebetween. On the other hand, when a first component is described as being "directly" on a second component, it can be understood that there are no intervening components therebetween.

[0114] Figure 1 is a schematic perspective view illustrating a power semiconductor device according to an embodiment of the present disclosure. Figure 2 is shown along Figure 1 A plan view of the power semiconductor device taken along line II-II. Figure 3 is shown along Figure 1 sectional view of the power semiconductor device taken along line III-III.

[0115] Reference Figures 1 to 3 The power semiconductor device 100 - 1 may include at least a semiconductor layer 105 , a gate insulating layer 118 , and a gate electrode layer 120 . For example, the power semiconductor device 100 - 1 may have a power MOSFET structure.

[0116] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers, for example, one epitaxial layer or multiple epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0117] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). In more detail, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0118] Silicon carbide (SiC) can have a wider band gap than silicon and can therefore maintain stability even at high temperatures compared to silicon. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-1 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0119] In more detail, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping an epitaxial layer of silicon carbide with impurities of the first conductivity type.

[0120] Well region 110 may be formed in semiconductor layer 105 to contact at least a portion of drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping drift region 107 with impurities of a second conductivity type opposite to the first conductivity type.

[0121] For example, the well region 110 may be formed to surround at least a portion of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In operation of the power semiconductor device 100-1, the vertical portion 107a may provide a vertical movement path for charges.

[0122] The well region 110 is Figure 1 107 a is shown as including two regions spaced apart from each other and a vertical portion 107 a interposed between the two regions, but various changes or modifications may be made to the well region 110. For example, the vertical portion 107 a may have a shape whose side is surrounded by the well region 110.

[0123] The source region 112 may be formed in the well region 110 and may have the first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the first conductivity type impurities doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0124] At least one channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have the second conductivity type such that an inversion channel is formed along one direction.

[0125] Because the channel region 110 a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110 a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110 a may not allow charge movement under normal circumstances; however, when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, thereby allowing charge movement.

[0126] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be formed to be continuously connected to the well region 110. The doping concentration of the second conductivity type impurities in the channel region 110a may be the same as or different from the doping concentration of the rest of the well region 110 for adjusting the threshold voltage.

[0127] In some embodiments, the well region 110, the channel region 110a, and the source region 112 may be formed symmetrically with respect to the vertical portion 107a of the drift region 107. For example, each of the well region 110, the channel region 110a, and the source region 112 may include a left portion and a right portion formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the channel region 110a, and the source region 112, the left portion and the right portion may be separated from each other or may be connected to each other.

[0128] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration of impurities than the drift region 107 .

[0129] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105.

[0130] At least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 to a given depth within the semiconductor layer 105. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to a length direction of the trench 116, rather than a depth direction, and may refer to a depth direction of the trench 116. Figure 1 The direction of the line II-II or III-III.

[0131] A gate insulating layer 118 may be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof. The thickness of the gate insulating layer 118 may be uniform, or a portion of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a portion of the gate insulating layer 118 formed on the sidewall of the trench 116.

[0132] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0133] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, a vertical portion 107a of the drift region 107 may extend vertically in the semiconductor layer 105 on one side of the gate electrode layer 120.

[0134] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on opposite sides of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107a extending vertically in the semiconductor layer 105 on opposite sides of the gate electrode layer 120.

[0135] The well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. In addition, the well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite end portions of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0136] This structure can reduce the concentration of the electric field on the bottom surface of trench 116, that is, at the lower portion of gate electrode layer 120. Therefore, in power semiconductor device 100-1 according to the embodiment, well region 110 can be formed deeper than gate electrode layer 120 without separately forming a deep well, thereby reducing the electric field concentration on the bottom surface of trench 116. A problem with conventional vertical channel structures is that as the distance between the deep well and the trench becomes shorter, the junction resistance and threshold voltage increase. However, this problem may not occur in power semiconductor device 100-1 according to the embodiment.

[0137] The channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120, between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0138] The above-described structure of the channel region 110 a may be referred to as a “lateral channel structure” because the channel region 110 a is formed along the sidewall of the gate electrode layer 120 .

[0139] In addition, a channel region 110 a may be formed in the semiconductor layer 105 on an opposite side of the gate electrode layer 120 between the vertical portion 107 a of the drift region 107 and the source region 112 .

[0140] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116 , and moreover, may be formed to further extend outside the trench 116 .

[0141] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0142] For example, a plurality of trenches 116 may be formed in parallel along one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0143] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trench 116. In this way, the trench-type gate electrode layer 120 may be formed in the semiconductor layer 105 and arranged to extend parallel to the trench 116 in the same direction.

[0144] In addition, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107 a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. A plurality of channel regions 110 a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107 a of the drift region 107 on one side or opposite sides of each gate electrode layer 120.

[0145] In some embodiments, the well region 110 may be formed deeper in the semiconductor layer 105 than the gate electrode layer 120 , thereby contacting the vertical portion 107 a of the drift region 107 and surrounding a bottom surface of the gate electrode layer 120 at opposite ends thereof.

[0146] An interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

[0147] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, or the like.

[0148] For clarity, with Figure 2 and Figure 3 Different, in Figure 1 The interlayer insulating layer 130 and the source electrode layer 140 are not shown.

[0149] In the power semiconductor device 100-1 described above, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of an n-type and a p-type. For example, when the first conductivity type is an n-type, the second conductivity type is a p-type, and vice versa.

[0150] In more detail, when the power semiconductor device 100 - 1 is an N-type MOSFET, the drift region 107 can be an N-region, the source region 112 , the source contact region 112 a and the drain region 102 can be N+ regions, the well region 110 and the channel region 110 a can be P-regions, and the well contact region 114 can be a P+ region.

[0151] In operation of the power semiconductor device 100 - 1 , current may generally flow in a vertical direction from the drain region 102 along the vertical portion 107 a of the drift region 107 , and then may flow through the channel region 110 a along the side surface of the gate electrode layer 120 to the source region 112 .

[0152] In the above-described power semiconductor device 100-1, the gate electrode layers 120 may be densely arranged in parallel in a stripe shape, and the channel regions 110a may be arranged on the side surfaces of the gate electrode layers 120. In this way, the channel density may be increased.

[0153] In addition, in power semiconductor device 100-1, since the bottom surface of gate electrode layer 120 is surrounded by well region 110, the breakdown phenomenon caused by the electric field concentration on the edge of trench 116 may be reduced. Therefore, the high withstand voltage characteristics of power semiconductor device 100-1 can be improved. This may mean that the reliability of operation of power semiconductor device 100-1 is improved.

[0154] Figure 4 is a schematic perspective view illustrating a power semiconductor device 100 a - 1 according to another embodiment of the present disclosure. Figure 5 It is shown along Figure 4 1 is a cross-sectional view of the power semiconductor device 100 a - 1 taken along line VV. Figure 6 is shown along Figure 4 1 is a cross-sectional view of the power semiconductor device 100 a - 1 taken along line VI-VI.

[0155] The power semiconductor device 100 a - 1 according to this embodiment may be modified by using or partially Figures 1 to 3 Therefore, additional description will be omitted to avoid redundancy.

[0156] Reference Figures 4 to 6 The source region 112 may include a source contact region 112 a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120 . For example, the source contact region 112 a as a portion of the source region 112 may refer to a portion connected to the source electrode layer 140 .

[0157] Well contact region 114 may be formed in source contact region 112a. For example, well contact region 114 may extend from well region 110 to penetrate source region 112 and may have the second conductivity type. One well contact region 114 or multiple well contact regions 114 may be formed in source contact region 112a.

[0158] For example, the well contact region 114 may be connected to the source electrode layer 140 and may be doped with second conductive type impurities at a higher concentration than that of the well region 110 to reduce contact resistance when connected to the source electrode layer 140 .

[0159] exist Figures 4 to 6 , source contact region 112 a and well contact region 114 are formed in source region 112 on one side of vertical portion 107 a of drift region 107. However, when each of source region 112 and well region 110 is divided into a plurality of regions, each of source contact region 112 a and well contact region 114 may be formed in each corresponding region.

[0160] In some embodiments, the plurality of trenches 116 may be arranged to be linearly spaced apart from one another along one direction. Thus, the gate electrode layer 120 may also be arranged to be linearly spaced apart from one another along the trenches 116. In this case, the well region 110 and the source region 112 may be formed in the semiconductor layer 105 such that the well region 110 and the source region 112 are located between the plurality of trenches 116 linearly spaced apart from one another along one direction.

[0161] For example, Figures 1 to 3 The structure of the power semiconductor device 100 - 1 shown may be arranged in plurality along one direction, and the well region 110 and the source region 112 may be formed therebetween.

[0162] For clarity, with Figure 5 and Figure 6 Different, in Figure 4 The interlayer insulating layer 130 and the source electrode layer 140 are not shown.

[0163] In the power semiconductor device 100a-1 according to the embodiment, the source contact region 112a and the well contact region 114 can be arranged outside the gate electrode layer 120, rather than between the gate electrode layers 120. Therefore, the gate electrode layers 120 can be arranged more densely. In this way, the channel density of the power semiconductor device 100a-1 can be significantly increased. In addition, according to the power semiconductor device 100a-1, the breakdown phenomenon caused by the concentration of the electric field on the edge of the trench 116 can be reduced, thereby improving the high voltage resistance characteristics of the power semiconductor device 100a-1. This may mean that the reliability of the operation of the power semiconductor device 100a-1 is improved.

[0164] Figures 7 to 9 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 a - 1 according to an embodiment of the present disclosure.

[0165] Reference Figure 7 A drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented using a substrate having a first conductivity type, and the drift region 107 can be formed on the substrate using one or more epitaxial layers.

[0166] Next, a well region 110 having the second conductivity type may be formed in semiconductor layer 105 so as to contact at least a portion of drift region 107. For example, the formation of well region 110 may be performed by implanting impurities of the second conductivity type into semiconductor layer 105.

[0167] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107 a, at least a portion of the vertical portion 107 a being surrounded by the well region 110. In more detail, the well region 110 may be formed by doping the drift region 107 with impurities having a conductivity type opposite to that of the drift region 107.

[0168] Then, a source region 112 having the first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities of the first conductivity type into the well region 110.

[0169] In addition to forming the source region 112, at least one channel region 110a having the second conductivity type, in which an inversion channel is formed along one direction, may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. For example, the channel region 110a may be formed between the source region 112 and the vertical portion 107a of the drift region 107.

[0170] In the above-described manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selective region.

[0171] Alternatively, a heat treatment process for activating or diffusing impurities may be performed after the ion implantation.

[0172] Reference Figure 8 , at least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0173] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110 .

[0174] In addition, a plurality of trenches 116 may be formed in parallel in one direction in the semiconductor layer 105 .

[0175] For example, the trench 116 can be formed by forming a photomask using photolithography and then etching the semiconductor layer 105 using the photomask as an etching protection layer.

[0176] Reference Figure 9 , a gate insulating layer 118 may be formed on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0177] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0178] The patterning process may be performed using photolithography and etching processes. The photolithography process may include forming a photoresist pattern as a mask layer using a photo process and a developing process, and the etching process may include selectively etching an underlying structure using the photoresist pattern.

[0179] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and a channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0180] In addition, refer to Figure 2 and Figure 3 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

[0181] Next, the source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may be formed by forming a conductive layer (eg, a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0182] at the same time, Figures 4 to 6The power semiconductor device 100 a - 1 in the embodiment may be manufactured by adding some processes to the above-described method for manufacturing the power semiconductor device 100 - 1 or by changing or modifying the manufacturing method.

[0183] For example, when manufacturing power semiconductor device 100a-1, forming source region 112 may include forming source contact region 112a connected to source electrode layer 140 outside at least one end of gate electrode layer 120. In some embodiments, source contact region 112a may not be separated from source region 112.

[0184] In addition, well contact region 114 may be formed in source contact region 112a before forming trench 116. For example, well contact region 114 may be formed by implanting a second conductivity type impurity having a higher concentration than well region 110 into a portion of well region 110.

[0185] When manufacturing the power semiconductor device 100 a - 1 , the trenches 116 may be arranged to be linearly spaced apart from each other in one direction. In addition, the well region 110 , the channel region 110 a , and the source region 112 may be formed in the semiconductor layer between the trenches 116 .

[0186] According to the above-described manufacturing method, the power semiconductor device 100 - 1 using the semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0187] Figure 10 is a schematic perspective view illustrating a power semiconductor device 100 - 2 according to an embodiment of the present disclosure. Figure 11 is shown along Figure 10 1 is a plan view of the power semiconductor device 100 - 2 taken along line II-II. Figure 12 is shown along Figure 11 1 is a cross-sectional view of the power semiconductor device 100 - 2 taken along line III-III.

[0188] Reference Figures 10 to 12 The power semiconductor device 100-2 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-2 may have a power MOSFET structure.

[0189] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers, for example, one epitaxial layer or multiple epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0190] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). In more detail, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0191] Silicon carbide (SiC) can have a wider band gap than silicon, and therefore maintains stability even at high temperatures compared to silicon. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-2 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0192] In more detail, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping an epitaxial layer of silicon carbide with impurities of the first conductivity type.

[0193] Well region 110 may be formed in semiconductor layer 105 to contact drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping drift region 107 with impurities of a second conductivity type opposite to the first conductivity type.

[0194] For example, the well region 110 may be formed to surround at least a portion of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In operation of the power semiconductor device 100-2, the vertical portion 107a may provide a vertical movement path for charges.

[0195] exist Figure 10 The well region 110 shown in FIG. 1 includes two regions spaced apart from each other and a vertical portion 107 a interposed between the two regions, but various changes or modifications may be made to the well region 110. For example, the vertical portion 107 a may have a shape whose side surfaces are surrounded by the well region 110.

[0196] The pillar region 111 may be formed in the semiconductor layer 105 below the well region 110 to contact the drift region 107. In this way, a super junction with the drift region 107 may be formed. For example, the pillar region 111 may be disposed below the well region 110 to contact the well region 110, and opposite side surfaces of the pillar region 111 may be disposed to contact the drift region 107.

[0197] The stud region 111 may have a conductivity type different from that of the drift region 107 and may be formed in the semiconductor layer 105 so as to form a superjunction with the drift region 107. For example, the stud region 111 may have a second conductivity type opposite to that of the drift region 107 and the same conductivity type as that of the well region 110. For example, the doping concentration of the second conductivity type impurity in the stud region 111 may be the same as or lower than the doping concentration of the second conductivity type impurity in the well region 110.

[0198] In some embodiments, the pillar region 111 may be formed to have a width narrower than that of the well region 110 based on one direction. The one direction may refer to Figure 11 In addition, opposite ends of the pillar region 111 may be arranged to be offset inward from opposite ends of the well region 110 based on one direction.

[0199] Thus, under the well region 110, the pillar region 111 may be formed to recede inward from opposite ends of the well region 110 while being in contact with the well region 110. For example, the pillar region 111 may be formed in two regions spaced apart from each other like the well region 110, and the spacing distance between the two pillar regions 111 may be greater than the spacing distance between the two well regions 110.

[0200] In some embodiments, the side surfaces and bottom surfaces of the stud region 111 may contact the drift region 107. For example, a plurality of stud regions 111 and a plurality of drift regions 107 may be alternately arranged so that the side surfaces of the stud regions 111 and the side surfaces of the drift region 107 contact each other, thereby forming a super junction structure. In addition, a plurality of stud regions 111 and a plurality of drift regions 107 may be alternately arranged below a single well region 110.

[0201] The source region 112 may be formed in the well region 110 and may have the first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the first conductivity type impurities doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0202] Channel region 110a may be formed in semiconductor layer 105 between drift region 107 and source region 112. For example, channel region 110a may have the second conductivity type, and an inversion channel may be formed in channel region 110a along one direction in operation of power semiconductor device 100-2.

[0203] Because the channel region 110 a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110 a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110 a may not allow charge movement under normal circumstances; however, when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, thereby allowing charge movement.

[0204] In some embodiments, the channel region 110a may be a portion of the well region 110. In this case, the channel region 110a may be entirely formed to be continuously connected to the well region 110. The doping concentration of the second conductivity type impurities of the channel region 110a may be the same as or different from the doping concentration of the rest of the well region 110 to adjust the threshold voltage.

[0205] In some embodiments, the well region 110, the pillar region 111, the channel region 110a, and the source region 112 may be formed symmetrically with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the pillar region 111, the channel region 110a, and the source region 112 may be formed at opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the pillar region 111, the channel region 110a, and the source region 112 may include a first portion and a second portion formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the pillar region 111, the channel region 110a, and the source region 112, the first portion and the second portion may be separated from each other or may be connected to each other.

[0206] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration of impurities than the drift region 107 .

[0207] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105.

[0208] At least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 to a given depth in the semiconductor layer 105. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to a length direction of the trench 116, rather than a depth direction, and may refer to a depth direction of the trench 116. Figure 11 The direction of the line III-III.

[0209] The gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or a portion of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a portion of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0210] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stack structure thereof.

[0211] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0212] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, a vertical portion 107a of the drift region 107 may extend vertically in the semiconductor layer 105 on one side of the gate electrode layer 120. A channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0213] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107 a extending vertically in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. The channel region 110 a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107 a of the drift region 107 and the source region 112.

[0214] The above-described structure of the channel region 110 a may be referred to as a “lateral channel structure” because the channel region 110 a is formed along the sidewall of the gate electrode layer 120 .

[0215] The well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. In addition, the well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite end of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0216] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116 , and moreover, may be formed to further extend outside the trench 116 .

[0217] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0218] For example, a plurality of trenches 116 may be formed in parallel along one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0219] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trench 116. In this way, the gate electrode layers 120 may be formed in a trench shape in the semiconductor layer 105 and may be arranged to extend parallel to the trench 116 in one direction.

[0220] In addition, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107 a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. A channel region 110 a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107 a of the drift region 107 on one side or opposite sides of each gate electrode layer 120.

[0221] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as oxide or nitride, or may include a stack structure thereof.

[0222] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, or the like.

[0223] In the power semiconductor device 100-2 described above, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of an n-type and a p-type. For example, when the first conductivity type is an n-type, the second conductivity type is a p-type, and vice versa.

[0224] In more detail, when the power semiconductor device 100 - 2 is an N-type MOSFET, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+ regions, and the well region 110 , the pillar region 111 and the channel region 110 a may be P-regions.

[0225] In operation of the power semiconductor device 100 - 2 , current may generally flow in a vertical direction from the drain region 102 along the vertical portion 107 a of the drift region 107 , and then may flow through the channel region 110 a along the side surface of the gate electrode layer 120 to the source region 112 .

[0226] In the power semiconductor device 100-2 described above, the gate electrode layers 120 in the trenches 116 may be densely arranged in parallel in a stripe or line type, and the channel regions 110a may be provided on the side surfaces of the gate electrode layers 120. In this way, the channel density may be increased.

[0227] In addition, in the power semiconductor device 100-2 described above, the well (110) structure can reduce the concentration of the electric field at the bottom surface of the trench 116, that is, at the lower portion of the gate electrode layer 120. As a result, the margin of the electric field of the gate insulating layer 118 covering the power semiconductor device 100-2 can be increased, thereby improving the reliability of the operation of the power semiconductor device 100-2. In addition, the junction resistance of the vertical portion 107a of the drift region 107 can be reduced by reducing the electric field at the bottom surface of the trench 116 and reducing the electric field covering the gate insulating layer 118.

[0228] At the same time, because power semiconductor device 100-2 is used for high-power switching, it requires high withstand voltage characteristics. When a high voltage is applied to drain region 102, a depletion region can expand from semiconductor layer 105 adjacent to drain region 102, lowering the voltage barrier of the channel. This phenomenon is called "drain-induced barrier lowering (DIBL)."

[0229] DIBL may cause abnormal conduction of the channel region 110 a and, furthermore, may induce a punch-through phenomenon in which a depletion region from the drain side reaches the source side as it expands.

[0230] However, the power semiconductor device 100 - 2 described above can ensure appropriate high withstand voltage characteristics by suppressing abnormal current and punch-through phenomena due to DIBL by using the pillar region 111 forming a super junction with the drift region 107 .

[0231] By adjusting the charge amount of the pillar region 111 and the charge amount of the drift region 107 , the high withstand voltage characteristic can be further improved.

[0232] Figure 23 is a graph showing a change in electric field according to the depth of the power semiconductor device 100 - 2 .

[0233] Reference Figure 23 When the charge amount Qp of the pillar region 111 is greater than the charge amount Qn of the drift region 107 , in operation of the power semiconductor device 100 - 2 , the breakdown voltage can be increased by allowing a maximum electric field to be formed in the drift region 107 on the same line as the bottom surface of the pillar region 111 . Figure 23 The slope of the electric field strength between position A and position B in FIG can be controlled by adjusting the charge amount Qp of the pillar region 111 .

[0234] For example, by making the doping concentration of the second conductivity type impurities in the pillar region 111 higher than the doping concentration of the first conductivity type impurities in the drift region 107, the charge amount Qp of the pillar region 111 can be made greater than the charge amount Qn of the drift region 107. Therefore, the high withstand voltage characteristics of the power semiconductor device 100-2 can be improved.

[0235] Figure 13 is a perspective view illustrating a power semiconductor device 100 a - 2 according to another embodiment of the present disclosure.

[0236] The power semiconductor device 100 a - 2 according to the embodiment may be modified by using or partially Figures 10 to 12 Therefore, additional description will be omitted to avoid redundancy.

[0237] Reference Figure 13 In the power semiconductor device 100a-2, a channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may have a first conductivity type, and during operation of the power semiconductor device 100a-2, an accumulation channel may be formed in the channel region 107b.

[0238] For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b may have the same doping type as that of the source region 112 and the drift region 107.

[0239] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the silicon carbide semiconductor layer 105, due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118, the energy band of the channel region 107b is bent upward, forming a potential barrier. In this way, an accumulation channel can be formed that allows charge or current to flow in the channel region 107b only when an operating voltage is applied to the gate electrode layer 120.

[0240] Therefore, the threshold voltage applied to the gate electrode layer 120 for forming an accumulation channel in the channel region 107b can be significantly lower than that for forming an accumulation channel. Figures 10 to 12 The inversion channel of the channel region 110a in the gate electrode layer 120 is applied to the threshold voltage.

[0241] In some embodiments, the channel region 107b may be a portion of the drift region 107. More specifically, the channel region 107b may be a portion of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 through the channel region 107b. That is, the drift region 107 and the source region 112 may be in contact with each other at the channel region (107b).

[0242] The doping concentration of the first conductive type impurities of the channel region 107 b may be the same as or different from the doping concentration of the rest of the drift region 107 to adjust a threshold voltage.

[0243] As a modified example of the embodiment, well region 110 may be formed to protrude farther toward vertical portion 107 a of drift region 107 than a portion of source region 112 , and channel region 107 b may be formed in semiconductor layer 105 on the protruding portion of well region 110 .

[0244] In addition, the well region 110 may further include a tap portion extending at an end of the protruding portion toward the gate electrode layer 120. The channel region 107b may be formed on the protruding portion and the tap portion of the well region 110 in a bent shape.

[0245] In addition, vertical portion 107a of drift region 107 may further extend between a lower portion of source region 112 and well region 110. In this case, channel region 107b may be formed to further extend between a lower portion of source region 112 and well region 110.

[0246] The above structure may allow the channel region 107 b to be more confined between the gate electrode layer 120 and the well region 110 .

[0247] The power semiconductor device 100a-2 may include Figures 10 to 12The advantages of the power semiconductor device 100 - 2 shown, and in addition, the threshold voltage can be made low.

[0248] Figure 14 is a schematic perspective view illustrating a power semiconductor device 100 b - 2 according to another embodiment of the present disclosure. Figure 15 It is shown along Figure 14 VI-VI is a plan view of the power semiconductor device 100 b - 2 . Figure 16 It shows that along Figure 15 VII-VII is a cross-sectional view of the power semiconductor device 100 b - 2 . Figure 17 It shows that along Figure 15 1 is a cross-sectional view of the power semiconductor device 100 b - 2 taken along line VIII-VIII.

[0249] The power semiconductor device 100 b - 2 according to the embodiment may be modified by using or partially Figures 10 to 12 Therefore, additional description will be omitted to avoid redundancy.

[0250] Reference Figures 14 to 17 In the power semiconductor device 100 b - 2 , the source region 112 may include a source contact region 112 a outside at least one end of the gate electrode layer 120 . For example, the source contact region 112 a as a portion of the source region 112 may refer to a portion connected to the source electrode layer 140 .

[0251] Well contact region 114 may be formed in source contact region 112a. For example, well contact region 114 may extend from well region 110 to penetrate source region 112 and may have the second conductivity type. One well contact region 114 or multiple well contact regions 114 may be formed in source contact region 112a.

[0252] For example, the well contact region 114 may be doped with second conductive type impurities at a higher concentration than that of the well region 110 to reduce contact resistance when connected to the source electrode layer 140 .

[0253] The source electrode layer 140 may be commonly connected to the source contact region 112 a and the well contact region 114 .

[0254] exist Figures 14 to 17 , an example is shown in which a source contact region 112 a and a well contact region 114 are formed in the source region 112 on one side of the vertical portion 107 a of the drift region 107. However, when each of the source region 112 and the well region 110 is divided into a plurality of regions, each of the source contact region 112 a and the well contact region 114 may be formed in each corresponding region.

[0255] In some embodiments, the plurality of trenches 116 may be arranged to be linearly spaced apart from one another along one direction. Thus, the gate electrode layer 120 may also be arranged to be linearly spaced apart from one another along the trenches 116 in the one direction. In this case, the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from one another along the one direction.

[0256] For example, the power semiconductor device 100b-2 can be formed by arranging a plurality of Figures 10 to 12 The structure of the power semiconductor device 100 - 2 is formed by arranging a well region 110 , a source region 112 , a source contact region 112 a and a well contact region 114 therebetween.

[0257] For example, when the power semiconductor device 100 - 2 is an N-type MOSFET, the source contact region 112 a may be an N+ region, and the well contact region 114 may be a P+ region.

[0258] According to the power semiconductor device 100 b - 2 , the source contact region 112 a and the well contact region 114 can be disposed outside the gate electrode layer 120 rather than between the gate electrode layers 120 , thereby allowing the gate electrode layers 120 to be arranged more densely. In this way, the channel density of the power semiconductor device 100 a - 2 can be significantly increased.

[0259] Figure 18 and Figure 19 100c-2 and 100d-2 according to other embodiments of the present disclosure. Figures 14 to 17 Therefore, additional description will be omitted to avoid redundancy.

[0260] Reference Figure 18 , power semiconductor device 100c-2 may include at least one recess 138 in source contact region 112a of source region 112, which is formed to penetrate source region 112 and be recessed into well region 110. Well contact region 114a may be formed on at least a bottom surface of recess 138 so as to contact well region 110.

[0261] A source electrode layer 140a may be formed to fill the groove 138, and thus the source electrode layer 140a may be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure may widen the contact area between the source electrode layer 140a and the well region 110, and the contact area between the source electrode layer 140a and the source region 112, thereby reducing the contact resistance therebetween.

[0262] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Therefore, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above-described structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0263] Reference Figure 19 ,replace Figure 14 and 17 The power semiconductor device 100b-2 may include a channel region 110a of the power semiconductor device 100d-2, and a channel region 107b forming an accumulation channel. The structure of the power semiconductor device 100d-2 including the channel region 107b may refer to Figure 13 Description given.

[0264] Therefore, the power semiconductor device 100d-2 may correspond to the following structure: Figure 13 The power semiconductor device 100 a - 2 is in a plurality of connections, with a well region 110 , a source region 112 , a source contact region 112 a and a well contact region 114 disposed therebetween.

[0265] Figures 20 to 22 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 2 according to an embodiment of the present disclosure.

[0266] Reference Figure 20 A drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented using a substrate of the first conductivity type, and the drift region 107 can be formed using one or more epitaxial layers on the substrate.

[0267] Next, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities having the second conductivity type into the semiconductor layer 105. The well region 110 may be formed substantially to a given depth from the surface of the semiconductor layer 105.

[0268] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In more detail, the well region 110 may be formed by doping the drift region 107 with impurities of a conductivity type opposite to that of the drift region 107.

[0269] Next, a stud region 111 having the second conductivity type may be formed in the semiconductor layer 105 below the well region 110, such that the stud region 111 contacts the drift region 107 to form a superjunction with the drift region 107. The stud region 111 may be formed by implanting impurities of the same second conductivity type as the well region 110. The well region 110 and the stud region 111 may be formed in any order.

[0270] Then, a source region 112 having the first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities of the first conductivity type into the well region 110. The source region 112 may be formed in the well region 110 substantially from the surface of the semiconductor layer 105 to a given depth.

[0271] In addition to forming the source region 112, a channel region 110 a having an inversion channel formed in one direction may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. The channel region 110 a may be formed between the source region 112 and the vertical portion 107 a of the drift region 107. For example, the channel region 110 a may be part of the well region 110 and may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0272] In a modified example of the embodiment, the order of forming the well region 110 , the pillar region 111 , the source region 112 , and the channel region 110 a or the order of doping impurities may be changed to any order.

[0273] In the above-described manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selective region.

[0274] Alternatively, a heat treatment process for activating or diffusing impurities may be performed after the ion implantation.

[0275] Reference Figure 21 , at least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0276] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110 .

[0277] In addition, the at least one trench 116 may include a plurality of trenches 116 , and the trenches 116 may be simultaneously formed in the semiconductor layer 105 , for example, in parallel in one direction. The channel region 110 a may be further limited by the trenches 116 .

[0278] For example, the trench 116 can be formed by forming a photomask using photolithography and then etching the semiconductor layer 105 using the photomask as an etching protection layer.

[0279] Reference Figure 22 A gate insulating layer 118 may be formed on the bottom and inner wall of the trench 116. For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0280] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0281] The patterning process may be performed using a photolithography process and an etching process. The photolithography process may include a process of forming a photoresist pattern as a mask layer by using a photo process and a development process, and the etching process may include a process of selectively etching a lower structure by using the photoresist pattern.

[0282] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0283] Next, an interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

[0284] Next, the source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may be formed by forming a conductive layer (eg, a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0285] at the same time, Figure 13 The power semiconductor device 100a-2 can be manufactured by adding some processes to the above-described method for manufacturing the power semiconductor device 100-2 or by changing or modifying the method. For example, the channel region 107b can be formed with a portion of the drift region 107 to form an accumulation channel.

[0286] Figures 14 to 17 The power semiconductor device 100 b - 2 may be manufactured by adding some processes to the above-described method for manufacturing the power semiconductor device 100 - 2 or by changing or modifying the manufacturing method.

[0287] For example, when manufacturing power semiconductor device 100b-2, forming source region 112 may include forming source contact region 112a connected to source electrode layer 140 outside at least one end of gate electrode layer 120. In some embodiments, source contact region 112a may be a portion of source region 112.

[0288] In addition, well contact region 114 may be formed in source contact region 112a before forming trench 116. For example, well contact region 114 may be formed by implanting a second conductivity type impurity having a higher concentration than well region 110 into a portion of well region 110.

[0289] When manufacturing the power semiconductor device 100 b - 2 , the trenches 116 may be arranged to be linearly spaced apart from each other in one direction. In addition, the well region 110 , the channel region 110 a , and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116 .

[0290] Reference Figure 18 The described manufacturing method of the power semiconductor device 100c-2 may further include: forming at least one groove 138 in the source region 112 to penetrate the source region 112 and be recessed into the well region 110; forming a well contact region 114 on the bottom surface of the groove 138 to contact the well region 110, and forming a source electrode layer 140 to be connected to the well contact region 114.

[0291] According to the above-described manufacturing method, the power semiconductor device 100 - 2 using the semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0292] Figure 24 is a schematic perspective view illustrating a power semiconductor device 100 - 3 according to an embodiment of the present disclosure. Figure 25 It is shown along Figure 24 A plan view of the power semiconductor device 100 - 3 taken along line II-II. Figure 24 . Figure 26 It is shown along Figure 25 1 is a cross-sectional view of the power semiconductor device 100 - 3 taken along line III-III. Figure 27 It shows that along Figure 25 1 is a cross-sectional view of the power semiconductor device 100 - 3 taken along line IV-IV.

[0293] Reference Figures 24 to 27 The power semiconductor device 100-3 may include a semiconductor layer 105, a gate insulating layer 118, and at least one gate electrode layer 120. For example, the power semiconductor device 100-3 may have a power MOSFET structure.

[0294] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers, for example, one epitaxial layer or multiple epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0295] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). In more detail, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0296] Silicon carbide (SiC) can have a wider band gap than silicon and therefore can maintain greater stability than silicon even at high temperatures. Furthermore, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-3 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0297] In more detail, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into an epitaxial layer of silicon carbide.

[0298] Well region 110 may be formed in semiconductor layer 105 to contact drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping drift region 107 with impurities of a second conductivity type opposite to the first conductivity type.

[0299] For example, the well region 110 may be formed to surround at least a portion of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In operation of the power semiconductor device 100-3, the vertical portion 107a may provide a vertical movement path for charges.

[0300] Figure 24 The well region 110 shown in FIG. 1 includes two regions spaced apart from each other and a vertical portion 107 a interposed between the two regions, but various changes or modifications may be made to the well region 110. For example, the vertical portion 107 a may have a shape whose side surfaces are surrounded by the well region 110.

[0301] Field reduction region 111 may be formed to be spaced apart from well region 110 at a given depth in semiconductor layer 105 and may have the second conductivity type. Field reduction region 111 may be formed by implanting impurities of the second conductivity type, and the doping concentration of field reduction region 111 may be the same as or lower than the doping concentration of well region 110.

[0302] The source region 112 may be formed in the well region 110 and may have the first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the first conductivity type impurities doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0303] The channel region 110a may be formed in the semiconductor layer 105 between the drift layer 107 and the source region 112. For example, the channel region 110a may have the second conductivity type, and an inversion channel may be formed in the channel region 110a along one direction during operation of the power semiconductor device 100-3.

[0304] Because the channel region 110 a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110 a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110 a may not allow charge movement under normal circumstances; however, when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, thereby allowing charge movement.

[0305] In some embodiments, the channel region 110a may be a portion of the well region 110. In this case, the channel region 110a may be entirely formed to be continuously connected to the well region 110. The doping concentration of the second conductivity type impurities of the channel region 110a may be the same as or different from the doping concentration of the impurities of the rest of the well region 110 to adjust the threshold voltage.

[0306] In some embodiments, the well region 110, the channel region 110a, and the source region 112 may be formed symmetrically with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 may be formed at opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the channel region 110a, and the source region 112 may include a first portion and a second portion that are formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the channel region 110a, and the source region 112, the first portion and the second portion may be separated from each other or may be connected to each other.

[0307] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration of impurities than the drift region 107 .

[0308] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105.

[0309] At least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 to a given depth in the semiconductor layer 105. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to a length direction of the trench 116, rather than a depth direction of the trench 116, and may refer to a depth of the trench 116. Figure 25 The direction of the line III-III.

[0310] The gate insulating layer 118 may be formed on at least the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or a portion of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a portion of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0311] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stack structure thereof.

[0312] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0313] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, a vertical portion 107a of the drift region 107 may extend vertically in the semiconductor layer 105 on one side of the gate electrode layer 120. A channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120, between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0314] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107 a extending vertically in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. The channel region 110 a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107 a of the drift region 107 and the source region 112.

[0315] The above-described structure of the channel region 110 a may be referred to as a “lateral channel structure” because the channel region 110 a is formed along the sidewall of the gate electrode layer 120 .

[0316] The well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. In addition, the well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite end of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0317] The field reduction region 111 may be formed in the semiconductor layer 105 below the bottom surface of the gate electrode layer 120 to be separated from the well region 110. In more detail, the field reduction region 111 may be formed to contact the gate insulating layer 118 below the bottom surface of the gate electrode layer 120 and to surround the bottom surface of the trench 116 or the gate electrode layer 120. The field reduction region 111 may have a floating structure to which an external power source is not directly applied.

[0318] According to this floating structure, well region 110 can surround the bottom surface of gate electrode layer 120 at its opposite ends, and field reduction region 111 can surround the bottom surface at the central portion of gate electrode layer 120. Therefore, the structure of well region 110 and the arrangement of field reduction region 111 can further alleviate the concentration of the electric field on the bottom surface of trench 116, that is, the concentration at the lower portion of gate electrode layer 120.

[0319] In this way, the electric field margin of the gate insulating layer 118 covering the power semiconductor device 100-3 can be increased, thereby improving the operational reliability of the power semiconductor device 100-3. In addition, the junction resistance of the vertical portion 107a of the drift region 107 can be reduced by reducing the electric field at the bottom surface of the trench 116 and reducing the electric field covering the gate insulating layer 118.

[0320] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116 , and moreover, may be formed to further extend outside the trench 116 .

[0321] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0322] For example, a plurality of trenches 116 may be formed in parallel along one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0323] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trench 116. In this way, the gate electrode layers 120 may be formed in a trench shape in the semiconductor layer 105 and may be arranged to extend parallel to the trench 116 in one direction.

[0324] Furthermore, the field reduction regions 111 may be respectively disposed below the bottom surface of the trench 116 or below the bottom surface of the gate electrode layer 120 to contact the gate insulating layer 118. In this case, the field reduction regions 111 may collectively refer to a plurality of island regions.

[0325] In addition, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107 a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. A channel region 110 a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107 a of the drift region 107 on one side or opposite sides of each gate electrode layer 120.

[0326] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as oxide or nitride, or may include a stack structure thereof.

[0327] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, or the like.

[0328] In the power semiconductor device 100-3 described above, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of an n-type and a p-type. For example, when the first conductivity type is an n-type, the second conductivity type is a p-type, and vice versa.

[0329] In more detail, when the power semiconductor device 100 - 3 is an N-type MOSFET, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+ regions, and the well region 110 , the field reduction region 111 and the channel region 110 a may be P-regions.

[0330] In operation of the power semiconductor device 100 - 3 , current may generally flow in a vertical direction from the drain region 102 along the vertical portion 107 a of the drift region 107 , and then may flow through the channel region 110 a along the side surface of the gate electrode layer 120 to the source region 112 .

[0331] In the power semiconductor device 100-3 described above, the gate electrode layers 120 in the trenches 116 may be densely arranged in parallel in a stripe or line type, and the channel regions 110a may be provided on side surfaces of the gate electrode layers 120. Therefore, the channel density may be increased.

[0332] Figure 28 and Figure 29 is a cross-sectional view showing a power semiconductor device 100a-3 according to another embodiment of the present disclosure. Figures 24 to 27 The power semiconductor device 100 a - 3 is implemented by a partial configuration of the power semiconductor device 100 - 3 in FIG. 1 , and therefore, additional description will be omitted to avoid redundancy.

[0333] Reference Figure 28 and 29 The field reduction region 111 a may be disposed below the bottom surface of the gate electrode layer 120, that is, may be formed to be spaced apart from the gate insulating layer 118 below the bottom surface of the gate electrode layer 120. In addition, the field reduction region 111 a may be arranged in an island structure or a floating structure to be surrounded by the drift region 107 below the gate electrode layer 120.

[0334] When a plurality of trenches 116 are provided, the field reducing regions 111 a may be disposed in a floating structure or an island structure below the bottom surface of the trenches 116 or below the bottom surface of the gate electrode layer 120 , respectively.

[0335] Even in the floating structure or the island structure, the field reduction region 111 a may be disposed below the bottom surface of the trench 116 , thereby alleviating electric field concentration on the gate insulating layer 118 at the bottom surface of the trench 116 .

[0336] Figure 30 is a cross-sectional view showing a power semiconductor device 100b-3 according to another embodiment of the present disclosure. The power semiconductor device 100b-3 may be formed by using or partially modifying Figures 24 to 29 Therefore, additional description will be omitted to avoid repetition.

[0337] Reference Figure 30 In the power semiconductor device 100 b - 3 , a channel region 107 b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112 . For example, the channel region 107 b may have a first conductivity type. During operation of the power semiconductor device 100 b - 3 , an accumulation channel may be formed in the channel region 107 b .

[0338] For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b may have the same doping type as the source region 112 and the drift region 107.

[0339] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the silicon carbide semiconductor layer 105, due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118, the energy band of the channel region 107b is bent upward, forming a potential barrier. In this way, an accumulation channel can be formed that allows charge or current to flow in the channel region 107b only when an operating voltage is applied to the gate electrode layer 120.

[0340] Therefore, the threshold voltage applied to the gate electrode layer 120 for forming an accumulation channel in the channel region 107b can be significantly lower than that for forming an accumulation channel. Figures 24 to 28 The inversion channel of the channel region 110a in the gate electrode layer 120 is applied to the threshold voltage.

[0341] In some embodiments, the channel region 107b may be a portion of the drift region 107. More specifically, the channel region 107b may be a portion of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be integrally formed with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 through the channel region 107b. That is, the drift region 107 and the source region 112 may be in contact with each other at the channel region (107b).

[0342] The doping concentration of the first conductivity type impurities of the channel region 107 b may be the same as or different from the doping concentration of the rest of the drift region 107 to adjust the threshold voltage.

[0343] As a modified example of the embodiment, well region 110 may be formed to protrude farther toward vertical portion 107 a of drift region 107 than a portion of source region 112 , and channel region 107 b may be formed in semiconductor layer 105 on the protruding portion of well region 110 .

[0344] In addition, the well region 110 may further include a tap portion extending at an end of the protruding portion toward the gate electrode layer 120. The channel region 107b may be formed on the protruding portion and the tap portion of the well region 110 in a bent shape.

[0345] In addition, vertical portion 107a of drift region 107 may further extend between a lower portion of source region 112 and well region 110. In this case, channel region 107b may be formed to further extend between a lower portion of source region 112 and well region 110.

[0346] The above structure may allow the channel region 107 b to be more confined between the gate electrode layer 120 and the well region 110 .

[0347] The power semiconductor device 100b-3 may include Figures 24 to 28 The advantages of the power semiconductor devices 100 - 3 and 100 a - 3 in FIG. 1 and FIG. 2 can be achieved by lowering the threshold voltage.

[0348] Figure 31 is a schematic perspective view illustrating a power semiconductor device 100 c - 3 according to another embodiment of the present disclosure. Figure 32 is shown along Figure 31 A plan view of the power semiconductor device 100 c - 3 taken along line IX-IX. Figure 33 is shown along Figure 32 1 is a cross-sectional view of the power semiconductor device 100 c - 3 taken along line XX.

[0349] The power semiconductor device 100 c - 3 according to the embodiment may be modified by using or partially Figures 24 to 27 Therefore, additional description will be omitted to avoid redundancy.

[0350] Reference Figures 31 to 33 In the power semiconductor device 100 c - 3 , the source region 112 may include a source contact region 112 a outside at least one end of the gate electrode layer 120 . For example, the source contact region 112 a as a portion of the source region 112 may refer to a portion connected to the source electrode layer 140 .

[0351] Well contact region 114 may be formed in source contact region 112a. For example, well contact region 114 may extend from well region 110 to penetrate source region 112 and may have the second conductivity type. One well contact region 114 or multiple well contact regions 114 may be formed in source contact region 112a.

[0352] For example, the well contact region 114 may be doped with second conductive type impurities at a higher concentration than that of the well region 110 to reduce contact resistance when connected to the source electrode layer 140 .

[0353] The source electrode layer 140 may be commonly connected to the source contact region 112 a and the well contact region 114 .

[0354] Source contact region 112 a and well contact region 114 may be formed in source region 112 on one side of vertical portion 107 a of drift region 107. In a modified example of the embodiment, when each of source region 112 and well region 110 is divided into a plurality of regions, each of source contact region 112 a and well contact region 114 may be formed in each corresponding region.

[0355] In some embodiments, the plurality of trenches 116 may be arranged to be linearly spaced apart from one another along one direction. Thus, the gate electrode layer 120 may also be arranged to be linearly spaced apart from one another along the trenches 116 in the one direction. In this case, the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from one another along the one direction.

[0356] For example, the power semiconductor device 100c-3 may be formed by arranging a plurality of Figures 24 to 27 The structure of the power semiconductor device 100 - 3 is formed by arranging a well region 110 , a source region 112 , a source contact region 112 a , and a well contact region 114 therebetween.

[0357] For example, when the power semiconductor device 100 - 3 is an N-type MOSFET, the source contact region 112 a may be an N+ region, and the well contact region 114 may be a P+ region.

[0358] According to the power semiconductor device 100c-3, the source contact region 112a and the well contact region 114 can be disposed outside the gate electrode layer 120 rather than between the gate electrode layers 120, thereby enabling the gate electrode layers 120 to be arranged more densely. In this way, the channel density of the power semiconductor device 100a-3 can be significantly increased.

[0359] Meanwhile, the structure of the power semiconductor device 100c-3 can be applied to Figure 28 and Figure 29 The power semiconductor device 100a-3 and Figure 30 That is, the power semiconductor device 100a-3 or the power semiconductor device 100b-3 may be arranged in a line in plurality, and the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 may be provided therebetween.

[0360] Figure 34is a cross-sectional view showing a power semiconductor device 100d-3 according to another embodiment of the present disclosure. Figures 31 to 33 The power semiconductor device 100d-3 is realized by partially configuring the power semiconductor device 100c-3 in FIG. Therefore, additional description will be omitted to avoid redundancy.

[0361] Reference Figure 34 , power semiconductor device 100d-3 may include at least one recess 138 in source contact region 112a of source region 112, the recess 138 being formed to penetrate source region 112 and recessed into well region 110. Well contact region 114a may be formed on at least a bottom surface of recess 138 to contact well region 110.

[0362] Source electrode layer 140a may be formed to fill groove 138 and may be connected to well contact region 114a, well region 110, and / or source region 112. The above structure may widen the contact area between source electrode layer 140a and well region 110 and the contact area between source electrode layer 140a and source region 112, thereby reducing contact resistance therebetween.

[0363] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Therefore, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above-described structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0364] Meanwhile, the field reduction region 111 may be disposed to be in contact with the gate insulating layer 118 , but may be modified to be spaced apart downward from the gate insulating layer 118 .

[0365] Figures 35 to 37 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 3 according to an embodiment of the present disclosure.

[0366] Reference Figure 35 A drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented using a substrate of the first conductivity type, and the drift region 107 can be formed using one or more epitaxial layers on the substrate.

[0367] Next, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities having the second conductivity type into the semiconductor layer 105. The well region 110 may be formed substantially from the surface of the semiconductor layer 105 to a given depth.

[0368] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107 a, at least a portion of which is surrounded by the well region 110. In more detail, the well region 110 may be formed by doping the drift region 107 with impurities of a conductivity type opposite to that of the drift region 107.

[0369] Before or after forming the well region 110, a field reduction region 111 having the second conductivity type may be formed at a given depth in the semiconductor layer 105 so as to be spaced apart from the well region 110. For example, the field reduction region 111 may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0370] Then, a source region 112 having the first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities of the first conductivity type into the well region 110. The source region 112 may be formed in the well region 110 substantially from the surface of the semiconductor layer 105 to a given depth.

[0371] In addition to the formation of the source region 112, a channel region 110a having an inversion channel formed in one direction may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. The channel region 110a may be formed between the source region 112 and a vertical portion 107a of the drift region 107. For example, the channel region 110a may be a portion of the well region 110 and may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0372] In a modified example of the embodiment, the order in which the well region 110 , the source region 112 , the channel region 110 a , and the field reducing region 111 are doped with impurities may be arbitrarily changed.

[0373] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selective region.

[0374] Alternatively, a heat treatment process for activating or diffusing impurities may be performed after the ion implantation.

[0375] Reference Figure 36, at least one trench 116 may be formed to be recessed into the semiconductor layer 105 to a given depth from the surface of the semiconductor layer 105 .

[0376] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110 .

[0377] In addition, the at least one trench 116 may include a plurality of trenches 116 , and for example, the trenches 116 may be simultaneously formed in parallel in one direction in the semiconductor layer 105 . The channel region 110 a may be further limited by the trenches 116 .

[0378] For example, the trench 116 can be formed by forming a photomask by using photolithography and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0379] Reference Figure 37 A gate insulating layer 118 may be formed on the bottom and inner wall of the trench 116. For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0380] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0381] The patterning process may be performed by using a photolithography process and an etching process. The photolithography process may include a process of forming a photoresist pattern as a mask layer by using a photo process and a development process, and the etching process may include a process of selectively etching a lower structure by using the photoresist pattern.

[0382] In this way, the well region 110 can be arranged deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120. Furthermore, the field reduction region 111 can be provided in contact with the gate insulating layer 118 below the bottom surface of the gate electrode layer 120.

[0383] Next, an interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

[0384] Next, the source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may be formed by forming a conductive layer (eg, a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0385] at the same time, Figure 30 The power semiconductor device 100b-3 in the embodiment can be manufactured by adding some processes to the above-described method for manufacturing the power semiconductor device 100-3 or by changing or modifying the method. For example, the channel region 107b can be formed with a portion of the drift region 107 to form an accumulation channel.

[0386] Figures 31 to 33 The power semiconductor device 100 c - 3 may be manufactured by adding some processes to the above-mentioned method for manufacturing the power semiconductor device 100 - 3 or by changing or modifying the manufacturing method.

[0387] For example, when manufacturing power semiconductor device 100c-3, forming source region 112 may include forming source contact region 112a connected to source electrode layer 140 outside at least one end of gate electrode layer 120. In some embodiments, source contact region 112a may be a portion of source region 112.

[0388] In addition, well contact region 114 may be formed in source contact region 112a before forming trench 116. For example, well contact region 114 may be formed by implanting a second conductivity type impurity having a higher concentration than well region 110 into a portion of well region 110.

[0389] When manufacturing the power semiconductor device 100 c - 3 , the trenches 116 may be arranged to be linearly spaced apart from each other in one direction. In addition, the well region 110 , the channel region 110 a , and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116 .

[0390] refer to Figure 34 The described method for manufacturing the power semiconductor device 100d-3 may further include: forming at least one groove 138 in the source region 112 to penetrate the source region 112 and be recessed into the well region 110; forming a well contact region 114 on the bottom surface of the groove 138 so as to contact the well region 110, and forming a source electrode layer 140 to be connected to the well region 114.

[0391] According to the above-described manufacturing method, the power semiconductor device 100 - 3 using the semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0392] Figure 38 is a schematic perspective view illustrating a power semiconductor device 100 - 4 according to an embodiment of the present disclosure. Figure 39 It is shown along Figure 38 1 is a plan view of the power semiconductor device 100 - 4 taken along line II-II. Figure 38 . Figure 40 It is shown along Figure 39 1 is a cross-sectional view of the power semiconductor device 100 - 4 taken along line III-III. Figure 41 is shown along Figure 39 1 is a cross-sectional view of the power semiconductor device 100 - 4 taken along line IV-IV.

[0393] Reference Figures 38 to 41 The power semiconductor device 100 - 4 may include at least a semiconductor layer 105 , a gate insulating layer 118 , and a gate electrode layer 120 . For example, the power semiconductor device 100 - 4 may have a power MOSFET structure.

[0394] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers, for example, one epitaxial layer or multiple epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0395] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). In more detail, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0396] Silicon carbide (SiC) can have a wider band gap than silicon and therefore maintains greater stability than silicon even at high temperatures. Furthermore, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-4 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0397] In more detail, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping an epitaxial layer of silicon carbide with impurities of the first conductivity type.

[0398] Well region 110 may be formed in semiconductor layer 105 to contact drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping drift region 107 with impurities of a second conductivity type opposite to the first conductivity type.

[0399] For example, the well region 110 may be formed to surround at least a portion of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In operation of the power semiconductor device 100-4, the vertical portion 107a may provide a vertical movement path for charges.

[0400] exist Figure 38 The well region 110 shown in FIG. 1 includes two regions spaced apart from each other and a vertical portion 107 a interposed between the two regions, but various changes or modifications may be made to the well region 110. For example, the vertical portion 107 a may have a shape whose side surfaces are surrounded by the well region 110.

[0401] The source region 112 may be formed in the well region 110 and may have the first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the first conductivity type impurities doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0402] The channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have the second conductivity type, and an inversion channel may be formed in the channel region 110a along one direction in operation of the power semiconductor device 100-4.

[0403] Because the channel region 110 a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110 a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110 a may not allow charge movement under normal circumstances; however, when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, thereby allowing charge movement.

[0404] In some embodiments, the channel region 110a may be a portion of the well region 110. In this case, the channel region 110a may be integrally formed to be continuously connected to the well region 110. The doping concentration of the second conductivity type impurities of the channel region 110a may be the same as or different from the doping concentration of the rest of the well region 110 for threshold voltage adjustment.

[0405] In some embodiments, the well region 110, the channel region 110a, and the source region 112 may be formed symmetrically with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 may be formed at opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the channel region 110a, and the source region 112 may include a first portion and a second portion formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the channel region 110a, and the source region 112, the first portion and the second portion may be separated from each other or may be connected to each other.

[0406] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration of impurities than the drift region 107 .

[0407] In some embodiments, the drain region 102 may be implemented with a substrate having a first conductivity type of silicon carbide. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105.

[0408] At least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 to a given depth in the semiconductor layer 105. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to a length direction of the trench 116, rather than a depth direction of the trench 116, and may refer to a depth of the trench 116. Figure 39 The direction of line III-III or line IV-IV.

[0409] The gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or a portion of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a portion of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0410] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stack structure thereof.

[0411] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0412] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, a vertical portion 107a of the drift region 107 may extend vertically in the semiconductor layer 105 on one side of the gate electrode layer 120. A channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0413] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107 a extending vertically in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. The channel region 110 a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107 a of the drift region 107 and the source region 112.

[0414] The above-described structure of the channel region 110 a may be referred to as a “lateral channel structure” because the channel region 110 a is formed along the sidewall of the gate electrode layer 120 .

[0415] The well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. In addition, the well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite end portions of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0416] The well (110) structure can further reduce the electric field concentration on the bottom surface of the trench 116 (i.e., the lower portion of the gate electrode layer 120). In addition, a deep well region 111 can be provided below the well region 110, thereby further reducing the electric field covering the gate insulating layer 118 and the electric field at the bottom surface of the trench 116. In this way, the margin of the electric field of the gate insulating layer 118 covering the power semiconductor device 100-4 can be increased, thereby improving the reliability of the operation of the power semiconductor device 100-4. In addition, the junction resistance of the vertical portion 107a of the drift region 107 can be reduced by reducing the electric field at the bottom surface of the trench 116 and reducing the electric field covering the gate insulating layer 118.

[0417] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116 , and moreover, may be formed to further extend to the outside of the trench 116 .

[0418] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0419] For example, a plurality of trenches 116 may be formed in parallel along one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0420] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trench 116. In this way, the trench-type gate electrode layer 120 may be formed in the semiconductor layer 105 and arranged to extend parallel to the trench 116 in the same direction.

[0421] In addition, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107 a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. A channel region 110 a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107 a of the drift region 107 on one side or opposite sides of each gate electrode layer 120.

[0422] In some embodiments, the well region 110 may be formed deeper in the semiconductor layer 105 than the gate electrode layer 120 to contact the vertical portion 107 a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at opposite ends thereof.

[0423] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as oxide or nitride, or may include a stack structure thereof.

[0424] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, or the like.

[0425] In addition, the source electrode layer 140 may be in contact with a portion of the drift region 107 to form a Schottky barrier diode (SBD). The Schottky barrier diode (SBD) may refer to a diode using a Schottky barrier through a junction of a semiconductor and a metal.

[0426] In addition to the Schottky barrier diode (SBD), a parasitic body diode may be formed in the power semiconductor device 100 - 4 . For example, the body diode may be formed between the well region 110 and the drift region 107 . The body diode may be a PN diode formed when different types of semiconductor materials are combined together.

[0427] from Figure 48 It can be understood that, compared with a PN diode, a Schottky barrier diode SBD has a low forward voltage VF and fast switching characteristics.

[0428] In the operation of the power semiconductor device 100 - 4 , the Schottky barrier diode (SBD) can reduce switching losses together with the body diode. For example, the Schottky barrier diode SBD and the body diode can serve as a freewheeling diode in the operation of the power semiconductor device 100 - 4 .

[0429] In some embodiments, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a may refer to a region of the semiconductor layer 105 connected to the source electrode layer 140.

[0430] For example, the source contact region 112 a may include a portion of the source region 112 outside at least one end of the gate electrode layer 120 , a portion of the well region 110 , and a protruding portion 107 c of the drift region 107 exposed from the well region 110 .

[0431] Well contact region 114 may be formed on a portion of well region 110 in source contact region 112 a and may have the second conductivity type. For example, one well contact region 114 or multiple well contact regions 114 may be formed in source contact region 112 a. In addition, well contact region 114 may be doped with second conductivity type impurities at a higher concentration than well region 110 to reduce contact resistance when connected to source electrode layer 140.

[0432] The source electrode layer 140 may be connected to the source contact region 112 a , and thus may be commonly connected to the source region 112 , the well contact region 114 , and the protruding portion 107 c of the drift region 107 .

[0433] In some embodiments, the plurality of trenches 116 may be arranged to be linearly spaced apart from one another along one direction. Thus, the gate electrode layer 120 may also be arranged to be linearly spaced apart from one another along the trenches 116 in the one direction. In this case, the well region 110, the source region 112, the source contact region 112a, the Schottky barrier diode SBD, and the well contact region 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from one another along the one direction.

[0434] In the power semiconductor device 100-4 described above, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of an n-type and a p-type. For example, when the first conductivity type is an n-type, the second conductivity type is a p-type, and vice versa.

[0435] In more detail, when the power semiconductor device 100 - 4 is an N-type MOSFET, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+ regions, the well region 110 and the channel region 110 a may be P-regions, and the well contact region 114 may be a P+ region.

[0436] In operation of the power semiconductor device 100 - 4 , current may generally flow from the drain region 102 in a vertical direction along the vertical portion 107 a of the drift region 107 , and then may flow through the channel region 110 a along the side surface of the gate electrode layer 120 to the source region 112 .

[0437] In the power semiconductor device 100-4 described above, the gate electrode layers 120 in the trenches 116 may be densely arranged in parallel in a stripe or line type, and the channel regions 110a may be provided on side surfaces of the gate electrode layers 120. Therefore, the channel density may be increased.

[0438] According to the power semiconductor device 100 - 4 , the source contact region 112 a and the well contact region 114 can be arranged outside the gate electrode layer 120 rather than between the gate electrode layers 120 , thereby allowing the gate electrode layers 120 to be arranged more densely. In this way, the channel density of the power semiconductor device 100 - 4 can be significantly increased.

[0439] Figure 42 and Figure 43 is a cross-sectional view showing a power semiconductor device 100a-4 according to another embodiment of the present disclosure. The power semiconductor device 100a-4 according to the embodiment can be modified by Figures 38 to 41 Therefore, additional description will be omitted to avoid repetition.

[0440] Reference Figure 42 and Figure 43 The power semiconductor device 100a-4 may include at least one recess 138 formed by etching a portion of the drift region 107 (eg, the protruding portion 107c), a portion of the source region 112, and a portion of the well region 110. For example, the recess 138 may be formed by etching Figures 38 to 41 The recess 138 is formed in the source contact region 112 a of the power semiconductor device 100 - 4 .

[0441] Well contact region 114a may be formed on a portion of well region 110 exposed from groove 138. For example, well contact region 114a may be formed on a portion of the bottom surface of well region 110 corresponding to groove 138. Well contact region 114a may have the second conductivity type and may be more heavily doped than well contact region 114.

[0442] A source electrode layer 140a may be formed to fill the groove 138 and may collectively contact the well contact region 114a, the protruding portion 107c of the drift region 107, and the source region 112 within the groove 138. The contact between the protruding portion 107c of the drift region 107 and the source electrode layer 140 may form a Schottky barrier diode SBD.

[0443] The above structure can widen the contact area between the source electrode layer 140 a and the source region 112 and the well contact region 114 a , thereby reducing the contact resistance therebetween.

[0444] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Therefore, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above-described structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0445] Figure 44 is a schematic cross-sectional view showing a power semiconductor device 100b-4 according to another embodiment of the present disclosure. The power semiconductor device 100b-4 according to the embodiment can be modified by Figures 38 to 41 Therefore, additional description will be omitted to avoid repetition.

[0446] Reference Figure 44 ,replace Figures 38 to 41 In the power semiconductor device 100 - 4 , the power semiconductor device 100 b - 4 may include a channel region 107 b forming an accumulation channel.

[0447] In power semiconductor device 100b-4, channel region 107b may be formed in semiconductor layer 105 between drift region 107 and source region 112. For example, channel region 107b may have a first conductivity type, and an accumulation channel may be formed in channel region 107b during operation of power semiconductor device 100b-4.

[0448] For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b may have the same doping type as the source region 112 and the drift region 107.

[0449] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the silicon carbide semiconductor layer 105, due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118, the energy band of the channel region 107b is bent upward, forming a potential barrier. In this way, an accumulation channel can be formed that allows charge or current to flow in the channel region 107b only when an operating voltage is applied to the gate electrode layer 120.

[0450] Therefore, the threshold voltage applied to the gate electrode layer 120 for forming an accumulation channel in the channel region 107b can be significantly lower than that for forming an accumulation channel. Figures 38 to 41 The inversion channel of the channel region 110a in the gate electrode layer 120 is applied to the threshold voltage.

[0451] In some embodiments, the channel region 107 b may be part of the drift region 107. More specifically, the channel region 107 b may be part of the vertical portion 107 a of the drift region 107. For example, the channel region 107 b may be integrally formed with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 via the channel region 107 b. That is, the drift region 107 and the source region 112 may be in contact with each other at the channel region 107 b portion.

[0452] The doping concentration of the first conductive type impurities of the channel region 107 b may be the same as or different from the doping concentration of the rest of the drift region 107 to adjust a threshold voltage.

[0453] As a modified example of the embodiment, well region 110 may be formed to protrude farther toward vertical portion 107 a of drift region 107 than a portion of source region 112 , and channel region 107 b may be formed in semiconductor layer 105 on the protruding portion of well region 110 .

[0454] In addition, the well region 110 may further include a tap portion extending at an end of the protruding portion toward the gate electrode layer 120. The channel region 107b may be formed on the protruding portion and the tap portion of the well region 110 in a bent shape.

[0455] Furthermore, vertical portion 107a of drift region 107 may further extend between a lower portion of source region 112 and well region 110. In this case, channel region 107b may be formed to further extend between a lower portion of source region 112 and well region 110.

[0456] The above structure may allow the channel region 107 b to be more confined between the gate electrode layer 120 and the well region 110 .

[0457] The power semiconductor device 100 b - 4 may include Figures 38 to 41 Advantages of the power semiconductor device 100 - 4 include that the threshold voltage can be made lower.

[0458] Figures 45 to 47 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 4 according to an embodiment of the present disclosure.

[0459] Reference Figure 45 A drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented using a substrate of the first conductivity type, and the drift region 107 can be formed using one or more epitaxial layers on the substrate.

[0460] Next, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities of the second conductivity type on the semiconductor layer 105.

[0461] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107 a, at least a portion of which is surrounded by the well region 110. In more detail, the well region 110 may be formed by doping the drift region 107 with impurities of a conductivity type opposite to that of the drift region 107.

[0462] Then, a source region 112 having the first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities of the first conductivity type into the well region 110.

[0463] In addition to forming the source region 112, a channel region 110 a having an inversion channel formed in one direction may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. The channel region 110 a may be formed between the source region 112 and a vertical portion 107 a of the drift region 107. For example, the channel region 110 a is a portion of the well region 110 and may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0464] In addition, when the source region 112 is formed, a source contact region 112 a including a portion of the source region 112 , a portion of the well region 110 , and a protruding portion 107 c of the drift region 107 exposed from the well region 110 may be formed at least outside one end of the gate electrode layer 120 .

[0465] In addition, a well contact region 114 having the second conductivity type and being doped higher than well region 110 may be formed on a portion of well region 110. For example, well contact region 114 may be formed by implanting second conductivity type impurities having a higher concentration than well region 110 into a portion of well region 110.

[0466] In the above steps, impurity implantation or impurity doping may be performed so that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selective region.

[0467] Alternatively, a heat treatment process for activating or diffusing impurities may be performed after the ion implantation.

[0468] Reference Figure 46 , at least one trench 116 may be formed to be recessed into the semiconductor layer 105 to a given depth from the surface of the semiconductor layer 105 .

[0469] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110 .

[0470] In addition, the at least one trench 116 may include a plurality of trenches 116 , and for example, the trenches 116 may be simultaneously formed in parallel in one direction in the semiconductor layer 105 . The channel region 110 a may be further limited by the trenches 116 .

[0471] For example, the trench 116 can be formed by forming a photomask using photolithography and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0472] In some embodiments, the trenches 116 may be arranged to be linearly spaced apart from each other along one direction. In addition, the well region 110 , the channel region 110 a , and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116 .

[0473] Reference Figure 47 , a gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0474] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0475] The patterning process may be performed by using a photolithography process and an etching process. The photolithography process may include a process of forming a photoresist pattern as a mask layer by using a photo process and a developing process, and the etching process may include a process of selectively etching a lower structure by using the photoresist pattern.

[0476] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0477] Next, an interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

[0478] Next, the source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may be formed by forming a conductive layer (eg, a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0479] For example, source electrode layer 140 may be connected to source region 112 and may be in contact with a portion of drift region 107, thereby forming a Schottky barrier diode (SBD). In some embodiments, source electrode layer 140 may be connected to source contact region 112 a, thereby being in contact with source region 112, well contact region 114, and protruding portion 107 c of drift region 107.

[0480] Figure 42 and Figure 43 The power semiconductor device 100a-4 can be manufactured by adding some processes to the above-mentioned method for manufacturing the power semiconductor device 100-4 or by changing or modifying the manufacturing method. For example, the method for manufacturing the power semiconductor device 100a-4 may further include: forming at least one recess 138 by etching a portion of the drift region 107 (e.g., the protruding portion 107a of the drift region 107), a portion of the source region 112, and a portion of the well region 110; forming a well contact region 114 on a portion of the well region 110 corresponding to the bottom surface of the recess 138; and forming a source electrode layer 140 connected to the source region 112, the protruding portion 107c of the drift region 107, and the well contact region 114 by filling the recess 138.

[0481] at the same time, Figure 44 The power semiconductor device 100 b - 4 can be manufactured by adding some processes to the above-described method for manufacturing the power semiconductor device 100 - 4 or by changing or modifying the method. For example, the channel region 107 b can be formed with a portion of the drift region 107 to form an accumulation channel.

[0482] According to the above-described manufacturing method, the power semiconductor device 100 - 4 using the semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0483] Figure 49 is a schematic perspective view illustrating a power semiconductor device 100 - 5 according to an embodiment of the present disclosure. Figure 50 is shown along Figure 49 1 is a plan view of the power semiconductor device 100 - 5 taken along line II-II. Figure 51 is shown along Figure 50 1 is a cross-sectional view of the power semiconductor device 100 - 5 taken along line III-III.

[0484] Reference Figures 49 to 51 The power semiconductor device 100-5 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-5 may have a power MOSFET structure.

[0485] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers, for example, one epitaxial layer or multiple epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0486] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). In more detail, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0487] Silicon carbide (SiC) can have a wider band gap than silicon, and therefore maintains greater stability than silicon even at high temperatures. Furthermore, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-5 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0488] In more detail, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping an epitaxial layer of silicon carbide with impurities of the first conductivity type.

[0489] Well region 110 may be formed in semiconductor layer 105 to contact drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping drift region 107 with impurities of a second conductivity type opposite to the first conductivity type.

[0490] For example, the well region 110 may be formed to surround at least a portion of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In operation of the power semiconductor device 100-5, the vertical portion 107a may provide a vertical movement path for charges.

[0491] The well region 110 is Figure 49 107 a is shown as including two regions spaced apart from each other and a vertical portion 107 a interposed between the two regions, but various changes or modifications may be made to the well region 110. For example, the vertical portion 107 a may have a shape whose side is surrounded by the well region 110.

[0492] Deep well region 111 may be formed below well region 110 to contact well region 110 and drift region 107. Like well region 110, deep well region 111 may have a second conductivity type. A doping concentration of an impurity of the second conductivity type in deep well region 111 may be equal to or lower than a doping concentration of an impurity of the second conductivity type in well region 110.

[0493] For example, the deep well region 111 may be formed to have a width narrower than that of the well region 110 based on one direction. One direction may refer to Figure 50 In addition, opposite ends of the deep well region 111 may be arranged to be offset inward from opposite ends of the well region 110 based on one direction.

[0494] Thus, below the well region 110 , the deep well region 111 may be provided to recede inward from opposite ends of the well region 110 while in contact with the well region 110 . The lower surface and side surfaces of the deep well region 111 may be in contact with the drift region 107 .

[0495] For example, when the deep well region 111 is formed in two regions spaced apart from each other like the well region 110 , the spacing distance between the two deep well regions 111 may be greater than the spacing distance between the two well regions 110 .

[0496] The source region 112 may be formed in the well region 110 and may have the first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the first conductivity type impurities doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0497] The channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have the second conductivity type, and an inversion channel may be formed in the channel region 110a along one direction in operation of the power semiconductor device 100-5.

[0498] Because the channel region 110 a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110 a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110 a may not allow charge movement under normal circumstances; however, when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, thereby allowing charge movement.

[0499] In some embodiments, the channel region 110a may be a portion of the well region 110. In this case, the channel region 110a may be entirely formed to be continuously connected to the well region 110. The doping concentration of the second conductivity type impurities of the channel region 110a may be the same as or different from the doping concentration of the impurities of the rest of the well region 110 to adjust the threshold voltage.

[0500] In some embodiments, the well region 110, the deep well region 111, the channel region 110a, and the source region 112 may be formed symmetrically with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the deep well region 111, the channel region 110a, and the source region 112 may be formed on opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the deep well region 111, the channel region 110a, and the source region 112 may include a first portion and a second portion formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the deep well region 111, the channel region 110a, and the source region 112, the first portion and the second portion may be separated from each other or may be connected to each other.

[0501] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration of impurities than the drift region 107 .

[0502] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105.

[0503] At least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 to a given depth within the semiconductor layer 105. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to a length direction of the trench 116, rather than a depth direction of the trench 116, and may refer to a depth of the trench 116. Figure 50 The direction of the line III-III.

[0504] The gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench. The thickness of the gate insulating layer 118 may be uniform, or a portion of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a portion of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0505] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stack structure thereof.

[0506] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0507] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, a vertical portion 107a of the drift region 107 may extend vertically in the semiconductor layer 105 on one side of the gate electrode layer 120. A channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120, between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction may be included in the semiconductor layer 105 on one side of the gate electrode layer 120.

[0508] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107 a extending vertically in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. The channel region 110 a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107 a of the drift region 107 and the source region 112.

[0509] The above-described structure of the channel region 110 a may be referred to as a “lateral channel structure” because the channel region 110 a is formed along the sidewall of the gate electrode layer 120 .

[0510] The well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. In addition, the well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0511] The well (110) structure can further reduce the electric field concentration on the bottom surface of the trench 116 (i.e., the lower portion of the gate electrode layer 120). In addition, a deep well region 111 can be provided below the well region 110, thereby further reducing the electric field covering the gate insulating layer 118 and the electric field at the bottom surface of the trench 116. In this way, the margin of the electric field of the gate insulating layer 118 covering the power semiconductor device 100-5 can be increased, thereby improving the reliability of the operation of the power semiconductor device 100-5. In addition, the junction resistance of the vertical portion 107a of the drift region 107 can be reduced by reducing the electric field at the bottom surface of the trench 116 and reducing the electric field covering the gate insulating layer 118.

[0512] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116 , and moreover, may be formed to further extend to the outside of the trench 116 .

[0513] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0514] For example, a plurality of trenches 116 may be formed in parallel along one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0515] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trench 116. In this way, the trench-type gate electrode layer 120 may be formed in the semiconductor layer 105 and arranged to extend parallel to the trench 116 in the same direction.

[0516] In addition, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107 a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. A channel region 110 a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107 a of the drift region 107 on one side or opposite sides of each gate electrode layer 120.

[0517] In some embodiments, the well region 110 may be formed deeper in the semiconductor layer 105 than the gate electrode layer 120 to contact the vertical portion 107 a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at opposite ends thereof.

[0518] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as oxide or nitride, or may include a stack structure thereof.

[0519] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, or the like.

[0520] In the power semiconductor device 100-5 described above, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of an n-type and a p-type. For example, when the first conductivity type is an n-type, the second conductivity type is a p-type, and vice versa.

[0521] In more detail, when the power semiconductor device 100 - 5 is an N-type MOSFET, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+ regions, and the well region 110 , the deep well region 111 and the channel region 110 a may be P-regions.

[0522] In operation of the power semiconductor device 100 - 5 , current may generally flow from the drain region 102 in a vertical direction along the vertical portion 107 a of the drift region 107 , and then may flow through the channel region 110 a along the side surface of the gate electrode layer 120 to the source region 112 .

[0523] In the power semiconductor device 100-5 described above, the gate electrode layers 120 in the trenches 116 may be densely arranged in parallel in a stripe or line type, and the channel regions 110a may be provided on side surfaces of the gate electrode layers 120. Therefore, the channel density may be increased.

[0524] Figure 52 is a perspective view illustrating a power semiconductor device 100 a - 5 according to another embodiment of the present disclosure.

[0525] The power semiconductor device 100 a - 5 according to the embodiment may be modified by using or partially Figures 49 to 51 Therefore, additional description will be omitted to avoid redundancy.

[0526] Reference Figure 52In the power semiconductor device 100a-5, a channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may have a first conductivity type, and an accumulation channel may be formed in the channel region 107b during operation of the power semiconductor device 100a-5.

[0527] For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b may have the same doping type as the source region 112 and the drift region 107.

[0528] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the silicon carbide semiconductor layer 105, due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118, the energy band of the channel region 107b is bent upward, forming a potential barrier. In this way, an accumulation channel can be formed that allows charge or current to flow in the channel region 107b only when an operating voltage is applied to the gate electrode layer 120.

[0529] Therefore, the threshold voltage applied to the gate electrode layer 120 for forming an accumulation channel in the channel region 107b can be significantly lower than that for forming an accumulation channel. Figures 49 to 51 The inversion channel of the channel region 110a in the gate electrode layer 120 is applied to the threshold voltage.

[0530] In some embodiments, the channel region 107b may be a portion of the drift region 107. More specifically, the channel region 107b may be a portion of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 through the channel region 107b. That is, the drift region 107 and the source region 112 may be in contact with each other at the channel region (107b).

[0531] The doping concentration of the first conductive type impurities of the channel region 107 b may be the same as or may be different from the doping concentration of the rest of the drift region 107 to adjust a threshold voltage.

[0532] As a modified example of the embodiment, well region 110 may be formed to protrude toward vertical portion 107 a of drift region 107 farther than a portion of source region 112 , and channel region 107 b may be formed in semiconductor layer 105 on the protruding portion of well region 110 .

[0533] In addition, the well region 110 may further include a tap portion extending at an end of the protruding portion toward the gate electrode layer 120. The channel region 107b may be formed on the protruding portion and the tap portion of the well region 110 in a bent shape.

[0534] In addition, vertical portion 107a of drift region 107 may further extend between a lower portion of source region 112 and well region 110. In this case, channel region 107b may be formed to further extend between a lower portion of source region 112 and well region 110.

[0535] The above structure may allow the channel region 107 b to be more confined between the gate electrode layer 120 and the well region 110 .

[0536] The power semiconductor device 100a-5 may include Figures 49 to 51 The power semiconductor device 100 - 5 has the advantage that, furthermore, the threshold voltage can be made low.

[0537] Figure 53 is a schematic perspective view illustrating a power semiconductor device 100 b - 5 according to another embodiment of the present disclosure. Figure 54 It is shown along Figure 53 VI-VI is a plan view of the power semiconductor device 100 b - 5 . Figure 55 It shows that along Figure 54 VII-VII is a cross-sectional view of the power semiconductor device 100 b - 5 . Figure 56 It is shown along Figure 54 1 is a cross-sectional view of the power semiconductor device 100 b - 5 taken along line VIII-VIII.

[0538] The power semiconductor device 100 b - 5 according to the embodiment may be modified by using or partially Figures 49 to 51 Therefore, additional description will be omitted to avoid redundancy.

[0539] Reference Figures 53 to 56 In the power semiconductor device 100 b - 5 , the source region 112 may include a source contact region 112 a outside at least one end of the gate electrode layer 120 . For example, the source contact region 112 a as a portion of the source region 112 may refer to a portion connected to the source electrode layer 140 .

[0540] Well contact region 114 may be formed in source contact region 112a. For example, well contact region 114 may extend from well region 110 to penetrate source region 112 and may have the second conductivity type. One well contact region 114 or multiple well contact regions 114 may be formed in source contact region 112a.

[0541] For example, the well contact region 114 may be doped with impurities of the second conductivity type at a higher concentration than that of the well region 110 to reduce contact resistance when connected to the source electrode layer 140 .

[0542] The source electrode layer 140 may be commonly connected to the source contact region 112 a and the well contact region 114 .

[0543] exist Figures 53 to 56 , source contact region 112 a and well contact region 114 are formed in source region 112 on one side of vertical portion 107 a of drift region 107. However, when each of source region 112 and well region 110 is divided into a plurality of regions, each of source contact region 112 a and well contact region 114 may be formed in each corresponding region.

[0544] In some embodiments, the plurality of trenches 116 may be arranged to be linearly spaced apart from one another along one direction. Thus, the gate electrode layer 120 may also be arranged to be linearly spaced apart from one another along the trenches 116 in the one direction. In this case, the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from one another along the one direction.

[0545] For example, by arranging multiple Figures 49 to 51 The power semiconductor device 100b-5 is formed by arranging the well region 110, the source region 112, the source contact region 112a and the well contact region 114 therebetween.

[0546] For example, when the power semiconductor device 100 - 5 is an N-type MOSFET, the source contact region 112 a may be an N+ region, and the well contact region 114 may be a P+ region.

[0547] According to the power semiconductor device 100 b - 5 , the source contact region 112 a and the well contact region 114 can be disposed outside the gate electrode layer 120 rather than between the gate electrode layers 120 . Therefore, the gate electrode layers 120 can be arranged more densely. In this way, the channel density of the power semiconductor device 100 b - 5 can be significantly increased.

[0548] Figure 57 and Figure 58 are cross-sectional views illustrating power semiconductor devices 100 c - 5 and 100 d - 5 according to other embodiments of the present disclosure.

[0549] Reference Figure 57 , power semiconductor device 100c-5 may include at least one recess 138 in source contact region 112a of source region 112, the recess 138 being formed to penetrate source region 112 and recessed into well region 110. Well contact region 114a may be formed on at least a bottom surface of recess 138 so as to contact well region 110.

[0550] Source electrode layer 140a may be formed to fill groove 138 and may be connected to well contact region 114a, well region 110, and / or source region 112. The above structure may widen the contact area between source electrode layer 140a and well region 110, and the contact area between source electrode layer 140a and source region 112, thereby reducing contact resistance therebetween.

[0551] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Therefore, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above-described structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0552] Reference Figure 58 ,replace Figures 53 to 56 The power semiconductor device 100b-5 may include a channel region 110a of the power semiconductor device 100d-5, and the power semiconductor device 100d-5 may include a channel region 107b forming an accumulation channel. The above structure of the power semiconductor device 100d-5 including the channel region 107b may refer to Figure 52 Description given.

[0553] Therefore, the power semiconductor device 100d-5 may correspond to the following structure: Figure 52 The power semiconductor device 100 a - 5 is connected in a plurality of ways, with a well region 110 , a source region 112 , a source contact region 112 a and a well contact region 114 disposed therebetween.

[0554] Figures 59 to 61 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 5 according to an embodiment of the present disclosure.

[0555] Reference Figure 59 A drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented using a substrate of the first conductivity type, and the drift region 107 can be formed using one or more epitaxial layers on the substrate.

[0556] Next, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0557] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In more detail, the well region 110 may be formed by doping the drift region 107 with impurities of a conductivity type opposite to that of the drift region 107.

[0558] Next, below the well region 110, a deep well region 111 having the second conductivity type may be formed to contact the well region 110 and the drift region 107. The deep well region 111 may be formed by implanting impurities of the same second conductivity type as the well region 110. The well region 110 and the deep well region 111 may be formed in any order.

[0559] Then, a source region 112 having the first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities of the first conductivity type into the well region 110.

[0560] In addition to forming the source region 112, a channel region 110 a having an inversion channel formed in one direction may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. The channel region 110 a may be formed between the source region 112 and the vertical portion 107 a of the drift region 107. For example, the channel region 110 a may be a portion of the well region 110 and may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0561] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selective region.

[0562] Alternatively, a heat treatment process for activating or diffusing impurities may be performed after the ion implantation.

[0563] Reference Figure 60 , at least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0564] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110 .

[0565] In addition, the at least one trench 116 may include a plurality of trenches 116 , and for example, the trenches 116 may be simultaneously formed in parallel in one direction in the semiconductor layer 105 . The channel region 110 a may be further limited by the trenches 116 .

[0566] For example, the trench 116 can be formed by forming a photomask using photolithography and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0567] Reference Figure 61 A gate insulating layer 118 may be formed on the bottom and inner wall of the trench 116. For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0568] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon or may be formed to include a conductive metal or metal silicide.

[0569] The patterning process may be performed using photolithography and etching processes. The photolithography process may include forming a photoresist pattern as a mask layer using a photo process and a developing process, and the etching process may include selectively etching an underlying structure using the photoresist pattern.

[0570] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0571] Next, an interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

[0572] Next, the source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may be formed by forming a conductive layer (eg, a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0573] at the same time, Figure 52 The power semiconductor device 100a-5 in the embodiment can be manufactured by adding some processes to the above-mentioned method for manufacturing the power semiconductor device 100-5 or changing or modifying the method. For example, the channel region 107b can be formed with a portion of the drift region 107 to form an accumulation channel.

[0574] Figures 53 to 56 The power semiconductor device 100 b - 5 can be manufactured by adding some processes to the above-mentioned method for manufacturing the power semiconductor device 100 - 5 or by changing or modifying the manufacturing method.

[0575] For example, when manufacturing power semiconductor device 100b-5, forming source region 112 may include forming source contact region 112a connected to source electrode layer 140 outside at least one end of gate electrode layer 120. In some embodiments, source contact region 112a may be a portion of source region 112.

[0576] In addition, well contact region 114 may be formed in source contact region 112a before forming trench 116. For example, well contact region 114 may be formed by implanting a second conductivity type impurity having a higher concentration than well region 110 into a portion of well region 110.

[0577] When manufacturing the power semiconductor device 100 b - 5 , the trenches 116 may be arranged to be linearly spaced apart from each other in one direction. In addition, the well region 110 , the channel region 110 a , and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116 .

[0578] Reference Figure 57 According to the description, the manufacturing method of the power semiconductor device 100c-5 may further include: forming at least one groove 138 in the source region 112 to penetrate the source region 112 and be recessed into the well region 110; forming a well contact region 114 on the bottom surface of the groove 138 so that the well contact region 114 contacts the well region 110, and forming a source electrode layer 140 to be connected to the well contact region 114.

[0579] According to the above-described manufacturing method, the power semiconductor device 100 - 5 using the semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0580] Figure 62 is a schematic perspective view illustrating a power semiconductor device 100 - 6 according to an embodiment of the present disclosure. Figure 63 It is shown along Figure 62 1 is a plan view of the power semiconductor device 100 - 6 taken along line II-II. Figure 64 is shown along Figure 63 1 is a cross-sectional view of the power semiconductor device 100 - 6 taken along line III-III.

[0581] Reference Figures 62 to 64 The power semiconductor device 100 - 6 may include at least a semiconductor layer 105 , a gate insulating layer 118 , and a gate electrode layer 120 . For example, the power semiconductor device 100 - 6 may have a power MOSFET structure.

[0582] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers, for example, one epitaxial layer or multiple epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0583] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). In more detail, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0584] Silicon carbide (SiC) can have a wider band gap than silicon, and therefore can maintain stability even at high temperatures compared to silicon. In addition, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-6 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0585] In more detail, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping an epitaxial layer of silicon carbide with impurities of the first conductivity type.

[0586] Well region 110 may be formed in semiconductor layer 105 to contact drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping drift region 107 with impurities of a second conductivity type opposite to the first conductivity type.

[0587] For example, the well region 110 may be formed to surround at least a portion of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In operation of the power semiconductor device 100-6, the vertical portion 107a may provide a vertical movement path for charges.

[0588] The well region 110 is Figure 62 107 a is shown as including two regions spaced apart from each other and a vertical portion 107 a interposed between the two regions, but various changes or modifications may be made to the well region 110. For example, the vertical portion 107 a may have a shape whose side is surrounded by the well region 110.

[0589] The source region 112 may be formed in the well region 110 and may have the first conductivity type. For example, the source region 112 may be formed by doping the well region 110 with impurities of the first conductivity type. The concentration of the first conductivity type impurities doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0590] The channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have the second conductivity type, and in operation of the power semiconductor device 100-6, an inversion channel may be formed in the channel region 110a along one direction. One direction may refer to Figure 63 The direction of the line III-III.

[0591] Because the channel region 110 a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110 a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110 a may not allow charge movement under normal circumstances; however, when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, thereby allowing charge movement.

[0592] In some embodiments, the channel region 110a may be a portion of the well region 110. In this case, the channel region 110a may be formed as a whole to be continuously connected to the well region 110. The doping concentration of the second conductivity type impurities of the channel region 110a may be the same as or different from the doping concentration of the rest of the well region 110 for threshold voltage adjustment.

[0593] In some embodiments, the well region 110, the channel region 110a, and the source region 112 may be formed symmetrically with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 may be formed at opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the channel region 110a, and the source region 112 may include a first portion and a second portion formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the channel region 110a, and the source region 112, the first portion and the second portion may be separated from each other or may be connected to each other.

[0594] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration of impurities than the drift region 107 .

[0595] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105.

[0596] At least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 to a given depth in the semiconductor layer 105. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to a length direction of the trench 116, rather than a depth direction of the trench 116, and may refer to a depth of the trench 116. Figure 63 The direction of the line III-III.

[0597] The gate insulating layer 118 may be formed on the bottom surface and inner wall of the trench 116. For example, the gate insulating layer 118 may include a first portion 118a formed with a first thickness from the bottom surface of the trench 116 and a second portion 118b formed on the inner wall of the trench 116 with a second thickness.

[0598] For example, first portion 118a may be formed to have a first thickness from the bottom surface of trench 116, thereby partially burying trench 116. Thus, second portion 118b may be formed substantially on first portion 118a and may be formed on the sidewalls of trench 116 without burying trench 116. Therefore, the second thickness of second portion 118b may be less than the first thickness of first portion 118a. For example, the first thickness may be 1 / 5 or more and 1 / 2 or less of the depth of trench 116, and the second thickness may be in the range of 1 / 5 to 1 / 30 of the first thickness.

[0599] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stack structure thereof.

[0600] As described above, by forming the first portion 118 a of the gate insulating layer 118 thicker than the second portion 118 b at the bottom of the trench 116 , electric field concentration on the bottom of the trench 116 during operation of the power semiconductor device 100 - 6 may be alleviated.

[0601] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0602] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 may extend vertically in the semiconductor layer 105 on one side of the gate electrode layer 120. The channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120, between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0603] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107 a extending vertically in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. The channel region 110 a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107 a of the drift region 107 and the source region 112.

[0604] The above-described structure of the channel region 110 a may be referred to as a “lateral channel structure” because the channel region 110 a is formed along the sidewall of the gate electrode layer 120 .

[0605] The well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. In addition, the well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite end portions of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0606] The well (110) structure can further reduce the electric field concentration on the bottom surface of the trench 116 (i.e., the lower portion of the gate electrode layer 120). Therefore, according to the power semiconductor device 100-6, the well region 110 can be formed to be deeper than the gate electrode layer 120 without the need to form a deep well, thereby reducing the electric field concentration on the bottom surface of the trench 116. The problem with the conventional vertical channel structure is that as the distance between the deep well and the trench becomes shorter, the junction resistance and the threshold voltage increase. However, in the power semiconductor device 100-6 according to the embodiment, this problem may not occur.

[0607] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116 , and moreover, may be formed to further extend outside the trench 116 .

[0608] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0609] For example, a plurality of trenches 116 may be formed in parallel along one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0610] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trench 116. In this way, the gate electrode layer 120 may be formed in a trench shape in the semiconductor layer 105 and may be arranged to extend parallel to the trench 116 in the same direction.

[0611] In addition, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107 a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. A channel region 110 a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107 a of the drift region 107 on one side or opposite sides of each gate electrode layer 120.

[0612] In some embodiments, the well region 110 may be formed deeper in the semiconductor layer 105 than the gate electrode layer 120 to contact the vertical portion 107 a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at opposite ends thereof.

[0613] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as oxide or nitride, or may include a stack structure thereof.

[0614] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, or the like.

[0615] In the power semiconductor device 100-6 described above, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of n-type and p-type. For example, when the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0616] In more detail, when the power semiconductor device 100 - 6 is an N-type MOSFET, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+ regions, and the well region 110 and the channel region 110 a may be P-regions.

[0617] In operation of the power semiconductor device 100 - 6 , current may generally flow in a vertical direction from the drain region 102 along the vertical portion 107 a of the drift region 107 , and then may flow through the channel region 110 a along the side surface of the gate electrode layer 120 to the source region 112 .

[0618] In the above-described power semiconductor device 100-6, the gate electrode layers 120 may be densely arranged in parallel in a stripe type or a line type, and the channel regions 110a may be provided on the side surfaces of the gate electrode layers 120. In this way, the channel density may be increased.

[0619] Furthermore, in power semiconductor device 100-6, because gate insulating layer 118 is formed thicker at the bottom of trench 116 and the bottom surface of gate electrode layer 120 is surrounded by well region 110, the breakdown phenomenon caused by electric field concentration at the edge of trench 116 can be reduced. Therefore, the high withstand voltage characteristics of power semiconductor device 100-6 can be improved. This may mean that the reliability of operation of power semiconductor device 100-6 is improved.

[0620] Figure 65 is a perspective view illustrating a power semiconductor device 100 a - 6 according to another embodiment of the present disclosure.

[0621] The power semiconductor device 100 a - 6 according to the embodiment may be modified by using or partially Figures 62 to 64 Therefore, additional description will be omitted to avoid redundancy.

[0622] Reference Figure 65 In the power semiconductor device 100a-6, a channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may have a first conductivity type. During operation of the power semiconductor device 100a-6, an accumulation channel may be formed in the channel region 107b.

[0623] For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b may have the same doping type as the source region 112 and the drift region 107.

[0624] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the silicon carbide semiconductor layer 105, due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118, the energy band of the channel region 107b is bent upward, forming a potential barrier. In this way, an accumulation channel can be formed that allows charge or current to flow in the channel region 107b only when an operating voltage is applied to the gate electrode layer 120.

[0625] Therefore, the threshold voltage applied to the gate electrode layer 120 for forming an accumulation channel in the channel region 107b can be significantly lower than that for forming an accumulation channel. Figures 62 to 64 The inversion channel of the channel region 110 a is formed and a threshold voltage is applied to the gate electrode layer 120 .

[0626] In some embodiments, the channel region 107b may be a portion of the drift region 107. More specifically, the channel region 107b may be a portion of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 through the channel region 107b. That is, the drift region 107 and the source region 112 may be in contact with each other at the channel region (107b).

[0627] The doping concentration of the first conductivity type impurities of the channel region 107 b may be the same as or different from the doping concentration of the rest of the drift region 107 for threshold voltage adjustment.

[0628] As a modified example of the embodiment, well region 110 may be formed to protrude farther toward vertical portion 107 a of drift region 107 than a portion of source region 112 , and channel region 107 b may be formed in semiconductor layer 105 on the protruding portion of well region 110 .

[0629] In addition, the well region 110 may further include a tap portion extending at an end of the protruding portion toward the gate electrode layer 120. The channel region 107b may be formed on the protruding portion and the tap portion of the well region 110 in a bent shape.

[0630] In addition, vertical portion 107a of drift region 107 may further extend between a lower portion of source region 112 and well region 110. In this case, channel region 107b may be formed to further extend between a lower portion of source region 112 and well region 110.

[0631] The above structure may allow the channel region 107 b to be more confined between the gate electrode layer 120 and the well region 110 .

[0632] The power semiconductor device 100a-6 may include Figures 62 to 64Advantages of the power semiconductor device 100 - 6 shown, and in addition, the threshold voltage can be made low.

[0633] Figure 66 is a schematic perspective view illustrating a power semiconductor device 100 b - 6 according to another embodiment of the present disclosure. Figure 67 is shown along Figure 66 VI-VI is a plan view of the power semiconductor device 100 b - 6 . Figure 68 is shown along Figure 67 VII-VII is a cross-sectional view of the power semiconductor device 100 b - 6 . Figure 69 is shown along Figure 67 1 is a cross-sectional view of the power semiconductor device 100 b - 6 taken along line VIII-VIII.

[0634] The power semiconductor device 100 b - 6 according to the embodiment may be modified by using or partially Figures 62 to 64 Therefore, additional description will be omitted to avoid redundancy.

[0635] Reference Figures 66 to 69 In the power semiconductor device 100 b - 6 , the source region 112 may include a source contact region 112 a outside at least one end of the gate electrode layer 120 . For example, the source contact region 112 a as a portion of the source region 112 may refer to a portion connected to the source electrode layer 140 .

[0636] Well contact region 114 may be formed in source contact region 112a. For example, well contact region 114 may extend from well region 110 to penetrate source region 112 and may have the second conductivity type. One well contact region 114 or multiple well contact regions 114 may be formed in source contact region 112a.

[0637] For example, the well contact region 114 may be doped with impurities of the second conductivity type at a higher concentration than that of the well region 110 to reduce contact resistance when connected to the source electrode layer 140 .

[0638] The source electrode layer 140 may be commonly connected to the source contact region 112 a and the well contact region 114 .

[0639] exist Figures 66 to 69 , an example is shown in which a source contact region 112 a and a well contact region 114 are formed in the source region 112 on one side of the vertical portion 107 a of the drift region 107. However, when each of the source region 112 and the well region 110 is divided into a plurality of regions, each of the source contact region 112 a and the well contact region 114 may be formed in each corresponding region.

[0640] In some embodiments, the plurality of trenches 116 may be arranged to be linearly spaced apart from one another along one direction. Thus, the gate electrode layer 120 may also be arranged to be linearly spaced apart from one another along the trenches 116 in the one direction. In this case, the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from one another along the one direction.

[0641] For example, the power semiconductor device 100b-6 can be formed by arranging a plurality of Figures 62 to 64 The structure of the power semiconductor device 100 - 6 is formed by arranging a well region 110 , a source region 112 , a source contact region 112 a and a well contact region 114 therebetween.

[0642] For example, when the power semiconductor device 100 - 6 is an N-type MOSFET, the source contact region 112 a may be an N+ region, and the well contact region 114 may be a P+ region.

[0643] According to the power semiconductor device 100 b - 6 , the source contact region 112 a and the well contact region 114 can be disposed outside the gate electrode layer 120 rather than between the gate electrode layers 120 , thereby allowing the gate electrode layers 120 to be arranged more densely. In this way, the channel density of the power semiconductor device 100 b - 6 can be significantly increased.

[0644] Figure 70 and Figure 71 are cross-sectional views illustrating power semiconductor devices 100 c - 6 and 100 d - 6 according to other embodiments of the present disclosure.

[0645] Reference Figure 70 , power semiconductor device 100c-6 may include at least one recess 138 in source contact region 112a of source region 112, the recess 138 being formed to penetrate source region 112 and recessed into well region 110. Well contact region 114a may be formed on at least a bottom surface of recess 138 so as to contact well region 110.

[0646] A source electrode layer 140a may be formed to fill the groove 138, and thus the source electrode layer 140a may be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure may widen the contact area between the source electrode layer 140a and the well region 110, and the contact area between the source electrode layer 140a and the source region 112, thereby reducing the contact resistance therebetween.

[0647] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Therefore, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above-described structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0648] Reference Figure 71 ,replace Figures 66 to 69 The power semiconductor device 100b-6 may include a channel region 110a of the power semiconductor device 100d-6, and a channel region 107b forming an accumulation channel. The structure of the power semiconductor device 100d-6 including the channel region 107b may refer to Figure 65 Description given.

[0649] Therefore, the power semiconductor device 100d-6 may correspond to the following structure: Figure 65 The power semiconductor device 100 a - 6 is in a plurality of connections, with a well region 110 , a source region 112 , a source contact region 112 a and a well contact region 114 disposed therebetween.

[0650] Figures 72 to 74 is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 - 6 according to an embodiment of the present disclosure.

[0651] Reference Figure 72 A drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented using a substrate of the first conductivity type, and the drift region 107 can be formed using one or more epitaxial layers on the substrate.

[0652] Next, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities having the second conductivity type into the semiconductor layer 105.

[0653] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In more detail, the well region 110 may be formed by doping the drift region 107 with impurities of a conductivity type opposite to that of the drift region 107.

[0654] Then, a source region 112 having the first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities of the first conductivity type into the well region 110.

[0655] In addition to forming the source region 112, a channel region 110 a having an inversion channel formed in one direction may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. The channel region 110 a may be formed between the source region 112 and the vertical portion 107 a of the drift region 107. For example, the channel region 110 a may be a portion of the well region 110 and may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0656] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selective region.

[0657] Alternatively, a heat treatment process for activating or diffusing impurities may be performed after the ion implantation.

[0658] Reference Figure 73 , at least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0659] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110 .

[0660] In addition, the at least one trench 116 may include a plurality of trenches 116 , and the trenches 116 may be simultaneously formed in the semiconductor layer 105 , for example, in parallel in one direction. The channel region 110 a may be further limited by the trenches 116 .

[0661] For example, the trench 116 can be formed by forming a photomask using photolithography and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0662] Reference Figure 74 , a gate insulating layer 118 may be formed on the bottom and inner wall of the trench 116. For example, the formation of the gate insulating layer 118 may include forming a first portion 118a having a first thickness from the bottom surface of the trench, and forming a second portion 118b having a second thickness on the inner wall of the trench 116.

[0663] For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105. In some embodiments, the first portion 118a may be formed by depositing an insulating material, and the second portion 118b may be formed by oxidizing the semiconductor layer 105 or depositing an insulating material.

[0664] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0665] The patterning process may be performed using a photolithography process and an etching process. The photolithography process may include a process of forming a photoresist pattern as a mask layer by using a photo process and a development process, and the etching process may include a process of selectively etching a lower structure by using the photoresist pattern.

[0666] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0667] Next, an interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

[0668] Next, the source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may be formed by forming a conductive layer (eg, a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0669] at the same time, Figure 65 The power semiconductor device 100a-6 can be manufactured by adding some processes to the above-mentioned method for manufacturing the power semiconductor device 100-6 or changing or modifying the method. For example, the channel region 107b can be formed with a portion of the drift region 107 to form an accumulation channel.

[0670] Figures 66 to 69 The power semiconductor device 100 b - 6 can be manufactured by adding some processes to the above-mentioned method for manufacturing the power semiconductor device 100 - 6 or by changing or modifying the manufacturing method.

[0671] For example, when manufacturing power semiconductor device 100b-6, forming source region 112 may include forming source contact region 112a connected to source electrode layer 140 outside at least one end of gate electrode layer 120. In some embodiments, source contact region 112a may be a portion of source region 112.

[0672] Furthermore, before forming trench 116 , well contact region 114 may be formed in source contact region 112 a. For example, well contact region 114 may be formed by implanting a second conductivity type impurity having a higher concentration than well region 110 into a portion of well region 110 .

[0673] When manufacturing the power semiconductor device 100 b - 6 , the trenches 116 may be arranged to be linearly spaced apart from each other in one direction. In addition, the well region 110 , the channel region 110 a , and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116 .

[0674] refer to Figure 70 The described method for manufacturing the power semiconductor device 100c-6 may further include: forming at least one groove 138 in the source region 112 to penetrate the source region 112 and be recessed into the well region 110; forming a well contact region 114 on the bottom surface of the groove 138 to contact the well region 110, and forming a source electrode layer 140 to be connected to the well contact region 114.

[0675] According to the above-described manufacturing method, the power semiconductor device 100 - 6 using the semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0676] Figure 75 is a schematic perspective view illustrating a power semiconductor device 100 - 7 according to an embodiment of the present disclosure. Figure 76 It is shown along Figure 75 1 is a plan view of the power semiconductor device 100 - 7 taken along line II-II. Figure 77 is shown along Figure 76 1 is a cross-sectional view of the power semiconductor device 100 - 7 taken along line III-III. Figure 78 It is shown along Figure 76 1 is a cross-sectional view of the power semiconductor device 100 - 7 taken along line IV-IV.

[0677] Reference Figures 75 to 78 The power semiconductor device 100-7 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-7 may have a power MOSFET structure.

[0678] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers, for example, one epitaxial layer or multiple epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0679] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). In more detail, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0680] Silicon carbide (SiC) can have a wider band gap than silicon and therefore can maintain greater stability than silicon even at high temperatures. Furthermore, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-7 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0681] In more detail, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into an epitaxial layer of silicon carbide.

[0682] Well region 110 may be formed in semiconductor layer 105 to contact at least a portion of drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping drift region 107 with impurities of a second conductivity type opposite to the first conductivity type.

[0683] For example, the well region 110 may be formed to surround at least a portion of the drift region 107. In more detail, the well region 110 may include a vertical portion 107a extending vertically in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, at least a portion of the vertical portion 107a of the drift region 107 may include the vertical portion 107a, which may be surrounded and confined by the well region 110. In operation of the power semiconductor device 100-7, the vertical portion 107a may provide a vertical movement path for charges.

[0684] Figure 75 The well region 110 shown in FIG. 1 includes two regions spaced apart from each other and a vertical portion 107 a interposed between the two regions, but various changes or modifications may be made to the well region 110. For example, the vertical portion 107 a may have a shape whose side surfaces are surrounded by the well region 110.

[0685] The source region 112 may be formed in the well region 110 and may have the first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the first conductivity type impurities doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0686] The channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may have a first conductivity type, and an accumulation channel may be formed in the channel region 107b during operation of the power semiconductor device 100-7.

[0687] For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b may have the same doping type as the source region 112 and the drift region 107.

[0688] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the silicon carbide semiconductor layer 105, due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118, the energy band of the channel region 107b is bent upward, forming a potential barrier. In this way, an accumulation channel can be formed that allows charge or current to flow in the channel region 107b only when an operating voltage is applied to the gate electrode layer 120.

[0689] Therefore, a threshold voltage applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107 b can be significantly lower than a threshold voltage applied to the gate electrode layer 120 to form a normal inversion channel.

[0690] In some embodiments, the channel region 107b may be a portion of the drift region 107. In more detail, the channel region 107b may be a portion of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be integrally formed with the drift region 107.

[0691] In this case, the drift region 107 may be connected to the source region 112 through the channel region 107b. That is, the drift region 107 and the source region 112 may be in contact with each other at the channel region (107b).

[0692] For example, the doping concentration of the first conductivity type impurities of the channel region 107 b may be the same as or different from the doping concentration of the rest of the drift region 107 for adjustment of the threshold voltage.

[0693] In some embodiments, the well region 110, the channel region 107b, and the source region 112 may be formed symmetrically with respect to the vertical portion 107a of the drift region 107. The well region 110, the channel region 107b, and the source region 112 may be formed in the semiconductor layer 105 on opposite sides of the vertical portion 107a, or each of the well region 110, the channel region 107b, and the source region 112 may include a first portion and a second portion formed symmetrically with respect to the vertical portion 107a. In each of the well region 110, the channel region 107b, and the source region 112, the first portion and the second portion may be separated from each other or may be connected to each other.

[0694] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration of impurities than the drift region 107 .

[0695] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105.

[0696] At least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 to a given depth within the semiconductor layer 105. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to a length direction of the trench 116, rather than a depth direction of the trench 116, and may refer to a depth of the trench 116. Figure 76 The direction of line III-III or line IV-IV.

[0697] The gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof. The thickness of the gate insulating layer 118 may be uniform, or a portion of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a portion of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0698] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0699] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, a vertical portion 107a of the drift region 107 may vertically extend in the semiconductor layer 105 on one side of the gate electrode layer 120.

[0700] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on opposite sides of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107a extending vertically in the semiconductor layer 105 on opposite sides of the gate electrode layer 120.

[0701] The well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. In addition, the well region 110 may be formed deeper than the gate electrode layer 120, thereby surrounding the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite end portions of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0702] This structure can reduce the concentration of the electric field on the bottom surface of trench 116, that is, at the lower portion of gate electrode layer 120. Therefore, in power semiconductor device 100-7 according to the embodiment, well region 110 can be formed deeper than gate electrode layer 120 without separately forming a deep well, thereby reducing the electric field concentration on the bottom surface of trench 116. A problem with conventional vertical channel structures is that as the distance between the deep well and the trench becomes shorter, the junction resistance and threshold voltage increase. However, this problem may not occur in power semiconductor device 100-7 according to the embodiment.

[0703] The channel region 107 b may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120, between the vertical portion 107 a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 107 b, and the vertical portion 107 a of the drift region 107 are connected in one direction.

[0704] The above-described structure of the channel region 107 b may be referred to as a “lateral channel structure” because the channel region 110 a is formed along the sidewall of the gate electrode layer 120 .

[0705] In addition, a channel region 107b may be formed in the semiconductor layer 105 between the vertical portion 107a of the drift region 107 and the source region 112 on the opposite side of the gate electrode layer 120. In the above embodiment, the channel region 107b may be a portion of the vertical portion 107a of the drift region 107.

[0706] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116 , and moreover, may be formed to further extend outside the trench 116 .

[0707] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0708] For example, a plurality of trenches 116 may be formed in parallel along one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0709] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trench 116. In this way, the gate electrode layer 120 may be formed in a trench shape in the semiconductor layer 105 and may be arranged to extend parallel to the trench 116 in the same direction.

[0710] In addition, the gate insulating layer 118 and the gate electrode layer 120 may further extend to the outside of the trench 116 , and thus may be widely formed on the semiconductor layer 105 across the trench 116 .

[0711] In addition, the well region 110 may extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 may be arranged in the semiconductor layer 105 between the gate electrode layers 120. The channel region 107b may be formed in the semiconductor layer 105 between the source region 112 on one side or opposite sides of each gate electrode layer 120 and the vertical portion 107a of the drift region 107.

[0712] In some embodiments, the source region 112 may be connected across the gate electrode layer 120 while surrounding an end portion of the gate electrode layer 120 .

[0713] In some embodiments, the well region 110 may be formed in the semiconductor layer 105 to be deeper than the gate electrode layer 120 , thereby contacting the vertical portion 107 a of the drift region 107 and surrounding the bottom surface of the gate electrode layer 120 at opposite ends thereof.

[0714] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as oxide or nitride, or may include a stack structure thereof.

[0715] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, or the like.

[0716] In the power semiconductor device 100-7 described above, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of an n-type and a p-type. For example, when the first conductivity type is an n-type, the second conductivity type is a p-type, and vice versa.

[0717] In more detail, when the power semiconductor device 100 - 7 is an N-type MOSFET, the drift region 107 and the channel region 107 b may be N-regions, the source region 112 and the drain 102 may be N+ regions, and the well region 110 may be a P-region.

[0718] In operation of the power semiconductor device 100 - 7 , current may generally flow from the drain region 102 in a vertical direction along the vertical portion 107 a of the drift region 107 , and then may flow through the channel region 107 b along the side surface of the gate electrode layer 120 to the source region 112 .

[0719] In the above-described power semiconductor device 100-7, the gate electrode layers 120 may be densely arranged in parallel in a stripe shape, and the channel regions 110a may be arranged on the side surfaces of the gate electrode layers 120. In this way, the channel density may be increased.

[0720] Furthermore, in power semiconductor device 100-7, since the bottom surface of gate electrode layer 120 is surrounded by well region 110, the breakdown phenomenon caused by electric field concentration on the edge of trench 116 may be reduced. Therefore, the high withstand voltage characteristics of power semiconductor device 100-7 may be improved. This may mean that the reliability of operation of power semiconductor device 100-7 is improved.

[0721] Figure 79 is a schematic perspective view illustrating a power semiconductor device 100 a - 7 according to another embodiment of the present disclosure. Figure 80 It is shown along Figure 79 VI-VI is a plan view of the power semiconductor device 100 a - 7 . Figure 81 is shown along Figure 80 VII-VII is a cross-sectional view of the power semiconductor device 100 a - 7 . Figure 82 is shown along Figure 80 1 is a cross-sectional view of the power semiconductor device 100 a - 7 taken along line VIII-VIII.

[0722] The power semiconductor device 100 a - 7 according to the embodiment may be formed by using or partially modifying Figures 75 to 78 Therefore, additional description will be omitted to avoid repetition.

[0723] Reference Figures 79 to 82 The source region 112 may include a source contact region 112 a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120 . For example, the source contact region 112 a as a portion of the source region 112 may refer to a portion connected to the source electrode layer 140 .

[0724] Well contact region 114 may be formed in source contact region 112a. For example, well contact region 114 may extend from well region 110 to penetrate source region 112 and may have the second conductivity type. One well contact region 114 or multiple well contact regions 114 may be formed in source contact region 112a.

[0725] For example, the well contact region 114 may be connected to the source electrode layer 140 and may be doped with impurities of the second conductivity type at a higher concentration than the well region 110 to reduce contact resistance when connected to the source electrode layer 140 .

[0726] exist Figures 79 to 82 , source contact region 112 a and well contact region 114 are formed in source region 112 on one side of vertical portion 107 a of drift region 107. However, source contact region 112 a and well contact region 114 may be formed on opposite sides of each vertical portion 107 a of drift region 107. Alternatively, when each of source region 112 and well region 110 is divided into a plurality of regions, each of source contact region 112 a and well contact region 114 may be formed in each corresponding region.

[0727] In some embodiments, the plurality of trenches 116 may be arranged to be linearly spaced apart from one another along one direction. Thus, the gate electrode layer 120 may also be arranged to be linearly spaced apart from one another along the trenches 116 in the one direction. In this case, the well region 110 and the source region 112 may be formed in the semiconductor layer 105 such that the well region 110 and the source region 112 are located between the plurality of trenches 116 arranged to be linearly spaced apart from one another along the one direction.

[0728] For example, Figures 75 to 77 The structure of the power semiconductor device 100 - 7 shown may be arranged in plurality along one direction, and a well region 110 , a source region 112 , a source contact region 112 a , and a well contact region 114 may be formed therebetween.

[0729] For example, when the power semiconductor device 100 - 7 is an N-type MOSFET, the source contact region 112 a may be an N+ region, and the well contact region 114 may be a P+ region.

[0730] In the power semiconductor device 100a-7 according to the embodiment, the source contact region 112a and the well contact region 114 can be arranged outside the gate electrode layer 120 rather than between the gate electrode layers 120. Therefore, the gate electrode layers 120 can be arranged more densely. In this way, the channel density of the power semiconductor device 100a-7 can be significantly increased.

[0731] Furthermore, according to the power semiconductor device 100a-7, the high withstand voltage characteristics of the power semiconductor device 100a-7 are improved because the threshold voltage is lowered by using the channel region 107b formed with the accumulation channel and the breakdown phenomenon caused by the concentration of the electric field on the edge of the trench 116 is alleviated. This may mean that the reliability of the operation of the power semiconductor device 100a-7 is improved.

[0732] Figures 83 to 86 100b-7, 100c-7, 100d-7, and 100e-7 according to other embodiments of the present disclosure. Figures 75 to 82 The present invention is implemented by the partial configuration of the power semiconductor device 100 - 7 or 100 a - 7 , and therefore, additional description will be omitted to avoid repetition.

[0733] Reference Figure 83 In the power semiconductor device 100 b - 7 , the well region 110 may protrude further toward the vertical portion 107 a of the drift region 107 than a portion of the source region 112 .

[0734] Channel region 107b1 may be formed in semiconductor layer 105 on the protruding portion of well region 110. For example, vertical portion 107a of drift region 107 may be further extended to a recessed portion formed between well region 110 and gate electrode layer 120, forming the protruding portion of well region 110. Channel region 107b1 may be formed on vertical portion 107a. This structure may further confine channel region 107b1 between gate electrode layer 120 and well region 110.

[0735] Reference Figure 84 In the power semiconductor device 100 c - 7 , the well region 110 may protrude further toward the vertical portion 107 a of the drift region 107 than a portion of the source region 112. Furthermore, the well region 110 may include a tap portion at an end thereof extending toward the gate electrode layer 120. For example, the well region 110 may protrude further toward the vertical portion 107 a of the drift region 107 than a portion of the source region 112 and may include a tap portion at an end thereof.

[0736] The channel region 107b2 may be formed in the semiconductor layer 105 on the protruding portion of the well region 110. For example, the channel region 107b2 may be formed in a curved shape on the protruding portion and the tap portion of the well region 110. This structure may further confine the channel region 107b2 between the gate electrode layer 120 and the well region 110.

[0737] Reference Figure 85 In the power semiconductor device 100d-7, the well region 110 may protrude further toward the vertical portion 107a of the drift region 107 than a portion of the source region 112. Furthermore, the well region 110 may include a tap portion at its end extending toward the gate electrode layer 120. For example, the well region 110 may protrude further toward the vertical portion 107a of the drift region 107 than a portion of the source region 112 and may include a tap portion at its end. Furthermore, the vertical portion 107a of the drift region 107 may further extend between a lower portion of the source region 112 and the well region 110.

[0738] The channel region 107b3 may be formed to further extend to between the lower portion of the source region 112 and the well region 110. For example, the channel region 107b3 may be formed in a curved shape from the tap portion of the well region 110 to the lower portion of the source region 112. This structure can widen the contact area between the channel region 107b3 and the source region 112.

[0739] Reference Figure 86 The power semiconductor device 100e-7 may include at least one recess 138 in the source contact region 112a of the source region 112, the recess 138 being formed to penetrate the source region 112 and recessed into the well region 110. A contact region 114a may be formed on at least a bottom surface of the recess 138 so as to contact the well region 110.

[0740] A source electrode layer 140a may be formed to fill the groove 138, so that the source electrode layer 140a may be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure may widen the contact area between the source electrode layer 140a and the well region 110 and the source region 112, thereby reducing the contact resistance therebetween.

[0741] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Therefore, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above-described structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0742] Figures 87 to 89is a schematic perspective view illustrating a method of manufacturing a power semiconductor device 100 a - 7 according to an embodiment of the present disclosure.

[0743] Reference Figure 87 A drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented using a substrate of the first conductivity type, and the drift region 107 can be formed on the substrate using one or more epitaxial layers.

[0744] Next, a well region 110 having the second conductivity type may be formed in semiconductor layer 105 to contact at least a portion of drift region 107. For example, the formation of well region 110 may be performed by implanting impurities having the second conductivity type into semiconductor layer 105.

[0745] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, at least a portion of which is surrounded by the well region 110. In more detail, the well region 110 may be formed by doping the drift region 107 with impurities of a conductivity type opposite to that of the drift region 107.

[0746] Then, a source region 112 having the first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities of the first conductivity type into the well region 110.

[0747] In addition to the formation of the source region 112, at least one channel region 107b having the second conductivity type, in which an accumulation channel is formed along one direction, may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. For example, the channel region 107b may be formed between the source region 112 and the vertical portion 107a of the drift region 107.

[0748] For example, when the channel region 107 b is a portion of the drift region 107 , the source region 112 may be formed to contact the drift region 107 through the channel region 107 b .

[0749] In the above manufacturing method, impurity implantation or impurity doping may be performed so that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selective region.

[0750] Alternatively, a heat treatment process for activating or diffusing impurities may be performed after the ion implantation.

[0751] Reference Figure 88, at least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0752] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110 .

[0753] In addition, a plurality of trenches 116 may be formed in parallel in one direction in the semiconductor layer 105 .

[0754] For example, the trench 116 can be formed by forming a photomask using photolithography and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0755] Reference Figure 89 , a gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0756] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0757] For example, the gate insulating layer 118 and the gate electrode layer 120 may be formed to further protrude outside the trench 116. In addition, the gate insulating layer 118 and the gate electrode layer 120 may be widely formed on the semiconductor layer 105 covering the trench 116.

[0758] The patterning process may be performed using a photolithography process and an etching process. The photolithography process may include a process of forming a photoresist pattern as a mask layer by using a photo process and a development process, and the etching process may include a process of selectively etching a lower structure by using the photoresist pattern.

[0759] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, so as to surround the bottom surface of the gate electrode layer 120 at least at one end of the gate electrode layer 120, and the channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0760] In addition, an interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

[0761] Next, the source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may be formed by forming a conductive layer (eg, a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0762] at the same time, Figures 79 to 82 The power semiconductor device 100 a - 7 shown can be manufactured by adding some processes to the above-mentioned method for manufacturing the power semiconductor device 100 - 7 or by changing or modifying the manufacturing method.

[0763] For example, when manufacturing power semiconductor device 100a-7, forming source region 112 may include forming source contact region 112a connected to source electrode layer 140 outside at least one end of gate electrode layer 120. In some embodiments, source contact region 112a may not be separated from source region 112.

[0764] In addition, well contact region 114 may be formed in source contact region 112a before forming trench 116. For example, well contact region 114 may be formed by implanting second conductivity type impurities having a higher concentration than well region 110 into a portion of well region 110.

[0765] When manufacturing the power semiconductor device 100 a - 7 , the trenches 116 may be arranged to be linearly spaced apart from each other in one direction. In addition, the well region 110 , the channel region 107 b , and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116 .

[0766] According to the above-described manufacturing method, the power semiconductor device 100 - 7 using the semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0767] Figure 90 is a schematic perspective view illustrating a power semiconductor device 100 - 8 according to an embodiment of the present disclosure. Figure 91 It is shown along Figure 90 1 is a plan view of the power semiconductor device 100 - 8 taken along line II-II. Figure 92 It is shown along Figure 91 1 is a cross-sectional view of the power semiconductor device 100 - 8 taken along line III-III.

[0768] refer to Figures 90 to 92 The power semiconductor device 100-8 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-8 may have a power MOSFET structure.

[0769] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers, for example, one epitaxial layer or multiple epitaxial layers. In addition, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0770] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). In more detail, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0771] Silicon carbide (SiC) can have a wider band gap than silicon and therefore can maintain greater stability than silicon even at high temperatures. Furthermore, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-8 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0772] In more detail, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into an epitaxial layer of silicon carbide.

[0773] Well region 110 may be formed in semiconductor layer 105 to contact drift region 107 and may have a second conductivity type. For example, well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in drift region 107. More specifically, well region 110 may be provided on drift region 107.

[0774] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the well region 110 with impurities of the first conductivity type. The concentration of the first conductivity type impurities doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0775] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be doped with a higher concentration of impurities than the drift region 107 .

[0776] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a portion of the semiconductor layer 105 or as a substrate independent of the semiconductor layer 105.

[0777] At least one trench 116 may be formed to be recessed from the surface of the semiconductor layer 105 to a given depth in the semiconductor layer 105. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to a length direction of the trench 116, rather than a depth direction of the trench 116, and may refer to a depth of the trench 116. Figure 91 The direction of the line III-III.

[0778] The gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or a portion of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a portion of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0779] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stack structure thereof.

[0780] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0781] In some embodiments, drift region 107 may be formed in semiconductor layer 105 below gate electrode layer 120. In semiconductor layer 105 above drift region 107, well region 110 may be formed deeper than gate electrode layer 120 to surround at least opposite sidewalls and a bottom edge of gate electrode layer 120.

[0782] Junction resistance reduction region 108 may be formed in semiconductor layer 105 to connect with drift region 107 below the bottom surface of gate electrode layer 120. Junction resistance reduction region 108 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into semiconductor layer 105.

[0783] In some embodiments, the well region 110 may be formed to surround the sidewalls and bottom surface of the gate electrode layer 120, and the junction resistance reduction region 108 may be formed between the bottom surface of the gate electrode layer 120 and the drift region 107 to penetrate the well region 110. In this case, the junction resistance reduction region 108 may be formed by doping the well region 110 with impurities of the first conductivity type.

[0784] The well (110) structure can further reduce the electric field concentration on the bottom surface of the trench 116 (i.e., the lower edge of the gate electrode layer 120). The above structure can increase the electric field margin of the gate insulating layer 118 covering the power semiconductor device 100-8, thereby improving the reliability of the operation of the power semiconductor device 100-8.

[0785] The channel region 110 a may be formed in the semiconductor layer 105 between the junction resistance reduction region 108 and the source region 112. For example, the channel region 110 a may be formed in the semiconductor layer 105 between the junction resistance reduction region 108 and the source region 112 along the sidewall of the gate electrode layer 120. For example, the channel region 110 a may have the second conductivity type, and in operation of the power semiconductor device 100 - 8 , an inversion channel may be formed in the channel region 110 a along one direction.

[0786] Because the channel region 110 a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110 a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110 a may not allow charge movement under normal circumstances; however, when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, thereby allowing charge movement.

[0787] In some embodiments, the channel region 110a may be a portion of the well region 110. In this case, the channel region 110a may be formed as a whole to be continuously connected to the well region 110. The doping concentration of the second conductivity type impurities of the channel region 110a may be the same as or different from the doping concentration of the rest of the well region 110 for adjusting the threshold voltage.

[0788] The doping concentration of the first conductivity type impurity in the junction resistance reduction region 108 may be equal to or higher than the doping concentration of the drift region 107. In some embodiments, the doping concentration of the first conductivity type impurity in the junction resistance reduction region 108 may be higher than the doping concentration of the drift region 107, thereby reducing the junction resistance. In this case, since the junction resistance reduction region 108, whose resistance is lower than that of the drift region 107, is joined to the channel region 110 a, the junction resistance can be reduced.

[0789] In addition, the doping concentration of the first conductivity type impurities of the junction resistance reduction region 108 may be equal to or lower than the doping concentration of the first conductivity type impurities of the source region 112 and the drain region 102 .

[0790] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116 , and moreover, may be formed to further extend to the outside of the trench 116 .

[0791] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0792] For example, a plurality of trenches 116 may be formed in parallel along one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0793] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trench 116. In this way, a trench-type gate electrode layer 120 may be formed in the semiconductor layer 105 and arranged to extend parallel to the trench 116 in the same direction.

[0794] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as oxide or nitride, or may include a stack structure thereof.

[0795] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of an appropriate conductive material (metal, etc.).

[0796] In the power semiconductor device 100-8 described above, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of an n-type and a p-type. For example, when the first conductivity type is an n-type, the second conductivity type is a p-type, and vice versa.

[0797] In more detail, when the power semiconductor device 100 - 8 is an N-type MOSFET, the drift region 107 can be an N-region, the junction resistance reduction region 108 can be an N-region, the source region 112 and the drain region 102 can be N+ regions, and the well region 110 and the channel region 110a can be P-regions.

[0798] In operation of the power semiconductor device 100 - 8 , current may generally flow in a vertical direction from the drain region 102 to the drift region 107 and the junction resistance reduction region 108 , and then may flow along the sidewalls of the gate electrode layer 120 on which the channel region is formed to the source region 112 .

[0799] In the power semiconductor device 100-8 described above, the gate electrode layers 120 in the trenches 116 may be densely arranged in parallel in a stripe or line type, and the channel regions may be provided on the side surfaces of the gate electrode layers 120. In this way, the channel density may be increased.

[0800] Figure 93 is a perspective view showing a power semiconductor device 100a-8 according to another embodiment of the present disclosure. The power semiconductor device 100a-8 according to the embodiment can be modified by using or partially Figures 90 to 92 Therefore, additional description will be omitted to avoid repetition.

[0801] Reference Figure 93 In the power semiconductor device 100a-8, the source region 112 may be continuously formed along the extension direction of the gate electrode layer 120. For example, the source region 112 may be widely formed to surround the upper region of the gate electrode layer 120. As described above, when the source region 112 is widely formed, the charge movement path from the drain region 102 to the source region 112 may be widened.

[0802] Figure 94 is a schematic perspective view illustrating a power semiconductor device 100 b - 8 according to another embodiment of the present disclosure. Figure 95 is shown along Figure 94 VI-VI is a plan view of the power semiconductor device 100 b - 8 . Figure 96 It is shown along Figure 95 VII-VII is a cross-sectional view of the power semiconductor device 100 b - 8 . Figure 97 It is shown along Figure 95 1 is a cross-sectional view of the power semiconductor device 100 b - 8 taken along line VIII-VIII.

[0803] The power semiconductor device 100 b - 8 according to the embodiment may be modified by using or partially Figures 90 to 92 Therefore, additional description will be omitted to avoid redundancy.

[0804] Reference Figures 94 to 97 In the power semiconductor device 100 b - 8 , the source region 112 may include a source contact region 112 a outside at least one end of the gate electrode layer 120 . For example, the source contact region 112 a as a portion of the source region 112 may refer to a portion connected to the source electrode layer 140 .

[0805] Well contact region 114 may be formed in source contact region 112a. For example, well contact region 114 may extend from well region 110 to penetrate source region 112 and may have the second conductivity type. One well contact region 114 or multiple well contact regions 114 may be formed in source contact region 112a.

[0806] For example, the well contact region 114 may be doped with impurities of the second conductivity type at a higher concentration than that of the well region 110 to reduce contact resistance when connected to the source electrode layer 140 .

[0807] The source electrode layer 140 may be commonly connected to the source contact region 112 a and the well contact region 114 .

[0808] In some embodiments, the plurality of trenches 116 may be arranged to be linearly spaced apart from one another along one direction. Thus, the gate electrode layer 120 may also be arranged to be linearly spaced apart from one another along the trenches 116 in the one direction. In this case, the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from one another along the one direction.

[0809] For example, the power semiconductor device 100b-8 can be arranged in a plurality of Figures 90 to 92 The structure of the power semiconductor device 100 - 8 is formed by arranging a well region 110 , a source region 112 , a source contact region 112 a , and a well contact region 114 therebetween.

[0810] For example, when the power semiconductor device 100 - 8 is an N-type MOSFET, the source contact region 112 a may be an N+ region, and the well contact region 114 may be a P+ region.

[0811] According to the power semiconductor device 100 b - 8 , the source contact region 112 a and the well contact region 114 can be disposed outside the gate electrode layer 120 rather than between the gate electrode layers 120 , thereby allowing the gate electrode layers 120 to be arranged more densely. In this way, the channel density of the power semiconductor device 100 b - 8 can be significantly increased.

[0812] Figure 98 is a cross-sectional view showing a power semiconductor device 100c-8 according to another embodiment of the present disclosure. Figures 94 to 97 The power semiconductor device 100c-8 is implemented by a partial configuration of the power semiconductor device 100b-8 in FIG. Therefore, additional descriptions will be omitted to avoid redundancy as they may refer to each other.

[0813] Reference Figure 98 , power semiconductor device 100c-8 may include at least one recess 138 in source contact region 112a of source region 112, the recess 138 being formed to penetrate source region 112 and recessed into well region 110. Well contact region 114a may be formed on at least a bottom surface of recess 138 to contact well region 110.

[0814] A source electrode layer 140a may be formed to fill the groove 138, and the source electrode layer 140a may be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure may widen the contact area between the source electrode layer 140a and the well region 110 and the contact area between the source electrode layer 140a and the source region 112, thereby reducing the contact resistance therebetween.

[0815] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Therefore, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above-described structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0816] Figure 99 is a cross-sectional view showing a power semiconductor device 100d-8 according to another embodiment of the present disclosure. Figures 94 to 97 The power semiconductor device 100d-8 is implemented by a partial configuration of the power semiconductor device 100b-8 in FIG. Therefore, additional descriptions will be omitted to avoid redundancy as they may refer to each other.

[0817] Reference Figure 99 In the power semiconductor device 100d-8, the source region 112 may be formed to be continuous along the extension direction of the gate electrode layer 120. For example, the source region 112 may extend along the upper portion of the gate electrode layer 120 and further extend between the gate electrode layers 120 arranged in a straight line.

[0818] The source region 112 may be widely formed to surround the upper region of the gate electrode layer 120. As described above, when the source region 112 is widely formed, a charge moving path from the drain region 102 to the source region 112 may be widened.

[0819] As described above, according to the embodiments of the present disclosure, a power semiconductor device and a method for manufacturing the same can alleviate the concentration of electric fields and can increase channel density, thereby improving the degree of integration.

[0820] Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

[0821] Although the present disclosure has been described above with reference to the exemplary embodiments and the accompanying drawings, the present disclosure is not limited thereto, and those skilled in the art to which the present disclosure pertains may make various modifications and changes to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A power semiconductor device, comprising: a first trench recessed into the semiconductor layer from a surface of the semiconductor layer along a first direction and extending along a second direction different from the first direction; a source contact region, contacting a surface of the semiconductor layer and spaced apart from the first trench in the second direction; a source region, contacting the source contact region and one side of the first trench, and having first conductivity type impurities; a well region, contacting a bottom surface and one side of the source region and contacting both sides and a bottom surface of the first trench, and having second conductivity type impurities; a drift region contacting a bottom surface of the well region and having first conductivity type impurities; as well as A junction resistance reduction region is provided in the well region, contacts the drift region and the bottom surface of the first trench, and has first conductivity type impurities.

2. The power semiconductor device according to claim 1, wherein: The source contact region further extends along a third direction perpendicular to the second direction.

3. The power semiconductor device according to claim 1, further comprising: a first gate insulating layer, disposed on an inner wall of the first trench; as well as A first gate electrode layer is disposed on the first gate insulating layer in the first trench, extends above the surface of the semiconductor layer, and covers at least a portion of the surface of the semiconductor layer.

4. The power semiconductor device according to claim 1, wherein: The first direction is perpendicular to the second direction.

5. The power semiconductor device according to claim 1, wherein: A concentration of the first conductive type impurity in the junction resistance reduction region is higher than a concentration of the first conductive type impurity in the drift region, and is lower than a concentration of the first conductive type impurity in the source region.

6. The power semiconductor device according to claim 1, further comprising: A drain region is disposed below the drift region and has the first conductive type impurities.

7. The power semiconductor device according to claim 1, further comprising: a second trench, recessed from the surface of the semiconductor layer into the semiconductor layer along the first direction, extending along the second direction, and spaced apart from the source contact region in the second direction; a second gate insulating layer, disposed on an inner wall of the second trench; as well as A second gate electrode layer is disposed on the second gate insulating layer in the second trench, extends above the surface of the semiconductor layer, and covers at least a portion of the surface of the semiconductor layer.

8. The power semiconductor device according to claim 1, further comprising: A well contact region penetrates the source region from the well region and contacts the surface of the semiconductor layer, and has second conductivity type impurities.

9. The power semiconductor device according to claim 8, further comprising: A source electrode layer contacts each of the source contact region and the well contact region.

10. A power semiconductor device, comprising: a plurality of trenches recessed into the semiconductor layer from a surface of the semiconductor layer along a first direction and extending along a second direction different from the first direction, the plurality of trenches being spaced apart from each other in a third direction; a source region, disposed between the plurality of trenches along the third direction and having first conductivity type impurities; a well region contacting a bottom surface and one side of the source region and contacting both sides and a bottom surface of each of the plurality of trenches, and having a second conductive type impurity; a drift region contacting a bottom surface of the well region and having first conductivity type impurities; as well as A plurality of junction resistance reduction regions are provided in the well region, contact the drift region and a bottom surface of each of the plurality of trenches, are spaced apart from each other in the third direction, and have first conductivity type impurities.

11. The power semiconductor device according to claim 10, wherein: The source region is provided from the surface of the semiconductor layer to a first depth, and The plurality of trenches are provided from a surface of the semiconductor layer to a second depth deeper than the first depth.

12. The power semiconductor device according to claim 10, further comprising: a gate insulating layer disposed on a surface of the semiconductor layer between inner walls of each of the plurality of trenches; as well as A gate electrode layer is provided on the gate insulating layer in the trench, extends above the surface of the semiconductor layer, and covers at least a portion of the surface of the semiconductor layer.

13. The power semiconductor device according to claim 10, wherein: The second direction is perpendicular to the first direction and the third direction is perpendicular to each of the first direction and the second direction, respectively.

14. The power semiconductor device according to claim 10, further comprising: The drain region is disposed below the drift region and has first conductive type impurities.

15. The power semiconductor device according to claim 10, further comprising: The concentration of the first conductive type impurities in the plurality of junction resistance reduction regions is higher than the concentration of the first conductive type impurities in the drift region.

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