Light emitting element and display device including the same

Abstract

The invention provides a light emitting element and a display device including the same. The light emitting element includes: a first semiconductor layer doped to have a first conductivity type; a stress relief layer disposed on the first semiconductor layer, the stress relief layer including an indium-containing layer containing an indium-containing nitride-based semiconductor material, and doped to have a first conductivity type; a light emitting layer disposed on the stress relief layer, the light emitting layer including a quantum well layer containing a nitride-based semiconductor material having an indium component greater than or equal to an indium component of the indium-containing layer; and a second semiconductor layer disposed on the light emitting layer and doped to have a second conductivity type, an indium component of the indium-containing layer being in a range of 30% to 100% of an indium component of the quantum well layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0018159 filed on February 6, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a light emitting element and a display device including the light emitting element. Background Art

[0004] Light-emitting elements are widely used as light sources in various electronic devices including display devices. For example, light-emitting elements are used as light sources in various electronic devices including portable electronic devices and televisions, as well as virtual reality (VR) devices and augmented reality (AR) devices.

[0005] It is to be understood that this background section is intended, in part, to provide a useful background for understanding the technology. However, this background section may also include ideas, concepts, or cognitions that were not known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0006] Aspects of the present disclosure provide a light emitting element having improved color purity and a display apparatus including the light emitting element.

[0007] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0008] According to one aspect of the present disclosure, a light-emitting element is provided. The light-emitting element may include: a first semiconductor layer doped to have a first conductivity type; a stress relief layer disposed on the first semiconductor layer, the stress relief layer including an indium-containing layer containing a nitride-based semiconductor material containing indium and doped to have the first conductivity type; a light-emitting layer disposed on the stress relief layer, the light-emitting layer including a quantum well layer containing a nitride-based semiconductor material having an indium content greater than or equal to the indium content of the indium-containing layer; and a second semiconductor layer disposed on the light-emitting layer and doped to have a second conductivity type. The indium content of the indium-containing layer may be in a range of 30% to 100% of the indium content of the quantum well layer.

[0009] In an embodiment, the doping concentration of the indium-containing layer may be 10 16 / cm 3 or higher.

[0010] In an embodiment, the doping concentration of the indium-containing layer may be lower than the doping concentration of the first semiconductor layer.

[0011] In an embodiment, the thickness of the indium-containing layer may be 2 nm or greater.

[0012] In an embodiment, the light emitting element may further include a superlattice layer disposed between the first semiconductor layer and the stress relief layer. The superlattice layer may be formed as a multilayer in which a first layer containing an indium-containing nitride-based semiconductor material and a second layer containing an indium-free nitride-based semiconductor material may be alternately disposed.

[0013] In an embodiment, the indium composition of the first layer of the superlattice layer may be less than 30% of the indium composition of the quantum well layer.

[0014] In an embodiment, the superlattice layer may be doped with a doping concentration lower than or equal to a doping concentration of the first semiconductor layer.

[0015] In an embodiment, the light emitting element may further include a spacer layer disposed between the superlattice layer and the stress relaxation layer, the spacer layer including a nitride-based semiconductor material not containing indium, and the thickness of the spacer layer may be 20 nm or more.

[0016] In an embodiment, the quantum well layer may contain InGaN, and the indium-containing layer may contain InGaN or InAlGaN.

[0017] In an embodiment, the indium-containing layer may directly contact the light-emitting layer.

[0018] In an embodiment, the stress relaxation layer may be a single layer formed of an indium-containing layer, and the indium composition of the stress relaxation layer may gradually change from a lower portion adjacent to the first semiconductor layer to an upper portion adjacent to the light emitting layer.

[0019] In an embodiment, the stress relaxation layer may be formed as a multilayer in which a plurality of indium-containing layers including an indium-containing layer and a plurality of intermediate layers containing a nitride-based semiconductor material not containing indium may be alternately disposed.

[0020] In an embodiment, the indium composition of the plurality of indium containing layers may gradually change from the indium containing layer at a lower portion adjacent to the first semiconductor layer among the plurality of indium containing layers to the indium containing layer at an upper portion adjacent to the light emitting layer among the plurality of indium containing layers.

[0021] In an embodiment, the doping concentration of the stress relaxation layer may gradually change from a lower portion adjacent to the first semiconductor layer to an upper portion adjacent to the light emitting layer.

[0022] In an embodiment, the doping concentration of the stress relaxation layer may gradually decrease from a lower portion adjacent to the first semiconductor layer to an upper portion adjacent to the light emitting layer.

[0023] In an embodiment, the indium fluctuation in the light emitting layer may be at least 10% higher than the indium fluctuation in the stress release layer.

[0024] In an embodiment, the indium composition of the quantum well layer may be 25% or more, and the emission wavelength of the light emitting layer may be in the range of 500 nm to 750 nm.

[0025] According to one aspect of the present disclosure, a display device is provided, which may include: a pixel including a first pixel electrode, a second pixel electrode, and a light-emitting element electrically connected between the first pixel electrode and the second pixel electrode. The light-emitting element may include: a first semiconductor layer doped to have a first conductivity type; a stress relief layer disposed on the first semiconductor layer, the stress relief layer including an indium-containing layer containing a nitride-based semiconductor material containing indium and doped to have the first conductivity type; a light-emitting layer disposed on the stress relief layer, the light-emitting layer including a quantum well layer containing a nitride-based semiconductor material containing indium; and a second semiconductor layer disposed on the light-emitting layer and doped to have a second conductivity type, wherein the indium content of the indium-containing layer may be in the range of 30% to 100% of the indium content of the quantum well layer.

[0026] In an embodiment, the doping concentration of the indium-containing layer may be 10 16 / cm 3 or higher.

[0027] In an embodiment, the light emitting element may further include a superlattice layer disposed between the first semiconductor layer and the stress relaxation layer, and the superlattice layer may contain a nitride-based semiconductor material having an indium content less than 30% of the indium content of the quantum well layer.

[0028] A light-emitting element according to an embodiment may include a stress relief layer disposed between a first semiconductor layer doped to have a first conductivity type and a light-emitting layer. The stress relief layer may include an indium-containing layer containing a nitride-based semiconductor material containing indium, and may be doped. The indium content of the indium-containing layer may be in a range of 30% to 100% of the indium content of a quantum well layer constituting the light-emitting layer.

[0029] According to an embodiment, a high-quality light-emitting element with improved color purity and a display device including the light-emitting element can be provided. For example, although a long-wavelength light-emitting element in which the indium composition of the quantum well layer is 25% or more is manufactured, due to the lattice matching effect of the stress release layer formed before the quantum well layer is formed, the in-plane strain can be alleviated, and indium can be smoothly injected into the quantum well layer. By doping the stress release layer, light of a wavelength corresponding to the indium composition of the stress release layer can be prevented from being generated in the stress release layer. Therefore, while emitting long-wavelength light such as green light or red light, a high-quality light-emitting element with improved color purity and reduced defects and a display device including the light-emitting element can be provided.

[0030] However, the effects according to the embodiments of the present disclosure are not limited to those described above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic cross-sectional view showing a light emitting element according to one embodiment;

[0033] Figure 2 is a schematic cross-sectional view showing a light emitting element according to one embodiment;

[0034] Figure 3 is a schematic cross-sectional view showing a light emitting element according to one embodiment;

[0035] Figure 4 is a schematic cross-sectional view showing a light emitting element according to one embodiment;

[0036] Figure 5 is a schematic cross-sectional view showing a light-emitting layer according to one embodiment;

[0037] Figure 6 is a schematic cross-sectional view showing a stress release layer according to one embodiment;

[0038] Figure 7 is a schematic cross-sectional view showing a superlattice layer according to one embodiment;

[0039] Figure 8 is a schematic cross-sectional view showing a stress release layer according to one embodiment;

[0040] Figure 9 is a schematic cross-sectional view showing a stress release layer according to one embodiment;

[0041] Figure 10 is a schematic cross-sectional view showing a stress release layer according to one embodiment;

[0042] Figure 11 is a schematic perspective view showing a display device according to one embodiment;

[0043] Figure 12 It shows Figure 11 A schematic plan view of an example of an area A1;

[0044] Figure 13 is a schematic cross-sectional view showing a display panel according to one embodiment;

[0045] Figure 14 is a diagram illustrating a virtual reality device including a display device according to one embodiment;

[0046] Figure 15 is a diagram illustrating a smart device including a display device according to one embodiment;

[0047] Figure 16 shows a car instrument panel and a center instrument panel including a display device according to one embodiment; and

[0048] Figure 17 is a diagram illustrating a transparent display device including a display device according to one embodiment. DETAILED DESCRIPTION

[0049] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0050] In the drawings, the size, thickness, ratio, and dimensions of elements may be exaggerated for ease of description and clarity. Like numbers refer to like elements throughout.

[0051] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0052] In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in conjunction or separately and may be understood to be equivalent to "and / or."

[0053] In the specification and claims, for purposes of its meaning and interpretation, the phrase "at least one" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B."

[0054] It will also be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer, or intervening layers may also be present. Like reference numerals refer to like parts throughout the specification.

[0055] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure. Similarly, the second element may also be referred to as the first element.

[0056] The term "overlap" or "overlapping" means that a first object can be above or below a second object, or to one side of the second object, and vice versa. Additionally, the term "overlap" may include layer, stack, facing, facing, extending over, covering, or partially covering, or any other suitable term as would be understood and appreciated by one of ordinary skill in the art.

[0057] The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements can be understood as being indirectly opposite to each other, although still facing each other.

[0058] When an element is described as being "non-overlapping" or "not "overlapping" another element, this can include the elements being spaced apart from each other, offset from each other, or disposed beside each other, or any other suitable terminology as would be understood and appreciated by one of ordinary skill in the art.

[0059] When used in this specification, the terms “comprises,” “comprising,” “includes,” and “including,” “has,” “have,” and / or “having,” and variations thereof, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0060] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, given the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0061] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0062] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other and may be technically coordinated with each other differently, and the various embodiments may be implemented independently of each other, or may be implemented together in association with each other.

[0063] Figure 1 is a schematic cross-sectional view showing a light emitting element LE according to one embodiment.

[0064] refer to Figure 1 , the light emitting element LE may be provided on the substrate SUB. For example, the light emitting element LE may be manufactured on the substrate SUB and separated from the substrate SUB.

[0065] Figure 1 A first direction DR1, a second direction DR2, and a third direction DR3 are shown as being perpendicular to each other. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other and define a plane parallel to the bottom surface (e.g., the lower surface or the upper surface) of the light-emitting element LE or the substrate SUB. The third direction DR3 may be perpendicular to the first direction DR1 and the second direction DR2. For example, the third direction DR3 may be a direction perpendicular to the bottom surface of the substrate SUB and may be a height direction or a thickness direction of the substrate SUB or the light-emitting element LE.

[0066] The substrate SUB (also referred to as a "growth substrate" or "fabrication substrate") may be a semiconductor substrate used to form the light-emitting element LE. The substrate SUB may be a fabrication substrate, a wafer, or the like suitable for epitaxial growth. For example, the first semiconductor layer SEM1, the stress relief layer SRL (e.g., a strain relief layer), the light-emitting layer EML, and the second semiconductor layer SEM2 of the light-emitting element LE may be formed by epitaxial growth on the substrate SUB.

[0067] In one embodiment, the substrate SUB may be a semiconductor substrate including silicon (Si), sapphire, GaAs, SiC, GaN, ZnO, or other materials. The type or material of the substrate SUB is not particularly limited as long as epitaxial growth for manufacturing the light emitting element LE can be smoothly performed.

[0068] In one embodiment, the substrate SUB can be used as a substrate for epitaxial growth of a light-emitting element LE and can ultimately be separated from the light-emitting element LE. For example, within the spirit and scope of the present disclosure, after sequentially forming (e.g., growing or regrowing) semiconductor layers to form the light-emitting element LE on the substrate SUB, a light-emitting element LE having a size smaller than that of the substrate SUB (e.g., an area smaller than that of the substrate SUB) can be formed by etching, cutting, etc. For example, after simultaneously forming the light-emitting element LE on the substrate SUB, the light-emitting element LE can be separated from the substrate SUB.

[0069] According to embodiments, the light emitting element LE may have various forms. In one embodiment, the light emitting element LE may include a side surface that is substantially perpendicular to the substrate SUB. For example, the light emitting element LE may have a cross-sectional shape such as a rectangle or a square. However, the shape of the light emitting element LE is not limited thereto. For example, the light emitting element LE may include a side surface that is inclined at an angle within a selectable range relative to the substrate SUB. For example, the light emitting element LE may have a cross-sectional shape such as a trapezoid or an inverted trapezoid. According to embodiments, the light emitting element LE may have various planar shapes. For example, when viewed on a plane defined by the first direction DR1 and the second direction DR2, the light emitting element LE may have a rectangular shape, a square shape, a hexagonal shape, a circular shape, an elliptical shape, or other planar shapes.

[0070] In one embodiment, the light-emitting element LE may be an inorganic light-emitting element made of an inorganic material. For example, the light-emitting element LE may be an inorganic light-emitting diode made of a nitride-based semiconductor material (e.g., GaN, AlGaN, GaAlN, InGaN, InAlGaN, AlN, InN, or another nitride-based semiconductor material) or another inorganic material. The light-emitting element LE may emit light of a given color. As an example, the light-emitting element LE may emit red light, green light, blue light, or light of another color.

[0071] In one embodiment, the light-emitting element LE may be a micro light-emitting diode (microLED) having a small size in the micrometer (μm) range. For example, the light-emitting element LE may be a microLED having a length (e.g., horizontal length) of several micrometers to several hundred micrometers in a first direction DR1, a length (e.g., vertical length) of several micrometers to several hundred micrometers in a second direction DR2, and a length (e.g., thickness or height) of several micrometers to several hundred micrometers in a third direction DR3. Each of the lengths of the light-emitting element LE in the first direction DR1, the second direction DR2, and the third direction DR3 may be 100 μm or less, but is not limited thereto.

[0072] The light emitting element LE may include a first semiconductor layer SEM1, a stress relief layer SRL, a light emitting layer EML, and a second semiconductor layer SEM2 sequentially disposed on a substrate SUB. In one embodiment, the light emitting element LE may further include a passivation layer surrounding the outer peripheral surfaces (e.g., side surfaces) of the first semiconductor layer SEM1, the stress relief layer SRL, the light emitting layer EML, and the second semiconductor layer SEM2.

[0073] The first semiconductor layer SEM1 may be disposed on the substrate SUB. The first semiconductor layer SEM1 may be a semiconductor layer doped to have a first conductivity type. For example, the first semiconductor layer SEM1 may include a semiconductor material including a first conductivity type dopant.

[0074] In one embodiment, the first semiconductor layer SEM1 may include a nitride-based semiconductor material and a first conductive type dopant doped into the nitride-based semiconductor material. For example, the first semiconductor layer SEM1 may be an n-type semiconductor layer (e.g., n-GaN) doped with an n-type dopant such as Si, Ge, Se, and Sn, but is not limited thereto.

[0075] The stress release layer SRL may be disposed on the first semiconductor layer SEM1 . For example, the stress release layer SRL may be disposed between the first semiconductor layer SEM1 and the light emitting layer EML.

[0076] In an embodiment, the stress relief layer SRL may include indium (In) and may be doped. In one embodiment, the stress relief layer SRL may be doped to have a first conductivity type. For example, the stress relief layer SRL may include a nitride-based semiconductor material (e.g., InGaN or InAlGaN) containing indium and a first conductivity type dopant doped into the nitride-based semiconductor material. In one embodiment, the stress relief layer SRL may include an n-type semiconductor layer (e.g., n-InGaN or n-InAlGaN) including a nitride-based semiconductor material containing indium and doped with an n-type dopant such as Si, Ge, Se, and Sn, but is not limited thereto.

[0077] The stress relief layer SRL may be a single layer or multiple layers. As an example, the stress relief layer SRL may include at least one indium-containing layer comprising a nitride-based semiconductor material containing indium. The stress relief layer SRL may include at least one intermediate layer that does not contain (e.g., substantially does not contain) indium, or may not include an intermediate layer.

[0078] In one embodiment, the indium composition of the stress release layer SRL (or the indium-containing layer included in the stress release layer SRL) may be less than or equal to that of the quantum well layer (eg, Figure 5 In one embodiment, the indium composition of the stress relief layer SRL may be in the range of 30% to 100% of the indium composition of the quantum well layer.

[0079] In some embodiments, the indium composition of the stress release layer SRL (or the indium-containing layer included in the stress release layer SRL) may be as shown in the following Table 1. In Table 1, the wavelengths of the light emitting layer EML and the stress release layer SRL are wavelengths (eg, emission wavelengths) calculated based on the indium composition.

[0080]

Table 1

[0081]

[0082] Referring to Table 1, as in Embodiment 1, when the indium composition of the light-emitting layer EML (e.g., the indium composition of the quantum well layer constituting the light-emitting layer EML) is approximately 20%, the indium composition of the stress relief layer SRL (e.g., the indium composition of the indium-containing layer constituting the stress relief layer SRL) may be 7% or more (e.g., within a range of 7% to 20%). As in Embodiments 2, 3, and 4, when the indium composition of the light-emitting layer EML is approximately 25%, approximately 30%, and approximately 35%, respectively, the indium composition of the stress relief layer SRL may be 8.75% or more (e.g., within a range of 8.75% to 25%), 10.5% or more (e.g., within a range of 10.5% to 30%), and 12.25% or more (e.g., within a range of 12.25% to 35%), respectively. The indium compositions of the light-emitting layer EML and the stress relief layer SRL are not limited to the embodiments disclosed in Table 1 and may vary depending on the embodiment.

[0083] The stress relief layer SRL can mitigate lattice mismatch through lattice matching. For example, by providing a stress relief layer SRL with a medium-sized lattice constant between the first semiconductor layer SEM1 and the light-emitting layer EML, stress (e.g., plane strain) caused by the lattice constant difference between the first semiconductor layer SEM1 and the light-emitting layer EML can be mitigated. In an embodiment, by forming the stress relief layer SRL (or an indium-containing layer included in the stress relief layer SRL) to have an indium composition in the range of 30% to 100% of the indium composition of the quantum well layer, the lattice mismatch between the first semiconductor layer SEM1 and the light-emitting layer EML can be more effectively mitigated and / or buffered. Therefore, in the step of forming the light-emitting layer EML on the stress relief layer SRL, indium can be smoothly injected into the light-emitting layer EML according to the target indium composition, and a high-quality light-emitting layer EML with reduced defects can be formed.

[0084] When the stress release layer SRL is doped (eg, doped to have the first conductivity type), light emission from the stress release layer SRL may be prevented or reduced. In one embodiment, the doping concentration of the stress release layer SRL (or the indium-containing layer included in the stress release layer SRL) may be 10 16 / cm 3or higher. Thus, the stress release layer SRL can be effectively prevented from inadvertently emitting light. For example, although the stress release layer SRL may contain indium in an amount of 30% or more of the indium component of the quantum well layer, the first conductive type dopant doped into the stress release layer SRL may cause non-radiative recombination of carriers (e.g., electrons or holes), so that the generation of light of a wavelength different from that of the light-emitting layer EML in the stress release layer SRL can be prevented or reduced. The stress release layer SRL can be appropriately doped so that the stress release layer SRL can be appropriately prevented from emitting light despite a high current flowing through the light-emitting element LE. Thus, color mixing can be prevented and the color purity of the light-emitting element LE can be improved.

[0085] In one embodiment, the doping concentration of the stress release layer SRL (or the indium-containing layer included in the stress release layer SRL) may be less than or equal to the doping concentration of the first semiconductor layer SEM1. Therefore, although the stress release layer SRL is formed at a growth temperature lower than or equal to the growth temperature of the first semiconductor layer SEM1, a high-quality stress release layer SRL with reduced defects may be formed, and defects that may occur at the interface between the stress release layer SRL and the first semiconductor layer SEM1 may be reduced.

[0086] The stress relief layer SRL may be formed to have an appropriate thickness taking into account at least one of a lattice matching effect, manufacturing efficiency of the light-emitting element LE, and luminous efficiency of the light-emitting element LE. For example, the stress relief layer SRL (or the indium-containing layer included in the stress relief layer SRL) may be formed to have a thickness of 2 nm or greater to obtain a desired lattice matching effect. Although the stress relief layer SRL is formed to have a thickness of 2 nm or greater, light emission from the stress relief layer SRL may be suppressed by doping.

[0087] In one embodiment, the thickness of the stress release layer SRL may be less than or equal to the thickness of the light emitting layer EML. For example, the thickness of the stress release layer SRL or each indium-containing layer constituting the stress release layer SRL may be in the range of 2 nm to 5 nm, but is not limited thereto.

[0088] The light-emitting layer (EML) may be disposed on the stress-releasing layer (SRL). For example, the light-emitting layer (EML) may be disposed between the stress-releasing layer (SRL) and the second semiconductor layer (SEM2). Within the spirit and scope of the present disclosure, the light-emitting layer (EML) may emit light by recombination of electron-hole pairs generated in response to an electrical signal applied through the first semiconductor layer (SEM1), the second semiconductor layer (SEM2), and the like.

[0089] The light-emitting layer EML may include a nitride-based semiconductor material or another semiconductor material and may have a single or multiple quantum well structures. For example, the light-emitting layer EML may include at least one quantum well layer including a nitride-based semiconductor material containing indium. In an embodiment, the quantum well layer may include a nitride-based semiconductor material containing indium with a composition greater than or equal to the indium composition of the stress relief layer SRL (or the indium-containing layer of the stress relief layer SRL). In one embodiment, the light-emitting layer EML may have a multi-quantum well structure including a quantum well layer including InGaN and a barrier layer including GaN, AlGaN, or GaAlN, but is not limited thereto.

[0090] In one embodiment, the light-emitting layer EML may emit light in a visible light wavelength band, for example, light in a wavelength band within a range of 400 nm to 900 nm. For example, the light-emitting layer EML may emit blue light with a peak wavelength within a range of 440 nm to 480 nm, green light with a peak wavelength within a range of 510 nm to 550 nm, or red light with a peak wavelength within a range of 610 nm to 750 nm (e.g., within a range of 610 nm to 650 nm). The light-emitting layer EML may emit light in a color different from the colors described above or in a wavelength band different from the wavelength band described above.

[0091] In one embodiment, the color of light emitted from the light-emitting layer (EML) can be adjusted or changed by adjusting the composition (or content) of indium included in the light-emitting layer (EML). For example, by controlling the composition (or content) of indium included in the light-emitting layer (EML) within a range of 20% to 30%, the emission wavelength of the light-emitting layer (EML) can be controlled so that the light-emitting layer (EML) emits green light. For example, by controlling the composition (or content) of indium included in the light-emitting layer (EML) within a range of 30% to 40%, the emission wavelength of the light-emitting layer (EML) can be controlled so that the light-emitting layer (EML) emits red light.

[0092] In one embodiment, the indium content of the light-emitting layer (EML) (e.g., the indium content of the quantum well layer) may be 25% or more, and the emission wavelength (e.g., the peak emission wavelength) of the light-emitting layer (EML) may be in the range of 500 nm to 750 nm. For example, the light-emitting layer (EML) may emit light having a long wavelength (e.g., green light or red light) equal to or longer than a green wavelength band.

[0093] In one embodiment, the indium content of the light-emitting layer (EML) (or the quantum well layer included in the light-emitting layer (EML)) may be higher than the indium content of the stress relief layer (SRL) (or the indium-containing layer included in the stress relief layer (SRL)). Therefore, the indium fluctuation in the light-emitting layer (EML) may be higher than the indium fluctuation in the stress relief layer (SRL). For example, the indium fluctuation in the light-emitting layer (EML) may be at least 10% higher than the indium fluctuation in the stress relief layer (SRL).

[0094] The second semiconductor layer SEM2 may be disposed on the light emitting layer EML. The second semiconductor layer SEM2 may be a semiconductor layer doped to have a second conductivity type. For example, the second semiconductor layer SEM2 may include a semiconductor material containing a second conductivity type dopant.

[0095] In one embodiment, the second semiconductor layer SEM2 may include a nitride-based semiconductor material and a second conductive type dopant doped into the nitride-based semiconductor material. For example, the second semiconductor layer SEM2 may be a p-type semiconductor layer (e.g., p-GaN) doped with a p-type dopant such as Mg, Zn, Ca, and Ba, but is not limited thereto.

[0096] Figure 2 is a schematic cross-sectional view showing a light emitting element LE according to one embodiment. Figure 3 is a schematic cross-sectional view showing a light emitting element LE according to one embodiment. Figure 4 : is a schematic cross-sectional view showing a light emitting element LE according to one embodiment. For example, Figures 2 to 4 Show the basis Figure 1 The light emitting elements LE of the different modified embodiments of the embodiment are shown in FIG.

[0097] refer to Figure 1 and Figure 2 The light emitting element LE may further include a superlattice layer SLT disposed between the first semiconductor layer SEM1 and the stress release layer SRL. In one embodiment, the light emitting element LE may further include a spacer layer SPL disposed between the superlattice layer SLT and the stress release layer SRL.

[0098] The superlattice layer SLT may include indium. For example, the superlattice layer SLT may include a nitride-based semiconductor material including indium.

[0099] In an embodiment, the indium composition of the superlattice layer SLT may be lower than the indium composition of the stress relief layer SRL. For example, the indium composition of the superlattice layer SLT may be less than 30% of the indium composition of the quantum well layer included in the light emitting layer EML. For example, the indium composition of the superlattice layer SLT may be 5% or less (e.g., in the range of 2% to 5%), but is not limited thereto.

[0100] By providing a superlattice layer SLT of intermediate lattice size between the first semiconductor layer SEM1 and the stress relief layer SRL, semiconductor layers containing indium (e.g., the superlattice layer SLT, the stress relief layer SRL, and the light-emitting layer EML) can be smoothly grown on the first semiconductor layer SEM1, and defects that may be generated on the surface of the first semiconductor layer SEM1 (e.g., the interface between the first semiconductor layer SEM1 and the superlattice layer SLT) can be reduced. Therefore, a high-quality and / or high-efficiency light-emitting element LE can be manufactured.

[0101] In one embodiment, the superlattice layer SLT can be formed to a thickness less than or equal to that of the first semiconductor layer SEM1. The superlattice layer SLT can be formed as a multilayer structure including first layers containing low-concentration indium and second layers disposed between the first layers, with each first layer having a limited thickness. As an example, each of the first layers of the superlattice layer SLT can be formed to a thickness of 2 nm or less. Thus, the superlattice layer SLT can be smoothly grown on the first semiconductor layer SEM1, while maintaining the electrical conductivity of the superlattice layer SLT.

[0102] The superlattice layer SLT may be doped or undoped. In one embodiment, the superlattice layer SLT may be doped to have a first conductivity type, and thus the conductivity of the superlattice layer SLT may be improved. In one embodiment, the doping concentration of the superlattice layer SLT may be less than or equal to the doping concentration of the first semiconductor layer SEM1. For example, the doping concentration of the first semiconductor layer SEM1 may be 3×0 18 / cm 3 or higher, and the doping concentration of the superlattice layer SLT can be lower than 3×10 18 / cm 3 Therefore, although the superlattice layer SLT is formed at a growth temperature lower than or equal to the growth temperature of the first semiconductor layer SEM1, a high-quality superlattice layer SLT with reduced defects can be formed, and defects that may occur at the interface between the superlattice layer SLT and the first semiconductor layer SEM1 can be reduced.

[0103] The spacer layer SPL may be disposed between the superlattice layer SLT and the stress release layer SRL. In one embodiment, the spacer layer SPL may be formed of a semiconductor layer that does not contain indium. For example, the spacer layer SPL may include a nitride-based semiconductor material (e.g., GaN) that does not contain indium. In one embodiment, the thickness of the spacer layer SPL may be 20 nm or greater. When the spacer layer SPL is disposed between the superlattice layer SLT and the stress release layer SRL, a space corresponding to the spacer layer SPL may be ensured between the superlattice layer SLT and the stress release layer SRL, and the lattice may be smoothly and / or appropriately adjusted. The spacer layer SPL may be doped or undoped. The spacer layer SPL may be omitted.

[0104] refer to Figures 1 to 3 The light-emitting element LE may further include at least one contact electrode CTE. As an example, the light-emitting element LE may further include a contact electrode CTE disposed on the second semiconductor layer SEM2. Within the spirit and scope of the present disclosure, the contact electrode CTE may be provided to the light-emitting element LE to protect the second semiconductor layer SEM2 and smoothly connect the second semiconductor layer SEM2 to at least one electrode, circuit element, line, or the like.

[0105] In one embodiment, to manufacture a light-emitting element LE including a contact electrode CTE, the contact electrode CTE may be further formed after forming the second semiconductor layer SEM2 on the substrate SUB. In one embodiment, the contact electrode CTE may be completely disposed on the second semiconductor layer SEM2. As an example, the contact electrode CTE may have a size corresponding to the second semiconductor layer SEM2 and may completely cover the upper surface of the second semiconductor layer SEM2. Thus, the second semiconductor layer SEM2 may be properly or stably protected. However, embodiments are not limited thereto. For example, the contact electrode CTE may be formed to cover only a portion of the second semiconductor layer SEM2 while exposing another portion of the second semiconductor layer SEM2.

[0106] The contact electrode CTE may include a metal, a metal oxide, or other conductive material. As an example, the contact electrode CTE may be made of a metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), or copper (Cu), an oxide or alloy thereof, or a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), or indium oxide (In2O3), or by mixing them, but is not limited thereto.

[0107] In one embodiment, the light emitting element LE including the contact electrode CTE may include a superlattice layer SLT and a spacer layer SPL. However, the embodiment is not limited thereto. For example, the light emitting element LE including the contact electrode CTE may not include at least one of the superlattice layer SLT and the spacer layer SPL.

[0108] refer to Figures 1 to 4 The light-emitting element LE may further include a first electrode ET1 disposed on the contact electrode CTE (or the second semiconductor layer SEM2) and a second electrode ET2 disposed on the first semiconductor layer SEM1. In one embodiment, the other upper semiconductor layer and / or the contact electrode CTE may be disposed only on a portion of the first semiconductor layer SEM1, and the other portion of the first semiconductor layer SEM1 may be exposed. The second electrode ET2 may be disposed on another portion of the first semiconductor layer SEM1. In one embodiment, the light-emitting element LE may include only one of the first electrode ET1 and the second electrode ET2, and may not include the other electrode.

[0109] Within the spirit and scope of the present disclosure, the first electrode ET1 may be a connection electrode (e.g., a bonding electrode) that smoothly connects the contact electrode CTE (or the second semiconductor layer SEM2) to another circuit element, electrode, line, or the like. In one embodiment, the first electrode ET1 may have a size smaller than the contact electrode CTE, but is not limited thereto. In one embodiment, the first electrode ET1 may be connected to a first pixel electrode provided in each pixel of a display device. In one embodiment, the first electrode ET1 may have a size corresponding to the first pixel electrode, but is not limited thereto.

[0110] Within the spirit and scope of the present disclosure, the second electrode ET2 may be a connection electrode (e.g., a bonding electrode) that smoothly connects the first semiconductor layer SEM1 to another circuit element, electrode, line, or the like. In one embodiment, the second electrode ET2 may have a size smaller than the exposed portion of the first semiconductor layer SEM1, but is not limited thereto. In one embodiment, the second electrode ET2 may be connected to a second pixel electrode provided in each pixel of the display device. In one embodiment, the second electrode ET2 may have a size corresponding to the second pixel electrode, but is not limited thereto.

[0111] The first electrode ET1 and the second electrode ET2 may include a metal, a metal oxide, or other conductive materials. For example, the first electrode ET1 and the second electrode ET2 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), but are not limited thereto.

[0112] In one embodiment, the light emitting element LE including at least one of the first electrode ET1 and the second electrode ET2 may include a superlattice layer SLT, a spacer layer SPL, and a contact electrode CTE. However, embodiments are not limited thereto. For example, the light emitting element LE including at least one of the first electrode ET1 and the second electrode ET2 may not include at least one of the superlattice layer SLT, the spacer layer SPL, and the contact electrode CTE.

[0113] Figure 5 : is a schematic cross-sectional view showing a light emitting layer EML according to one embodiment. For example, Figure 5 Show Figures 1 to 4 One embodiment of the light emitting layer EML is shown in FIG.

[0114] refer to Figures 1 to 5 The light-emitting layer (EML) may have a multi-quantum well structure including quantum well layers (QWL) and barrier layers (BRL). For example, the light-emitting layer (EML) may include quantum well layers (QWL) and barrier layers (BRL) alternately arranged along the third direction (DR3) on the stress relief layer (SRL). In one embodiment, each barrier layer (BRL) may be provided as the bottommost and topmost layers of the light-emitting layer (EML).

[0115] However, embodiments are not limited thereto. For example, the light emitting layer EML may have a single quantum well structure including a single quantum well layer QWL.

[0116] The quantum well layer QWL may include a nitride-based semiconductor material including indium. As an example, the quantum well layer QWL may include InGaN, but is not limited thereto.

[0117] In an embodiment, the indium composition of the quantum well layer QWL may be greater than or equal to the indium composition of the stress relief layer SRL. In one embodiment, the indium composition of the quantum well layer QWL may be approximately 25%, and the light generated from the quantum well layer QWL may be long-wavelength light equal to or longer than the green wavelength band. The indium composition of the quantum well layer QWL and the emission wavelength may vary depending on the embodiment.

[0118] The barrier layer BRL may not contain indium. In one embodiment, the barrier layer BRL may include a nitride-based semiconductor material that does not contain indium. As an example, the barrier layer BRL may include GaN, but is not limited thereto.

[0119] Figure 6 : is a schematic cross-sectional view showing a stress release layer SRL according to one embodiment. For example, Figure 6 Show Figures 1 to 4 One embodiment of a stress relief layer SRL is shown in FIG.

[0120] refer to Figures 1 to 6The stress relief layer SRL may be formed as a single layer containing indium. As an example, the stress relief layer SRL may be formed as a single indium-containing layer containing indium with a uniform composition and / or concentration throughout, and may be doped.

[0121] In one embodiment, the stress relief layer SRL may include InGaN or InAlGaN and may be doped to have the first conductivity type. For example, the stress relief layer SRL may include a dopant of the first conductivity type. The doping concentration of the stress relief layer SRL may be uniform throughout, or may gradually change (e.g., gradually decrease) along the third direction DR3.

[0122] In one embodiment, the indium composition of the stress release layer SRL may be in the range of 30% to 100% of the indium composition of the quantum well layer QWL. In one embodiment, the doping concentration of the stress release layer SRL may be 10 16 / cm 3 or higher, and may be lower than the doping concentration of the first semiconductor layer SEM1. In one embodiment, the thickness of the stress relaxation layer SRL may be 2 nm or more, and may be several micrometers (eg, 3 μm) or less.

[0123] In one embodiment, the stress relief layer (SRL) may be in direct contact with the light-emitting layer (EML). For example, the stress relief layer (SRL) may be in contact with the barrier layer (BRL) positioned at the lowest portion of the light-emitting layer (EML), and may be positioned very close to the quantum well layer (QWL) on the barrier layer (BRL). This improves or ensures lattice matching of the stress relief layer (SRL), and when forming the light-emitting layer (EML), indium can be more smoothly injected into the quantum well layer (QWL).

[0124] Figure 7 : is a schematic cross-sectional view showing a superlattice layer SLT according to one embodiment. For example, Figure 7 Show Figures 2 to 4 One embodiment of a superlattice layer SLT is shown in FIG.

[0125] refer to Figures 2 to 7 The superlattice layer SLT may be formed as a multilayer structure including at least one pair of first layers SLT1 and second layers SLT2 sequentially or alternately disposed along the third direction DR3 on the first semiconductor layer SEM1. As an example, the superlattice layer SLT may include a multilayer structure including first layers SLT1 and second layers SLT2 alternately disposed along the third direction DR3 on the first semiconductor layer SEM1.

[0126] The first layer SLT1 may include indium. For example, the first layer SLT1 may include a nitride-based semiconductor material including indium. In one embodiment, the indium content of the first layer SLT1 may be lower than the indium content of the stress relief layer SRL. For example, the indium content of the first layer SLT1 may be less than approximately 30% of the indium content of the quantum well layer QWL. Therefore, the superlattice layer SLT including the first layer SLT1 may be smoothly or properly formed on the first semiconductor layer SEM1.

[0127] In one embodiment, the first layer SLT1 may have a thickness limited to 5 nm or less. For example, the thickness of the first layer SLT1 may be 2 nm or less and may be less than the thickness of the stress relief layer SRL (or the indium-containing layer included in the stress relief layer SRL). Therefore, the first layer SLT1 may be smoothly or properly formed, and the conductivity of the first layer SLT1 and the superlattice layer SLT including the first layer SLT1 may be improved or ensured.

[0128] In one embodiment, the first layer SLT1 may be doped. As an example, the first layer SLT1 may be doped to have a first conductivity type and may therefore include a dopant of the first conductivity type. In one embodiment, the doping concentration of the first layer SLT1 may be less than or equal to the doping concentration of the first semiconductor layer SEM1. Therefore, while improving the conductivity of the first layer SLT1 and the superlattice layer SLT including the first layer SLT1, defects in the superlattice layer SLT and the light-emitting element LE including the superlattice layer SLT may be reduced.

[0129] The second layer SLT2 may not include indium. For example, the second layer SLT2 may include a nitride-based semiconductor material that does not include indium.

[0130] In one embodiment, the second layer SLT2 may have a low thickness of 5 nm or less. For example, the thickness of the second layer SLT2 may be 2 nm or less and may be less than the thickness of the stress relief layer SRL (or the indium-containing layer included in the stress relief layer SRL). In one embodiment, the thickness of the first layer SLT1 and the second layer SLT2 may be substantially the same. Therefore, the low thickness of the first layer SLT1 and the second layer SLT2 may improve or ensure the conductivity of the superlattice layer SLT.

[0131] The second layer SLT2 may be doped or undoped. As an example, the second layer SLT2 may be doped to have the first conductivity type or may be undoped. In one embodiment in which the second layer SLT2 is doped, the doping concentration of the second layer SLT2 may be less than or equal to the doping concentration of the first semiconductor layer SEM1. Therefore, while improving the conductivity of the second layer SLT2 and the superlattice layer SLT including the second layer SLT2, defects in the superlattice layer SLT and the light-emitting element LE including the superlattice layer SLT may be reduced.

[0132] Figure 8 is a schematic cross-sectional view illustrating a stress relaxation layer SRL according to one embodiment. Figure 9 is a schematic cross-sectional view illustrating a stress relaxation layer SRL according to one embodiment. Figure 10 : is a schematic cross-sectional view showing a stress release layer SRL according to one embodiment. For example, Figures 8 to 10 Show Figures 1 to 4 Different embodiments of the stress relief layer SRL are shown in FIG.

[0133] refer to Figures 1 to 8 , the stress relief layer SRL may be formed as a single layer containing indium and may be doped. As an example, the stress relief layer SRL may be formed as a single indium-containing layer and may be doped to have the first conductivity type.

[0134] In one embodiment, the indium composition of the stress release layer SRL may gradually change from a lower portion adjacent to the separator layer SPL to an upper portion adjacent to the light-emitting layer EML. For example, the indium composition of the stress release layer SRL may gradually increase from a lower portion to an upper portion along the third direction DR3. For example, the stress release layer SRL may be formed (e.g., grown) while gradually increasing the indium composition to optimize lattice matching. However, embodiments are not limited thereto. For example, the indium composition of the stress release layer SRL may gradually increase from a lower portion to an upper portion and decrease again at the topmost layer in order to optimize lattice matching. For example, in order to optimize lattice matching, the stress release layer SRL may be grown by gradually increasing the indium composition, and when the growth of the stress release layer SRL is about to be completed, the indium composition may be appropriately adjusted to match the target lattice size.

[0135] The doping concentration of the stress release layer SRL may be uniform or non-uniform. For example, the doping concentration of the stress release layer SRL may be uniform throughout, or may gradually change from a lower portion to an upper portion along the third direction DR3.

[0136] In one embodiment, the doping concentration of the stress release layer SRL may gradually decrease from the lower portion to the upper portion, thereby preventing or reducing diffusion of dopants of the stress release layer SRL into the light emitting layer EML.

[0137] Apart from Figures 1 to 8 In addition, refer to Figure 9 and Figure 10 The stress relief layer SRL may be formed as a multilayer including at least one pair of indium-containing layers SRL1 and intermediate layers SRL2 sequentially or alternately disposed along the third direction DR3 on the superlattice layer SLT and / or the spacer layer SPL (or the first semiconductor layer SEM1). As an example, the stress relief layer SRL may have a multilayer structure including the indium-containing layers SRL1 and intermediate layers SRL2 alternately disposed along the third direction DR3 on the spacer layer SPL.

[0138] The indium-containing layer SRL1 may include indium. For example, the indium-containing layer SRL1 may include a nitride-based semiconductor material including indium. As an example, the indium-containing layer SRL1 may include InGaN or InAlGaN, and may be doped to have a first conductivity type.

[0139] In one embodiment, the indium content of the indium containing layer SRL1 may be in the range of 30% to 100% of the indium content of the quantum well layer QWL. In one embodiment, the doping concentration of the indium containing layer SRL1 may be 10 16 / cm 3 or higher, and may be lower than the doping concentration of the first semiconductor layer SEM1. In one embodiment, the thickness of the indium-containing layer SRL1 may be 2 nm or more, and may be several micrometers (e.g., 3 μm) or less. In one embodiment, the indium-containing layer SRL1 provided as the uppermost layer of the stress release layer SRL may be in direct contact with the light-emitting layer EML. In one embodiment, the indium-containing layer SRL1 provided as the lowermost layer of the stress release layer SRL may be in direct contact with the spacer layer SPL, or may be provided close to the spacer layer SPL with an intermediate layer SRL2 therebetween.

[0140] The indium content of the indium-containing layer SRL1 may be uniform or non-uniform. Figure 9 As in the embodiment of the present invention, the indium composition of the indium-containing layer SRL1 can be substantially the same. Figure 10 As in the embodiment of the present invention, the indium composition of the indium containing layer SRL1 may gradually change from the lower portion of the indium containing layer SRL1 adjacent to the separator layer SPL to the upper portion of the indium containing layer SRL1 adjacent to the light emitting layer EML. For example, the indium composition of the indium containing layer SRL1 may gradually increase or gradually increase and decrease along the third direction DR3.

[0141] In one embodiment, the indium-containing layer SRL1 may be doped. As an example, the indium-containing layer SRL1 may be doped to have the first conductivity type. The doping concentration of the indium-containing layer SRL1 may be uniform or non-uniform. For example, the doping concentration of the indium-containing layer SRL1 may be substantially uniform or may gradually change (e.g., gradually decrease) along the third direction DR3.

[0142] Intermediate layers SRL2 may be disposed between indium-containing layers SRL1. Each of the intermediate layers SRL2 may not contain indium. For example, the intermediate layers SRL2 may include a nitride-based semiconductor material that does not contain indium. As an example, the intermediate layers SRL2 may include GaN. The intermediate layers SRL2 may be doped or undoped.

[0143] By sequentially forming (e.g., growing) the indium-containing layer SRL1 with the intermediate layer SRL2 formed therebetween, the indium-containing layer SRL1 can be formed more smoothly and / or appropriately.

[0144] In one embodiment, the doping concentration of the indium containing layer SRL1 and / or the intermediate layer SRL2 may be uniform or non-uniform. For example, the doping concentration of the indium containing layer SRL1 and / or the intermediate layer SRL2 may be uniform throughout, or may gradually change from the lower portion to the upper portion along the third direction DR3.

[0145] In one embodiment, the doping concentration of the indium containing layer SRL1 and / or the intermediate layer SRL2 may gradually decrease from the lower portion to the upper portion, thereby preventing or reducing diffusion of dopants from the indium containing layer SRL1 and / or the intermediate layer SRL2 into the light emitting layer EML.

[0146] Figure 11 is a schematic perspective view showing a display device 10 according to one embodiment. Figure 12 It shows Figure 11 Schematic plan view of an example of area A1.

[0147] refer to Figure 11 and Figure 12 , a display device 10 according to one embodiment may include a display panel 100 including a display area DA and a non-display area NDA.

[0148] The display panel 100 may have a quadrilateral planar shape having long sides in the first direction DR1 and short sides in the second direction DR2. Figure 11 and Figure 12, the first direction DR1 may refer to the horizontal direction (or vertical direction) of the display panel 100, and the second direction DR2 may refer to the vertical direction (or horizontal direction) of the display panel 100. The third direction DR3 may refer to the thickness direction or height direction of the display panel 100. However, the planar shape of the display panel 100 is not limited thereto, and the display panel 100 may have a different shape. For example, the display panel 100 may have a polygonal shape other than a quadrilateral shape, a circular shape, an elliptical shape, or an irregular planar shape.

[0149] The display area DA may be a region in which an image is displayed, and the non-display area NDA may be a region in which an image is not displayed. In one embodiment, a planar shape of the display area DA may follow a planar shape of the display panel 100 . Figure 11 An embodiment in which the display area DA has a quadrilateral shape in a plan view is shown. The display area DA may be provided in the central area of the display panel 100. The non-display area NDA may be provided around the display area DA. For example, the non-display area NDA may surround the display area DA.

[0150] The display panel 100 may include pixels PX arranged or disposed in the display area DA. For example, the display panel 100 may include a first pixel PX1 (e.g., a first color subpixel) that emits light of a first color, a second pixel PX2 (e.g., a second color subpixel) that emits light of a second color, and a third pixel PX3 (e.g., a third color subpixel) that emits light of a third color. In one embodiment, the first color may be red, the second color may be green, and the third color may be blue, but they are not limited thereto. At least one first pixel PX1, at least one second pixel PX2, and at least one third pixel PX3 adjacent to each other may constitute each unit pixel UPX capable of emitting light of various colors. As an example, a first pixel PX1, a second pixel PX2, and a third pixel PX3 arranged sequentially along the first direction DR1 in the Kth row (K is a natural number greater than 0) of the display area DA may constitute a unit pixel UPX. The number, type, and / or arrangement structure of the pixels PX constituting the unit pixel UPX may vary depending on the embodiment.

[0151] Each pixel PX may include at least one light-emitting element LE. In one embodiment, the pixel PX may include respective light-emitting elements LE that emit light of different colors. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include light-emitting elements LE that emit light of a first color, light of a second color, and light of a third color, respectively. However, embodiments are not limited thereto. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include light-emitting elements LE that emit light of the same color, and a light conversion pattern (e.g., a wavelength conversion pattern including quantum dots) and / or a color filter for converting or controlling the color of light emitted from the light-emitting element LE provided in each of the pixels PX may be provided in the emission region of the first pixel PX1, the second pixel PX2, and / or the third pixel PX3.

[0152] In one embodiment, at least one pixel PX may include a light emitting element LE according to at least one of the above embodiments. For example, each of the first pixels PX1 may include a light emitting element LE including: Figures 1 to 10 The light emitting element LE (eg, Figure 13 The first light emitting element LE1).

[0153] The pixels PX may include light emitting elements LE of substantially the same size or may include light emitting elements LE of different sizes. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include light emitting elements LE of substantially the same size or may include light emitting elements LE of different sizes.

[0154] The pixels PX may include light-emitting elements LE having substantially the same structure, or may include light-emitting elements LE having different structures. For example, each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a light-emitting element LE including a stress release layer SRL. For example, some of the first pixel PX1, the second pixel PX2, and the third pixel PX3 (e.g., the first pixel PX1) may include a corresponding light-emitting element LE including the stress release layer SRL according to the embodiment described above, and the other ones of the first pixel PX1, the second pixel PX2, and the third pixel PX3 (e.g., the second pixel PX2 and / or the third pixel PX3) may include a corresponding light-emitting element LE not including the stress release layer SRL.

[0155] In one embodiment, the pixels PX may be arranged or disposed in the display area DA in a matrix form, a stripe form, or any other form. The sizes of the pixels PX (or the emission areas of the pixels PX) may be substantially the same as or different from each other. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may have substantially the same size (e.g., the same area) or may have different sizes. The arrangement type, position, or size of the pixels PX may vary depending on the embodiment.

[0156] In one embodiment, the pixel PX may have a quadrilateral planar shape such as a rectangular shape or a diamond shape, but the embodiment is not limited thereto. For example, the pixel PX may have a quadrilateral shape or other polygonal shape (e.g., a diamond shape or a hexagonal shape), a circular shape, an elliptical shape, or other planar shapes.

[0157] The non-display area NDA may include a first common voltage supply area CVA1 , a second common voltage supply area CVA2 , a first pad area PDA1 , a second pad area PDA2 , and a peripheral area PHA.

[0158] The first common voltage supply area CVA1 may be disposed between the first pad area PDA1 and the display area DA. The second common voltage supply area CVA2 may be disposed between the second pad area PDA2 and the display area DA. Each of the first common voltage supply area CVA1 and the second common voltage supply area CVA2 may include a common electrode connection portion CVS electrically connected to a second pixel electrode (e.g., a common electrode) of each pixel PX. A second pixel voltage (e.g., a low-potential pixel voltage or a common voltage) may be supplied to the pixel PX through the common electrode connection portion CVS.

[0159] The common electrode connection portion CVS may be disposed in the common voltage supply area (eg, the first common voltage supply area CVA1 and / or the second common voltage supply area CVA2) of the non-display area NDA and may include a conductive material (eg, a metal material such as aluminum (Al)). Figure 11 and Figure 12 The display device 10 is shown in which the common electrode connection portion CVS is positioned in the non-display area NDA, but embodiments are not limited thereto. For example, the common electrode connection portion CVS may be positioned in the display area DA.

[0160] The common electrode connection portion CVS of the first common voltage supply area CVA1 may be electrically connected to any one of the first pads PD1 of the first pad area PDA1. For example, the common electrode connection portion CVS of the first common voltage supply area CVA1 may receive the second pixel voltage (e.g., the common voltage) from any one of the first pads PD1 of the first pad area PDA1.

[0161] The first pad PD1 may be provided in the first pad area PDA1. The first pad PD1 may be connected to a circuit board (not shown) through a conductive connection member. For example, the first pad PD1 may be electrically connected to a circuit pad provided on the circuit board through a wire.

[0162] The common electrode connection portion CVS of the second common voltage supply area CVA2 may be electrically connected to any one of the second pads of the second pad area PDA2. For example, the common electrode connection portion CVS of the second common voltage supply area CVA2 may receive the second pixel voltage from any one of the second pads of the second pad area PDA2. In one embodiment, the display panel 100 may not include the second common voltage supply area CVA2.

[0163] The first pad area PDA1 may be provided at one side or a side (eg, an upper side) of the display panel 100. The first pad area PDA1 may include first pads PD1 to be connected to an external circuit board.

[0164] The second pad area PDA2 may be provided on one side or a side (eg, the lower side) of the display panel 100. The second pad area PDA2 may include a second pad to be connected to an external circuit board. In one embodiment, the display panel 100 may not include the second pad area PDA2.

[0165] The second pad may be disposed in the second pad area PDA2 of the non-display area NDA. The second pad may be connected to a circuit board (not shown) via a conductive connection member. For example, the second pad may be electrically connected to a circuit pad disposed on the circuit board via a wire.

[0166] The peripheral area PHA may be a remaining area of the non-display area NDA excluding the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. The peripheral area PHA may surround not only the display area DA but also the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2.

[0167] Figure 13is a schematic cross-sectional view showing a display panel 100 according to one embodiment. For example, Figure 13 The display panel 100 is shown Figure 12 1 , and illustrates schematic cross sections of a first pixel PX1 , a second pixel PX2 , and a third pixel PX3 adjacent to each other in a first direction DR1 .

[0168] Figure 13 The display device 10 is shown as an embodiment of a light-emitting diode on silicon (LEDoS), in which a light-emitting diode as a light-emitting element LE is provided on a semiconductor circuit substrate 110 formed by a semiconductor process using a silicon wafer. However, the device including the light-emitting element LE according to the embodiment is not limited thereto. For example, the light-emitting element LE manufactured according to the embodiment can be applied to display devices of different types and / or structures, or can be applied to devices of different types and / or structures such as lighting devices.

[0169] Apart from Figures 1 to 10 In addition, refer to Figures 11 to 13 The display panel 100 may include a semiconductor circuit substrate 110 and a light emitting element layer 120. In one embodiment, the display panel 100 may further include a connection electrode CNE disposed on the semiconductor circuit substrate 110 and connecting the pixel circuit PXC of the semiconductor circuit substrate 110 to the light emitting element LE of the light emitting element layer 120.

[0170] In one embodiment, the display panel 100 may further include additional configurations. As an example, the display panel 100 may further include at least one of a light conversion layer, a color filter layer, and an emission structure (e.g., a lens, etc.), wherein the light conversion layer is used to convert the color and / or wavelength of light emitted from at least some of the light-emitting elements LE, the color filter layer is used to perform control so that light of a given color is emitted from each of the emission regions, and the emission structure (e.g., a lens, etc.) is used to improve the light emission efficiency of the pixel PX. In one embodiment, the light conversion layer, the color filter layer, and / or the emission structure may be provided on the light-emitting element layer 120.

[0171] The semiconductor circuit substrate 110 may include a display area DA in which a pixel circuit PXC of a pixel PX is formed. The semiconductor circuit substrate 110 may also include Figure 11 and Figure 12 For example, the semiconductor circuit substrate 110 may further include a common electrode connection portion CVS, a first pad PD1, and / or a second pad positioned in the non-display area NDA.

[0172] The semiconductor circuit substrate 110 may include a base substrate SB and pixel circuits PXC disposed or formed on the base substrate SB. The semiconductor circuit substrate 110 may further include a first pixel electrode PXE1 connected to each of the pixel circuits PXC and a first insulating layer INS1 disposed around the first pixel electrode PXE1.

[0173] The semiconductor circuit substrate 110 may further include lines. For example, the semiconductor circuit substrate 110 may further include lines (eg, power lines and signal lines) connected to the pixels PX.

[0174] In one embodiment, the semiconductor circuit substrate 110 may be formed by a semiconductor process using a silicon wafer. For example, the base substrate SB may be a silicon wafer. In one embodiment, the base substrate SB may be made of single crystal silicon.

[0175] The pixel circuit PXC may be provided on the semiconductor circuit substrate 110 corresponding to each pixel region, wherein each of the pixels PX is provided in each pixel region. In one embodiment, each of the pixel circuits PXC may include a complementary metal oxide semiconductor (CMOS) circuit formed using a semiconductor process. In one embodiment, each of the pixel circuits PXC may include at least one transistor and at least one capacitor formed using a semiconductor process. As an example of an element provided on the semiconductor circuit substrate 110, Figure 13 Schematic positions of pixel circuits PXC provided in the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 are shown.

[0176] The first pixel electrodes PXE1 may be disposed on the pixel circuits PXC, respectively. The first pixel electrodes PXE1 may be connected to the pixel circuits PXC, respectively. For example, the pixel circuit PXC of each pixel PX may be electrically connected to the first pixel electrode PXE1 of the corresponding pixel PX. The first pixel electrodes PXE1 may receive a first pixel voltage or an anode voltage from the pixel circuits PXC, respectively.

[0177] In one embodiment, the first pixel electrode PXE1 may be integrated with the corresponding pixel circuit PXC. As an example, the first pixel electrode PXE1 may be an exposed electrode protruding from a top surface of the corresponding pixel circuit PXC.

[0178] The first pixel electrode PXE1 may include at least one conductive material. For example, the first pixel electrode PXE1 may include copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof. In one embodiment, the first pixel electrode PXE1 may have a multilayer structure with two or more layers.

[0179] The first insulating layer INS1 may surround the first pixel electrode PXE1. As an example, the first insulating layer INS1 may be disposed on the base substrate SB to surround the side surface of the first pixel electrode PXE1.

[0180] The first insulating layer INS1 may include an opening corresponding to the first pixel electrode PXE1. As an example, the first insulating layer INS1 may be opened to expose the upper surface of the first pixel electrode PXE1.

[0181] The first insulating layer INS1 may include at least one insulating material and may have a single layer or multi-layer structure. In one embodiment, the first insulating layer INS1 may include an inorganic insulating material (eg, silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al x O y ), titanium oxide (Ti x O y ), hafnium oxide (HfO x ) or other inorganic insulating materials).

[0182] The connection electrode CNE may be disposed on the first pixel electrode PXE1. In one embodiment, the connection electrode CNE may be disposed on the semiconductor circuit substrate 110 to be directly disposed or formed on the corresponding first pixel electrode PXE1, but is not limited thereto. The connection electrode CNE may be electrically connected to the corresponding first pixel electrode PXE1.

[0183] The connection electrode CNE may serve as a bonding metal for adhering the first pixel electrode PXE1 to the light emitting element LE. For example, the corresponding light emitting element LE may be bonded to the connection electrode CNE. The light emitting element LE may be electrically connected to the corresponding first pixel electrode PXE1 through the connection electrode CNE.

[0184] The connection electrode CNE may include a conductive metal. For example, the connection electrode CNE may include at least one of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag). The connection electrode CNE may reduce the contact resistance between the light emitting element LE and the first pixel electrode PXE1.

[0185] In one embodiment, the connection electrode CNE may have a larger area than the light emitting element LE. For example, when viewed in a plan view, the connection electrode CNE may protrude outward from the light emitting element LE.

[0186] In one embodiment, the display panel 100 may not include the connection electrode CNE. As an example, the corresponding light emitting element LE may be directly disposed or connected to the first pixel electrode PXE1.

[0187] The light emitting element layer 120 may include a light emitting element LE and a second pixel electrode PXE2 of the pixel PX. In one embodiment, the light emitting element layer 120 may further include at least one of a second insulating layer INS2, a third insulating layer INS3, and a capping layer CPL.

[0188] The light-emitting element LE may be disposed on a corresponding connection electrode CNE. For example, the light-emitting element LE of each pixel PX may be bonded to the connection electrode CNE of the corresponding pixel PX and may be electrically connected to the first pixel electrode PXE1 and the pixel circuit PXC of the corresponding pixel PX via the connection electrode CNE. As an example, the first light-emitting element LE1 disposed in the first pixel PX1 may be disposed on the connection electrode CNE of the first pixel PX1 and may be electrically connected to the first pixel electrode PXE1 and the pixel circuit PXC of the first pixel PX1 via the connection electrode CNE. The second light-emitting element LE2 disposed in the second pixel PX2 may be disposed on the connection electrode CNE of the second pixel PX2 and may be electrically connected to the first pixel electrode PXE1 and the pixel circuit PXC of the second pixel PX2 via the connection electrode CNE. The third light-emitting element LE3 disposed in the third pixel PX3 may be disposed on the connection electrode CNE of the third pixel PX3 and may be electrically connected to the first pixel electrode PXE1 and the pixel circuit PXC of the third pixel PX3 via the connection electrode CNE.

[0189] Each of the light-emitting elements LE may include a first semiconductor layer SEM1 and a second semiconductor layer SEM2 doped to have a first conductivity type and a second conductivity type, respectively, and a light-emitting layer EML disposed between the first semiconductor layer SEM1 and the second semiconductor layer SEM2. In one embodiment, the light-emitting layer EML may include a quantum well layer QWL including a nitride-based semiconductor material containing indium. The quantum well layer QWL may contain indium at a composition corresponding to the emission wavelength of each of the light-emitting elements LE.

[0190] In one embodiment, each of the light emitting elements LE may further include a contact electrode CTE. The contact electrode CTE may be disposed on the connection electrode CNE of the corresponding pixel PX to be connected to the connection electrode CNE.

[0191] In one embodiment, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 can emit light of different colors. For example, the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 can emit light of a first color (e.g., red light), a second color (e.g., green light), and a third color (e.g., blue light), respectively. In this case, the light-emitting layer EML of the first light-emitting element LE1 (hereinafter referred to as "first light-emitting layer EML1"), the light-emitting layer EML of the second light-emitting element LE2 (hereinafter referred to as "second light-emitting layer EML2"), and the light-emitting layer EML of the third light-emitting element LE3 (hereinafter referred to as "third light-emitting layer EML3") can emit light in different wavelength bands. The first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may include indium with different compositions. For example, the quantum well layer QWL of the first light-emitting layer EML1, which emits light of a longer wavelength, may include an indium composition higher than that of the quantum well layer QWL of each of the second light-emitting layer EML2 and the third light-emitting layer EML3.

[0192] In one embodiment, at least one light-emitting element LE may further include a stress relief layer SRL. For example, a light-emitting element LE that emits light having a long wavelength greater than or equal to a given wavelength band may further include a stress relief layer SRL containing indium in a range of 30% to 100% of the indium content of the quantum well layer QWL included in the light-emitting layer EML.

[0193] In one embodiment, the first light emitting element LE1 emits light of a longer wavelength (e.g., red light) than the second light emitting element LE2 and the third light emitting element LE3, and may include a stress relief layer SRL disposed between the first semiconductor layer SEM1 and the first light emitting layer EML1. The stress relief layer SRL of the first light emitting element LE1 may include at least one indium-containing layer including a nitride-based semiconductor material containing indium in a composition ranging from 30% to 100% of the indium composition of the quantum well layer QWL in the first light emitting layer EML1. The stress relief layer SRL of the first light emitting element LE1 may be doped. As an example, the stress relief layer SRL of the first light emitting element LE1 may be doped with 10 16 / cm 3 Therefore, although a high current corresponding to a high grayscale data signal flows through the first light emitting element LE1, light may not be generated in the stress release layer SRL.

[0194] Each of the second light emitting element LE2 and the third light emitting element LE3 may include or may not include a stress release layer SRL disposed between the light emitting layer EML (eg, the second light emitting layer EML2 or the third light emitting layer EML3) and the first semiconductor layer SEM1. Figure 13 As in the embodiment of the present invention, the second light-emitting element LE2 and the third light-emitting element LE3 may not include the stress relief layer SRL. In an embodiment, each of the first light-emitting element LE1 and the second light-emitting element LE2 may include the stress relief layer SRL, and the third light-emitting element LE3 may not include the stress relief layer SRL. In an embodiment, each of the first light-emitting element LE1, the second light-emitting element LE2, and the third light-emitting element LE3 may include the stress relief layer SRL. The stress relief layer SRL of the light-emitting element LE may include an indium-containing layer containing indium at a composition ratio corresponding to the indium included in each of the light-emitting layers EML.

[0195] In the case where at least one of the second light-emitting element LE2 and the third light-emitting element LE3 does not include the stress release layer SRL, the light-emitting elements LE provided in the pixel PX may have different structures depending on the emission wavelength. As an example, the first light-emitting element LE1 may include the stress release layer SRL, and at least one of the second light-emitting element LE2 and the third light-emitting element LE3 may not include the stress release layer SRL.

[0196] In one embodiment, at least one light emitting element LE may further include a superlattice layer SLT. For example, at least one of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may further include the superlattice layer SLT according to the above-described embodiment. In one embodiment, the light emitting element LE including the superlattice layer SLT may further include a spacer layer SPL disposed between the superlattice layer SLT and the stress relief layer SRL (or the first semiconductor layer SEM1), or may not include the spacer layer SPL.

[0197] The second insulating layer INS2 may be disposed around the light emitting element LE to surround at least a portion of the light emitting element LE. As an example, the second insulating layer INS2 may be disposed on the semiconductor circuit substrate 110 and may surround a side surface of the light emitting element LE.

[0198] The second insulating layer INS2 may include an opening exposing a portion of the light emitting element LE. For example, the second insulating layer INS2 may be open to expose an upper surface of the light emitting element LE (eg, one of the surfaces of the first semiconductor layer SEM1).

[0199] The second insulating layer INS2 may include at least one insulating material and may have a single layer or multi-layer structure. In one embodiment, the second insulating layer INS2 may include at least one inorganic insulating layer including an inorganic insulating material. The second insulating layer INS2 may be omitted.

[0200] The third insulating layer INS3 may be provided around the light emitting element LE and / or the second insulating layer INS2. For example, the third insulating layer INS3 may be filled between the light emitting elements LE surrounded by the second insulating layer INS2. In one embodiment, the third insulating layer INS3 may be formed to have substantially the same height as or a similar height to the light emitting element LE, thereby reducing a step portion caused by the light emitting element LE.

[0201] In one embodiment, the third insulating layer INS3 may include an organic insulating material. For example, the third insulating layer INS3 may be a single layer or multiple layers of an organic insulating layer including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating materials. In another embodiment, the third insulating layer INS3 may include a silicon oxide (SiO x ) or at least one inorganic insulating layer of other inorganic insulating materials, and the third insulating layer INS3 may be optionally planarized.

[0202] The second pixel electrode PXE2 may be disposed on the light emitting element LE and may be connected to the light emitting element LE. As an example, the second pixel electrode PXE2 may be disposed on the first semiconductor layer SEM1 of the light emitting element LE.

[0203] In one embodiment, the second pixel electrode PXE2 may be completely disposed in the display area DA. As an example, the second pixel electrode PXE2 may be disposed on the light-emitting element LE and the third insulating layer INS3 and may be formed as a common electrode shared by the pixels PX. The second pixel electrode PXE2 may be connected to at least one common electrode connection portion CVS or a power line connected thereto (e.g., a second pixel power line) and may be provided with a second pixel voltage (e.g., a common voltage) or a cathode voltage. In an embodiment, the pixel PX may include individually separated second pixel electrodes PXE2, and the second pixel electrodes PXE2 may be commonly connected to the common electrode connection portion CVS.

[0204] The capping layer CPL may be disposed on the second pixel electrode PXE2. For example, the capping layer CPL may be entirely disposed in the display area DA to cover the second pixel electrode PXE2. In one embodiment, the capping layer CPL may include at least one inorganic insulating layer including an inorganic insulating material.

[0205] In one embodiment, the display panel 100 may further include additional configurations. For example, the display panel 100 may further include at least one of a reflective layer and a light blocking layer disposed around the light emitting element LE, and a cover layer disposed on the capping layer CPL.

[0206] Figure 14 is a diagram illustrating a virtual reality device 1 including a display device 10_1 according to one embodiment.

[0207] refer to Figure 14 According to one embodiment, the virtual reality device 1 may be a glasses-type device. According to one embodiment, the virtual reality device 1 may include a display device 10_1, a left lens 10a, a right lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0208] although Figure 14 The virtual reality device 1 is shown as including temples 30a and 30b, but the embodiment is not limited thereto. For example, the virtual reality device 1 may be applied to a head-mounted display including a headband that can be worn on the head instead of temples 30a and 30b. The virtual reality device 1 according to the embodiment may be applied to other electronic devices in various forms.

[0209] The display device housing 50 can accommodate the display device 10_1 and the reflective member 40. The image displayed on the display device 10_1 can be reflected by the reflective member 40 and provided to the user's right eye through the right lens 10b. Therefore, the user can observe the virtual reality image displayed on the display device 10_1 through the right eye.

[0210] although Figure 14 The display device housing 50 is shown to be arranged at the right end of the support frame 20, but embodiments are not limited thereto. For example, the display device housing 50 can be arranged at the left end of the support frame 20, and in this case, the image displayed on the display device 10_1 can be reflected by the reflective member 40 and provided to the user's left eye through the left lens 10a. Therefore, the user can observe the virtual reality image displayed on the display device 10_1 through the left eye. For example, the display device housing 50 can be arranged at both the left and right ends of the support frame 20. In this case, the user can observe the virtual reality image displayed on the display device 10_1 through both the left eye and the right eye.

[0211] Figure 15 10_2 is a diagram illustrating a smart device including a display device 10_2 according to one embodiment.

[0212] refer to Figure 15 , the display device 10_2 according to one embodiment can be applied to a smart watch 2 as one of the smart devices. The planar shape of the clock display unit of the smart watch 2 can follow the planar shape of the display device 10_2. For example, in the case where the display device 10_2 according to one embodiment has a planar shape such as a circular shape or an elliptical shape, the clock display unit of the smart watch 2 can have a planar shape such as a circular shape or an elliptical shape. For example, in the case where the display device 10_2 according to one embodiment has a quadrilateral planar shape, the clock display unit of the smart watch 2 can have a quadrilateral planar shape. However, the embodiment is not limited thereto, and the clock display unit of the smart watch 2 may not follow the planar shape of the display device 10_2.

[0213] Figure 16 A car instrument panel and a center instrument panel including display devices 10_a, 10_b, 10_c, 10_d, and 10_e are shown according to one embodiment. Figure 15 A vehicle is shown to which display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to one embodiment are applied.

[0214] refer to Figure 16The display devices 10_a, 10_b, and 10_c according to one embodiment can be applied to a dashboard, a center instrument panel, or a central information display (CID) of a dashboard of a car. For example, the display devices 10_d and 10_e according to one embodiment can be applied to an interior rearview mirror display, replacing a side mirror of a car.

[0215] Figure 17 is a diagram illustrating a transparent display device including a display device 10_3 according to one embodiment.

[0216] refer to Figure 17 The display device 10_3 according to one embodiment can be applied to a transparent display device. The transparent display device can display an image IM and also transmit light. Therefore, a user in front of the transparent display device can observe an object RS or background behind the transparent display device as well as the image IM displayed on the display device 10_3. When the display device 10_3 is applied to a transparent display device, the display panel 100 may include a light-transmitting portion that transmits light, or may be formed on a substrate member made of a light-transmitting material.

[0217] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. Light-emitting element, including: a first semiconductor layer doped to have a first conductivity type; a stress release layer disposed on the first semiconductor layer, the stress release layer comprising an indium-containing layer and doped to have the first conductivity type, the indium-containing layer comprising a nitride-based semiconductor material containing indium; a light-emitting layer disposed on the stress-releasing layer, the light-emitting layer comprising a quantum well layer containing a nitride-based semiconductor material having an indium content greater than or equal to an indium content of the indium-containing layer; as well as a second semiconductor layer, disposed on the light emitting layer and doped to have a second conductivity type; The indium content of the indium-containing layer is in a range of 30% to 100% of the indium content of the quantum well layer.

2. The light-emitting element according to claim 1, wherein The doping concentration of the indium-containing layer is 10 16 / cm 3 or higher.

3. The light-emitting element according to claim 1, wherein The doping concentration of the indium-containing layer is lower than the doping concentration of the first semiconductor layer.

4. The light-emitting element according to claim 1, wherein The thickness of the indium-containing layer is 2 nm or greater.

5. The light-emitting element according to claim 1, further comprising: a superlattice layer, disposed between the first semiconductor layer and the stress release layer, The superlattice layer is formed as a multilayer in which a first layer containing a nitride-based semiconductor material containing indium and a second layer containing a nitride-based semiconductor material not containing indium are alternately arranged. The light-emitting element according to claim 5 , wherein The indium composition of the first layer of the superlattice layer is less than 30% of the indium composition of the quantum well layer.

7. The light-emitting element according to claim 5, wherein The superlattice layer is doped with a doping concentration lower than or equal to a doping concentration of the first semiconductor layer.

8. The light-emitting element according to claim 5, further comprising: a spacer layer disposed between the superlattice layer and the stress relief layer, the spacer layer comprising a nitride-based semiconductor material that does not contain indium, Wherein, the thickness of the separation layer is 20 nm or greater.

9. The light-emitting element according to claim 1, wherein The quantum well layer contains InGaN, and The indium-containing layer contains InGaN or InAlGaN.

10. The light-emitting element according to claim 1, wherein The indium-containing layer directly contacts the light-emitting layer. The light-emitting element according to claim 1 , wherein The stress release layer is a single layer formed of the indium-containing layer, and The indium composition of the stress release layer gradually changes from a lower portion adjacent to the first semiconductor layer to an upper portion adjacent to the light emitting layer.

12. The light-emitting element according to claim 1, wherein The stress relaxation layer is formed as a multilayer in which a plurality of indium-containing layers including the indium-containing layer and a plurality of intermediate layers containing a nitride-based semiconductor material not containing indium are alternately arranged.

13. The light-emitting element according to claim 12, wherein The indium composition of the plurality of indium-containing layers gradually changes from the indium-containing layer at a lower portion adjacent to the first semiconductor layer among the plurality of indium-containing layers to the indium-containing layer at an upper portion adjacent to the light-emitting layer among the plurality of indium-containing layers.

14. The light-emitting element according to claim 1, wherein The doping concentration of the stress release layer gradually changes from a lower portion adjacent to the first semiconductor layer to an upper portion adjacent to the light emitting layer.

15. The light-emitting element according to claim 14, wherein The doping concentration of the stress release layer gradually decreases from the lower portion adjacent to the first semiconductor layer to the upper portion adjacent to the light emitting layer.

16. The light-emitting element according to claim 1, wherein The indium fluctuation in the light emitting layer is at least 10% higher than the indium fluctuation in the stress release layer.

17. The light-emitting element according to claim 1, wherein The indium composition of the quantum well layer is 25% or more, and The emission wavelength of the light emitting layer is in the range of 500 nm to 750 nm.

18. Display devices, including: A pixel includes a first pixel electrode, a second pixel electrode, and a light-emitting element electrically connected between the first pixel electrode and the second pixel electrode, wherein: The light emitting element comprises: a first semiconductor layer doped to have a first conductivity type; a stress release layer disposed on the first semiconductor layer, the stress release layer comprising an indium-containing layer containing a nitride-based semiconductor material containing indium and doped to have the first conductivity type; a light emitting layer disposed on the stress release layer, the light emitting layer comprising a quantum well layer containing a nitride-based semiconductor material containing indium; and a second semiconductor layer disposed on the light emitting layer and doped to have a second conductivity type, and The indium composition of the indium-containing layer is in a range of 30% to 100% of the indium composition of the quantum well layer.

19. The display device according to claim 18, wherein The doping concentration of the indium-containing layer is 10 16 / cm 3 or higher.

20. The display device according to claim 18, wherein The light emitting element further includes a superlattice layer disposed between the first semiconductor layer and the stress release layer, and The superlattice layer contains a nitride-based semiconductor material having an indium-containing composition that is less than 30% of the indium composition of the quantum well layer.

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