Low resistivity gap fill for logic devices

Abstract

Embodiments of the present disclosure relate to methods for metal gap fill with lower resistivity for logic devices. Particular embodiments provide an integrated separate tungsten PVD process using plasma etching to address overhang problems caused by tungsten PVD and high resistivity caused by nucleation.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to methods for depositing metal gap fillers within substrate features. More particularly, embodiments of the present disclosure are directed to methods for providing gap fills having improved resistivity. Background Art

[0002] Gapfilling is an essential process for several semiconductor manufacturing processes. Gapfilling can be used to fill gaps (or features) with insulating or conductive materials. For example, shallow trench isolation, intermetallic dielectric layers, passivation layers, and dummy gates are all typically implemented using gapfilling.

[0003] As device geometries continue to shrink (eg, critical dimensions <20 nm, <10 nm, and smaller), the reduced metal volume results in higher resistivity for metal interconnects.

[0004] Typically, for tungsten gapfill, a nucleation layer containing silicon or boron is deposited on top of a PVD tungsten liner before forming the tungsten bulk fill to promote the formation / growth of the bulk fill on the PVD liner. However, these nucleation layers result in a relatively high resistance stack due to the presence of boron tungsten (BW) and / or tungsten silicide (WSi). Additionally, the overhang effect of tungsten physical vapor deposition (WPVD) is problematic, limiting gapfill performance.

[0005] Therefore, there is a need for gap filling methods that provide lower resistivity. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to a method for forming a logic device, the method comprising: depositing a first metal layer on a substrate surface by physical vapor deposition (PVD), the substrate surface comprising at least one feature extending a certain depth from the substrate surface to a bottom and having two sidewalls; exposing the first metal layer to a nucleation presoak to form a nucleation layer on the first metal layer; exposing the nucleation layer to plasma to etch the nucleation layer; depositing a second metal layer on the nucleation layer by physical vapor deposition (PVD); and depositing a metal gap filler on the second metal layer to fill the at least one feature and form a metal stack.

[0007] Further embodiments of the present disclosure are directed to a method for forming a semiconductor device, the method comprising: depositing a first metal layer comprising tungsten (W) on a substrate surface by physical vapor deposition (PVD), the substrate surface comprising at least one feature extending a certain depth from the substrate surface to a bottom and having two sidewalls; exposing the first metal layer to a nucleation pre-dip comprising boron to form a boron nucleation layer; exposing the boron nucleation layer to plasma to etch the boron nucleation layer; depositing a second metal layer comprising tungsten (W) on the boron nucleation layer by physical vapor deposition (PVD); and depositing a metal gap filler comprising tungsten (W) on the second metal layer to fill the at least one feature and form a metal stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to be able to understand in detail the manner in which the features described above of the present disclosure are described, a more particular description of the present disclosure, briefly summarized above, may be made with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the present disclosure and, therefore, should not be considered as limiting the scope of the present disclosure, as the present disclosure may admit to other equally effective embodiments. The embodiments as described herein are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like reference numerals indicate similar elements.

[0009] Figure 1 A process flow diagram illustrating a deposition method according to one or more embodiments is shown;

[0010] Figure 2A illustrates a cross-sectional view of a substrate during processing according to one or more embodiments;

[0011] Figure 2B illustrates a cross-sectional view of a substrate during processing according to one or more embodiments;

[0012] Figure 2C illustrates a cross-sectional view of a substrate during processing according to one or more embodiments;

[0013] Figure 2D illustrates a cross-sectional view of a substrate during processing according to one or more embodiments;

[0014] Figure 2E illustrates a cross-sectional view of a substrate during processing according to one or more embodiments;

[0015] Figure 2F illustrates a cross-sectional view of a substrate during processing according to one or more embodiments; and

[0016] Figure 3 A schematic top view of a multi-chamber processing system is illustrated in accordance with one or more embodiments. DETAILED DESCRIPTION

[0017] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps described in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0018] As used herein, the term "about" means approximately or close to, and in the context of a recited numerical value or range, means a variation of ±15% or less of the value. For example, values that differ by ±14%, ±10%, ±5%, ±2%, ±1%, ±0.5%, or ±0.1% would meet the definition of "about."

[0019] As used in this specification and the appended claims, the term "substrate" or "wafer" refers to a surface or portion of a surface upon which a process is performed. Those skilled in the art will also understand that reference to a substrate may refer only to a portion of a substrate, unless the context clearly indicates otherwise. Additionally, reference to a step of depositing on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0020] As used herein, "substrate surface" refers to the surface of any substrate or material formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any film processing step disclosed may also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlayer as indicated by the context. Thus, for example, when a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0021] The substrate surface may have one or more features formed therein, one or more layers formed thereon, and combinations thereof. The shape of the feature may be any suitable shape, including but not limited to grooves, holes, and vias (circular or polygonal). As used in this context, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include but are not limited to grooves (having a top, two sidewalls, and a bottom extending into the substrate) and vias (having one or more sidewalls extending into the substrate to the bottom).

[0022] The term "on" indicates direct contact between elements, and intervening elements or layers may be present. The term "directly on" indicates direct contact between elements without intervening devices.

[0023] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gaseous species that can react with a substrate surface.

[0024] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is exposed separately to the two or more reactive compounds in a reaction zone introduced into a processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay to allow each compound to adhere and / or react on the substrate surface and then be purged from the processing chamber. The reactive compounds are said to be exposed to the substrate sequentially. In a spatial ALD process, different portions of the substrate surface or the material on the substrate surface are exposed to two or more reactive compounds simultaneously so that any given point on the substrate is not substantially exposed to more than one reactive compound at the same time. As used in this specification and the appended claims, the term "substantially" as used in this regard means that, as will be understood by those skilled in the art, due to diffusion, small portions of the substrate may be exposed to multiple reactive gases at the same time, but the simultaneous exposure is unintentional.

[0025] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction region, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction region, followed by a second delay. During each time delay, a purge gas (e.g., argon) is introduced into the processing chamber to purge the reaction region or otherwise remove any residual reactive compounds or reaction byproducts from the reaction region. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. Under either scheme, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. A cycle may start with either compound A or compound B and continue a separate sequence of cycles until a film having a predetermined thickness is achieved.

[0026] In an embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen) are delivered simultaneously to a reaction region, but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery apparatus so that any given point on the substrate is exposed to both the first and second reactive gases.

[0027] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or common reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to situations where there is co-flow or where a substantial portion of the exposure of the precursors overlaps.

[0028] Plasma enhanced chemical vapor deposition (PECVD) is widely used for depositing films due to its cost-effectiveness and versatility in film properties. In the PECVD process, for example, a hydrocarbon source (e.g., vapor of a gaseous hydrocarbon or a liquid hydrocarbon entrained in a carrier gas) is introduced into the PECVD chamber. A plasma-initiating gas (typically helium) is also introduced into the chamber. Subsequently, a plasma is initiated in the chamber to generate excited CH radicals. The excited CH radicals chemically bond to the surface of a substrate placed in the chamber, thereby forming a desired film thereon. Any suitable film deposition system can be used to perform the embodiments described herein with reference to the PECVD process. Any equipment description described herein is illustrative and should not be interpreted or construed as limiting the scope of the embodiments described herein.

[0029] As used herein, "physical vapor deposition" (PVD) refers to a variety of vacuum deposition methods that can be used to produce thin films and coatings on substrates including metals, ceramics, glass, and polymers. PVD is characterized by a process in which a material transitions from a condensed phase to a vapor phase and then back to a thin film condensed phase.

[0030] Currently, a boron tungsten (BW) nucleation process is used to allow good sidewall coverage, but the boron tungsten (BW) nucleation process causes a resistivity penalty due to the introduction of boron. Additionally, the overhang effect of tungsten physical vapor deposition (WPVD) is also problematic, limiting gap filling performance. In one or more embodiments, a separate WPVD process is advantageously integrated with plasma etching to solve the overhang problem of WPVD and the high resistivity problem of nucleation, thereby providing good gap filling in logic features with low resistivity. In one or more embodiments, a separate WPVD process allows for smaller overhangs in features. In addition, the second WPVD layer serves as a seeding layer for bulk tungsten deposition, which results in lower resistivity. In one or more embodiments, a BW nucleation process is included, which provides better sidewall step coverage in the feature. In order to further reduce the stack resistivity, plasma etching is included in the process of cleaning the WPVD film.

[0031] Embodiments of the present disclosure are described with reference to the accompanying drawings, which illustrate devices (e.g., logic devices) and processes for forming the devices according to one or more embodiments of the present disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications illustrated.

[0032] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of example embodiments (and intermediate structures). Accordingly, variations in the illustrated shapes are to be expected due to, for example, manufacturing techniques and / or tolerances. Thus, example embodiments should not be construed as limited to the particular shapes of the regions illustrated herein, but may include deviations in shape due to, for example, manufacturing. Accordingly, the regions illustrated in the drawings are schematic in nature, and their shapes may not be intended to illustrate the actual shape of regions of a device and are not intended to limit the scope of the example embodiments.

[0033] Figure 1 A process flow diagram illustrating a method 10 for forming a semiconductor device according to one or more embodiments of the present disclosure is illustrated. Figures 2A to 2F A cross-sectional view of a semiconductor device according to one or more embodiments is illustrated. Figures 2A to 2F Method 10 is described. Method 10 may be part of a multi-step fabrication flow for a semiconductor device.

[0034] In one or more embodiments, method 10 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may include a process chamber for fabricating semiconductor devices, such as a chamber configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber for fabricating semiconductor devices.

[0035] refer to Figure 1 In operation 12 of method 10, a metal layer is deposited using PVD. In operation 14, a nucleation layer is formed on the metal layer. In operation 16, the substrate is etched using plasma. In operation 18, a second metal layer is deposited. In operation 20, a metal gap filler is deposited.

[0036] Figure 2A A substrate 100 is illustrated having a substrate surface 105. As described above, a substrate surface refers to an exposed surface of a substrate on which a layer can be formed. Substrate surface 105 has at least one feature 110 formed therein. Although only a single feature is labeled in the figures, those skilled in the art will recognize that multiple features can be affected by the disclosed method, each in a similar manner.

[0037] At least one feature 110 has an opening 112 having a width W. Opening 112 is formed in a top surface 115 of substrate 100. Feature 110 also has one or more sidewalls 114 and extends a depth D from top surface 115 to a bottom 116. Although straight, vertical sidewalls are shown in the figures, the disclosed methods can also be performed on sloped, irregular, or reentrant sidewalls.

[0038] In one or more embodiments, the width W of the opening 112 is greater than or equal to about 10 nm, greater than or equal to about 15 nm, greater than or equal to about 20 nm, greater than or equal to about 25 nm, greater than or equal to about 30 nm, or greater than or equal to about 35 nm. In one or more embodiments, the width W is in a range of about 5 nm to about 15 nm, or in a range of about 10 nm to about 35 nm.

[0039] In one or more embodiments, the depth D of the feature 110 is greater than or equal to about 50 nm, greater than or equal to about 75 nm, greater than or equal to about 100 nm, greater than or equal to about 150 nm, greater than or equal to about 200 nm, or greater than or equal to about 250 nm. In one or more embodiments, the depth D is in the range of about 50 nm to about 250 nm, or in the range of about 200 nm to about 250 nm.

[0040] Those skilled in the art will recognize that depositing metal gap fillers in features with narrowing widths (also referred to as critical dimensions (CD)) and / or increasing depths is an increasing challenge. The aspect ratio of at least one feature 110 is defined as the depth D divided by the width W of the feature 110. In one or more embodiments, the at least one feature has an aspect ratio (D:W) greater than or equal to approximately 2:1, greater than or equal to approximately 5:1, greater than or equal to approximately 10:1, or greater than or equal to approximately 20:1.

[0041] refer to Figure 1 and Figure 2B , method 10 begins at operation 12, where a metal layer 120 is deposited on substrate surface 105. In one or more embodiments, the metal layer 120 is deposited by a physical vapor deposition process. In one or more embodiments, as Figure 2B As shown, metal layer 120 is discontinuous and is deposited on top surface 115, sidewalls 114, and bottom 116 of substrate surface 105. In one or more embodiments, metal layer 120 only partially covers sidewalls 114 of at least one feature 110.

[0042] In one or more embodiments, the metal layer 120 is formed with an overhang 122 on the top surface 115 of the substrate surface, and the overhang 122 partially extends into the opening 112 of the at least one feature 110. In one or more embodiments, the overhang 122 of the metal layer 120 has an average thickness of less than or equal to about or less than or equal to approximately

[0043] In one or more embodiments, the metal layer 120 may include any suitable material known to those skilled in the art. In one or more embodiments, the metal layer 120 includes tungsten (W).

[0044] refer to Figure 1 and Figure 2C At operation 14, a nucleation layer 130 is formed on the metal layer 120 and within the at least one feature 110. In one or more embodiments, as Figure 2C As shown, nucleation layer 130 is continuous and deposited on all surfaces of metal layer 120 and on the sidewalls 114 and bottom of at least one feature 110 .

[0045] At operation 14, a nucleation layer 130 may be formed by exposing the substrate to a nucleation predip. In one or more embodiments, the nucleation predip comprises a silicon compound. In one or more embodiments, the nucleation predip comprises a boron compound. As used herein, a "silicon compound" or "boron compound" is any material capable of forming a silicon layer or a boron layer, respectively, on the metal layer 120.

[0046] In one or more embodiments, the silicon compound comprises or consists essentially of silane (SiH4), disilane, trisilane, butasilane, cyclopentasilane, or cyclohexasilane. In one or more embodiments, the boron compound comprises or consists essentially of borane, diborane (B2H6), triborane, tetraborane, or cycloborane. As used in this context, a process gas that "consists essentially of" the material includes greater than about 95%, greater than about 98%, greater than about 99%, or greater than about 99.5% of the material on a molar basis, excluding any inert diluent or carrier gas.

[0047] In one or more embodiments, the first metal layer 120 is exposed to a nucleation predip including boron to form a boron nucleation layer. In other embodiments, the first metal layer 120 is exposed to a nucleation predip including silicon to form a silicon nucleation layer.

[0048] In one or more embodiments, the nucleation layer 130 is substantially conformal. As used in this context, a "substantially conformal" layer has an average thickness that varies by less than 10%, less than 5%, or less than 2% of the average thickness of the layer. In one or more embodiments, the nucleation layer 130 has a thickness less than or less than In one or more embodiments, the nucleation layer 130 includes one to two monolayers of silicon and / or boron.

[0049] In one or more embodiments, forming the nucleation layer 130 at operation 14 represents a chemical vapor deposition (CVD) process. In one or more embodiments, the temperature of the CVD process is in a range of about 250° C. to about 450° C., in a range of about 250° C. to about 350° C., or in a range of about 350° C. to about 450° C. In one or more embodiments, the CVD process is performed without plasma.

[0050] refer to Figure 1 and Figure 2D, method 10 continues at operation 16 where the device is exposed to a plasma 140 to etch the nucleation layer 130. In some embodiments, the plasma 140 cleans the nucleation layer 130 and removes a portion of the nucleation layer 130. In one or more embodiments, the plasma 140 etching step removes a portion of the nucleation layer 130 from the top, sidewalls, and bottom of the at least one feature 110. In one or more embodiments, the step of etching the nucleation layer 130 completely removes the nucleation layer from the top surface of the substrate surface 105 and from the bottom 116 of the at least one feature, thereby exposing the metal layer 120. In one or more embodiments, the step of etching the nucleation layer 130 reduces the thickness of the nucleation layer 130 on the sidewalls 114. In some embodiments, the thickness of the nucleation layer 130 is reduced by about In some embodiments, the plasma 140 etch may remove a portion of the nucleation layer 130 from the overhang 122 of the metal layer 120 .

[0051] In some embodiments, the etching process may include conventional plasma etching or a remote plasma assisted dry etching process, such as SiCoNi available from Applied Materials, Inc., located in Santa Clara, California. TM Etching process. TM During the etching process, the device is exposed to Ar, H2, NF3 and / or NH3 plasma species, such as plasma excited hydrogen and fluorine species. For example, in some embodiments, the device can be exposed to Ar, H2, NF3 and NH3 plasma at the same time. TM Etching process can be used on SiCoNi TM The process is performed in a pre-clean chamber that can be integrated into one of a variety of multi-processing platforms, including those available from Applied Obtained Dual ACP, GT and The plasma process may be any suitable plasma (eg, conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0052] In one or more embodiments, the plasma etching process of operation 16 advantageously reduces the concentration of boron in the nucleation layer. In some embodiments, before the plasma etching, the boron concentration of the nucleation layer 130 is in a range from 3% to 7%, including in a range from 4% to 6%. In one or more embodiments, after the plasma etching process of operation 16, the boron concentration of the nucleation layer 130 is in a range from >0% to 3%, including in a range from 0.5% to 2.5%. Reducing the boron concentration in the nucleation layer 130 advantageously results in lower resistivity of the metal stack of the logic device.

[0053] Method 10 continues at operation 18 by forming a second metal layer 148. In one or more embodiments, the second metal layer 148 is deposited by a physical vapor deposition process. Figure 2E As shown, when second metal layer 148 is deposited on nucleation layer 130 on sidewalls 114 of at least one feature 110 , second metal layer 148 is not continuous.

[0054] In one or more embodiments, the second metal layer 148 has a thickness less than or less than or less than In one or more embodiments, the thickness of the second metal layer 148 is greater than the thickness of the first metal layer 120 .

[0055] In one or more embodiments, the second metal layer 148 may include any suitable material known to those skilled in the art. In one or more embodiments, the metal layer 148 includes tungsten (W).

[0056] refer to Figure 1 and Figure 2F , method 10 continues at operation 20 where a metal gap filler 150 is deposited on the second metal layer 148. In one or more embodiments, the metal gap filler 150 is deposited by an atomic layer deposition (ALD) process. In one or more embodiments, the metal gap filler 150 is deposited by a chemical vapor deposition (CVD) process. In one or more embodiments, the metal gap filler 150 is deposited by an atomic layer deposition (ALD) process followed by a chemical vapor deposition (CVD) process.

[0057] In one or more embodiments, the metal gap filler 150 is formed directly on the metal layer 148. As described above, without being bound by theory, it is believed that the disclosed method provides a metal gap filler without using or forming a high resistance nucleation layer. In one or more embodiments, the metal layer 148 and the metal gap filler 150 are referred to as a metal stack. In one or more embodiments, the nucleation layer 130 does not increase the resistance of the metal stack. In one or more embodiments, it has been surprisingly found that the presence of the nucleation layer 130 does not adversely affect the bonding of the metal stack to the underlying substrate. Additionally, in one or more embodiments, the plasma etch process following the nucleation process cleans the nucleation layer, which further results in a reduction in resistivity. In summary, by combining a separate WPVD process with a plasma etch process, The film can achieve a total resistivity reduction of at least 25%. In one or more embodiments, because the deposition of the first metal layer 120 and the second metal layer 148 (e.g., WPVD layer) is discontinuous, the metal gap filler 150 can be formed on the WPVD layer or the plasma-etched nucleation layer. Through the etching process of one or more embodiments, the nucleation layer 130 will not significantly increase the resistivity of the structure.

[0058] The gap filling process may include any suitable gap filling process known to those skilled in the art. For example, in one or more embodiments, the gap filling process may be an atomic layer deposition process. In other embodiments, the gap filling process may be a chemical vapor deposition process. In one or more embodiments, the gap filling process includes exposing the semiconductor structure 100 (specifically, the logic structure) to a metal precursor and a reactant. In some embodiments, the metal precursor includes one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor. In one or more specific embodiments, the metal precursor includes a tungsten precursor, and the metal gap filler 150 includes tungsten (W).

[0059] In some embodiments, the gap-fill process is a bottom-up gap-fill process. In other embodiments, the gap-fill process includes a conformal gap-fill process.

[0060] Embodiments of the present disclosure advantageously provide metal films (e.g., metal gap filler 150) that are free or substantially free of voids and seams. As used in this context, "substantially free" means that less than about 5%, including less than about 4%, less than about 3%, less than about 2%, less than about 1%, less than about 0.5%, and less than about 0.1%, of the total composition of the conformally deposited metal film (e.g., metal gap filler 150), on an atomic basis, comprises voids and / or seams.

[0061] Method described herein can be performed in any suitable processing chamber known to those skilled in the art.In certain embodiments, the operation of method described herein is performed in the same processing chamber or in the same processing system.In certain embodiments, the operation of method described herein is performed in different processing chambers.In certain embodiments, different processing chambers are connected as a part for a processing system.In certain embodiments, the operation of method described herein is performed in different processing chambers, and each different processing chamber is a part for an independent processing system.In certain embodiments, the operation of method described herein is performed without intervening vacuum break.

[0062] In one or more embodiments, one or more of the operations of the methods described herein are performed in situ without breaking vacuum. In some embodiments, one or more of the operations of the methods described herein are performed ex situ. As used herein, the term "in situ" refers to each of the operations of the methods described herein being performed in the same processing chamber or different processing chambers connected as part of a processing system, such that each of the operations of the methods described herein is performed without an intervening vacuum break. As used herein, the term "ex situ" refers to each of the operations of the methods described herein being performed in the same processing chamber or different processing chambers, such that one or more of the operations of the methods described herein are performed with an intervening vacuum break.

[0063] Figure 3 FIG3 is a schematic top view of an exemplary multi-chamber processing system 300 according to an embodiment of the present disclosure. The processing system 300 generally includes a factory interface 302, load lock chambers 304, 306, transfer chambers 308, 310 with respective transfer robots 312, 314, holding chambers 316, 318, and processing chambers 320, 322, 324, 326, 328, 330. As described in detail herein, wafers in the processing system 300 can be processed in and transferred between the various chambers without exposing the wafers to an ambient environment external to the processing system 300 (e.g., an atmospheric ambient environment, such as may exist in a wafer fab). For example, wafers can be processed in and transferred between the various chambers in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without disrupting the low pressure or vacuum environment between various processes performed on the wafers in the processing system 300. Thus, processing system 300 may provide an integrated solution for some processing of a wafer.

[0064] Examples of processing systems that may be appropriately modified according to the teachings provided herein include or An integrated processing system or other suitable processing system is commercially available from Applied Materials, Inc., located in Santa Clara, Calif. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the aspects described herein.

[0065] exist Figure 3 In the illustrated example, the factory interface 302 includes a docking station 340 and a factory interface robot 342 to facilitate wafer transfer. The docking station 340 is configured to receive one or more front-opening unified pods (FOUPs) 344. In some examples, each factory interface robot 342 generally includes a blade 348 disposed at one end of the respective factory interface robot 342. The factory interface robots 342 are configured to transfer wafers from the factory interface 302 to the load lock chambers 304 and 306.

[0066] The load lock chambers 304, 306 have respective ports 350, 352 coupled to the factory interface 302 and respective ports 354, 356 coupled to the transfer chamber 308. The transfer chamber 308 further has respective ports 358, 360 coupled to the holding chambers 316, 318 and respective ports 362, 364 coupled to the processing chambers 320, 322. Similarly, the transfer chamber 310 has respective ports 366, 368 coupled to the holding chambers 316, 318 and respective ports 370, 372, 374, 376 coupled to the processing chambers 324, 326, 328, 330. Ports 354, 356, 358, 360, 362, 364, 366, 368, 370, 372, 374, 376 may be, for example, slit valve openings having slit valves for allowing wafers to pass through the slit valve openings by transfer robots 312, 314 and for providing a seal between the respective chambers to prevent gas from passing between the respective chambers. Generally, any port is open for transferring a wafer therethrough. Otherwise, the port is closed.

[0067] The load lock chambers 304, 306, transfer chambers 308, 310, holding chambers 316, 318, and processing chambers 320, 322, 324, 326, 328, 330 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 342 transfers wafers from the FOUP 344 to the load lock chamber 304 or 306 via port 350 or 352. The gas and pressure control system then evacuates the load lock chamber 304 or 306. The gas and pressure control system further maintains the transfer chambers 308, 310 and holding chambers 316, 318 at an internal low pressure or vacuum environment (which may include an inert gas). Thus, evacuating the load lock chamber 304 or 306 facilitates transferring wafers between, for example, the atmospheric environment of the factory interface 302 and the low pressure or vacuum environment of the transfer chamber 308 .

[0068] With the wafer in the evacuated load lock chamber 304 or 306, the transfer robot 312 transfers the wafer from the load lock chamber 304 or 306 to the transfer chamber 308 via the port 354 or 356. The transfer robot 312 can then transfer the wafer to and / or between any of the processing chambers 320, 322 for processing via the respective ports 362, 364, and transfer the wafer to the holding chambers 316, 318 via the respective ports 358, 360 for holding pending further transfer. Similarly, the transfer robot 314 can access wafers in the holding chamber 316 or 318 via port 366 or 368, and can transfer wafers to any of the processing chambers 324, 326, 328, 330 and / or transfer wafers between any of the processing chambers 324, 326, 328, 330 for processing via respective ports 370, 372, 374, 376, and transfer wafers to the holding chambers 316, 318 for holding pending further transfer via respective ports 366, 368. The transfer and holding of wafers within and between the various chambers can be in a low pressure or vacuum environment provided by a gas and pressure control system.

[0069] The processing chambers 320, 322, 324, 326, 328, 330 may be any suitable chambers for processing wafers. In one or more embodiments, the processing chamber 320 may be capable of performing a nucleation pre-soak, the processing chamber 322 may be capable of performing a PVD deposition process, and the processing chamber 324 may be capable of performing an ALD and / or CVD deposition process.

[0070] A system controller 390 is coupled to the processing system 300 for controlling the processing system 300 or components thereof. For example, the system controller 390 can control the operation of the processing system 300 by directly controlling the chambers 304, 306, 308, 316, 318, 310, 320, 322, 324, 326, 328, 330 of the processing system 300 or by controlling controllers associated with the chambers 304, 306, 308, 316, 318, 310, 320, 322, 324, 326, 328, 330. In operation, the system controller 390 enables data collection and feedback from the respective chambers to coordinate the performance of the processing system 300.

[0071] The system controller 390 generally includes a central processing unit (CPU) 392, memory 394, and support circuits 396. The CPU 392 can be any general-purpose processor used in an industrial setting. The memory 394, or non-transitory computer-readable medium, is accessible by the CPU 392 and can be one or more of the following: random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. The support circuits 396 are coupled to the CPU 392 and can include cache memory, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented as, for example, software routines, under the control of the CPU 392, by the CPU 392 executing a computer script stored in the memory 394 (or in the memory of a particular process chamber). When the computer script is executed by the CPU 392, the CPU 392 controls the chamber to perform processes according to the various methods.

[0072] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 308 and 310 and holding chambers 316 and 318. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chamber) may be implemented as a transfer apparatus in a processing system.

[0073] The process can typically be stored as a software routine in the memory of the system controller 390, which, when executed by the processor, causes the process chamber to perform the process of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown), which is remote from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be executed in hardware. Therefore, the process can be implemented in software and executed using a computer system, implemented in hardware (e.g., an application specific integrated circuit or other type of hardware implementation), or implemented as a combination of software and hardware. The software routine, when executed by the processor, transforms a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber so that the process is performed.

[0074] Embodiments of the present disclosure are directed to non-transitory computer-readable media. In one or more embodiments, the non-transitory computer-readable medium includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform operations of any of the methods described herein (e.g., gap filling method 10). In one or more embodiments, the controller causes the processing chamber to perform operations of deposition method 10. In one or more embodiments, the controller causes the processing chamber to perform an operation of depositing a metal layer on a substrate surface having at least one feature therein by PVD (operation 12). The at least one feature includes at least one surface defining a via having a bottom surface and at least one sidewall. In one or more embodiments, the controller causes the processing chamber to deposit a nucleation layer on the metal layer (operation 14). In one or more embodiments, the controller causes the processing chamber to expose the device to plasma to etch the nucleation layer (operation 16). In one or more embodiments, the controller causes the processing chamber to deposit a second metal layer on the nucleation layer by PVD (operation 18). In one or more embodiments, the controller causes the processing chamber to deposit a metal gap filler in the at least one feature (operation 20).

[0075] For ease of description, spatially relative terms may be used herein, such as “beneath,” “below,” “lower,” “above,” “upper,” etc., to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying drawings. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is flipped, elements described as being “below” or “beneath” other elements or features will be oriented “above” the other elements or features. Thus, the exemplary term “below” may encompass both orientations of above and below. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0076] The use of the terms "a" and "an" and "the" and similar designations in the context of describing the materials and methods discussed herein (especially in the context of the appended claims) will be interpreted as covering both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the recitation of ranges of values herein is intended merely to serve as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as if the value were individually recited herein. Unless otherwise indicated herein or otherwise clearly contradicted by the context, all methods described herein can be performed in any suitable order. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods and does not constitute a limitation on the scope unless otherwise claimed. No language in the specification should be interpreted as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0077] Reference throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment," or "in an embodiment" appearing throughout this specification are not necessarily referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0078] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that the present disclosure include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a logic device, the method comprising: depositing a first metal layer on a substrate surface by physical vapor deposition (PVD), the substrate surface including at least one feature extending a depth from the substrate surface to a bottom and having two sidewalls; exposing the first metal layer to a nucleation predip to form a nucleation layer on the first metal layer; exposing the nucleation layer to plasma to etch the nucleation layer; depositing a second metal layer on the nucleation layer by physical vapor deposition (PVD); as well as A metal gap filler is deposited on the second metal layer to fill the at least one feature and form a metal stack.

2. The method of claim 1 wherein the at least one feature has an aspect ratio of at least 5:

1. 3 . The method of claim 1 , wherein the first metal layer, the second metal layer, and the metal gap filler comprise tungsten (W). The method of claim 1 , wherein the nucleating prepreg comprises a silicon compound.

5. The method of claim 4, wherein the nucleating predip consists essentially of silane (SiH4). The method of claim 1 , wherein the nucleating predip comprises a boron compound.

7. The method of claim 6 wherein the nucleating predip consists essentially of diborane (B2H6).

8. The method of claim 1, wherein the nucleation layer comprises one to two monolayers of silicon and / or boron.

9. The method of claim 1 , wherein the first metal layer forms an overhang into the at least one feature, the overhang having a length of approximately The average thickness of 10. The method of claim 1, wherein the metal gap filler is deposited by atomic layer deposition (ALD).

11. The method of claim 1 , wherein the metal gap filler is deposited by chemical vapor deposition (CVD).

12. The method of claim 1, wherein the metal gap filler is formed directly on the second metal layer.

13. The method of claim 1, wherein the nucleation layer does not increase the resistance of the metal stack.

14. The method of claim 9, wherein the plasma removes at least a portion of the overhang.

15. A method of forming a semiconductor device, the method comprising: depositing a first metal layer comprising tungsten (W) on a substrate surface by physical vapor deposition (PVD), the substrate surface comprising at least one feature extending a depth from the substrate surface to a bottom and having two sidewalls; exposing the first metal layer to a nucleation predip comprising boron to form a boron nucleation layer; exposing the boron nucleation layer to plasma to etch the boron nucleation layer; depositing a second metal layer comprising tungsten (W) on the boron nucleation layer by physical vapor deposition (PVD); as well as A metal gap filler comprising tungsten (W) is deposited on the second metal layer to fill the at least one feature and form a metal stack.

16. The method of claim 15, wherein the boron nucleation layer comprises an average of one to two monolayers of boron.

17. The method of claim 15, wherein the first metal layer forms an overhang into the at least one feature, the overhang having a length of approximately The average thickness of 18. The method of claim 17, wherein the plasma removes at least a portion of the overhang.

19. The method of claim 15, wherein the nucleating predip comprises a boron compound.

20. The method of claim 15, wherein the nucleating predip consists essentially of diborane (B2H6).

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