PCB bonding pad gasket for three-pin MOSFET assembly

Abstract

A printed circuit board (PCB) pad pad for a three-pin metal oxide semiconductor field effect transistor (MOSFET) component includes four pads, wherein a split pad is used for a drain terminal of the MOSFET component. The PCB pad pad includes: a first pad to connect a gate terminal of the MOSFET component to a PCB; a second pad to connect a source terminal of the MOSFET component to the PCB; a third pad corresponding to connecting a drain terminal of the MOSFET component to the PCB; and a fourth pad to connect the drain terminal of the MOSFET component to the PCB (printed circuit board).

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 457,581, filed April 6, 2023, and U.S. Provisional Application No. 63 / 435,505, filed December 27, 2022, the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure relate generally to printed circuit boards (PCBs), and more particularly, to PCB pads for asymmetric three-pin metal oxide semiconductor field effect transistors (MOSFETs). Background Art

[0004] MOSFETs are the most common form of transistor used in today's electronic devices. They can be classified as either N-type or P-type MOSFETs, with electrons being the primary charge carriers in the N-type and holes being the primary charge carriers in the P-type. In addition to the billions of transistors already used within the die of a memory cell, memory devices such as solid-state drives (SSDs) also use MOSFETs in the form of small outline transistors (SOTs). In this context, a MOSFET is primarily used to control the conductivity between its source and drain terminals depending on the amount of voltage applied to its gate terminal.

[0005] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 A diagram illustrating a PCB pad pad for a three-pin MOSFET according to some embodiments of the present disclosure.

[0008] Figure 2 is a flow chart of an example method for assembling a PCB including at least one PCB pad for a three-pin MOSFET component, according to some embodiments of the present disclosure.

[0009] Figure 3 A flow chart of an example method for producing an assembled PCB based on a PCB including at least one PCB pad for a three-pin MOSFET component according to some example embodiments of the present disclosure is provided.

[0010] Figure 4 To illustrate a diagram of an example of a memory subsystem according to some embodiments of the present disclosure, any of more components of the memory subsystem may be implemented based on a PCB including at least one PCB pad for a three-pin MOSFET component.

[0011] Figure 5

[0015] An example machine is illustrated in the form of a computer system within which a set of instructions may be executed, causing the machine to perform any one or more of the methodologies discussed herein. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to a PCB pad liner for an asymmetric three-pin MOSFET component. While the various embodiments described herein may be extended to any assembled PCB or PCB assembly process, one or more embodiments may find particular application within the context of a PCB implementing a memory subsystem. The memory subsystem may be a storage device (e.g., a solid-state drive (SSD)), a memory module, or a combination of a storage device and a memory module. Figure 4 Examples of other storage devices and memory modules are described. Generally speaking, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem. A memory subsystem controller typically receives commands or operations from the host system and converts the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components of the memory subsystem.

[0013] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. A NAND memory device may include multiple NAND dies. Each die may include one or more planes, and each plane includes multiple blocks. Each block includes an array, which includes pages (rows) and strings (columns). A string includes multiple memory cells connected in series. A memory cell ("cell") is an electronic circuit (usually a transistor) that stores information. Depending on the cell type, a cell can store one or more binary bits of information and have various logical states related to the number of bits stored. The logical state can be represented by a binary value (e.g., "0" and "1") or a combination of such values.

[0014] Various electronic devices, such as memory subsystems (e.g., SSDs, DIMMs), are implemented using one or more printed circuit boards. Generally speaking, PCB assembly involves a pick-and-place process, in which various circuit components are picked up from a tape and reel or tray and placed at specific points on the PCB, and a reflow process, in which a forced convection oven is used to melt pre-placed solder deposits to form reliable joints between the components and the PCB. As used herein, an assembled PCB may refer to a PCB after one or more components have been mounted to the PCB. An assembled PCB may include various circuit components that are soldered or otherwise connected to the PCB. Circuit components may include, for example, resistors, capacitors, inductors, transistors, fuses, integrated circuits (ICs) or chips, trim pots, electroacoustic devices, microelectromechanical devices (MEMs), electro-optical devices, microprocessor chips, memory chips, multi-pin connectors, and various types of sensors.

[0015] During the reflow process of PCB assembly, circuit components may be soldered to one or more pads on the PCB. Pads are exposed areas of metal on the PCB to which component pins are soldered. In other words, pads serve as designated surface areas for electrical contact between the component and the board. As used herein, the term "PCB pad" encompasses a group of pads designated for a specific component.

[0016] There are generally two types of pads: through-hole pads and surface-mount pads. Through-hole pads are used to mount through-hole components. Surface-mount pads are used to mount surface-mount components. One type of surface-mount pad is a solder mask-defined pad. Solder mask-defined pads are defined by the apertures of a solder mask applied to the pad. These pads have solder mask apertures that are smaller than the area of the pad they cover. This is done to reduce the size of the copper pad to which the circuit component will be soldered.

[0017] As mentioned above, metal oxide semiconductor field effect transistors (MOSFETs) are ubiquitous in electronic devices and are widely used in memory devices such as SSDs. MOSFET components typically include three pins (also referred to herein as "terminals"): a gate terminal, a drain terminal, and a source terminal. Conventionally, a PCB pad with three pads is used to connect the MOSFET component to the PCB during assembly, with each terminal of the MOSFET connected to a separate pad on the PCB. Typically, the pad for the drain terminal is much larger than the pads for the source and gate terminals.

[0018] Conventional three-pad designs for MOSFET PCB pad pads can lead to defects in assembled PCBs. These defects are becoming more prevalent in micro MOSFET assemblies due to challenges in PCB and component manufacturing. For example, conventional three-pad pad pad designs for micro MOSFETs can lead to air gap mismatches between the PCB pads and the component terminal connections (also referred to herein as "component terminals"). Open solder joints can be caused by air gap mismatches, which can be further amplified by component displacement toward the larger drain terminal during the reflow process of PCB assembly. Due to this component displacement and uneven surface tension, the component can tilt and shift even more toward the drain pad, resulting in open solder joint defects at the source or gate terminals of the MOSFET component.

[0019] Aspects of the present disclosure address the aforementioned issues with conventional PCB pads for MOSFETs by dividing the pad for the drain terminal of the MOSFET into two pads. Specifically, the present disclosure provides an improved PCB pad for a three-pin MOSFET, comprising four pads: a first pad for connecting the gate terminal of the MOSFET to the PCB; a second pad for connecting the source terminal of the MOSFET to the PCB; and third and fourth pads for connecting the drain terminal of the MOSFET to the PCB.

[0020] When compared to conventional pad liner designs, in the case of a four-pad PCB pad liner, the volume of solder applied to the pad is more uniform (relatively average), thereby balancing the surface tension on the four corners of the MOSFET component. As a result, the MOSFET component does not shift toward the drain terminal during the reflow process. Thus, the four-pad PCB MOSFET pad liner prevents component shifting and tilting, thereby ensuring high-quality solder joints. In addition, the four-pad design for the MOSFET pad liner is solder mask defined. With the solder mask defining the pads, a uniform (relatively average) standoff height is maintained across the four solder joints, which helps prevent component tilting.

[0021] In addition, uniform gap height benefits the mechanical reliability of the assembly. For example, when comparing a four-pad design for MOSFET pads with conventional MOSFET pads, the source and gate terminal pad sizes of conventional MOSFET pads have a smaller area ratio, with the current standard template thickness being 0.1 mm. The template thickness can be reduced (e.g., to 0.075 mm) to improve solder printing yield (via a better area ratio than 0.1 mm) to achieve better throughput and yield from surface mount lines. However, a reduction in solder volume (e.g., a 25% reduction) can affect the mechanical reliability (shear strength) of the assembly. By increasing the pad size relative to the conventional design for MOSFET pads, as with the four-pad design for MOSFET pads, a better solder printing aspect ratio can be achieved without overprinting the pads (e.g., using a 0.1 mm thick template). This reduces defectivity by minimizing tilt and improves mechanical reliability tolerance due to the increased solder content in the joint.

[0022] Figure 1 FIG. 1 is a diagram illustrating a PCB pad 100 for a three-pin MOSFET component 110 with bottom-only termination, according to some embodiments of the present disclosure. Figure 1 Also shown in FIG. 1 is an equivalent MOSFET circuit 120 corresponding to the MOSFET component 110. The MOSFET circuit 120 includes a source terminal 122, a gate terminal 124, and a drain terminal 126.

[0023] Unlike conventional PCB land pads for three-pin MOSFET components that include a single pad for each terminal, land pad 100 includes four pads, with the pad for drain terminal 126 being split into two. For example, as shown, land pad 100 includes source pad 102, gate pad 104, drain pad 106, and drain pad 108. For some embodiments, source pad 102, gate pad 104, drain pad 106, and drain pad 108 are uniform in size and are arranged symmetrically with source pad 102 and gate pad 104 on land pad 100.

[0024] In some embodiments, pad 100 is solder mask defined. That is, during PCB assembly, before solder paste is applied, a solder mask defining the source pad 102, gate pad 104, and drain pads 106 and 108 of pad 100 is applied to the copper layer. The solder mask further defines an air gap 109 separating drain pad 106 from drain pad 108, and an air gap 111 between source pad 102 and gate pad 104. In some embodiments, air gap 109 and air gap 111 are identical. Additionally, the solder mask further defines an air gap 113 separating gate pad 104 from drain pad 106, and an air gap 115 separating source pad 102 from drain pad 108.

[0025] For some embodiments, air gaps 109 and 111 are approximately 0.15 mm, and air gaps 113 and 115 are approximately 0.3 mm, where standard manufacturing tolerances may apply to each air gap during PCB manufacturing (e.g., + / - 35 μm). Consistent with these embodiments, the uniform length of each of pads 102, 104, 106, and 108 is 0.45 mm, and the uniform width of each of pads 102, 104, 106, and 108 is 0.2 mm. Consistent with these embodiments, a solder paste stencil aperture having a vertical length of 0.4 mm, a horizontal length of 0.165 mm, and a 0.05 mm corner radius may be used for each of pads 102, 104, 106, and 108, where a horizontal air gap of 0.175 mm and a vertical air gap of 0.31 mm separate each of the stencil apertures.

[0026] As described above, each pad is an exposed area on the PCB where metal components are soldered to. Here, source pad 102 is used to connect source terminal 122 of MOSFET component 110 to the PCB, gate pad 104 is used to connect gate terminal 124 of MOSFET component 110 to the PCB, and drain pads 106 and 108 are used to connect drain terminal 126 of MOSFET component 110 to the PCB.

[0027] During a placement process performed as part of PCB assembly, as shown, MOSFET component 110 is placed on land pad 100. More specifically, source terminal 122 of MOSFET component 110 is placed on source pad 102, gate terminal 124 of MOSFET component 110 is placed on gate pad 104, and drain terminal 126 is placed on drain pads 106 and 108.

[0028] During a reflow process performed as part of PCB assembly, the terminals of the MOSFET component 110 are soldered to the land pads 100. More specifically, the source terminal 122 of the MOSFET component 110 is soldered to the source pad 102, the gate terminal 124 of the MOSFET component 110 is soldered to the gate pad 104, and the drain terminal 126 is soldered to the drain pads 106 and 108. The split pad design for the drain terminal 126 (i.e., the drain pads 106 and 108) balances the surface tension on the four corners of the MOSFET component 110 during reflow, thereby minimizing the displacement of the MOSFET component 110 toward the drain terminal, which is further reduced considering that the land pads 100 are solder mask defined. Overall, the reduced displacement and tilting prevent open solder joint defects of the three-pin MOSFET component 110.

[0029] Figure 2 2 is a flow chart of an example method 200 for assembling a PCB including one or more PCB pads (e.g., one or more of pads 100) according to some embodiments of the present disclosure. The figures described herein should be understood as examples only, and one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment; other process flows are possible.

[0030] At operation 205, a solder mask is applied to the copper layer of the PCB. The solder mask insulates the copper traces to prevent accidental contact with other conductive materials, which could cause a short circuit. The solder mask defines a PCB pad for bottom-only termination of a surface-mounted three-pin MOSFET component (hereinafter referred to as a "three-pin MOSFET pad"). Referring to the three-pin MOSFET pad, the solder mask defines four pads, with the pad for the drain terminal of the MOSFET component being divided into two. For example, the three-pin MOSFET pad includes a source pad, a gate pad, and two drain pads. In some embodiments, the two drain pads are uniform in size and arranged symmetrically with the source and gate pads on the three-pin MOSFET pad. In some embodiments, the solder mask defines a 0.15 mm air gap separating the first drain pad from the second drain pad. Consistent with these embodiments, the solder mask further defines a 0.15 mm air gap between the source pad and the drain pad.

[0031] Solder paste is applied to exposed copper pads on the PCB at operation 210. As part of applying the solder paste to the PCB, a thin stainless steel or nickel stencil is placed over the PCB to allow the assembly system to apply solder paste only to certain portions of the PCB where components will be located in the assembled PCB (e.g., pads).

[0032] In the aforementioned example, mechanical fasteners hold the PCB and solder stencil in place, and an applicator machine places solder paste in precise amounts on the desired areas. The applicator machine spreads the paste over the stencil, applying it evenly to each open area. After the stencil is removed, the solder paste remains in its specific location on the PCB pads.

[0033] The application of solder paste includes applying solder paste to the source pad, gate pad, and two drain pads of the three-pin MOSFET pad pad to allow the terminals of the MOSFET component to be soldered to the corresponding pads. For some embodiments, a uniform (relatively average) volume of solder is applied to the source pad, gate pad, and two drain pads of the three-pin MOSFET pad pad. For example, a template for applying solder paste may have uniformly sized orifices for the source pad, gate pad, and two drain pads of the three-pin MOSFET pad pad. The uniform solder volume on the pads balances the surface tension on the four corners of the MOSFET component to prevent the component from shifting and tilting toward the drain terminal during the reflow process.

[0034] For some embodiments, the stencil aperture is configured to have an air gap of 0.175 mm, thus creating an air gap between the solder paste deposits of the source and gate pads and between the first and second drain pads of the three-pin MOSFET pad pads.

[0035] At operation 215, a component placement process is performed. During the component placement process, one or more circuit components are placed on specific areas on the PCB. Component placement can be done manually (e.g., by one or more people) or with the aid of a machine, such as a pick-and-place machine. The pick-and-place device is a robotic device that places surface-mount components on the PCB. In an example of a placement process, the pick-and-place device picks up the PCB using a vacuum gripper and moves it to a pick-and-place station. At the pick-and-place station, the pick-and-place device (robot) orients itself to the PCB and applies one or more surface-mount components to the PCB surface.

[0036] As part of the component placement process, a three-pin MOSFET component (e.g., MOSFET component 110) is placed on the pads. More specifically, the source terminal of the MOSFET component is placed on the source pad, the gate terminal of the MOSFET component is placed on the gate pad, and the drain terminals are placed on the two drain pads.

[0037] A reflow process is performed at operation 220. The reflow process involves melting the solder in the solder paste and cooling it to create a permanent solder joint between the circuit component and the PCB.

[0038] During the reflow process, the terminals of the MOSFET component 110 are soldered to the solder pads 100. More specifically, the source terminal of the MOSFET component is soldered to the source pad, the gate terminal of the MOSFET component is soldered to the gate pad, and the drain terminal is soldered to the first drain pad and the second drain pad. The split pad design (i.e., two drain pads) for the drain terminal and the uniformly sized, spaced-apart source and gate pads balance the surface tension on the four corners of the MOSFET component during reflow, thereby preventing the MOSFET component from shifting and tilting toward the drain terminal, thereby creating an open solder joint defect.

[0039] In an example of a reflow process performed at operation 220, a PCB and circuit components placed on the PCB (including a three-pin MOSFET component placed on a three-pin MOSFET pad) are placed on a conveyor and moved through a reflow oven, which heats the solder, thereby liquefying it and ensuring that a connection is formed between the PCB and the circuit components via the pads. The reflow oven includes a series of heaters that gradually heat the board to a temperature sufficient to melt the solder in the solder paste (e.g., 250 degrees Celsius or 480 degrees Fahrenheit). After melting the solder, the conveyor moves the PCB to a cooler where the solder is cooled to control resolidification, thereby creating a permanent solder joint that connects the circuit components to the PCB, resulting in an assembled PCB with electrical interconnections.

[0040] In various embodiments, the assembled PCB may fully or partially implement a memory subsystem, a memory device for storing data from a host system, or a memory subsystem controller that may be operatively coupled to one or more memory devices.

[0041] Figure 3A flowchart of an example method 300 for producing an assembled PCB based on a PCB including at least one pad (e.g., pad liner 100) for a three-pin MOSFET component (with bottom-only terminations) according to some example embodiments of the present disclosure is provided. Method 300 may be performed using processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 300 is performed at least in part by a circuit design system (e.g., an electronic design automation (EDA) system). Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. Other process flows are possible.

[0042] At operation 305, circuit design data is configured for forming (e.g., manufacturing) a PCB including at least one PCB pad for a surface-mounted three-pin MOSFET component (hereinafter referred to as a "three-pin MOSFET pad"). Referring to the three-pin MOSFET pad, the circuit design data defines four pads, wherein the pad for the drain terminal of the MOSFET component is divided into two. For example, the three-pin MOSFET pad includes a source pad, a gate pad, and two drain pads.

[0043] For some embodiments, the pads of the pad pad are uniform in size. For some embodiments, the two drain pads are arranged symmetrically with the source pad and gate pad on the three-pin MOSFET pad pad. For some embodiments, the circuit design data defines an air gap of 0.15 mm separating the first drain pad from the second drain pad. Consistent with some of these embodiments, the circuit design data may further define an air gap of 0.15 mm between the source pad and the gate pad.

[0044] The circuit design data can be generated or configured by a circuit design system (e.g., an EDA system), which can assist in designing a PCB, designing a template, generating inspection procedures for pre-reflow (after solder printing and before reflow) and post-reflow, and generating a placement configuration for one or more circuit components on the PCB.

[0045] At operation 310, a PCB assembly process is performed using the circuit design data, resulting in an assembled PCB. The PCB assembly process may include any one or more of the operations of method 200 described above. As an example, the circuit design data may be used to configure or generate a solder mask that is partially used to define a three-pin MOSFET pad. As another example, the circuit design data may be used to configure or generate a template used during solder paste application to apply solder to four pads of the three-pin MOSFET pad, wherein a uniform volume of solder is applied to the four pads. As yet another example, the circuit design data may be used to instruct or control a pick-and-place device to place a surface-mounted three-pin MOSFET component on the three-pin MOSFET pad, and / or to generate an inspection recipe in a surface mounting line to check the quality of the solder volume after printing and the quality of the solder joint after reflow.

[0046] Figure 4 A block diagram illustrating a memory subsystem 410 that may be implemented at least in part by an example printed circuit board according to some embodiments of the present disclosure is shown. Memory subsystem 410 may include media such as one or more volatile memory devices (e.g., memory device 440), one or more non-volatile memory devices (e.g., memory device 430), or a combination thereof.

[0047] The memory subsystem 410 can be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include SSDs, flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), and their subcategories include small outline DIMMs (SO-DIMMs), registered DIMMs (RDIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0048] Memory devices 430 and 440 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 440) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0049] Some examples of nonvolatile memory devices (e.g., memory device 430) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point (3D cross-point) memory device, which is a cross-point array of nonvolatile memory cells. The cross-point array of nonvolatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, compared to many flash-based memories, cross-point nonvolatile memory can perform write-in-place operations, in which nonvolatile memory cells can be programmed without first erasing the nonvolatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and 3D NAND.

[0050] Each of the memory devices 430 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell.

[0051] Although nonvolatile memory components such as NAND-type flash memory (e.g., 2D NAND, 3D NAND) and a 3D cross-point nonvolatile memory cell array are described, the memory device 430 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0052] The memory subsystem controller 415 (or, for simplicity, the controller 415) can communicate with the memory device 430 to perform operations such as reading data, writing data, or erasing data at the memory device 430, and other such operations. The memory subsystem controller 415 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 415 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0053] The memory subsystem controller 415 may include a processor 417 (processing device) configured to execute instructions stored in a local memory 419. In the illustrated example, the local memory 419 of the memory subsystem controller 415 includes embedded memory configured to store instructions to perform various processes, operations, logic flows, and routines that control the operation of the memory subsystem 410, including handling communications between the memory subsystem 410 and a host system.

[0054] In some embodiments, local memory 419 may include memory registers that store memory pointers, fetched data, etc. Local memory 419 may also include ROM for storing microcode. Figure 4 The example memory subsystem 410 in FIG has been illustrated as including a memory subsystem controller 415, but in another embodiment of the present disclosure, the memory subsystem 410 does not include a memory subsystem controller 415 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0055] In general, the memory subsystem controller 415 may receive commands or operations from the host system and convert them into instructions or appropriate commands to enable the desired access to the memory device 430 and / or the memory device 440. The memory subsystem controller 415 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 430. The memory subsystem controller 415 may further include host interface circuitry to communicate with the host system via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 430 and / or the memory device 440, and convert responses associated with the memory device 430 and / or the memory device 440 into information for the host system.

[0056] As shown, the memory subsystem controller 415 includes at least one three-pin MOSFET component 110. As described above, for some embodiments, the memory subsystem controller 415 can be implemented in whole or in part by a PCB that includes a four-pad solder pad for the three-pin MOSFET component 110. In an example, the three-pin MOSFET component 110 of the memory subsystem controller 415 is connected (e.g., soldered) to an instance of the solder pad 100 on the PCB that fully or partially implements the memory subsystem controller 415.

[0057] In some embodiments, the memory device 430 includes a local media controller 435 that operates in conjunction with the memory subsystem controller 415 to perform operations on one or more memory cells of the memory device 430. It should be understood that although Figure 4 The memory subsystem controller 415 is illustrated as including at least one three-pin MOSFET component 110 , but the local media controller 435 may also include at least one three-pin MOSFET component 110 .

[0058] In view of the above disclosure, various examples are described below. It should be noted that one or more features of the examples taken independently or in combination should be considered to be within the disclosure of this application.

[0059] Example 1. A printed circuit board (PCB) solder pad for a metal oxide semiconductor field effect transistor (MOSFET) component, comprising: a first pad for connecting the gate terminal of the MOSFET component to the PCB; a second pad for connecting the source terminal of the MOSFET component to the PCB; a third pad corresponding to connecting the drain terminal of the MOSFET component to the PCB; and a fourth pad for connecting the drain terminal of the MOSFET component to the PCB.

[0060] Example 2. The PCB pad of Example 1, wherein the first pad, the second pad, the third pad, and the fourth pad are solder mask defined.

[0061] Example 3. The PCB pad according to any one of Examples 1 or 2, wherein the first pad and the second pad are symmetrical with the third pad and the fourth pad.

[0062] Example 4. A PCB pad gasket according to any one of Examples 1 to 3, wherein: a first air gap separates the third gasket from the fourth gasket; a second air gap separates the first gasket from the second gasket; and the first gasket and the second gasket are the same.

[0063] Example 5. The PCB pad of any one of Examples 1 to 4, wherein the air gap is 0.15 mm.

[0064] Example 6. The PCB pad of any one of Examples 1 to 5, wherein the MOSFET component is a three-pin surface mount component with bottom-only termination.

[0065] Example 7. The PCB pad of any one of Examples 1 to 6, wherein each of the first pad, the second pad, the third pad, and the fourth pad comprises an exposed area of copper metal on a PCB.

[0066] Example 8. An assembled printed circuit board (PCB), comprising: a PCB including a pad pad for a three-pin metal oxide semiconductor field effect transistor (MOSFET) component, the pad pad including a gate pad, a source pad, a first drain pad, and a second drain pad; and a three-pin MOSFET component soldered to the pad pad of the PCB, the MOSFET component including a gate terminal, a source terminal, and a drain terminal, the gate terminal soldered to the gate pad, the source terminal soldered to the source pad, and the drain terminal soldered to the first drain pad and the second drain pad.

[0067] Example 9. The assembled PCB of Example 8, wherein the land pads are solder mask defined.

[0068] Example 10. The assembled PCB of any of Examples 8 or 9, wherein the gate pad and the source pad are symmetrical with the first drain pad and the second drain pad.

[0069] Example 11. The assembled PCB of any of Examples 8 to 10, wherein an air gap separates the first drain pad from the second drain pad.

[0070] Example 12. The assembled PCB of any of Examples 8 to 11, wherein a uniform volume of solder is applied to the gate pad, the source pad, the first drain pad, and the second drain pad.

[0071] Example 13. The assembled PCB of any of Examples 8 to 12, wherein the MOSFET component is a three-pin surface mount component with bottom-only termination.

[0072] Example 14. A method for producing an assembled printed circuit board (PCB), the method comprising: applying a solder mask to a copper layer of the PCB, the solder mask defining pads for a metal oxide semiconductor field effect transistor (MOSFET) component, the pads comprising a gate pad, a source pad, a first drain pad, and a second drain pad, the MOSFET component comprising a gate terminal, a source terminal, and a drain terminal; applying solder paste to the solder masked copper layer, the applying of the solder paste comprising applying the solder paste to the gate pad, the source pad, a first drain pad, and a second drain pad. The MOSFET component is provided with a first solder paste and a second solder paste, wherein the first and second drain pads are connected to each other; the ...

[0073] Example 15. The method of Example 14, further comprising configuring circuit design data for forming the PCB including the pad liner for the MOSFET component.

[0074] Example 16. The method of any of Examples 14 or 15, wherein one or more of the applying of the solder mask, the applying of the solder paste, and the placing of the MOSFET components is based on the circuit design data.

[0075] Example 17. The method of any of Examples 14 to 16, wherein the solder mask defines an air gap of 0.15 mm between the first drain pad and the second drain pad.

[0076] Example 18. A method according to any one of Examples 14 to 17, wherein applying the solder paste to the gate pad, the source pad, the first drain pad, and the second drain pad includes applying a uniform volume of solder to the gate pad, the source pad, the first drain pad, and the second drain pad.

[0077] Example 19. The method of any one of Examples 14 to 18, wherein placing the MOSFET component on the land pad comprises surface mounting the MOSFET component to the PCB.

[0078] Example 20. The method of any one of Examples 14 to 19, wherein the first drain liner and the second drain liner are uniform in size.

[0079] Figure 5 An example machine is illustrated in the form of a computer system 500 within which a set of instructions may be executed for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 500 may be configured to perform the operations of a controller. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0080] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0081] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., ROM, flash memory, DRAM such as SDRAM or RDRAM, etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0082] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an ASIC, an FPGA, a digital signal processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communicating via a network 520.

[0083] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon a set of one or more instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, with the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 4 Memory subsystem 410.

[0084] In one embodiment, instructions 526 include circuit design data (eg, Figure 3 300). Although machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0085] Some portions of the previously described detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0086] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0087] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), ROM, RAM, EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0088] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures for various of these systems will be presented as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure described herein may be implemented using a variety of programming languages.

[0089] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, or the like.

[0090] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A printed circuit board (PCB) pad for a metal oxide semiconductor field effect transistor (MOSFET) component, comprising: a first pad for connecting the gate terminal of the MOSFET component to a PCB; a second pad for connecting the source terminal of the MOSFET component to the PCB; a third pad corresponding to connecting the drain terminal of the MOSFET component to the PCB; and A fourth pad is used to connect the drain terminal of the MOSFET component to the PCB. 2 . The PCB pad according to claim 1 , wherein the first pad, the second pad, the third pad, and the fourth pad are solder mask defined. 3 . The PCB pad according to claim 1 , wherein the first pad and the second pad are symmetrical to the third pad and the fourth pad.

4. The PCB pad according to claim 1, wherein: A first air gap separates the third pad from the fourth pad; a second air gap separating the first liner from the second liner; and The first air gap and the second air gap are identical. The PCB pad gasket according to claim 4 , wherein the air gap is 0.15 mm.

6. The PCB pad of claim 1, wherein the MOSFET component is a three-pin surface mount component with bottom-only termination. 7 . The PCB pad according to claim 1 , wherein each of the first pad, the second pad, the third pad, and the fourth pad comprises an exposed area of copper metal on a PCB.

8. An assembled printed circuit board (PCB), comprising: a PCB including a pad pad for a three-pin metal oxide semiconductor field effect transistor (MOSFET) component, the pad pad including a gate pad, a source pad, a first drain pad, and a second drain pad; and A three-pin MOSFET component is soldered to the solder pad of the PCB, the MOSFET component including a gate terminal, a source terminal, and a drain terminal, the gate terminal is soldered to the gate pad, the source terminal is soldered to the source pad, and the drain terminal is soldered to the first drain pad and the second drain pad.

9. The assembled PCB of claim 8, wherein the land pads are solder mask defined. 10 . The assembled PCB of claim 8 , wherein the gate pad and the source pad are symmetrical to the first drain pad and the second drain pad.

11. The assembled PCB of claim 8, wherein an air gap separates the first drain pad from the second drain pad. 12 . The assembled PCB of claim 8 , wherein a uniform volume of solder is applied to the gate pad, the source pad, the first drain pad, and the second drain pad.

13. The assembled PCB of claim 8, wherein the MOSFET component is a three-pin surface mount component with bottom-only termination.

14. A method for producing an assembled printed circuit board (PCB), the method comprising: applying a solder mask to a copper layer of the PCB, the solder mask defining land pads for a metal oxide semiconductor field effect transistor (MOSFET) component, the land pads including a gate pad, a source pad, a first drain pad, and a second drain pad, the MOSFET component including a gate terminal, a source terminal, and a drain terminal; applying solder paste to the solder masked copper layer, said applying of solder paste comprising applying solder paste to said gate pad, said source pad, said first drain pad, and said second drain pad; Placing the MOSFET component on the pad pad, wherein placing the component on the pad pad includes placing the drain terminal of the MOSFET component on the first drain pad and the second drain pad; and A permanent solder joint is created between the MOSFET component and the land pad, the creation of the permanent solder joint comprising melting the solder paste to solder the drain terminal to the first drain pad and to the second drain pad.

15. The method of claim 14, further comprising configuring circuit design data for forming the PCB including the land pads for the MOSFET component.

16. The method of claim 15, wherein one or more of the applying of the solder mask, the applying of the solder paste, and the placing of the MOSFET component is based on the circuit design data. 17 . The method of claim 14 , wherein the solder mask defines an air gap of 0.15 mm between the first drain pad and the second drain pad.

18. The method of claim 14, wherein applying the solder paste to the gate pad, the source pad, the first drain pad, and the second drain pad comprises applying a uniform volume of solder to the gate pad, the source pad, the first drain pad, and the second drain pad.

19. The method of claim 14, wherein placing the MOSFET component on the land pad comprises surface mounting the MOSFET component to the PCB.

20. The method of claim 14, wherein the first drain liner and the second drain liner are uniform in size.

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